Freescale AN1759 Add a non-volatile clock to the mc68hc705j1a Datasheet

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AN1759
Add a Non-Volatile Clock to the MC68HC705J1A
By Mark Glenewinkel
Field Applications Engineering
Consumer Systems Group
Austin, Texas
Introduction
Many embedded systems require the measurement of time. This can be
accomplished internally by some MCUs that have on-chip real-time
clocks. Even so, for date, month, and leap year measurement, this task
can take substantial amounts of bandwidth and code space.
The DS1307 64x8 serial real-time clock provides calendar and time
keeping functions along with system-enhancing non-volatile RAM. With
a 2-wire interface, timekeeping can be managed easily.
Some applications of using the DS1307 are:
•
Logging of chronological events
•
Tracking power down time of a system
•
Providing alarm functions
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Motorola, Inc., 1998
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Application Note
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The non-volatile RAM (random-access memory) also gives the user
additional applications such as:
•
Power down information storage for consumer electronics like
TVs, VCRs, and hand-held portables
•
Identification number storage for remote addressing or security
•
Storage of telecommunication information like phone number
recall and speed dialing
This application note describes the interface between the
MC68HC705J1A (J1A) and the DS1307. Circuitry and example code are
given to demonstrate the interface between the two parts.
Features
Description
The DS1307 provides these features:
•
Real-time clock counts seconds, minutes, hours, day of the week,
date, month, and year.
•
Leap year compensation valid up to 2100
•
56 bytes of non-volatile RAM for data storage
•
2-wire serial interface
•
Programmable square wave output with frequencies of 1 Hz,
4.096 kHz, 8.192 kHz, and 32.768 kHz
•
Automatic power switching to battery when main power fails
•
In battery backup mode, less than 500 nA consumed at 25 °C
•
8-pin DIP or SOIC package
•
Optional industrial temperature range of –40 °C to +85 °C
The DS1307 is a low-power binary coded decimal (BCD) clock calendar
that provides seconds, minutes, hours, day, date, month, and year. In
addition, it has 56 bytes of non-volatile RAM. End-of-the-month
adjustments are automatic for months with less than 31 days. The
device also corrects for leap years. The clock can operate in either
12-hour or 24-hour mode. In 12-hour mode, an a.m./p.m indicator is
used.
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Application Note
DS1307 Hardware Interface
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The DS1307 has built-in power management circuitry to detect power
failures on the VDD pin and when detected will switch power over to the
battery back-up pin, VBAT. Access to the device is terminated when VDD
falls below 1.25 x VBAT. Further accesses to the device are not allowed.
On power up, the device switches power from VBAT to VDD when the VDD
pin is 0.2 volts above VBAT. Once VDD is higher than 1.25 x VBAT, normal
operations can continue.
Address and data are communicated via the 2-wire bus. The DS1307
operates as a slave at all times and is accessed by first transmitting the
DS1307’s identification code on the bus.
DS1307 Hardware Interface
Pinout and Pin
Descriptions
X1
1
8
VDD
X2
2
7
SQW/OUT
VBAT
3
6
SCL
GND
4
5
SDA
Figure 1. DS1307 Pinout
VDD and GND
These pins serve as the main power source for the device. When
+5 volts is applied to this pin, the device is fully accessible and data can
be read or written. If the power on the VDD pin falls below 1.25 x VDD, the
device switches its power supply to VBAT. At this point, reading and
writing to the device is prohibited. The timekeeping function and nonvolatile RAM are unaffected.
VBAT
This pin is the power input for any standard 3-volt lithium battery or other
3-volt source. For proper operation, this voltage must be held between
2.5 and 3.5 volts. A lithium battery with at least a 35-mA hours rating will
back up the DS1307 for more than 10 years in the absence of power.
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Application Note
X1 and X2
These pins are used to connect a 32.768-kHz crystal to the device. No
other capacitors or resistors are needed for this crystal circuit. The
internal oscillator circuitry is designed for a crystal with load capacitance
of 12.5 pF. For the test circuit described in this application note, an
Epson C-001R crystal was used. The Digi-key part number for this
device is SE3201-ND.
SQW/OUT
When enabled, this pin outputs one of four selectable frequencies:
•
1 Hz
•
4.096 kHz
•
8.192 kHz
•
32.768 kHz
The 1-Hz signal can be used to feed an external interrupt pin on an MCU.
This allows the MCU to use minimal bandwidth when servicing the
timekeeping function of a system.
When disabled, the pin acts as a normal output pin. It is controlled via
the DS1307 control register.
SCL
The SCL pin is the clock input for the DS1307 2-wire serial interface.
SDA
The SDA pin is an I/O pin used to transmit and receive data off the 2-wire
serial interface. SDA is an open-drain pin that requires an external pullup
resistor.
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DS1307 Hardware Interface
Block Diagram
VDD
VBAT
GND
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SQW/OUT
X1
POWER
CONTROL
X2
OSCILLATOR
& DIVIDER
REAL-TIME
CLOCK RAM
SQUARE
WAVE OUT
CONTROL
LOGIC
SDA
SCL
SERIAL
BUS INTERFACE
RAM
56 X 8
ADDRESS
REGISTER
Figure 2. DS1307 Block Diagram
Serial Interface
The DS1307 supports the bidirectional, 2-wire protocol. The protocol has
these characteristics:
•
Any device sending out data is defined as a transmitter.
•
Any device receiving data is defined as a receiver.
•
The device controlling the transfer is called the master.
•
The device being controlled is called the slave.
•
The master initiates all transactions.
•
The master always provides the clock for both transmit and
receive operations.
•
The DS1307 is always considered the slave.
•
The clock signal is called SCL.
•
The data signal is called SDA.
•
All data is sent most significant bit (MSB) first.
Figure 3 shows the 2-wire bus interface between a master and slave.
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Application Note
+5 V
BUS MASTER
DS1307 2-WIRE PORT
5 kΩ
SDA
RX
RX
PORT PIN
DIRECTION
TX
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TX
TX
SCL
RX
Figure 3. 2-Wire Serial Bus Interface
Bus Idle
In idle mode, both the SDA and SCL are held high.
Start Transfer
All transfers begin with the start transfer condition. This is done by
bringing the SDA pin from HIGH to LOW while the SCL pin is HIGH. The
DS1307 is monitoring the bus for this signal and will not start any
transactions until this condition is met. See Figure 4.
Stop Transfer
All transfers must be terminated with the stop transfer condition. This is
done by bringing the SDA pin from LOW to HIGH while the SCL pin is
HIGH. A stop transfer can be used only after the transmitting device
releases the bus. See Figure 4.
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DS1307 Hardware Interface
SCL
SDA
START
STOP
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Figure 4. Start and Stop Transfer Timing
Data Transfer
Data is transmitted on the rising edge of SCL. Data can only be changed
while SCL is LOW. The receiving device samples the bus after SCL goes
HIGH. There is one clock pulse per bit of data transmitted. See Figure 5.
SCL
SDA
DATA
STABLE
DATA
CHANGE
DATA
STABLE
Figure 5. Data Transfer Timing
Acknowledge
Transfer
The acknowledge transfer is a type of handshaking convention used to
signify that a successful transfer of data has taken place. After the
transmitting device sends out the eighth bit of a byte of data, it releases
the bus. The master sends out a ninth clock signal and the receiver
acknowledges the transfer by pulling SDA LOW. Once the transmitter
reads the LOW condition of SDA, it proceeds by taking over the bus and
sending out the next byte of data.
If the DS1307 is transmitting data and the master wants to end further
transmissions, the master sends a NO ACK signal (HIGH) back to the
DS1307. This tells the DS1307 that no more transfers are needed and
the stop transfer condition will be initiated soon. See Figure 6 for these
different timing patterns.
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Application Note
ACK FROM SLAVE
SCL
SDA
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ACK FROM MASTER
SCL
IF LAST RECEIVE, SDA IS HIGH
SDA
Figure 6. Acknowledge Timing
2-Wire Protocol
Example
An example of the protocol needed to write $10 to address $07 of the
DS1307 is:
1. The master transmits a start transfer.
2. The master transmits the DS1307 7-bit identification code,
%1101000.
3. Since this is a data write transfer, the master then transmits a 0.
4. Since a byte has just been transmitted, the receiver (DS1307) will
now send out a LOW to acknowledge the transfer.
5. The master reads the SDA pin for a LOW.
6. The master sends out the address of $07 to the DS1307 and
receives back an acknowledge.
7. The master sends out the data, $10, to the DS1307 and receives
back an acknowledge. The DS1307 writes $10 to address $07.
8. Finally, a stop transfer is sent to the DS1307 to complete the
transaction.
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Application Note
DS1307 Software Interface
DS1307 Software Interface
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Memory Map
The DS1307’s memory map is shown in Figure 7. The real-time clock
registers are located in address locations $00 to $07. The 56 bytes of
non-volatile RAM are located in address locations $08 to $3F. During
multibyte addresses, the address pointer wraps around to $00 after it
reaches $3F.
$00
$07
$08
SECONDS
MINUTES
HOURS
DAY
DATE
MONTH
YEAR
CONTROL
RAM
56X8
$3F
Figure 7. DS1307 Memory Map
Register Map
The real-time clock registers are shown in detail in Figure 8. The time
and calendar are set by writing to the appropriate registers. The
information is in binary coded decimal (BCD) format.
To enable the processor, write a 0 to the CLOCK HALT bit in register
$00. The DS1307 is shipped with this bit set to 1.
Either 12-hour or 24-hour clock format can be used. If bit 6 of register
$02 is a 0, the device is in 24-hour mode. Likewise, when bit 6 is a 1, the
device is in 12-hour mode. Bit 5 of address $02 is used for the second
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Application Note
10 hours when in 24-hour mode. When using 12-hour mode, bit 5 is a
1 for p.m. and a 0 for a.m.
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BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
$00 CLOCK
HALT
10 SECONDS
SECONDS
$01
X
10 MINUTES
MINUTES
$02
X
12
24
A/P
10 HR
10
HR
$03
X
X
X
X
$04
X
X
10 DATE
DATE
$05
X
X
10 MONTH
MONTH
$06
$07
HOURS
X
YEAR
10 YEAR
OUT
X
X
DAY
SQWE
X
X
RS1
RS0
Figure 8. DS1307 Register Map
Control Register
The control register is used to control the SQW/OUT pin.
OUT — Controls the output level of the SQW/OUT pin when SQWE = 0.
1 = SQW/OUT pin HIGH
0 = SQW/OUT pin LOW
SQWE — Enables the oscillator square wave on the SQW/OUT pin
1 = Square wave enabled
0 = Square wave disabled
RS — Square wave output frequency
•
RS1 = 0 and RS0 = 0 —> 1 Hz
•
RS1 = 0 and RS1 = 1 —> 4.096 kHz
•
RS1 = 1 and RS1 = 0 —> 8.192 kHz
•
RS1 = 1 and RS1 = 1 —> 32.768 kHz
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Application Note
DS1307 Software Interface
The first byte transmitted in a write to the DS1307 is its 7-bit identification
code followed by the R/W bit. For writes, this bit will be 0. The next byte
transmitted is the DS1307 address pointer. After this, bytes of data to be
written to the DS1307 RAM are transmitted. After each byte of data is
written, the address pointer is incremented. See Figure 9.
Data Write
Sequence
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START
DS1307 ADDRESSR/W
ADDRESS POINTER
ACK
1101000
0 ACK
XXXX,XXXX
DATA (N)
XXXX,XXXX
ACK
DATA (N+?)
XXXX,XXXX
ACK
STOP
Figure 9. Data Write Sequence
The first byte transmitted in a read from the DS1307 is its 7-bit
identification code followed by the R/W bit. For reads, this bit will be 1.
Then the DS1307 will begin transmitting data back to the master. As long
as the DS1307 receives clocks and acknowledgments, it keeps
transmitting data. The starting address is the previous address pointer
from the last write transaction. If needed, a write sequence with only an
address can be used to initialize the address pointer for reads.
Data Read
Sequence
NOTE:
Remember that for the last byte read, the master sends back a No ACK
to the DS1307.
DS1307 ADDRESS R/W
START
1101000
1 ACK
DATA (N)
XXXX,XXXX
DATA (N+?)
ACK
XXXX,XXXX
ACK STOP
Figure 10. Data Read Sequence
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Application Note
MC68HC705J1A Hardware Interface
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With only 20 pins, the J1A is one of the smallest members of the HC05
Family. It has a total of 1240 bytes of erasable programmable read-only
memory (EPROM) and includes 14 I/O (input/output) pins. The
schematic used for testing the J1A to DS1307 interface on the MMEVS
development system is shown in Figure 11. The pins used to drive the
DS1307 on the J1A are listed here also.
•
Port A, bit 0 — This I/O pin (SCL) is configured as an output to
drive the serial clock pin, SCL, of the DS1307.
•
Port A, bit 1 — This I/O pin (SDA) is used to transmit and receive
data on the SDA pin of the DS1307.
For further information on the HC705J1A, consult the MC68HC705J1A
Technical Databook (MC68HC705J1A/D).
EPSON #C-301R
32.768-kHZ XTAL
3-V BATTERY
+5 V
+5 V
DS1307
1
X1
VDD
8
2
X2 SQW/OUT
7
3
VBAT
SCL
6
4
GND
SDA
5
+5 V
4.7 kΩ
TP
4.7 kΩ
MMEVS
J1A INTERFACE
PA1
PA0
Figure 11. J1A-to DS1307 Interface Test Circuit
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Application Note
MC68HC705J1A Software Interface
MC68HC705J1A Software Interface
I/O driving or manipulation is the process of toggling I/O pins with
software instructions to create a certain hardware peripheral. The HC05
CPU provides special instructions specifically to manipulate single
I/O pins.
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Five subroutines were created to provide an easy application
programming interface (API). These routines are:
•
START_SER — Sends out a start condition on the bus
•
STOP_SER — Sends out a stop condition on the bus
•
TXD — The master takes the contents of AccA and transmits it
MSB first to the DS1307. The master also checks for
acknowledgement from the DS1307.
•
RXD — After the master addresses the DS1307 with its
identification code and the read bit, the DS1307 transmits a byte
of data back to the master. This routine reads that byte and puts it
into AccA. The master also generates an acknowledgment back to
the DS1307.
•
RXD_LAST — This routine is just like RXD but it is used for the
last byte read from the DS1307. It does not generate an
acknowledgment back to the DS1307.
The flowcharts for the DS1620 serial I/O drivers are shown in
Flowcharts for the Test Interface. These routines were written
especially for the DS1307 and may not be able to properly drive other
MCU peripherals with 2-wire serial buses.
A typical application would use the SQW/OUT pin on the DS1307. When
configuring this pin for a 1-Hz signal, feed the signal to the IRQ pin of an
MCU. An interrupt routine can be created to read the contents of the
DS1307 every time a 1-Hz signal hits the IRQ pin. This should take
minimal CPU bandwidth and provide the user an easy way to retrieve
time and date information.
The main test routine was written to verify the bus interface between the
DS1307 and the J1A. It writes a known date and time into the DS1307
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Application Note
and then reads it back out. The data read is put into a RAM buffer on the
HC05. When the emulator is stopped, read the contents of the HC05
RAM buffer to verify the transmission process.
The test routine sequence is shown in Figure 15. The assembly code for
the test routine is provided in the section titled Code Listing.
The sequence of tests is:
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1. Configure the device to turn on a 1-Hz signal on the SQW/OUT
pin.
a. Transmit a start condition.
b. Transmit the DS1307 code to write to the device of
%11010000.
c.
Transmit the control register address and then $10.
d. Transmit a stop condition.
2. Write start time.
a. Transmit a start condition.
b. Transmit the DS1307 code to write to the device of
%11010000.
c.
Transmit the starting address of $00, the seconds register.
d. Transmit Saturday, June 20, 1998, 4:30:00 p.m. (By writing a
0 to bit 7 of the seconds register, the crystal circuit has been
turned on.)
e. Transmit a stop condition.
3. Read time and date, store away to HC05 RAM buffer.
a. Transmit a start condition.
b. Transmit the DS1307 code to write to the device of
%11010000.
c.
Transmit the starting address of $00.
d. Transmit a stop condition.
e. Transmit a start condition.
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Development Tools
f.
Transmit the DS1307 code to read from the device of
%11010001.
g. Read the date and time and store away to HC05 RAM.
h. Transmit a stop condition.
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Since the real-time clock is running, you can restart the code at step 3
and verify that it is keeping time.
This routine demonstrates the interface software needed to
communicate with the DS1307. Although the J1A was used, any HC05
device could utilize this interface code. Minor adjustments of port pins
and memory maps might be necessary.
Development Tools
The interface was created and tested using these development tools:
•
M68MMPFB0508 — Freescale MMEVS platform board
•
X68EM05J1A — Freescale J1A emulation module
•
Win IDE Version 1.02 — Editor, assembler, and debugger by
P&E Microcomputer Systems
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Flowcharts for the Test Interface
START_SER
TAKE SDA LOW
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TAKE SCL LOW
RETURN FROM SUB
STOP_SER
TAKE SCL HIGH
TAKE SDA HIGH
RETURN FROM SUB
Figure 12. START_SER and STOP_SER Subroutines
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Flowcharts for the Test Interface
TXD
SET X = 8 AS A COUNTER
A
LEFT SHIFT ACCA, CARRY = MSB
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YES
MAKE SDA AN INPUT
NO
CARRY = 1?
SET SDA = 1
SCL = 1
SDA PIN = 0?
SET SDA = 0
YES
SLAVE SENT ACK
TOGGLE CLOCK
SCL = 1
SCL = 0
SCL = 0
DECREMENT X
MAKE SDA AN OUTPUT
X = 0?, LOOP DONE?
NO ACK
RETURN FROM SUB
NO
YES
A
NO ACK ERROR LOOP
Figure 13. TXD Subroutine
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RXD/RXD_LAST
MAKE SDA AN INPUT
SET X = 8 AS A COUNTER
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SCL=1
SDA PIN = 0?
CARRY BIT = SDA
YES
NO
ROTATE LEFT ACCA
PUTS CARRY BIT INTO ACCA MSB
SCL = 0
DECREMENT X
NO
X = 0?
YES, RECEIVED 8-BIT DATA
MAKE SDA AN OUTPUT
SDA = 0
RXD — ACK WITH SDA = 0
RXD_LAST — NO ACK WITH SDA = 1
TOGGLE CLOCK
SCL=1
SCL=0
RETURN FROM SUB
Figure 14. RXD/RXD_LAST Subroutines
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Flowcharts for the Test Interface
START
Config CONTROL reg
Transmit START_SER
TXD DS1307_WRITE
TXD CONTROL
TXD $10
Transmit STOP_SER
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Write Start Time
Transmit START_SER
TXD DS1307_WRITE
TXD SECONDS
TXD START_SECONDS
TXD START_MINUTES
TXD START_HOURS
TXD START_DAY
TXD START_DATE
TXD START_MONTH
TXD START_YEAR
Transmit STOP_SER
Read Time, store to HC05 RAM
Transmit START_SER
TXD DS1307_WRITE
TXD SECONDS
Transmit SER_STOP
Transmit START_SER
TXD DS1307
RXD store to BUF_SECONDS
RXD store to BUF_MINUTES
RXD store to BUF_HOURS
RXD store to BUF_DAY
RXD store to BUF_DATE
RXD store to BUF_MONTH
RXD_LAST store to BUF_YEAR
Transmit SER_STOP
Infinite Loop
Figure 15. Flowchart for Main Test Routine
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Application Note
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Code Listing
************************************************************************************
*
* File name: DS1307.ASM
* Example Code for the MC68HC705J1A Interface to the
*
Dallas DS1307 Serial Real Time Clock
* Ver: 1.0
* Date: June 1, 1998
* Author: Mark Glenewinkel
*
Freescale Field Applications
*
Consumer Systems Group
* Assembler: P&E IDE ver 1.02
*
* For code explanation and flow charts, please consult Freescale Application Note
*
"Add a Non-volatile Clock to the MC68HC705J1A" Literature # AN1759/D
*
************************************************************************************
*** SYSTEM DEFINITIONS AND EQUATES **************************************************
*** Internal Register Definitions
PORTA
EQU
$00
;PortA
DDRA
EQU
$04
;data direction for PortA
*** Application
SER_PORT
SCL
SDA
Specific Definitions
EQU
$00
EQU
0T
EQU
1T
;PORTA is SER_PORT
;PORTA, bit 0, clock signal
;PORTA, bit 1, data signal
DS1307_WRITE
DS1307_READ
SECONDS
MINUTES
HOURS
DAY
DATE
MONTH
YEAR
CONTROL
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
;addresses the DS1307 for write
;addresses the DS1307 for read
;DS1307 address for seconds
;DS1307 address for minutes
;DS1307 address for hours
;DS1307 address for the day
;DS1307 address for the date
;DS1307 address for the month
;DS1307 address for the year
;DS1307 address for control
$D0
$D1
$00
$01
$02
$03
$04
$05
$06
$07
*** Memory Definitions
EPROM
EQU
$300
RAM
EQU
$C0
RESET
EQU
$7FE
;start of EPROM mem
;start of RAM mem
;vector for reset
*** Time Start Definitions for test
*** Start on Saturday, June 20th, 1998, 4:30:00 PM
START_SECONDS
EQU
$00
;0 seconds
START_MINUTES
EQU
$30
;30 minutes
START_HOURS
EQU
$64
;4 hours, PM, 12 Hour mode
START_DAY
EQU
$06
;Saturday
START_DATE
EQU
$20
;20th
START_MONTH
EQU
$06
;June
START_YEAR
EQU
$98
;1998
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Application Note
Code Listing
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*** RAM VARIABLES ******************************************************************
* Buffer for test reading data from the DS1307
ORG
RAM
BUF_SECONDS
DB
1
;buffer on HC05 for seconds
BUF_MINUTES
DB
1
;buffer on HC05 for hours
BUF_DAY
DB
1
;buffer on HC05 for the day
BUF_DATE
DB
1
;buffer on HC05 for the date
BUF_MONTH
DB
1
;buffer on HC05 for the month
BUF_YEAR
DB
1
;buffer on HC05 for the year
*** MAIN ROUTINE *******************************************************************
ORG
EPROM
;start at begining of EPROM
*** Intialize Ports
START
lda
#$03
;init SER_PORT
sta
SER_PORT
lda
#$03
;make SER_PORT pins outputs
sta
DDRA
*** DS1307 configuration
*** Turn on osc, turn on SQW/OUT pin with 1 Hz signal
jsr
START_SER
;start serial transmission
lda
jsr
lda
jsr
lda
jsr
#DS1307_WRITE
TXD
#CONTROL
TXD
#$10
TXD
;send address of control reg
jsr
STOP_SER
;stop serial transmission
*** Write Starting Time to DS1307
jsr
START_SER
lda
jsr
lda
jsr
lda
jsr
lda
jsr
lda
jsr
lda
jsr
lda
jsr
lda
jsr
lda
jsr
#DS1307_WRITE
TXD
#SECONDS
TXD
#START_SECONDS
TXD
#START_MINUTES
TXD
#START_HOURS
TXD
#START_DAY
TXD
#START_DATE
TXD
#START_MONTH
TXD
#START_YEAR
TXD
jsr
STOP_SER
;address the DS1307 device, write
;send config data
;start serial transmission
;address the DS1307 device, write
;start address of DS1307
;write seconds
;write minutes
;write hours
;write day
;write date
;write month
;write year
;stop serial transmission
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Application Note
*** Read Time, store away in HC05 time buffer for verification
* Write starting address
jsr
START_SER
;start serial transmission
lda
jsr
lda
jsr
#DS1307_WRITE
TXD
#SECONDS
TXD
;start address of DS1307 read
jsr
STOP_SER
;stop serial transmission
Freescale Semiconductor, Inc...
* Read Time data put in HC05 buffer
jsr
START_SER
DUMMY
;address the DS1307 device, write
;start serial transmission
lda
jsr
jsr
sta
jsr
sta
jsr
sta
jsr
sta
jsr
sta
jsr
sta
jsr
sta
#DS1307_READ
TXD
RXD
BUF_SECOND
RXD
BUF_MINUTES
RXD
BUF_HOURS
RXD
BUF_DAY
RXD
BUF_DATE
RXD
BUF_MONTH
RXD_LAST
BUF_YEAR
;address the DS1307 device, read
jsr
STOP_SER
;stop serial transmission
bra
DUMMY
;test sequence is over
;read seconds, store to buffer
;read minutes, store to buffer
;read hours, store to buffer
;read the day, store to buffer
;read the date, store to buffer
;read the month, store to buffer
;read the year, store to buffer
*** SUBROUTINES ********************************************************************
*** Sends out Start command on bus
START_SER
bclr
SDA,SER_PORT
;SDA=0
bclr
SCL,SER_PORT
;SCL=0
rts
*** Sends out Stop command on bus
STOP_SER
bset
SCL,SER_PORT
bset
SDA,SER_PORT
rts
;SCL=1
;SDA=1
*** Routine takes contents of AccA and transmits it serially to
*** the DS1307, MSB first
*** Looks for ACK, goes to ERROR routine if no ACK
TXD
ldx
#8T
;set counter
WRITE
J1
asla
bcc
bset
bra
bclr
brn
;Carry bit = MSB
J1
SDA,SER_PORT
CLOCK_IT
SDA,SER_PORT
J1
;SDA=1
;branch to clock_it
;SDA=0
;evens it out
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Freescale Semiconductor, Inc.
Application Note
Code Listing
Freescale Semiconductor, Inc...
CLOCK_IT
bset
bclr
decx
bne
* Check for ACK
bclr
bset
brclr
SCL,SER_PORT
SCL,SER_PORT
;SCL=1
;SCL=0
;decrement counter
SDA,DDRA
SCL,SER_PORT
SDA,SER_PORT,J2
;SDA is input
;SCL=1
;if SDA=0, slave ACK
ACK_ERROR
bra
ACK_ERROR
;no slave ACK, error loop
J2
bclr
bset
rts
SCL,SER_PORT
SDA,DDRA
;SCL=0
;SDA is output
;return from sub
WRITE
*** Routine clocks the
*** 8 bit contents are
*** Generates ACK back
RXD
bclr
ldx
DS1307 to read data from SDA, MSB first
put in AccA
to slave
SDA,DDRA
;make the SDA pin on J1A input
#8T
;set counter
READ
SCL,SER_PORT
SDA,SER_PORT,J3
J3
bset
brclr
rola
bclr
decx
bne
* ACK back to slave
bset
bclr
bset
bclr
rts
SCL,SER_PORT
;SCL=1
;carry bit = SDA
;put carry bit into AccA MSB
;SCL=0
;decrement counter
READ
SDA,DDRA
SDA,SER_PORT
SCL,SER_PORT
SCL,SER_PORT
;make the SDA pin on J1A output
;SDA=0
;SCL=1
;SCL=0
;return from sub
*** Routine clocks the DS1307 to read data from SDA, MSB first
*** 8 bit contents are put in AccA
*** Generates NO ACK back to slave, signals last read to DS1307
RXD_LAST
bclr
SDA,DDRA
;make the SDA pin on J1A input
ldx
#8T
;set counter
READ_LAST
J4
bset
brclr
rola
bclr
decx
bne
* NO ACK back to slave
bset
bset
bset
bclr
rts
SCL,SER_PORT
SDA,SER_PORT,J4
SCL,SER_PORT
;SCL=1
;carry bit = SDA
;put carry bit into AccA MSB
;SCL=0
;decrement counter
READ_LAST
SDA,DDRA
SDA,SER_PORT
SCL,SER_PORT
SCL,SER_PORT
;make the SDA pin on J1A output
;SDA=1
;SCL=1
;SCL=0
;return from sub
*** VECTOR TABLE *******************************************************************
ORG
RESET
DW
START
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R E Q U I R E D
Application Note
References
MC68HC705J1A Technical Data, Freescale document order number
MC68HC705J1A/D, 1996.
M68HC05 Applications Guide, Freescale document order number
M68HC05AG/AD, 1996.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
DS1307 Datasheet, Dallas Semiconductor, 1997.
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