Cypress CY7C1059DV33-10ZSXI 8-mbit (1m x 8) static ram Datasheet

PRELIMINARY
CY7C1059DV33
8-Mbit (1M x 8) Static RAM
Functional Description[1]
Features
• High speed
— tAA = 10 ns
The CY7C1059DV33 is a high-performance CMOS Static
RAM organized as 1M words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A19).
• Low active power
— ICC = 110 mA
• Low CMOS standby power
— ISB2 = 20 mA
• 2.0V data retention
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in lead-free 36-ball FBGA and 44-pin TSOP II
ZS44 packages
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1059DV33 is available in 36-ball FBGA and 44-pin
TSOP II package with center power and ground (revolutionary)
pinout.
Logic Block Diagram
I/O 0
BUFFER
I/O 1
I/O 2
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
ROW DECODER
INPUT
1M x 8
ARRAY
I/O 3
I/O 4
I/O 5
I/O 6
POWER
DOWN
COLUMN
DECODER
CE
I/O 7
A19
OE
A11
A12
A13
A14
A15
A16
A17
A18
WE
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-00061 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 21, 2006
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CY7C1059DV33
PRELIMINARY
Pin Configuration
36-ball FBGA
(Top View)
1
2
3
4
5
TSOP II
Top View
6
A0
A1
NC
A3
A6
A8
A
I/O4
A2
WE
A4
A7
I/O0
B
A19
A5
I/O1
C
I/O5
VSS
VCC
D
VCC
VSS
E
I/O6
A18
A17
I/O2
F
I/O7
OE
CE
A16
A15
I/O3
G
A9
A10
A11
A12
A13
A14
H
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
A19
NC
NC
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Document #: 001-00061 Rev. *B
–10
10
110
20
Unit
ns
mA
mA
Page 2 of 9
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CY7C1059DV33
PRELIMINARY
DC Input Voltage[2] ................................ –0.3V to VCC + 0.3V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............. ...............................>2001V
Storage Temperature ................................. –65°C to +150°C
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Latch-up Current...................................................... >200 mA
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V
Operating Range
DC Voltage Applied to Outputs
in High-Z State[2] ....................................–0.3V to VCC + 0.3V
Range
Ambient Temperature
VCC
–40°C to +85°C
3.3V ± 0.3V
Industrial
Electrical Characteristics Over the Operating Range
–10
Parameter
Description
Test Conditions
Min.
Max.
Unit
0.4
V
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
2.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
VIL
Input LOW Voltage[2]
–0.3
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
µA
IOZ
Output Leakage Current
GND < VOUT < VCC, Output Disabled
–1
+1
µA
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX = 1/tRC
100 MHz
110
mA
83 MHz
100
66 MHz
90
40 MHz
80
ISB1
Automatic CE Power-down Max. VCC, CE > VIH VIN > VIH
Current —TTL Inputs
or VIN < VIL, f = fMAX
40
mA
ISB2
Automatic CE Power-down Max. VCC, CE > VCC – 0.3V,
Current —CMOS Inputs
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
20
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz,
VCC = 3.3V
16
pF
16
pF
Thermal Resistance[3]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
FBGA
TSOP II
Unit
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
TBD
TBD
°C/W
TBD
TBD
°C/W
Notes:
2. VIL (min.) = –2.0V and VIH (max.) = VCC + 2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-00061 Rev. *B
Page 3 of 9
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CY7C1059DV33
PRELIMINARY
AC Test Loads and Waveforms[4]
Z = 50Ω
ALL INPUT PULSES
3.0V
OUTPUT
90%
50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
90%
10%
10%
GND
1.5V
High-Z characteristics:
(b)
Rise Time: 1 V/ns
(a)
Fall Time: 1 V/ns
R 317Ω
3.3V
OUTPUT
R2
351Ω
5 pF
(c)
AC Switching
Characteristics[5]
Over the Operating Range
–10
Parameter
Description
Min.
Max.
Unit
Read Cycle
tpower[6]
VCC(typical) to the first access
100
µs
tRC
Read Cycle Time
10
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[7, 8]
Low-Z[8]
tLZCE
CE LOW to
tHZCE
CE HIGH to High-Z[7, 8]
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
10
3
ns
ns
10
5
0
ns
ns
ns
5
ns
5
ns
10
ns
3
ns
0
ns
Write Cycle[9, 10]
tWC
Write Cycle Time
10
ns
tSCE
CE LOW to Write End
7
ns
tAW
Address Set-up to Write End
7
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
7
ns
tSD
Data Set-up to Write End
5
ns
tHD
Data Hold from Write End
0
ns
Low-Z[8]
tLZWE
WE HIGH to
tHZWE
WE LOW to High-Z[7, 8]
3
ns
5
ns
Notes:
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of
these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-00061 Rev. *B
Page 4 of 9
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CY7C1059DV33
PRELIMINARY
Data Retention Characteristics Over the Operating Range
Parameter
Conditions[11]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[3]
Chip Deselect to Data Retention Time
tR[12]
Operation Recovery Time
Min.
Max.
2.0
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
Unit
V
20
mA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
3.0V
VDR > 2V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[13, 14]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tHZCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
ICC
50%
ISB
Notes:
11. No inputs may exceed VCC + 0.3V
12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document #: 001-00061 Rev. *B
Page 5 of 9
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CY7C1059DV33
PRELIMINARY
Switching Waveforms(continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[16, 17]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 18
tHZOE
Write Cycle No. 2 (WE Controlled, OE LOW)[17]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 18
tHD
DATA VALID
tHZWE
tLZWE
Notes:
16. Data I/O is high-impedance if OE = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-00061 Rev. *B
Page 6 of 9
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CY7C1059DV33
PRELIMINARY
Truth Table
CE
H
OE
X
WE
X
I/O0–I/O7
High-Z
Mode
Power-down
Power
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
Ordering Code
Package
Diagram
Operating
Range
Package Type
CY7C1059DV33-10BAXI
51-85105
36-ball FBGA (Pb-Free)
CY7C1059DV33-10ZSXI
51-85087
44-pin TSOP II (Pb-Free)
Industrial
Please contact your local Cypress sales representative for availability of these parts.
Package Diagrams
36-Ball FBGA (7.00 mm x 8.5 mm x 1.2 mm) (51-85105)
51-85105-*D
Document #: 001-00061 Rev. *B
Page 7 of 9
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PRELIMINARY
CY7C1059DV33
Package Diagrams (continued)
44-pin TSOP II (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-00061 Rev. *B
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
CY7C1059DV33
Document History Page
Document Title: CY7C1059DV33 8-Mbit (1M x 8) Static RAM
Document Number: 001-00061
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
342195
See ECN
PCI
New Data Sheet
*A
380574
See ECN
SYT
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8,
10 and 12 ns speed bins respectively
ICC (Ind’l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8,
10 and 12 ns speed bins respectively
Changed the Capacitance values from 8 pF to 10 pF on Page # 3
*B
485796
See ECN
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed -8 and -12 Speed bins from product offering,
Removed Commercial Operating Range option,
Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and
VCC + 0.5V to VCC + 0.3V
Updated footnote #7 on High-Z parameter measurement
Added footnote #11
Changed the Description of IIX from Input Load Current to
Input Leakage Current.
Updated the Ordering Information table and Replaced Package Name column
with Package Diagram.
Document #: 001-00061 Rev. *B
Page 9 of 9
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