[ /Title (CD74 HC390 , CD74 HCT39 0) /Subject (High Speed CMOS CD74HC390, CD54HCT390, CD74HCT390 Data sheet acquired from Harris Semiconductor SCHS185C High-Speed CMOS Logic Dual Decade Ripple Counter September 1997 - Revised October 2003 Features Description • Two BCD Decade or Bi-Quinary Counters The CD74HC390 and ’HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and are pin compatible with low-power Schottky TTL (LSTTL). These devices are divided into four separately clocked sections. The counters have two divide-by-2 sections and two divideby-5 sections. These sections are normally used in a BCD decade or bi-quinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the High-to-Low transition of the input pulses (nCP0 and nCP1). • One Package Can Be Configured to Divide-by-2, 4, 5,10, 20, 25, 50 or 100 • Two Master Reset Inputs to Clear Each Decade Counter Individually • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide-by-5 section. For bi-quinary decade operation, the nO3 output is connected to the nCP0 input and nQ0 becomes the decade output. • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V The master reset inputs (1MR and 2MR) are active-High asynchronous inputs to each decade counter which operates on the portion of the counter identified by the “1” and “2” prefixes in the pin configuration. A High level on the nMR input overrides the clock and sets the four outputs Low. • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Ordering Information TEMP. RANGE (oC) PACKAGE CD54HCT390F3A -55 to 125 16 Ld CERDIP CD74HC390E -55 to 125 16 Ld PDIP CD74HC390M -55 to 125 16 Ld SOIC CD74HC390MT -55 to 125 16 Ld SOIC CD74HC390M96 -55 to 125 16 Ld SOIC PART NUMBER Pinout CD54HCT390 (CERDIP) CD74HC390, CD74HCT390 (PDIP, SOIC) TOP VIEW 1CP0 1 16 VCC 1MR 2 15 2CP0 1Q0 3 14 2MR CD74HCT390E -55 to 125 16 Ld PDIP 1CP1 4 13 2Q0 CD74HCT390M -55 to 125 16 Ld SOIC CD74HCT390MT -55 to 125 16 Ld SOIC CD74HCT390M96 -55 to 125 16 Ld SOIC 1Q1 5 12 2CP1 1Q2 6 11 2Q1 1Q3 7 10 2Q2 GND 8 9 2Q3 NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD74HC390, CD54HCT390, CD74HCT390 Functional Diagram 1 (15) nCP0 2 (14) nMR 3 (13) nQ0 ÷2 COUNTER 5 (11) 4 (12) nCP1 ÷5 6 (10) COUNTER 7 (9) nQ1 nQ2 nQ3 GND = 8 VCC = 16 TRUTH TABLE INPUTS CP MR ACTION ↑ L No Change ↓ L Count X H All Qs Low H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low. B-QUINARY COUNT SEQUENCE FOR 1/2 THE 390 BCD COUNT SEQUENCE FOR 1/2 THE 390 OUTPUTS OUTPUTS COUNT Q0 Q1 Q2 Q3 COUNT Q0 Q1 Q2 Q3 0 L L L L 0 L L L L 1 H L L L 1 L H L L 2 L H L L 2 L L H L 3 H H L L 3 L H H L 4 L L H L 4 L L L H 5 H L H L 5 H L L L 6 L H H L 6 H H H L 7 H H H L 7 H L H L 8 L L L H 8 H H H L 9 H L L H 9 H L L H Output nQ3 connected to nCP0 with counter input on nCP1. Output nQ0 connected to nCP1 with counter input on nCP0. 2 CD74HC390, CD54HCT390, CD74HCT390 Logic Diagram 4(12) nCP1 Q 1(15) nCP0 2(14) nMR Q Φ Q Φ R Q Φ R Φ R R VCC = 16 GND = 8 3(13) nQ0 5(11) nQ1 3 6(10) nQ2 7(9) nQ3 CD74HC390, CD54HCT390, CD74HCT390 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 4 CD74HC390, CD54HCT390, CD74HCT390 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS nCP0 0.45 nCP1, MR 0.6 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Prerequisite for Switching Specifications 25oC CHARACTERISTIC -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS fMAX 2 6 - - 5 - 4 - MHz 4.5 30 - - 24 - 20 - MHz 6 35 - - 28 - 24 - MHz 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns HC TYPES Maximum Clock Frequency Clock Pulse Width, nCP0, nCP1 tW 5 CD74HC390, CD54HCT390, CD74HCT390 Prerequisite for Switching Specifications (Continued) 25oC CHARACTERISTIC Reset Removal Time Reset Pulse Width -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tREM 2 70 - - 90 - 105 - ns 4.5 14 - - 18 - 21 - ns 6 12 - - 15 - 18 - ns 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns fMAX 4.5 27 - - 22 - 18 - MHz tW 4.5 19 - - 24 - 29 - ns tREM 4.5 15 - - 19 - 22 - ns tW 4.5 13 - - 16 - 20 - ns tW HCT TYPES Maximum Clock Frequency Clock Pulse Width, nCP0, nCP1 Reset Removal Time Reset Pulse Width Switching Specifications Input tr, tf = 6ns PARAMETER HC TYPES Propagation Delay (Figure 1) nCP0 to nQ0 nCP1 to nQ1 nCP1 to nQ2 nCP1 to nQ3 nCP0 to nQ3 (nQ0 connected to nCP1) MR to Qn TEST SYMBOL CONDITIONS tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns CL = 50pF 2 - - 185 - 230 - 280 ns 4.5 - - 37 - 46 - 56 ns 6 - - 31 - 39 - 48 ns 2 - - 245 - 305 - 370 ns 4.5 - - 49 - 61 - 74 ns 6 - - 42 - 52 - 63 ns 2 - - 180 - 225 - 270 ns 4.5 - - 36 - 45 - 54 ns 5 - 15 - - - - - ns 6 - - 31 - 38 - 46 ns 2 - - 365 - 455 - 550 ns 4.5 - - 73 - 91 - 110 ns 6 - - 62 - 77 - 94 ns 2 - - 190 - 240 - 285 ns 4.5 - - 38 - 48 - 57 ns CL =15pF 5 - 16 - - - - - ns CL = 50pF 6 - - 32 - 41 - 48 ns CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF 6 CD74HC390, CD54HCT390, CD74HCT390 Switching Specifications Input tr, tf = 6ns (Continued) TEST SYMBOL CONDITIONS PARAMETER Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD CL =15pF 5 - 28 - - - - - pF tPLH, tPHL CL = 50pF 4.5 - - 40 - 50 - 60 ns CL =15pF 5 - 17 - - - - - ns nCP1 to nQ1 tPLH, tPHL CL = 50pF 4.5 - - 43 - 51 - 65 ns nCP1 to nQ2 tPLH, tPHL CL = 50pF 4.5 - - 55 - 69 - 83 ns nCP1 to nQ3 tPLH, tPHL CL = 50pF 4.5 - - 42 - 53 - 63 ns CL =15pF 5 - 18 - - - - - ns HCT TYPES Propagation Delay (Figure 1) nCP0 to nQ0 nCP0 to nQ2 (nQ0 connected to nCP1) tPLH, tPHL CL = 50pF 4.5 - - 84 - 105 - 126 ns MR to Qn tPLH, tPHL CL = 50pF 4.5 - - 42 - 53 - 63 ns CL =15pF 5 - 18 - - - - - ns 4.5 - - 15 - 19 - 22 ns Output Transition tTLH, tTHL CL = 50pF Input Capacitance CIN CL =15pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD CL =15pF 5 - 32 - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per multiplexer. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 7 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9098401MEA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HCT390F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC390E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC390EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC390M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC390M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC390M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC390M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC390ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC390MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC390MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC390MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC390MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT390E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT390EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT390M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT390M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT390M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT390M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT390ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT390MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT390MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT390MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT390MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC390M96 D 16 SITE 27 330 16 6.5 10.3 2.1 8 16 Q1 CD74HCT390M96 D 16 SITE 27 330 16 6.5 10.3 2.1 8 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) CD74HC390M96 D 16 SITE 27 342.9 336.6 28.58 CD74HCT390M96 D 16 SITE 27 342.9 336.6 28.58 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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