ON MC33170 Rf amplifier companion chip for dual-band cellular subscriber terminal Datasheet

MC33170
RF Amplifier Companion Chip
for Dual-Band Cellular
Subscriber Terminal
The MC33170 is a complete solution for drain modulated
dual–band GSM 900MHz and DCS–1800MHz Power Amplifiers.
Thanks to its internal decoder, the MC33170 drastically simplifies the
interface between the PAs and the baseband logic section, providing
an immediate gain in part count but also in occupied copper area. The
device is also ready for 1V platforms since it accepts logic high control
signals down to 900mV@25°C.
A priority management system ensures the negative is present
before authorizing the power modulation, giving the necessary
ruggedness to the final design. This function can easily be disabled for
PAs not requiring a negative bias.
The device is able to directly drive an external P or N–channel with
the possibility to linearize the overall response via the internal
high–performance control amplifier and easily implement system
gain.
Finally, an LDO delivers a stable voltage, usable for external biasing
purposes.
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14
1
TSSOP–14
DTB SUFFIX
CASE 948G
PIN CONNECTIONS
•
•
•
•
•
14
Tx Enable
2
GSM-900
3
13 Negative
Regulator
12 Out
11 Vboost
DCS-1800 4
• 1V platform compatible: ON voltage = 900mV, OFF voltage =
300mV max
Priority management system prevents power modulation before
negative bias establishes
High performance 4.5MHz gain–bandwidth product operational
amplifier
Drives N or P–channel MOSFET
2.5V low–noise LDO
Idle mode input for very low power consumption (standby mode)
Common Enable
1
Band Selection
PA Start-up
5
10 INV
Gnd
6
9
NINV
Vbat
7
8
LDO
(Top View)
ORDERING INFORMATION
Device
MC33170DTB
Package
Shipping
TSSOP–14
96 Units / Rail
MC33170DTBR2 TSSOP–14 2500 / Tape & Reel
NINV
Vboost Vbat (5.5 V Max)
9
Shutdown
2.5 V
Low Dropout
2.5 V
11
7
6
12
Vbat
Shutdown
LDO
Output
Common
Enable
TX
Enable
Band
Selection
2.5 V
8
+
-
14
2
Open–Collector BG
Decoder
BD
1
B′G
1 mA
Continuous
3
GSM–900
 Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 1
4
700 mA
Peak
50 mA
Continuous
DCS–1800
1
NEGOK?
5
PA Start–Up
Clip
to –5 V
13
10
Negative INV
Regulator
Out
Publication Order Number:
MC33170/D
MC33170
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PIN DESCRIPTION
Pin No.
Pin Name
Function
Description
1
Band Selection
Selects the transmit band
A level high on this input selects the DCS chain. A zero selects the GSM
chain.
2
Tx Enable
Starts the power
A level high on this pin enables the DCS/GSM chain and establishes a
low–resistance link between pin 5 and 7
3
GSM–900
Biases the 900MHz section
When pin 1 is at zero and pin 2 goes high, the LDO voltage appears on
this pin (pin 14 is high)
4
DCS–1800
Biases the 1.8GHz section
When pin 1 is at one and pin 2 goes high, the LDO voltage appears on
this pin (pin 14 is high)
5
PA Start–up
Enables the PA power section
6
Gnd
The IC ground
7
Vbat
The IC power supply
8
LDO
Low DropOut regulator
This output requires a 100nF decoupling and is able to deliver up to
10mA continuous
9
NINV
Positive OPAMP input
The non–inverting OPAMP input
10
INV
Negative OPAMP input
The inverting OPAMP input
11
Vboost
Boost voltage from the PA
When pin 2 goes high, the battery voltage appears on this pin with a
700mA peak current capability (pin 14 is high)
The IC ground
This pin is wired to the battery terminal. A 100nF decoupling capacitor is
recommended, depending on the supply impedance
This pin connects to a boost voltage delivered by the RF PA. This boost
is necessary when driving an N–channel
12
Out
The OPAMP output
The output of the OPAMP/MOSFET driver pin
13
Negative Reg.
The PA negative clip
This pin clips the PA negative bias to —5V and prevents/authorizes the
modulation depending on its typical level :
<5.5V ––– 2.5V> OK
<1.3V ––– –3.5V> NOTOK
<–4.2V ––– –5V> OK
Max. clipping current is 5mA
14
Common Enable
Enables the whole IC
When high, this pin puts the IC in on–mode
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2
MC33170
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MAXIMUM RATINGS
Rating
Pin No.
Symbol
Value
MIN
Value
MAX
Units
Band selection
1
Vband
0
5.5
V
Tx Enable
2
TxEn
0
5.5
V
GSM–900
3
VGSM
–5
5.5
V
DCS–1800
4
VDCS
–5
5.5
V
PA Start–up
5
Vstartup
0
5.5
V
Vbat
7
Vbat
0
5.5
V
NINV
9
V+
0
5.5
V
INV
10
V–
0
5.5
V
Boost voltage
11
Vboost
0
12
V
Negative regulation pin
13
VZ
–5.4
5.5
V
Common Enable
14
CE
0
5.5
V
ESD capability, HBM model
All pins
2
kV
ESD capability, Machine model
All pins
200
V
GSM/DCS
PA startup
PA startup
1
50
700
mA
mA
mA
Maximum power dissipation
NW suffix, plastic package @Tj=25°C
NW suffix, plastic package @Tj=85°C
Thermal resistance Junction–to–Air
PD
PD
RJ–A
500
200
200
mW
mW
°C/W
Operating Ambient Temperature
Maximum Junction Temperature
Maximum Operating Junction Temperature
TA
Tjmax
Tj
–40 to +85
150
125
°C
°C
°C
Storage Temperature Range
TSTG
–60 to +150
°C
Steering Switch, continuous output current
Steering Switch, continuous output current
Steering Switch, peak output current < 1µs
3–4
5
5
Note1: The control pins, CE, TxEn and Bands shall never exceed Vcc + 0.3V
Note2: A 100nF decoupling capacitor is recommended between the IC Vcc and ground
Note3: To avoid any damage to the IC, the following sequence must be secured:
CE goes up then Tx goes up ––––> modulation startup
TX goes down then CE goes down ––––> modulation stop
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3
MC33170
ELECTRICAL CHARACTERISTICS
Characteristic
Pin #
Symbol
Min
Typ
Max
Unit
3.6
5.5
V
INPUT SPECIFICATIONS
(For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, Max TJ = 125°C unless otherwise noted)
7
Input voltage range
Vbat
2.7
Quiescent Current (ON mode)
1 band operating, no load, Vneg. Reg.= –4.2V, VCE = 900mV
IQON
1.0
3.0
mA
Standby current (OFF mode)
CE pin at low level, Vbat = 5.5V, VNEG and Vboost open
IQOFF
1.0
10
µA
LOGIC CONTROL SPECIFICATIONS
Logic Levels (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, Max TJ = 125°C unless otherwise noted)
Logic Level zero
Band Selection, Common Enable, TxEn
1–2
14
OFF
Logic Level one
Band Selection, Common Enable, TxEn
1–2
14
ON
300
mV
900
mV
Timings (TA = 25°C)
µs
4.0
Transmission Enable, device already ON
10% of TxEn to 90% of Vbat on PA start–up pin
VOLTAGE REGULATOR SPECIFICATIONS
Option section (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, Max TJ = 125°C unless otherwise noted)
Output voltage
8
Output current
8
IregOUT
Short circuit current (Vout = Vnominal – 300mV)
8
IregSHORT
Line regulation
Vin = Vout + 1V to 5.5V, device is ON 10mA load on pin 8, 100nF
VregOUT
2.45
2.5
2.55
V
10
mA
20
7–8
mA
µV
400
Dropout voltage at Iout = 10mA
8
VregDROP
150
mV
Output capacitor
8
CregOUT
100
nF
Ripple rejection
F = 1kHz, Vin = Vout + 1V, Iout = 1mA, Cout = 100nF
8
PSRR
RMS Noise voltage
Iout = 1mA, Cout = 100nF, <20Hz — 200kHz>
8
Noise density @ 1kHz
Iout = 1mA, Cout = 100nF
8
Dynamic parameters (TA = 25°C)
Rise time : 10% of CE to 90% of VregOUT
en
14–8
–70
dB
100
µV
330
nV/Hz
5.0
µs
CONTROL AMPLIFIER SPECIFICATIONS
(For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, Max TJ = 125°C unless otherwise noted)
Continuous current
12
ICONT
2.0
mA
Peak current (sink and source)
12
IPEAK
10
mA
Quiescent current entering pin 11 at 8V
Device is in ON state and no load on pin 12
12
IQON
1.0
mA
IIB
600
nA
AVOL
60
dB
GBW
5.5
MHz
Input bias current, V+ = V– = 2V
Open–loop voltage gain, TA = 25°C
Gain Bandwidth Product measured at 100kHz
Output voltage levels, Vnegreg=–5V
Level high : Isource = 1mA
Level low : Isink = 1mA
12
V
VOH
VOL
Input offset voltage
9–10
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4
7.75
0.25
10
mV
MC33170
Characteristic
Pin #
Symbol
Min
Typ
Max
Unit
–4.2
V
PROTECTION AND STABILIZATION CIRCUIT
(For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, Max TJ = 125°C unless otherwise noted)
Negative bias present
12
No Negative protection disabled
12
2.5
Regulation level
12
–5.4
Sink current
12
V
–5.0
–4.6
V
5.0
MA
60
160
STEERING SWITCHES, SERIES RESISTANCE
(For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, Max TJ = 125°C unless otherwise noted)
GSM–900 @ Id = 1mA, Vbat = 5.5V
3
DCS–1800 @ Id = 1mA, Vbat = 5.5V
4
60
160
Power Amplifier Startup @ Id = 50mA, Vbat = 5.5V
5
1.0
2.0
Lack of negative circuitry behavior:
The MC33170 hosts a circuitry that prevents the power
modulation startup if the negative bias is not established.
However, to accommodate with PAs that do make use of a
negative bias, it is possible to connect pin 13 to pin 7 and thus
invalidate the protection circuitry. The below sketch details
the available levels to fulfil this function
Vpin 13
OK
2.5V
0V
NOT OK
–4.2V
OK
–5V
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MC33170 operating truth table, pin levels:
TxEN
Band Selection
Common Enable
GSM–900
DCS–1800
PA startup
X
X
0
High–impedance
High–impedance
High–impedance
0
X
1
High–impedance
High–impedance
High–impedance
1
0
1
VLDO–Io.RDS(ON)
High–impedance
VBAT–Io.RDS(ON)
1
1
1
High–impedance
VLDO–Io.RDS(ON)
VBAT–Io.RDS(ON)
Io is the current delivered by the considered pin, RDS(ON) is the switch series resistance as defined in the section Steering
Switches
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MC33170
TYPICAL OPERATING CHARACTERISTICS
2.502
900
800
700
600
BAND
500
400
2.498
TxEn
Vout (V)
LOGIC LEVEL (mV)
ILDOout = 5mA
2.500
CE
300
ILDOout = 10mA
2.496
2.494
2.492
200
2.490
100
0
-40
-20
20
0
40
80
60
100
120
2.488
-50
140
150
Figure 2. LDO Voltage Output Variation with
Temperature
140
2.55
120
2.53
Dropout = 10mA
100
DROPOUT (mV)
LDO OUTPUT VOLTAGE (V)
100
TEMPERATURE (°C)
Figure 1. TxEn, BAND, CE Logic Level with Temperature
2.51
2.49
VLDOout @ Vbat = 3.6V, 25°C
2.45
80
Dropout = 5mA
60
40
2.47
Dropout = 1mA
20
0
2
4
6
8
10
12
14
0
-40
16
-20
0
ILDOout (mA)
1400
2.0
1200
1.0
THRESHOLD (V)
3.0
1000
800
600
-4.0
40
60
100
120
140
80
100
120
-5.0
-40
140
Negative Neg-Reg Threshold
-2.0
200
20
80
-1.0
-3.0
0
60
0
400
-20
40
Figure 4. LDO Dropout versus ILDOout Current @ 25°C
1600
0
-40
20
TEMPERATURE (°C)
Figure 3. LDO Output Voltage versus LDO Output
Current @ 25°C
QUIESCENT CURRENT (nA)
50
0
TEMPERATURE (°C)
TEMPERATURE (°C)
Positive Neg-Reg Threshold
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 5. Quiescent Current versus Temperature
Figure 6. Neg–Reg Thresholds versus Temperature
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140
MC33170
-4.25
-4.94
-4.35
-4.96
-4.45
-4.98
NEG-REG CLAMP (V)
NEG-REG CLAMP VOLTAGE (V)
TYPICAL OPERATING CHARACTERISTICS (cont.)
-4.55
-4.65
-4.75
-4.85
-4.95
-5.00
-5.02
-5.04
-5.06
-5.10
-5.15
-5.12
-5.25
0
4
2
6
8
NegReg Clamp @ 3mA
-5.08
-5.05
-5.14
-40
10
-20
0
20
INEG-REG (mA)
Figure 7. Clamp Voltage vs INeg–Reg Current @ 25°C
100
4.50
RISE TIME (µ s)
TRANSMISSION TIME (ns)
140
4.52
TxEn 0.9V
80
TxEn 5.5V
60
40
20
4.48
4.46
4.44
4.42
10
60
110
4.40
160
2
4
6
8
TEMPERATURE (°C)
10
12
14
ILDOout (mA)
Figure 9. Transmission Enable Propagation Delay
versus Temperature
Figure 10. LDO Rise Time versus Load @ 25°C
600
500
450
500
400
400
NVdson (mV)
GROUND CURRENT (µ A)
120
100
4.54
120
300
200
350
I load=50mA
300
250
200
I load=100mA
150
100
100
0
-40
80
Figure 8. NegReg Clamp @ 3mA versus Temperature
140
0
-40
60
40
TEMPERATURE (°C)
50
10
60
0
-40
160
110
TEMPERATURE (°C)
I load=300mA
-20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 11. Ground Current versus Temperature
Figure 12. PA Start up Vdson @ Vbat 3.6V
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7
120
140
MC33170
CHARACTERIZATION CURVES
Iout, 5mA/div
Vout, 10mV/div
TA = 25°C
Vout = 2.5V
X = 50ms/div
LDO’s output when banged from 0 to 10mA
Audio susceptibility measurement fixture
Measurement conditions:
Tx = CE = 1.0V, Vcc = 3.6V, NegOut = Vcc, Cbyp = 100nF
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MC33170
0
-10
-20
dB
-30
-40
-50
-60
-70
10mA
1mA
-80
-90
-50
50
0
100
150
FREQUENCY (Hz)
Input voltage rejection at Iout = 1mA and 10mA
Input audio susceptibility at Iout = 1mA/10mA
Gain/phase measurement fixture
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MC33170
180
50
135
Phase
45
30
20
Cout = 0
10
0
0
-45
Gain (dB)
90
40
Gain
-10
Phase
Operational amplifier AC measurements with:
Vcc = 3.6V, Tx = CE = 1.0V, Vboost = 8V,
Pin 12 loaded not loaded
-20
-90
-30
-135
-40
-180
10000
100000
1000000
10000000
-50
100000000
FREQUENCY (Hz)
MC33170 Bode plot
50
200
150
40
Gain
30
20
50
10
0
0
-50
-100
Cout = 1nF
-10
Phase
Operational amplifier AC measurements with:
Vcc = 3.6V, Tx = CE = 1.0V, Vboost = 8V,
Pin 12 loaded by 1nF
-20
-30
-150
-200
10000
Gain (dB)
Phase
100
-40
100000
1000000
10000000
-50
100000000
FREQUENCY (Hz)
MC33170 Bode plot
450
400
nV/sqrt Hz
350
300
LDO output noise measurement with:
Vcc = 3.6V, Tx = CE = 1.0V, Cout = 100nF, Iout = 1mA
Integrated noise:
20Hz – 200kHz = 100µVrms
20Hz – 1MHz = 170µVrms
250
200
150
100
50
0
100
1000
10000
100000
1000000
FREQUENCY (Hz)
Spectral noise density at Iout = 1mA
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MC33170
MC33170 application hints
The MC33170 represents a major leap toward
miniaturization and compactness of Power Amplifiers (PAs)
systems. Prior to talk about the 33170 application circuits,
let us review how a classical dual–band transmission chain
is implemented. At the beginning of the chain, the power
ramping signal is delivered by the Baseband’s Digital to
Analog Converter (DAC). Because of the digitization, a
natural discontinuity appears between the various steps the
signal is made of. As a matter of fact, this sharp transitions
create undesirable effects and need to be smoothed by an
external circuitry (figure 13).
DAC staircase
Filter action
Figure 13. DAC’s signal can be smoothed by an appropriate circuitry
this purpose. Unfortunately, to keep the quiescent power at
its minimum during the GSM/DCS time–frame pauses (e.g.
no power delivered), it is important to quickly remove the
bias from the PAs. Conversely, the LDO shall be fast enough
to bias the PAs at anytime, without hampering the overall
response time. Such a task is difficult for an off–the–shelf
regulator: a specific component has to be found.
Thanks to their innovative designs, ON Semiconductor
PAs, such as the aforementioned ones, do not require any
external negative sources. However, some synchronization
signals are needed to activate the internal circuitry and
provide them with a stable operating point. This is usually
done by using external low/high power switches.
Finally, a safety system needs to be implemented to
prevent the modulation start in case the negative bias is not
established.
Gathering all these information onto a final drawing gives
birth to figure 14.
The filtering action can be implemented in a various way,
but usually a 3rd order Bessel filter represents a good choice.
Actual solutions require the use of an external operational
amplifier (OPAMP) dedicated to this function.
For drain–controlled PAs, the power is directly dependent
upon the supply delivered to the device. Several methods
exist but the preferred one stays the N or P channel
modulation. In this application, the N–channel is wired in a
source–follower configuration and therefore needs an
external voltage to ensure its adequate enhancement. This
upper voltage can be obtained from a step–up converter or
directly from ON Semiconductor PAs, as with the
MRFIC0919 or MRFIC1819. To quickly charge/discharge
the MOSFET Ciss capacitor, a dedicated driver is needed,
with a voltage swing high enough to bias the N–channel
toward its specified RDSON.
Radio–Frequency PAs need stable bias levels to keep their
operating point at the right place, despite supply variations.
A Low DropOut (LDO) regulator is the obvious choice for
Vboost
Digital
Analog
Converter
Active
3rd Order
BESSEL Filter
MOSFET Driver
Level
Translation
Power Module
Vbat
LDO for
Bias Point
Shutdown
Shutdown
900 MHz
1.8 GHz
TX
Negative
Present?
Dual RF PA
Figure 14. Actual solution to drive a two–PA configuration
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MC33170
MC33170 as a Bessel filter
Thanks to its package, the MC33170 simplifies the
implementation of any filtering/driving configuration, e.g.
with either an N or P–channel MOSFET. Figure 15a details
the way to wire a 100kHz filter while driving an N–channel
MOSFET. In this application, a third order filter is achieved
by combining a first pole passive RC–filter, followed by a
second–order Sallen–Key complex pole–pair section.
Vboost
33 pF
Input
1k
19.88 k
+
-
10
680 pF
MC33170
OPAMP Section
11
9
108.4 k
Vbattery
12
MTSF3N02HD
6
22 pF
10 pF
100 k
100 k
To Power
Amplifier’s Drain
Figure 15a. Using the MC33170’s OPAMP to filter out the DAC discontinuities
through the feedback resistor (the 100k network in
figure 3) and forces the output to follow the input ramp.
With N–channels, it brings several benefits:
1. The input ramp does no longer deals with the MOSFET
threshold voltage which can introduce a certain amount of
delay in the response time.
2. At low powers, the distributions between the RDS(ON)
is automatically compensated.
With P–channels, the application does not need an
elevated voltage to ensure the channel enhancement but
maximizes the presence of the OPAMP to ensure a fully
linear chain.
As one can see, it is easy to select the desired gain value
via the 100k feedback resistors and accordingly tailor it to
the DAC output level. Figure 15a performs the filtering
function but also delivers the adequate sink/source current
to drive the MOSFET transistor. The two–component
section of figure 2 is reduced into a single one, saving cost
and PCB area. It also important to point out that the OPAMP
section can be totally disabled by the Common Enable pin.
Benefits of the closed loop configuration
One of the MC33170’s key applications is to make the
modulation section operating in a closed–loop
configuration. That is to say, the power chain is closed
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MC33170
1: input ramp
1: input ramp
2: output voltage
Rload = 220nF//5
2: output voltage
Rload = 220nF//5
Figure 15b. Going down with the 100kHz filter
Figure 15c. Going up with the 100kHz filter
The need of a fast regulator
Since the internal LDO controls the PA’s bias points, it is
important to quickly drive the regulator in order to ensure the
minimum consumption during the non–modulation phases.
A standard LDO has difficulties to react in less than 30µs.
This delay would be unacceptable in a system operating with
fast frames. The MC33170 internal LDO has be designed to
react within less than 10µs, ensuring a prompt bias
establishment. Figure 16 shows the way the bias voltage
takes place, without any overshoot.
1: Common Enable
Shot with 5µs per
division
2: LDO output
Rload = 220nF//1k
Figure 16. A fast LDO ensures an immediate bias availability
operating bias voltage to the PAs. With two distinct
switches, the MC33170 low–current switches control the
RF PA GSM 900MHz or DCS 1.8GHz. Once again, the
reaction time of these elements is optimized to ensure a fast
operation. Figure 17a depicts the typical signal variations.
Please note that the Tx pin is controlled via a logic 0 1 of 1V
ensuring the compatibility with 1V platforms.
The LDO requires a standard 100nF decoupling capacitor
to keep its output stable. The typical output noise stays
within 100µV from 100Hz to 100kHz.
High and low current switches
The MC33170 hosts two types of steering switch. The first
one only deals with low currents since it delivers the
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MC33170
1: Tx Enable
2: Start-up in
1: Tx Enable
Start-up current
68//220nF
500mA/div
2: GSM/DCS control pin
Figure 17a. Typical GSM/DCS pins response time
Figure 17b. Peak current capability of the power switch
Complete dual–band application
Figure 18 shows how implementing the MC33170 in a
complete dual–band application where a 100kHz filter is
combined with the MOSFET driver.
+ Battery
R9
19.88 k
R8
1k
Modulation
Ramp
Chip Enable
C6
680 pF
Band
Selection
1
TX Enable
2
CE 14
Band
TxEn Neg. Reg 13
3
GSM
Out 12
4
DCS
Vboost 11
5
PA Start
6
GND
NINV 9
7
Vbat
LDO 8
C8
33 pF
R10
108 k
M2
MTSF3N02HD
C9
10 pF
INV 10
R7
100 k
R6
100 k
MC33170
C5
100 nF
GSM
DCS
C7
22 pF
Zener
Start
Vboost
Power
Figure 18. A complete dual–band application with the MC33170
Application
The MC33170 has been designed to fulfill the
requirements of the new ON Semiconductor dual–band RF
amplifier, the MRFIC1859. For demonstration purposes, the
device was driven by the MC33170 in a simple gain two
configuration. The below picture shows how the power
signal drives the PA’s drain.
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MC33170
Gate Signal
Control Signal
Figure 19. The driving signal delivered by the MC33170 allows fully linear power modulation
GSM specifications
In order to meet the GSM specifications, the modulation
edges must be smoothed to fit into the spectral template.
This can be accomplished by implementing figure 18’s
Bessel filter and adjusting the cutoff frequency. Once the
edges are smoothed, the complete systems nicely fits into the
GSM template, as depicted by figure 20.
Figure 20. Thanks to its flexibility, the MC33170 helps reaching the GSM specs
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MC33170
PACKAGE DIMENSIONS
TSSOP–14
DTB SUFFIX
PLASTIC PACKAGE
CASE 948G–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
–U–
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
–V–
ÉÉ
ÇÇ
ÇÇ
ÉÉ
K1
J J1
SECTION N–N
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
D
G
H
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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MC33170/D