Freescale MKE02Z16VLC2 Operating characteristics : flash write voltage range: 2.7 to 5.5 v Datasheet

Freescale Semiconductor
Data Sheet: Technical Data
KE02 Sub-Family
Document Number MKE02P64M20SF0
Rev 3, 07/2013
MKE02P64M20SF0
Supports the following:
MKE02Z16VLC2(R),
MKE02Z32VLC2(R),
MKE02Z64VLC2(R),
MKE02Z16VLD2(R),
MKE02Z32VLD2(R),
MKE02Z64VLD2(R),
MKE02Z32VLH2(R),
MKE02Z64VLH2(R),
MKE02Z32VQH2(R), and
MKE02Z64VQH2(R)
Key features
• Operating characteristics
– Voltage range: 2.7 to 5.5 V
– Flash write voltage range: 2.7 to 5.5 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 20 MHz ARM® Cortex-M0+ core
– Single cycle 32-bit x 32-bit multiplier
– Single cycle I/O access port
• Memories and memory interfaces
– Up to 64 KB flash
– Up to 256 B EEPROM
– Up to 4 KB RAM
• Clocks
– Oscillator (OSC) - loop-controlled Pierce
oscillator, crystal or ceramic resonator range of
31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz
– Internal clock source (ICS) - internal FLL with
internal or external reference, precision
trimming of internal reference allowing 1%
deviation across temperature range of 0 °C to
70 °C and 1.5% deviation across temperature
range of -40 °C to 105 °C, up to 20 MHz
– Internal 1 kHz low-power oscillator (LPO)
• System peripherals
– Power management module (PMC) with three
power modes: Run, Wait, Stop
– Low-voltage detection (LVD) with reset or
interrupt, selectable trip points
– Watchdog with independent clock source
(WDOG)
– Programmable cyclic redundancy check module
(CRC)
– Serial wire debug interface (SWD)
– Bit manipulation engine (BME)
• Security and integrity modules
– 64-bit unique identification (ID) number per chip
• Human-machine interface
– Up to 57 general-purpose input/output (GPIO)
– Two 8-bit keyboard interrupt modules (KBI)
– Interrupt (IRQ)
• Analog modules
– One 16-channel 12-bit SAR ADC, operation in
Stop mode, optional hardware trigger (ADC)
– Two analog comparators containing a 6-bit
DAC and programmable reference input
(ACMP)
• Timers
– One 6-channel FlexTimer/PWM (FTM)
– Two 2-channel FlexTimer/PWM (FTM)
– One 2-channel periodic interrupt timer (PIT)
– One real-time clock (RTC)
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2013 Freescale Semiconductor, Inc.
• Communication interfaces
– Two SPI modules (SPI)
– Three UART modules (UART)
– One I2C module (I2C)
• Package options
– 64-pin QFP/LQFP
– 44-pin LQFP
– 32-pin LQFP
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
2
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................4
1.1 Determining valid orderable parts......................................4
2 Part identification......................................................................4
5.2.2
FTM module timing...............................................17
5.3 Thermal specifications.......................................................18
5.3.1
Thermal characteristics.........................................18
2.1 Description.........................................................................4
6 Peripheral operating requirements and behaviors....................19
2.2 Format...............................................................................4
6.1 Core modules....................................................................19
2.3 Fields.................................................................................4
6.1.1
SWD electricals ....................................................19
2.4 Example............................................................................5
6.2 External oscillator (OSC) and ICS characteristics.............20
3 Parameter classification............................................................5
6.3 NVM specifications............................................................22
4 Ratings......................................................................................6
6.4 Analog...............................................................................23
4.1 Thermal handling ratings...................................................6
6.4.1
ADC characteristics...............................................24
4.2 Moisture handling ratings..................................................6
6.4.2
Analog comparator (ACMP) electricals.................26
4.3 ESD handling ratings.........................................................6
4.4 Voltage and current operating ratings...............................6
6.5 Communication interfaces.................................................27
6.5.1
SPI switching specifications..................................27
5 General.....................................................................................7
7 Dimensions...............................................................................30
5.1 Nonswitching electrical specifications...............................7
7.1 Obtaining package dimensions.........................................30
5.1.1
DC characteristics.................................................7
5.1.2
Supply current characteristics...............................14
8.1 Signal multiplexing and pin assignments...........................31
5.1.3
EMC performance.................................................15
8.2 Device pin assignment......................................................33
5.2 Switching specifications.....................................................16
9 Revision history.........................................................................34
5.2.1
8 Pinout........................................................................................31
Control timing........................................................16
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
3
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: KE02Z.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q KE## A FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
KE##
Kinetis family
• KE02
A
Key attribute
• Z = M0+ core
FFF
Program flash memory size
R
Silicon revision
• M = Fully qualified, general market flow
• P = Prequalification
• 16 = 16 KB
• 32 = 32 KB
• 64 = 64 KB
• (Blank) = Main
• A = Revision after main
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
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Freescale Semiconductor, Inc.
Parameter classification
Field
Description
T
Temperature range (°C)
PP
Package identifier
CC
Maximum CPU frequency (MHz)
N
Packaging type
Values
• V = –40 to 105
•
•
•
•
LC = 32 LQFP (7 mm x 7 mm)
LD = 44 LQFP (10 mm x 10 mm)
QH = 64 QFP (14 mm x 14 mm)
LH = 64 LQFP (10 mm x 10 mm)
• 2 = 20 MHz
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MKE02Z64VQH2
3 Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods.
To give the customer a better understanding, the following classification is used and the
parameters are tagged accordingly in the tables where appropriate:
Table 1. Parameter classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant sample size
across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices under
typical conditions unless otherwise noted. All values shown in the typical column are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the
parameter tables where appropriate.
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
5
Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
1
VHBM
Electrostatic discharge voltage, human body model
–6000
+6000
V
VCDM
Electrostatic discharge voltage, charged-device model
–500
+500
V
Latch-up current at ambient temperature of 105°C
–100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
4.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in the following table may
affect device reliability or cause permanent damage to the device. For functional
operating conditions, refer to the remaining tables in this document.
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
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Freescale Semiconductor, Inc.
General
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate
logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor
associated with the pin is enabled.
Table 2. Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
–0.3
6.0
V
IDD
Maximum current into VDD
—
120
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
VDD + 0.3
V
VAIO
Analog1,
–0.3
VDD + 0.3
V
–25
25
mA
VDD – 0.3
VDD + 0.3
V
ID
VDDA
RESET, EXTAL, and XTAL input voltage
Instantaneous maximum current single pin limit (applies to all
port pins)
Analog supply voltage
1. Analog pins are defined as pins that do not have an associated general-purpose I/O port function.
5 General
5.1 Nonswitching electrical specifications
5.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin
characteristics.
Table 3. DC characteristics
Symbol
C
—
—
VOH
P
Descriptions
Operating voltage
Output high
voltage
P
C
Typical1
Max
Unit
2.7
—
5.5
V
All I/O pins, standard- 5 V, Iload = –
drive strength
5 mA
VDD – 0.8
—
—
V
3 V, Iload = –
2.5 mA
VDD – 0.8
—
—
V
5 V, Iload = –
20 mA
VDD – 0.8
—
—
V
3 V, Iload = –
10 mA
VDD – 0.8
—
—
V
C
High current drive
pins, high-drive
strength
—
Min
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
7
Nonswitching electrical specifications
Table 3. DC characteristics (continued)
Symbol
C
IOHT
D
VOL
P
Min
Typical1
Max
Unit
5V
—
—
–100
mA
3V
—
—
–60
—
—
0.8
V
3 V, Iload =
2.5 mA
—
—
0.8
V
5 V, Iload
=20 mA
—
—
0.8
V
3 V, Iload =
10 mA
—
—
0.8
V
—
—
100
mA
Descriptions
Output high
current
Output low
voltage
Max total IOH for all
ports
All I/O pins, standard- 5 V, Iload = 5
drive strength
mA
C
P
High current drive
pins, high-drive
strength2
C
IOLT
D
Output low
current
Max total IOL for all
ports
5V
3V
—
—
60
VIH
P
Input high
voltage
All digital inputs
VDD>4.5 V
0.70 × VDD
—
—
VDD>2.7 V
0.75 × VDD
—
—
Input low
voltage
All digital inputs
VDD>4.5 V
—
—
0.30 × VDD
VDD>2.7 V
—
—
0.35 × VDD
VIL
P
V
V
Vhys
C
Input
hysteresis
All digital inputs
—
0.06 × VDD
—
—
mV
|IIn|
P
Input leakage
current
All input only pins
(per pin)
VIN = VDD or
VSS
—
0.1
1
µA
|IOZ|
C
Hi-Z (offstate) leakage
current
All input/output (per
pin)
VIN = VDD or
VSS
—
0.1
1
µA
|IOZTOT|
C
Total leakage All input only and I/O VIN = VDD or
combined for
VSS
all inputs and
Hi-Z pins
—
—
2
µA
RPU
P
Pullup
resistors
All digital inputs,
when enabled
—
30.0
—
50.0
kΩ
IIC
D
DC injection
current3, 4, 5
Single pin limit
VIN < VSS,
VIN > VDD
-0.2
—
2
mA
-5
—
25
Total MCU limit,
includes sum of all
stressed pins
CIn
C
Input capacitance, all pins
—
—
—
7
pF
VRAM
C
RAM retention voltage
—
2.0
—
—
V
1.
2.
3.
4.
Typical values are measured at 25 °C. Characterized, not tested.
Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support ultra high current output.
All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the large value.
5. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than
maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is
very low (which would reduce overall power consumption).
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
8
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Table 4. LVD and POR specification
Symbol
C
Description
Min
Typ
Max
Unit
VPOR
D
POR re-arm voltage1
1.5
1.75
2.0
V
VLVDH
C
Falling low-voltage detect
threshold—high range (LVDV
= 1)2
4.2
4.3
4.4
V
VLVW1H
C
Level 1 falling
(LVWV = 00)
4.3
4.4
4.5
V
VLVW2H
C
Level 2 falling
(LVWV = 01)
4.5
4.5
4.6
V
VLVW3H
C
Level 3 falling
(LVWV = 10)
4.6
4.6
4.7
V
VLVW4H
C
Level 4 falling
(LVWV = 11)
4.7
4.7
4.8
V
VHYSH
C
High range low-voltage
detect/warning hysteresis
—
100
—
mV
VLVDL
C
Falling low-voltage detect
threshold—low range (LVDV
= 0)
2.56
2.61
2.66
V
VLVW1L
C
Level 1 falling
(LVWV = 00)
2.62
2.7
2.78
V
VLVW2L
C
Level 2 falling
(LVWV = 01)
2.72
2.8
2.88
V
VLVW3L
C
Falling lowvoltage
warning
threshold—
low range
Level 3 falling
(LVWV = 10)
2.82
2.9
2.98
V
VLVW4L
C
Level 4 falling
(LVWV = 11)
2.92
3.0
3.08
V
VHYSDL
C
Low range low-voltage detect
hysteresis
—
40
—
mV
VHYSWL
C
Low range low-voltage
warning hysteresis
—
80
—
mV
VBG
P
Buffered bandgap output 3
1.14
1.16
1.18
V
Falling lowvoltage
warning
threshold—
high range
1. Maximum is highest voltage that POR is guaranteed.
2. Rising thresholds are falling threshold + hysteresis.
3. voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
9
Nonswitching electrical specifications
Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V)
VDD-VOH(V)
IOH(mA)
Figure 1. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V)
Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3 V)
VDD-VOH(V)
IOH(mA)
Figure 2. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
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Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 5 V)
VDD-VOH(V)
IOH(mA)
Figure 3. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 5 V)
Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 3 V)
VDD-VOH(V)
IOH(mA)
Figure 4. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
11
Nonswitching electrical specifications
Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V)
VOL(V)
IOL(mA)
Figure 5. Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V)
Typical IOL Vs. VOL (standard drive strength) (VDD = 3 V)
VOL(V)
IOL(mA)
Figure 6. Typical IOL Vs. VOL (standard drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
12
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Typical IOL Vs. VOL(high drive strength) (VDD = 5 V)
VOL(V)
IOL(mA)
Figure 7. Typical IOL Vs. VOL (high drive strength) (VDD = 5 V)
Typical IOL Vs. VOL(high drive strength) (VDD = 3 V)
VOL(V)
IOL(mA)
Figure 8. Typical IOL Vs. VOL (high drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
13
Nonswitching electrical specifications
5.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes.
Table 5. Supply current characteristics
C
Parameter
Symbol
Bus Freq
VDD (V)
Typical1
Max
Unit
Temp
C
Run supply current FEI
mode, all modules clocks
enabled; run from flash
RIDD
20 MHz
5
6.7
—
mA
–40 to 105 °C
10 MHz
4.5
—
1 MHz
1.5
—
6.6
—
mA
–40 to 105 °C
mA
–40 to 105 °C
mA
–40 to 105 °C
mA
–40 to 105 °C
µA
–40 to 105 °C
C
C
20 MHz
C
10 MHz
4.4
—
1 MHz
1.45
—
5.3
—
10 MHz
3.7
—
1 MHz
1.5
—
5.3
—
C
C
Run supply current FEI
mode, all modules clocks
disabled; run from flash
RIDD
20 MHz
3
5
C
20 MHz
C
10 MHz
3.7
—
1 MHz
1.4
—
P
C
Run supply current FBE
mode, all modules clocks
enabled; run from RAM
RIDD
20 MHz
3
9
14.8
10 MHz
5
5.2
—
1 MHz
1.45
—
8.8
11.8
P
20 MHz
C
10 MHz
5.1
—
1 MHz
1.4
—
8
12.3
4.4
—
P
C
Run supply current FBE
mode, all modules clocks
disabled; run from RAM
RIDD
20 MHz
1 MHz
1.35
—
7.8
9.2
10 MHz
4.2
—
1 MHz
1.3
—
5.5
—
10 MHz
3.5
—
1 MHz
1.4
—
5.4
—
10 MHz
3.4
—
1 MHz
1.4
—
20 MHz
C
C
Wait mode current FEI
mode, all modules clocks
enabled
WIDD
C
P
20 MHz
20 MHz
SIDD
P
Stop mode supply current
no clocks active (except 1
kHz LPO clock)2, 3
C
ADC adder to Stop
—
ADLPC = 1
5
10 MHz
P
P
3
3
5
3
—
5
2
85
—
3
1.9
80
—
5
86 (64-, 44pin
packages)
—
–40 to 105 °C
µA
–40 to 105 °C
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
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Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Table 5. Supply current characteristics (continued)
C
Parameter
Symbol
Bus Freq
VDD (V)
ADLSMP = 1
C
Typical1
Max
Unit
Temp
µA
–40 to 105 °C
42 (32-pin
package)
ADCO = 1
3
MODE = 10B
ADICLK = 11B
82 (64-, 44pin
packages)
—
41 (32-pin
package)
C
LVD adder to stop4
—
C
1.
2.
3.
4.
—
5
128
—
3
124
—
Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
RTC adder causes IDD to increase typically by less than 1 µA; RTC clock source is 1 kHz LPO clock.
ACMP adder causes IDD to increase typically by less than 1 µA.
LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.
5.1.3 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components as well as MCU software
operation play a significant role in EMC performance. The system designer must consult
the following Freescale applications notes, available on freescale.com for advice and
guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
15
Switching specifications

5.2 Switching specifications

5.2.1 Control timing
Table 6. Control timing
Symbol
Min
Typical1
Max

Unit
fBus
DC
—
20
MHz
fLPO
0.67 
1.0
1.25
KHz
textrst
1.5 ×
—
—
ns
—
—
ns
Num
C
Rating
1
P
Bus frequency (tcyc = 1/fBus)
2
P
Internal low power oscillator frequency
3
D
External reset pulse width
4
D
Reset low drive
trstdrv
5
D
IRQ pulse width
Asynchronous
path2
tILIH
100
—
—
ns
Synchronous path
tIHIL
1.5 × tcyc
—
—
ns
Asynchronous
path2
tILIH
100
—
—
ns
Synchronous path
tIHIL
1.5 × tcyc
—
—
ns
Port rise and fall time Normal drive strength
(load = 50 pF)
—
tRise
—
10.2
—
ns
tFall
—
9.5
—
ns
Port rise and fall time high drive strength (load =
50 pF)3
—
tRise
—
5.4
—
ns
tFall
—
4.6
—
ns
D
6
D
Keyboard interrupt pulse
width
D
7
C
C
C
C
tcyc

34 × tcyc
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise
 stated.
2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
3. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.
textrst
RESET_b pin
Figure 9. Reset timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 10. KBIPx timing
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
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Freescale Semiconductor, Inc.

Switching specifications


5.2.2 FTM module timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the
fastest clock that can be used as the optional external source to
 the timer counter. These
synchronizers operate from the current bus rate clock.
Table 7. FTM input timing
No.
C
Function
Symbol
1
D
External clock
frequency
2
D
3

Min
Max
Unit
fTCLK
0
fBus/4
Hz
External clock
period
tTCLK
4
—
tcyc
D
External clock
high time
tclkh
— 
tcyc
4
D
External clock
low time
tclkl
1.5
—
tcyc
5
D
Input capture
pulse width
tICPW
1.5
—
tcyc


1.5


tTCLK
tclkh
TCLK
tclkl
Figure 11. Timer external clock
tICPW
FTMCHn
FTMCHn
tICPW
Figure 12. Timer input capture pulse
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
17
Thermal specifications
5.3 Thermal specifications
5.3.1 Thermal characteristics
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is userdetermined rather than being controlled by the MCU design. To take PI/O into account in
power calculations, determine the difference between actual pin voltage and VSS or VDD
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin
current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
Table 8. Thermal attributes
Board type
Symbol
Single-layer (1S)
RθJA
Four-layer (2s2p)
Description
64
LQFP
64 QFP
44
LQFP
32
LQFP
Unit
Notes
Thermal resistance, junction
to ambient (natural
convection)
71
61
75
86
°C/W
1, 2
RθJA
Thermal resistance, junction
to ambient (natural
convection)
53
47
53
57
°C/W
1, 3
Single-layer (1S)
RθJMA
Thermal resistance, junction
to ambient (200 ft./min. air
speed)
59
50
62
72
°C/W
1, 3
Four-layer (2s2p)
RθJMA
Thermal resistance, junction
to ambient (200 ft./min. air
speed)
46
41
47
51
°C/W
1, 3
—
RθJB
Thermal resistance, junction
to board
35
32
34
33
°C/W
4
—
RθJC
Thermal resistance, junction
to case
20
23
20
24
°C/W
5
—
ΨJT
Thermal characterization
parameter, junction to
package top outside center
(natural convection)
5
8
5
6
°C/W
6
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
18
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts - chip internal power
PI/O = Power dissipation on input and output pins - user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship
between PD and TJ (if PI/O is neglected) is:
PD = K ÷ (TJ + 273 °C)
Solving the equations above for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2
where K is a constant pertaining to the particular part. K can be determined by measuring
PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can
be obtained by solving the above equations iteratively for any value of TA.
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD electricals
Table 9. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
5.5
V
0
25
MHz
1/J1
—
ns
20
—
ns
SWD_CLK frequency of operation
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
19
Peripheral operating requirements and behaviors
Table 9. SWD full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
• Serial wire debug
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 13. Serial wire clock input timing
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 14. Serial wire data timing
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
20
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.2 External oscillator (OSC) and ICS characteristics
Table 10. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)
Symbol
Min
Typical1
Max
Unit
Low range (RANGE = 0)
flo
31.25
—
39.0625
kHz
High range (RANGE = 1)
FEE or FBE mode
fhi
4
—
20
MHz
C
High range (RANGE = 1),
high gain (HGO = 1),
FBELP mode
fhi
4
—
20
MHz
C
High range (RANGE = 1),
low power (HGO = 0),
FBELP mode
fhi
4
—
20
MHz
Num
C
1
C
C
2
D
3
D
4
5
Oscillator
crystal or
resonator
Load capacitors
Feedback
resistor
Low Frequency, Low-Power
Mode
—
—
—
MΩ
Low Frequency, High-Gain
Mode
—
10
—
MΩ
High Frequency, LowPower Mode
—
1
—
MΩ
High Frequency, High-Gain
Mode
—
1
—
MΩ
—
—
—
kΩ
—
200
—
kΩ
—
—
—
kΩ
4 MHz
—
0
—
kΩ
8 MHz
—
0
—
kΩ
16 MHz
—
0
—
kΩ
—
1000
—
ms
—
800
—
ms
—
3
—
ms
—
1.5
—
ms
tIRST
—
20
50
µs
fextal
0.03125
—
5
MHz
0
—
20
MHz
Low-Power Mode 4
D
Series resistor High Frequency
Mode4
D
Series resistor High
Frequency,
High-Gain Mode
D
C
C
C
C
7
T
8
D
D
Crystal start-up
time low range
= 31.25 kHz
crystal; High
range = 20 MHz
crystal, 6
RF
RS
High-Gain Mode
Low-Power
Low range, low power
RS
tCSTL
Low range, high power
High range, low power
tCSTH
High range, high power
Internal reference start-up time
Square wave
input clock
frequency
See Note3
C1, C2
Series resistor Low Frequency
D
D
6
Characteristic
FEE or FBE mode2
FBELP mode
9
P
Average target internal reference frequency trimmed
fint_t
—
31.25
—
kHz
10
P
DCO output frequency range - trimmed
fdco_t
16
—
20
MHz
11
P
Δfdco_t
—
—
±2.0
%fdco
C
C
12
C
Total deviation
of DCO output
from trimmed
frequency5
Over full voltage and
temperature range
±1.5
Over fixed voltage and
temperature range of 0 to
70 °C
FLL acquisition time5, 7
±1.0
tAcquire
—
—
2
ms
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
Table 10. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)
(continued)
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
13
C
Long term jitter of DCO output clock
(averaged over 2 ms interval)8
CJitter
—
0.02
0.2
%fdco
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25
kHz to 39.0625 kHz.
3. See crystal or resonator manufacturer's recommendation.
4. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
0.
5. This parameter is characterized and not tested on each device.
6. Proper PC board layout procedures must be followed to achieve specifications.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed,
DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
OSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 15. Typical crystal or resonator circuit
6.3 NVM specifications
This section provides details about program/erase times and program/erase endurance for
the flash and EEPROM memories.
Table 11. Flash and EEPROM characteristics
C
Characteristic
Symbol
Min1
Typical2
Max3
Unit4
D
Supply voltage for program/erase –40
°C to 105 °C
Vprog/erase
2.7
—
5.5
V
D
Supply voltage for read operation
VRead
2.7
—
5.5
V
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 11. Flash and EEPROM characteristics
(continued)
1.
2.
3.
4.
C
Characteristic
Symbol
Min1
Typical2
Max3
Unit4
D
NVM Bus frequency
fNVMBUS
1
—
25
MHz
D
NVM Operating frequency
fNVMOP
0.8
1
1.05
MHz
D
Erase Verify All Blocks
tVFYALL
—
—
17338
tcyc
D
Erase Verify Flash Block
tRD1BLK
—
—
16913
tcyc
D
Erase Verify EEPROM Block
tRD1BLK
—
—
810
tcyc
D
Erase Verify Flash Section
tRD1SEC
—
—
484
tcyc
D
Erase Verify EEPROM Section
tDRD1SEC
—
—
555
tcyc
D
Read Once
tRDONCE
—
—
450
tcyc
D
Program Flash (2 word)
tPGM2
0.12
0.12
0.29
ms
D
Program Flash (4 word)
tPGM4
0.20
0.21
0.46
ms
D
Program Once
tPGMONCE
0.20
0.21
0.21
ms
D
Program EEPROM (1 Byte)
tDPGM1
0.10
0.10
0.27
ms
D
Program EEPROM (2 Byte)
tDPGM2
0.17
0.18
0.43
ms
D
Program EEPROM (3 Byte)
tDPGM3
0.25
0.26
0.60
ms
D
Program EEPROM (4 Byte)
tDPGM4
0.32
0.33
0.77
ms
D
Erase All Blocks
tERSALL
96.01
100.78
101.49
ms
D
Erase Flash Block
tERSBLK
95.98
100.75
101.44
ms
D
Erase Flash Sector
tERSPG
19.10
20.05
20.08
ms
D
Erase EEPROM Sector
tDERSPG
4.81
5.05
20.57
ms
D
Unsecure Flash
tUNSECU
96.01
100.78
101.48
ms
D
Verify Backdoor Access Key
tVFYKEY
—
—
464
tcyc
D
Set User Margin Level
tMLOADU
—
—
407
tcyc
C
FLASH Program/erase endurance TL to
TH = -40 °C to 105 °C
nFLPE
10 k
100 k
—
Cycles
C
EEPROM Program/erase endurance TL
to TH = -40 °C to 105 °C
nFLPE
50 k
500 k
—
Cycles
C
Data retention at an average junction
temperature of TJavg = 85°C after up to
10,000 program/erase cycles
tD_ret
15
100
—
years
Minimum times are based on maximum fNVMOP and maximum fNVMBUS
Typical times are based on typical fNVMOP and maximum fNVMBUS
Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
tcyc = 1 / fNVMBUS
Program and erase operations do not require any special power sources other than the
normal VDD supply. For more detailed information about program/erase operations, see
the Flash Memory Module section in the reference manual.
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
6.4 Analog
6.4.1 ADC characteristics
Table 12. 5 V 12-bit ADC operating conditions
Characteri
stic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Supply
voltage
Absolute
VDDA
2.7
—
5.5
V
—
Delta to VDD (VDD-VDDAD)
ΔVDDA
-100
0
+100
mV
)1
ΔVSSA
-100
0
+100
mV
Input
voltage
VADIN
VREFL
—
VREFH
V
Input
capacitance
CADIN
—
4.5
5.5
pF
Input
resistance
RADIN
—
3
5
kΩ
—
RAS
—
—
2
kΩ
External to
MCU
—
—
5
—
—
5
—
—
10
—
—
10
0.4
—
8.0
MHz
—
0.4
—
4.0
Ground
voltage
Analog
source
resistance
Delta to VSS (VSS-VSSA
•
•
12-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
•
•
10-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
8-bit mode
(all valid fADCK)
ADC
conversion
clock
frequency
High speed (ADLPC=0)
Low power (ADLPC=1)
fADCK
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
1. DC potential difference.
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
R AS
ADC SAR
ENGINE
R ADIN
v ADIN
C AS
v AS
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
INPUT PIN
C ADIN
Figure 16. ADC input impedance equivalency diagram
Table 13. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Characteristic
Conditions
Supply current
C
Symb
Min
Typ1
Max
Unit
T
IDDA
—
133
—
µA
T
IDDA
—
218
—
µA
T
IDDA
—
327
—
µA
T
IDDAD
—
582
990
µA
ADLPC = 1
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
Supply current
Stop, reset, module
off
T
IDDA
—
0.011
1
µA
ADC asynchronous
clock source
High speed (ADLPC
= 0)
P
fADACK
2
3.3
5
MHz
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
Table 13. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Characteristic
Conditions
C
Symb
Low power (ADLPC
= 1)
Conversion time
(including sample
time)
Short sample
(ADLSMP = 0)
Sample time
Short sample
(ADLSMP = 0)
T
tADC
Long sample
(ADLSMP = 1)
T
tADS
Long sample
(ADLSMP = 1)
Total unadjusted
Error
Typ1
Max
1.25
2
3.3
—
20
—
—
40
—
—
3.5
—
—
23.5
—
12-bit mode
T
—
±5.0
—
10-bit mode
P
—
±1.5
±2.0
8-bit mode
P
—
±0.7
±1.0
12-bit mode
T
—
±1.0
—
10-bit mode
P
—
±0.25
±0.5
mode3
P
—
±0.15
±0.25
Integral Non-Linearity 12-bit mode
T
—
±1.0
—
10-bit mode
T
—
±0.3
±0.5
—
±0.15
±0.25
—
±2.0
—
Differential NonLiniarity
8-bit
ETUE
Min
DNL
INL
Unit
ADCK
cycles
ADCK
cycles
LSB
LSB2
LSB2
8-bit mode
T
12-bit mode
C
10-bit mode
P
—
±0.25
±1.0
8-bit mode
P
—
±0.65
±1.0
12-bit mode
T
—
±2.5
—
10-bit mode
T
—
±0.5
±1.0
8-bit mode
T
—
±0.5
±1.0
Quantization error
≤12 bit modes
D
EQ
—
—
±0.5
LSB2
Input leakage error7
all modes
D
EIL
Temp sensor slope
-40 °C–25 °C
D
m
mV/°C
Zero-scale error
Full-scale
error6
EZS
EFS
25 °C–125 °C
Temp sensor voltage 25 °C
D
VTEMP25
IIn * RAS
LSB2
LSB2
mV
—
3.266
—
—
3.638
—
—
1.396
—
V
1. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. 1 LSB = (VREFH - VREFL)/2N
3. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
4. VADIN = VDDA
5. IIn = leakage current (refer to DC characteristics)
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4.2 Analog comparator (ACMP) electricals
Table 14. Comparator electrical specifications
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage
VDDA
2.7
—
5.5
V
T
Supply current (Operation mode)
IDDA
—
10
20
µA
D
Analog input voltage
VAIN
VSS - 0.3
—
VDDA
V
P
Analog input offset voltage
VAIO
—
—
40
mV
C
Analog comparator hysteresis (HYST=0)
VH
—
15
20
mV
C
Analog comparator hysteresis (HYST=1)
VH
—
20
30
mV
T
Supply current (Off mode)
IDDAOFF
—
60
—
nA
C
Propagation Delay
tD
—
0.4
1
µs
6.5 Communication interfaces
6.5.1 SPI switching specifications
The serial peripheral interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's reference manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes
slew rate control is disabled and high-drive strength is enabled for SPI output pins.
Table 15. SPI master mode timing
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
fBus/2048
fBus/2
Hz
fBus is the bus
clock
2
tSPSCK
2 x tBus
2048 x tBus
ns
tBus = 1/fBus
3
tLead
Enable lead time
1/2
—
tSPSCK
—
4
tLag
Enable lag time
1/2
—
tSPSCK
—
5
tWSPSCK
6
tSU
Data setup time (inputs)
tBus – 30
1024 x tBus
ns
—
15
—
ns
—
7
tHI
Data hold time (inputs)
0
—
ns
—
8
tv
Data valid (after SPSCK edge)
—
25
ns
—
9
tHO
Data hold time (outputs)
0
—
ns
—
10
tRI
Rise time input
—
tBus – 25
ns
—
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 15. SPI master mode timing (continued)
Nu
m.
11
Symbol
Description
tFI
Fall time input
tRO
Rise time output
tFO
Fall time output
Min.
Max.
Unit
Comment
—
25
ns
—
SS1
(OUTPUT)
3
2
SPSCK
(CPOL = 0)
(OUTPUT)
10
11
10
11
4
5
5
SPSCK
(CPOL = 1)
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
8
MOSI
(OUTPUT)
MSB OUT2
9
BIT 6 . . . 1
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI master mode timing (CPHA=0)
SS1
(OUTPUT)
2
SPSCK
(CPOL = 0)
(OUTPUT)
SPSCK
(CPOL = 1)
(OUTPUT)
3
5
6
MISO
(INPUT)
5
10
11
10
11
4
7
MSB IN2
8
MOSI
2
(OUTPUT)PORT DATA MASTER MSB OUT
BIT 6 . . . 1
LSB IN
9
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI master mode timing (CPHA=1)
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 16. SPI slave mode timing
Nu
m.
Symbol
Description
1
fop
2
tSPSCK
3
tLead
Enable lead time
4
tLag
Enable lag time
5
tWSPSCK
6
tSU
7
Min.
Max.
Unit
Comment
0
fBus/4
Hz
fBus is the bus clock as
defined in .
4 x tBus
—
ns
tBus = 1/fBus
1
—
tBus
—
Frequency of operation
SPSCK period
1
—
tBus
—
tBus - 30
—
ns
—
Data setup time (inputs)
15
—
ns
—
tHI
Data hold time (inputs)
25
—
ns
—
8
ta
Slave access time
—
tBus
ns
Time to data active from
high-impedance state
9
tdis
Slave MISO disable time
—
tBus
ns
Hold time to highimpedance state
10
tv
Data valid (after SPSCK edge)
—
25
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tBus - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
13
Clock (SPSCK) high or low time
SS
(INPUT)
2
SPSCK
(CPOL = 0)
(INPUT)
5
3
SPSCK
(CPOL = 1)
(INPUT)
13 4
12
13
9
8
MISO
(OUTPUT)
5
12
10
see
note
6
MOSI
(INPUT)
SLAVE MSB
BIT 6 . . . 1
11
11
SLAVE LSB OUT
SEE
NOTE
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined
Figure 19. SPI slave mode timing (CPHA = 0)
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
29
Dimensions
SS
(INPUT)
4
2
3
SPSCK
(CPOL = 0)
(INPUT)
5
SPSCK
(CPOL = 1)
(INPUT)
5
see
note
8
MOSI
(INPUT)
13
12
13
9
11
10
MISO
(OUTPUT)
12
SLAVE
MSB OUT
6
BIT 6 . . . 1
SLAVE LSB OUT
7
MSB IN
LSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 20. SPI slave mode timing (CPHA=1)
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
Then use this document number
32-pin LQFP
98ASH70029A
44-pin LQFP
98ASS23225W
64-pin QFP
98ASB42844B
64-pin LQFP
98ASS23234W
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
30
Freescale Semiconductor, Inc.
Pinout
8 Pinout
8.1 Signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Table 17. Pin availability by package pin-count
Pin Number
Lowest Priority <-- --> Highest
64-QFP/
LQFP
44-LQFP
32-LQFP
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
1
1
1
PTD11
KBI1_P1
FTM2_CH3
SPI1_MOSI
—
KBI1_P0
FTM2_CH2
SPI1_SCK
—
—
—
—
2
2
2
PTD01
3
—
—
PTH7
—
4
—
—
PTH6
—
—
—
—
5
3
—
PTE7
—
FTM2_CLK
—
FTM1_CH1
6
4
—
PTH2
—
BUSOUT
—
FTM1_CH0
7
5
3
—
—
—
—
VDD
8
6
4
—
—
—
VDDA
VREFH2
9
7
5
—
—
—
—
VREFL
10
8
6
—
—
—
VSSA
VSS3
11
9
7
PTB7
—
I2C0_SCL
—
EXTAL
12
10
8
PTB6
—
I2C0_SDA
—
XTAL
13
11
—
—
—
—
—
VSS
14
—
—
PTH11
—
FTM2_CH1
—
—
—
FTM2_CH0
—
—
15
—
—
PTH01
16
—
—
PTE6
—
—
—
—
17
—
—
PTE5
—
—
—
—
9
PTB51
FTM2_CH5
SPI0_PCS0
ACMP1_OUT
—
FTM2_CH4
SPI0_MISO
NMI
ACMP1_IN2
18
12
19
13
10
PTB41
20
14
11
PTC3
FTM2_CH3
—
—
ADC0_SE11
21
15
12
PTC2
FTM2_CH2
—
—
ADC0_SE10
22
16
—
PTD7
KBI1_P7
UART2_TX
—
—
23
17
—
PTD6
KBI1_P6
UART2_RX
—
—
24
18
—
PTD5
KBI1_P5
—
—
—
25
19
13
PTC1
—
FTM2_CH1
—
ADC0_SE9
26
20
14
PTC0
—
FTM2_CH0
—
ADC0_SE8
27
—
—
PTF7
—
—
—
ADC0_SE15
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
31
Pinout
Table 17. Pin availability by package pin-count (continued)
Pin Number
Lowest Priority <-- --> Highest
64-QFP/
LQFP
44-LQFP
32-LQFP
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
28
—
—
PTF6
—
—
—
ADC0_SE14
29
—
—
PTF5
—
—
—
ADC0_SE13
30
—
—
PTF4
—
—
—
ADC0_SE12
31
21
15
PTB3
KBI0_P7
SPI0_MOSI
FTM0_CH1
ADC0_SE7
32
22
16
PTB2
KBI0_P6
SPI0_SCK
FTM0_CH0
ADC0_SE6
33
23
17
PTB1
KBI0_P5
UART0_TX
—
ADC0_SE5
34
24
18
PTB0
KBI0_P4
UART0_RX
—
ADC0_SE4
35
—
—
PTF3
—
—
—
—
36
—
—
PTF2
—
—
—
—
37
25
19
PTA7
—
FTM2_FLT2
ACMP1_IN1
ADC0_SE3
38
26
20
PTA6
—
FTM2_FLT1
ACMP1_IN0
ADC0_SE2
39
—
—
PTE4
—
—
—
—
40
27
—
—
—
—
—
VSS
41
28
—
—
—
—
—
VDD
42
—
—
PTF1
—
—
—
—
43
—
—
PTF0
—
—
—
—
44
29
—
PTD4
KBI1_P4
—
—
—
45
30
21
PTD3
KBI1_P3
SPI1_PCS0
—
—
46
31
22
PTD2
KBI1_P2
SPI1_MISO
—
—
23
PTA34
KBI0_P3
UART0_TX
I2C0_SCL
—
KBI0_P2
UART0_RX
I2C0_SDA
—
47
32
48
33
24
PTA24
49
34
25
PTA1
KBI0_P1
FTM0_CH1
ACMP0_IN1
ADC0_SE1
50
35
26
PTA0
KBI0_P0
FTM0_CH0
ACMP0_IN0
ADC0_SE0
51
36
27
PTC7
—
UART1_TX
—
—
52
37
28
PTC6
—
UART1_RX
—
—
53
—
—
PTE3
—
SPI0_PCS0
—
—
54
38
—
PTE2
—
SPI0_MISO
—
—
55
—
—
PTG3
—
—
—
—
56
—
—
PTG2
—
—
—
—
57
—
—
PTG1
—
—
—
—
58
—
—
PTG0
—
—
—
—
59
39
—
PTE11
—
SPI0_MOSI
—
—
—
SPI0_SCK
FTM1_CLK
—
60
40
—
PTE01
61
41
29
PTC5
—
FTM1_CH1
—
RTCO
62
42
30
PTC4
RTCO
FTM1_CH0
ACMP0_IN2
SWD_CLK
63
43
31
PTA5
IRQ
FTM0_CLK
—
RESET
64
44
32
PTA4
—
ACMP0_OUT
—
SWD_DIO
1. This is a high-current drive pin when operated as output.
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
32
Freescale Semiconductor, Inc.
Pinout
2. VREFH and VDDA are internally connected.
3. VSSA and VSS are internally connected.
4. This is a true open-drain pin when operated as output.
Note
When an alternative function is first enabled, it is possible to
get a spurious edge to the module. User software must clear any
associated flags before interrupts are enabled. Table 17
illustrates the priority if multiple modules are enabled. The
highest priority module will have control over the pin. Selecting
a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority
module. Disable all modules that share a pin before enabling
another module.
PTE3
PTC6
PTC7
PTA0
PTA1
52
51
50
49
PTE2
PTG1
57
54
PTG0
58
53
PTE11
59
PTG2
PTE01
PTG3
PTC5
60
55
PTC4
62
61
56
PTA4
PTA5
64
63
8.2 Device pin assignment
PTD1 1
1
48
PTA22
PTD0 1
2
47
PTA32
PTD2
PTH7
3
46
PTH6
4
45
PTD3
PTE7
5
44
PTD4
PTH2
VDD
6
43
PTF0
7
42
PTF1
8
41
VDD
9
40
VSS
10
39
PTE4
PTA6
VDDA/VREFH
VREFL
VSSA/VSS
32
29
PTF5
PTB2
28
31
27
PTF7
PTF6
30
26
PTC0
PTF4
25
PTC1
PTB3
24
PTB1
PTD5
33
23
16
22
PTB0
PTE6
PTD6
PTF3
34
PTD7
35
15
21
14
PTH01
PTC2
PTH11
19
PTF2
20
PTA7
36
PTB4 1
PTC3
37
13
17
12
VSS
18
38
PTE5
11
PTB5 1
PTB7
PTB6
Pins in bold are not available on less pi n-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 21. 64-pin QFP/LQFP packages
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
33
PTC6
PTC7
PTA0
PTA1
36
35
34
PTE2
38
37
PTE01
PTE11
PTC5
41
39
PTC4
42
40
PTA4
PTA5
43
44
Revision history
PTB0
23
PTB1
22
24
11
21
10
VSS
PTB2
PTA7
PTB3
PTA6
PTB7
PTB6
20
26
25
PTC0
8
9
19
VSS
18
VDD
27
PTC1
28
7
PTD5
6
VREFL
VSSA/VSS
17
PTD4
PTD6
29
16
5
PTD7
PTD3
VDD
VDDA/VREFH
15
30
14
4
PTC2
PTH2
PTC3
3
31
PTA32
PTE7
13
PTA22
32
12
33
2
PTB4 1
1
PTD0 1
PTB5 1
PTD1 1
PTD2
Pins in bold are not available on less pi n-count packages.
1. High source/sink current pins
2. True open drain pins
PTC6
PTA0
PTA1
26
25
PTC5
29
PTC7
PTC4
30
28
PTA5
31
27
PTA4
32
Figure 22. 44-pin LQFP package
PTD1 1
1
24
PTA22
PTD0 1
2
23
PTA32
VDD
VDDA/VREFH
3
22
PTD2
4
21
PTD3
13
14
15
16
PTB3
PTB2
PTB1
PTC0
17
PTC1
8
11
PTB0
PTB6
12
PTA7
18
PTC3
19
7
PTC2
6
PTB7
10
PTA6
PTB4 1
20
9
5
PTB5 1
VREFL
VSSA/VSS
1. High source/sink current pins
2. True open drain pins
Figure 23. 32-pin LQFP package
9 Revision history
The following table provides a revision history for this document.
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
34
Freescale Semiconductor, Inc.
Revision history
Table 18. Revision history
Rev. No.
Date
3
07/2013
Substantial Changes
Initial public release.
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
35
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Document Number MKE02P64M20SF0
Revision 3, 07/2013