LAN9118 High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller PRODUCT FEATURES Data Brief Highlights ■ ■ ■ — Low-cost, low-pin count non-PCI interface for embedded designs Optimized for high-data rate applications such as video, high-definition video and multi-media applications Efficient architecture with low CPU overhead; easily interfaces to most Embedded CPU’s Reduces system and design costs ■ — — — — — ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Cable, satellite, and IP set-top boxes Digital video recorders High definition televisions Digital music jukeboxes Digital media clients/servers DVD recorders/players Home gateways Video-over IP Solutions Wireless routers & access points IP PBX & video phones ■ ■ ■ ■ ■ Minimizes CPU overhead Reduces system cost and increases design flexibility — SRAM-like interface easily interfaces to most Embedded CPU’s or SoC’s ■ ■ SMSC LAN9118 High-Performance host bus interface Miscellaneous features — — — — — — Supports Slave-DMA — Interrupt Pin with Programmable Hold-off timer ■ Integrated Ethernet PHY — Simple, SRAM-like interface — 32/16-bit data bus — Large, 16Kbyte FIFO memory that can be allocated to RX or TX functions — One configurable Host interrupt Eliminates dropped packets — Internal SRAM can store over 200 packets — Supports automatic or host-triggered PAUSE and backpressure flow control ■ One 48-bit perfect address 64 hash-filtered multicast addresses Pass all multicast Promiscuous mode Inverse filtering Pass all incoming with status report Disable reception of broadcast packets — Auto-negotiation — Automatic polarity detection and correction Supports high and ultra-high performance applications — Highest performing non-PCI Ethernet controller in the market — 32-bit interface with 45ns bus cycle times — Burst-mode read support ■ Fully compliant with IEEE 802.3/802.3u standards Integrated Ethernet MAC and PHY 10BASE-T and 100BASE-TX support Full- and Half-duplex support Full-duplex flow control Backpressure for half-duplex flow control Preamble generation and removal Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal Loop-back modes Flexible address filtering modes — — — — — — — Key Benefits Numerous power management modes Wake on LAN Magic packet wakeup Wakeup indicator event signal Link Status Change Single chip Ethernet controller — — — — — — — — — — Target Applications ■ Architected for Low Power Low profile 100-pin TQFP package Integral 1.8V regulator General Purpose Timer Support for optional EEPROM Support for 3 status LEDs multiplexed with Programmable GPIO signals 3.3V Power Supply with 5V tolerant I/O 0 to 70°C PRODUCT PREVIEW Revision 0.5 (09-09-04) High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller ■ ORDERING INFORMATION: LAN9118-MD FOR 100 PIN, TQFP PACKAGE LAN9118-MT FOR 100 PIN, LEAD-FREE TQFP PACKAGE 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © SMSC 2004. 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Revision 0.5 (09-09-04) 2 PRODUCT PREVIEW SMSC LAN9118 High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller General Description The LAN9118 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and low cost are required. The LAN9118 has been specifically architected to provide the highest performance possible for any given architecture. The LAN9118 is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant. The LAN9118 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16 and 32-bit microprocessors and microcontrollers. LAN9118 includes large transmit and receive data FIFO’s with a high-speed host bus interface to accommodate high bandwidth, high latency applications. In addition, the LAN9118 memory buffer architecture allows the most efficient use of memory resources by optimizing packet granularity. Applications The LAN9118 is well suited for many high-performance embedded applications, including: ■ Digital television ■ Video record/playback systems ■ Set-top boxes ■ Printers and scanners The LAN9118 supports numerous power management and wakeup features. The LAN9118 can be placed in a reduced power mode and can be programmed to issue an external wake signal via several methods, including Magic Packet, Wake on LAN and Link Status Change. This signal is ideal for triggering system power-up using remote Ethernet wakeup events. The device can be removed from the low power state via a host processor command. The LAN9118 also supports features which reduce or eliminate packet loss. Its internal 16k SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9118 can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating a network collision. The host controller can also. The diagram shown in Figure 1, "System Block Diagram utilizing the SMSC LAN9118", describes a typical system configuration of the LAN9118 in a typical embedded environment. The LAN9118 is designed to be general purpose Ethernet controller that is platform independent. The LAN9118 consists of four major functional blocks. The four blocks are: 1. 10/100 Ethernet PHY 2. 10/100 Ethernet MAC 3. RX/TX FIFO’s 4. Slave Interface Module SMSC LAN9118 3 PRODUCT PREVIEW Revision 0.5 (09-09-04) High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller Block Diagrams System Memory System Memory System Peripherals Embedded Microprocessor/ Microcontroller Magnetics System Bus Ethernet LAN9118 LEDS/GPIO 25MHz XTAL EEPROM (Optional) Figure 1 System Block Diagram utilizing the SMSC LAN9118 Revision 0.5 (09-09-04) 4 PRODUCT PREVIEW SMSC LAN9118 High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller 25MHz EEPROM (Optional) +3.3V 3.3Vto1.8V Regulator EEPROM Controller PLL 2kBto14kB Configurable TXFIFO PIOController SRAMI/F Host Bus Interface (HBI) IRQ 10/100 Ethernet MAC TXStatus FIFO Interrupt Controller FIFO_SEL GPTimer RXStatusFIFO 2kBto14kB Configurable RXFIFO 10/100 Ethernet PHY LAN MIL- RXElastic Buffer - 128bytes MIL- TXElastic Buffer - 2K Figure 2 LAN9118 Internal Block Diagram SMSC LAN9118 5 PRODUCT PREVIEW Revision 0.5 (09-09-04) High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller Package Outline Figure 3 100 Pin TQFP Package Outline Table 1 100 Pin TQFP Package Parameters A A1 A2 D D1 E E1 H L L1 e θ W R1 R2 ccc MIN ~ NOMINAL ~ MAX 1.60 REMARKS Overall Package Height 0.05 1.35 15.80 13.90 15.80 13.90 0.09 0.45 ~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.50 Basic ~ 0.22 ~ ~ ~ 0.15 1.45 16.20 14.10 16.20 14.10 0.20 0.75 ~ Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity 0o 0.17 0.08 0.08 ~ 7o 0.27 ~ 0.20 0.08 Notes: 1 Controlling Unit: millimeter. 2 Tolerance on the true position of the leads is ± 0.04 mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. Revision 0.5 (09-09-04) 6 PRODUCT PREVIEW SMSC LAN9118