Features • Utilizes the AVR® RISC Architecture • AVR - High-performance and Low-power RISC Architecture • • • • • • • • – 118 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 1MIPS Throughput at 1MHz Data and Nonvolatile Program Memory – 2K Bytes of In-System Programmable Flash Endurance 1,000 Write/Erase Cycles – 128 Bytes of internal SRAM – 128 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler – Programmable Watchdog Timer with On-chip Oscillator – SPI Serial Interface for In-System Programming Special Microcontroller Features – Low-power Idle and Power Down Modes – External and Internal Interrupt Sources – Power-on Reset Circuit – On-chip RC Oscillator Specifications – Low-power, High-speed CMOS Process Technology – Fully Static Operation Power Consumption at 3V, 25°C – Active: 1.5 mA – Idle Mode: 100 µA – Power Down Mode: <1 µA I/O and Packages – 5 Programmable I/O Lines – 8-pin PDIP and SOIC Operating Voltages – 2.7 - 6.0V Speed Grade – Internal Oscillator ~1MHz @ 5.0V 8-bit Microcontroller with 2K Bytes of In-System Programmable Flash ATtiny22L Preliminary Description The ATtiny22L is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny22L achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), Pin Configuration PDIP/SOIC RESET PB3 PB4 GND 1 2 3 4 8 7 6 5 VCC PB2 (SCK/T0) PB1 (MISO/INT0) PB0 (MOSI) Rev. 1273BS–02/00 Note: This is a summary document. For the complete 56-page document, please visit our web site at www.atmel.com or e-mail at1 [email protected] and request literature #1273B. allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. Block Diagram Figure 1. The ATtiny22L Block Diagram VCC 8-BIT DATA BUS INTERNAL OSCILLATOR GND PROGRAM COUNTER STACK POINTER WATCHDOG TIMER PROGRAM FLASH SRAM MCU CONTROL REGISTER INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES TIMER/ COUNTER GENERAL PURPOSE REGISTERS X Y Z INTERRUPT UNIT ALU EEPROM STATUS REGISTER PROGRAMMING LOGIC SPI DATA REGISTER PORTB DATA DIR. REG. PORTB PORTB DRIVERS PB0 - PB4 2 ATtiny22L TIMING AND CONTROL RESET ATtiny22L The ATtiny22L provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, five general purpose I/O lines, 32 general purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, an SPI serial port for Flash Memory downloading and two software selectable power saving modes. The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The power down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip Flash allows the program memory to be reprogrammed in-system through an SPI serial interface. By combining an 8-bit RISC CPU with ISP Flash on a monolithic chip, the Atmel ATtiny22L is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny22L AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Pin Descriptions ATtiny22L VCC Supply voltage pin. GND Ground pin. Port B (PB4..PB0) Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated. Port B also serves the functions of various special features. Port pins can provide internal pull-up resistors (selected for each bit). The port B pins are tri-stated when a reset condition becomes active. RESET Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. Clock Source The ATtiny22L is clocked by an on-chip RC oscillator. This RC oscillator runs at a nominal frequency of 1 MHz (VCC = 5V). Architectural Overview The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one arithmetic logic unit (ALU) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function registers are the 16-bit X-register, Y-register and Z-register. 3 Figure 2. The ATtiny22L AVR RISC Architecture AVR ATtiny22L Architecture Data Bus 8-bit 1K x 16 Program Flash Program Counter Status and Test 32 x 8 General Purpose Registers Control Lines Direct Addressing Instruction Decoder Indirect Addressing Instruction Register Control Registers Interrupt Unit SPI Unit 8-bit Timer/Counter ALU Watchdog Timer 128 x 8 Data SRAM I/O Lines 128 x 8 EEPROM The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 2 shows the ATtiny22L AVR RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-converters, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F. The AVR has Harvard architecture - with separate memories and buses for program and data. The program memory is accessed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory. With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit stack pointer SP is read/write accessible in the I/O space. The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. 4 ATtiny22L ATtiny22L Figure 3. Memory Maps EEPROM Data Memory $000 EEPROM (128 x 8) $07F A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. 5 Register Summary Address Name $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) … $00 ($20) SREG Reserved SPL Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB Reserved Reserved Reserved Notes: 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page I T H S V N Z C page 16 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 17 - INT0 INTF0 - - - - - - - - - - - TOIE0 TOV0 - page 23 page 23 page 23 page 24 SE - SM - - CS02 ISC01 EXTRF CS01 ISC00 PORF CS00 page 24 page 22 page 27 page 28 - WDTOE WDE WDP2 WDP1 WDP0 page 28 Timer/Counter0 (8 Bit) - - EEPROM Address Register EEPROM Data register - - - - PORTB DDB4 PINB4 - EEMW EEWE EERE page 30 page 30 page 30 PORTB DDB3 PINB3 PORTB DDB2 PINB2 PORTB DDB1 PINB1 PORTB DDB0 PINB0 page 32 page 32 page 32 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. ATtiny22L ATtiny22L Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBIW Rdl,K Subtract Immediate from Word SBC Rd, Rr Subtract with Carry two Registers SBCI Rd, K Subtract with Carry Constant from Reg. AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One’s Complement NEG Rd Two’s Complement SBR Rd,K Set Bit(s) in Register CBR Rd,K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register BRANCH INSTRUCTIONS RJMP k Relative Jump IJMP Indirect Jump to (Z) RCALL k Relative Subroutine Call ICALL Indirect Call to (Z) RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled Operation Flags #Clock Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd − Rr Rd ← Rd − K Rdh:Rdl ← Rdh:Rdl − K Rd ← Rd − Rr − C Rd ← Rd − K − C Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← $FF − Rd Rd ← $00 − Rd Rd ← Rd v K Rd ← Rd • ($FF − K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← $FF Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PC ← PC + k + 1 PC ← Z PC ← PC + k + 1 PC ← Z PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (R(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC + k + 1 if (SREG(s) = 0) then PC←PC + k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if (I = 1) then PC ← PC + k + 1 if (I = 0) then PC ← PC + k + 1 None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 7 Instruction Set Summary (Continued) Mnemonics Operands DATA TRANSFER INSTRUCTIONS MOV Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, - X LD Rd, Y LD Rd, Y+ LD Rd, - Y LDD Rd,Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST - X, Rr ST Y, Rr ST Y+, Rr ST - Y, Rr STD Y+q,Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q,Rr STS k, Rr LPM IN Rd, P OUT P, Rr PUSH Rr POP Rd BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR 8 Description Operation Flags #Clock Move Between Registers Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Rd ← Rr Rd ← K Rd ← (X) Rd ← (X), X ← X + 1 X ← X − 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1 Y ← Y − 1, Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z), Z ← Z+1 Z ← Z - 1, Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr, X ← X + 1 X ← X - 1, (X) ← Rr (Y) ← Rr (Y) ← Rr, Y ← Y + 1 Y ← Y - 1, (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr, Z ← Z + 1 Z ← Z - 1, (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← P P ← Rr STACK ← Rr Rd ← STACK None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 1 2 2 Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 T←0 H←1 H←0 None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 ATtiny22L (see specific descr. for Sleep (see specific descr. for WDR/timer) ATtiny22L Ordering Information Power Supply Speed (MHz) Ordering Code Package Operation Range 2.7 - 6.0V Internal Osc [email protected] ATtiny22L-1PC ATtiny22L-1SC 8P3 8S2 Commercial (0°C to 70°C) ATtiny22L-1PI ATtiny22L-1SI 8P3 8S2 Industrial (-40°C to 85°C) Package Type 8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 9 Packaging Information 8P3, 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) 8S2, 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA .020 (.508) .012 (.305) .400 (10.16) .355 (9.02) PIN 1 .280 (7.11) .240 (6.10) .300 (7.62) REF .210 (5.33) MAX .037 (.940) .027 (.690) .050 (1.27) BSC .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) .015 (.380) MIN .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .022 (.559) .014 (.356) .013 (.330) .004 (.102) .325 (8.26) .300 (7.62) 0 REF 15 .430 (10.9) MAX 10 .330 (8.38) .300 (7.62) .100 (2.54) BSC SEATING PLANE .012 (.305) .008 (.203) .213 (5.41) .205 (5.21) PIN 1 ATtiny22L 0 REF 8 .035 (.889) .020 (.508) .010 (.254) .007 (.178) Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 e-mail [email protected] Web Site http://www.atmel.com BBS 1-(408) 436-4309 © Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 1273BS–02/00/xM