HT93LC46 CMOS 1K 3-Wire Serial EEPROM Features · Operating voltage: · Automatic erase-before-write operation 2.2V~5.5V for temperature -40°C to +85°C · Word/chip erase and write operation · Low power consumption · Write operation with built-in timer - Operating: 5mA max. - Standby: 2mA max. · Software controlled write protection · 40-year data retention · User selectable internal organization · 106 rewrite cycles per word - 1K(HT93LC46): 128´8 or 64´16 · Industrial temperature range (-40°C to +85°C) · 3-wire Serial Interface · 8-pin DIP/SOP/TSSOP package · Write cycle time: 5ms max. General Description The HT93LC46 is a 1K-bit low voltage nonvolatile, serial electrically erasable programmable read only memory device using the CMOS floating gate process. Its 1024 bits of memory are organized into 64 words of 16 bits each when the ORG pin is connected to VCC or organized into 128 words of 8 bits each when it is tied to VSS. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. By popular microcontroller, the versatile serial interface including chip select (CS), serial clock (SK), data input (DI) and data output (DO) can be easily controlled. Block Diagram C S A d d re s s R e g is te r S K C o n tro l L o g ic a n d C lo c k G e n e ra te r O R G V C C A d d re s s D e c o d e r V S S D I D a ta R e g is te r M e m o r y C e ll A rra y 1 K : (1 2 8 ´ 8 o r 6 4 ´ 1 6 ) O u tp u t B u ffe r D O Pin Assignment C S 1 8 V C C S K 2 7 N C 3 6 O R G 4 5 V S S D I D O 1 8 2 7 V S S C S S K 3 6 D O 4 5 D I O R G H T 9 3 L C 4 6 8 S O P -B H T 9 3 L C 4 6 8 D IP -A /S O P -A /T S S O P -A Rev. 2.00 N C V C C 1 May 6, 2010 HT93LC46 Pin Description Pin Name I/O Description CS I Chip select input SK I Serial clock input DI I Serial data input DO O Serial data output VSS ¾ Negative power supply, ground ORG I Internal Organization When ORG is connected to VDD or ORG is floated, the (´16) memory organization is selected. When ORG is tied to VSS, the (´8) memory organization is selected. There is an internal pull-up resistor on the ORG pin. NC ¾ No connection VCC ¾ Positive power supply Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C Input Voltage.............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Test Conditions VCC Conditions Min. Typ. Max. Unit VCC Operating Voltage ¾ -40°C to +85°C 2.2 ¾ 5.5 V ICC1 Operating Current (TTL) 5V DO unload, SK=1MHz ¾ ¾ 5 mA 5V DO unload, SK=1MHz ¾ ¾ 5 mA 2.2V~5.5V DO unload, SK=250kHz ¾ ¾ 5 mA 2.2V~5.5V CS=SK=DI=0V ¾ ¾ 2 mA ICC2 Operating Current (CMOS) ISTB Standby Current (CMOS) ILI Input Leakage Current 5V VIN=VSS~VCC 0 ¾ 1 mA ILO Output Leakage Current 5V VOUT=VSS~VCC, CS=0V 0 ¾ 1 mA VIL 5V ¾ 0 ¾ 0.8 V Input Low Voltage 2.2V~5.5V ¾ 0 ¾ 0.1VCC V 5V ¾ 2 ¾ VCC V 2.2V~5.5V ¾ 0.9VCC ¾ VCC V VIH VOL VOH Input High Voltage 5V IOL=2.1mA ¾ ¾ 0.4 V 2.2V~5.5V IOL=10mA ¾ ¾ 0.2 V 5V IOH=-400mA 2.4 ¾ ¾ V 2.2V~5.5V IOH=-10mA VCC-0.2 ¾ ¾ V Output Low Voltage Output High Voltage CIN Input Capacitance ¾ VIN=0V, f=250kHz ¾ ¾ 5 pF COUT Output Capacitance ¾ VOUT=0V, f=250kHz ¾ ¾ 5 pF Rev. 2.00 2 May 6, 2010 HT93LC46 A.C. Characteristics Symbol VCC=5V±10% Parameter VCC=2.2V VCC=3V±10% Unit Min. Max. Min. Max. Min. Max. 0 2000 0 1000 0 500 kHz fSK Clock Frequency tSKH SK High Time 250 ¾ 500 ¾ 1000 ¾ ns tSKL SK Low Time 250 ¾ 500 ¾ 1000 ¾ ns tCSS CS Setup Time 50 ¾ 100 ¾ 100 ¾ ns tCSH CS Hold Time 0 ¾ 0 ¾ 0 ¾ ns tCDS CS Deselect Time 250 ¾ 250 ¾ 500 ¾ ns tDIS DI Setup Time 100 ¾ 150 ¾ 200 ¾ ns tDIH DI Hold Time 100 ¾ 150 ¾ 200 ¾ ns tPD1 DO Delay to ²1² ¾ 250 ¾ 500 ¾ 1000 ns tPD0 DO Delay to ²0² ¾ 250 ¾ 500 ¾ 1000 ns tSV Status Valid Time ¾ 250 ¾ 250 ¾ 250 ns DO Disable Time ¾ 100 ¾ 200 ¾ 400 ns Write Cycle Time ¾ 5 ¾ 5 ¾ 5 ms tHZ tPR A.C. Test Conditions V C C = 1 .9 5 2 V Input rise and fall time: 5ns (1V to 2V) Input and output timing reference levels: 1.5V 8 0 0 W Output load: See Figure right D O 1 0 0 p F * * ln c lu d in g s c o p e a n d jig Output Load Circuit C S tC S S tC tS S K tD D I IS t D IH V a lid D a ta tP D O Rev. 2.00 K H D 0 tS K L tC D S S H V a lid D a ta tP D 1 H i- Z 3 May 6, 2010 HT93LC46 Functional Description ERASE The HT93LC46 is accessed via a three-wire serial communication interface. The device is arranged into 64 words by 16 bits or 128 words by 8 bits depending whether the ORG pin is connected to VCC or VSS. The HT93LC46 contains seven instructions: READ, ERASE, WRITE, EWEN, EWDS, ERAL and WRAL. When the user selectable internal organization is arranged into 64´16 (128´8), these instructions are all made up of 9(10) bits data: 1 start bit, 2 op code bits and 6(7) address bits. The ERASE instruction erases data at the specified addresses in the programming enable mode. After the ERASE op-code and the specified address have been issued, the data erase is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signals for the internal erase, so the SK clock is not required. During the internal erase, we can verify the busy/ready status if CS is high. The DO pin will remain low but when the operation is over, the DO pin will return to high and further instructions can be executed. By using the control signal CS, SK and data input signal DI, these instructions can be given to the HT93LC46. These serial instruction data presented at the DI input will be written into the device at the rising edge of SK. During the READ cycle, DO pin acts as the data output and during the WRITE or ERASE cycle, DO pin indicates the BUSY/READY status. When the DO pin is active for read data or as a BUSY/READY indicator the CS pin must be high; otherwise DO pin will be in a high-impedance state. For successful instructions, CS must be low once after the instruction is sent. After power on, the device is by default in the EWDS state. And, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. The following are the functional descriptions and timing diagrams of all seven instructions. WRITE The WRITE instruction writes data into the device at the specified addresses in the programming enable mode. After the WRITE op-code and the specified address and data have been issued, the data writing is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signal for the internal writing, so the SK clock is not required. The auto-timing write cycle includes an automatic erase-before-write capability. So, it is not necessary to erase data before the WRITE instruction. During the internal writing, we can verify the busy/ready status if CS is high. The DO pin will remain low but when the operation is over, the DO pin will return to high and further instructions can be executed. READ The READ instruction will stream out data at a specified address on the DO pin. The data on DO pin changes during the low-to-high edge of SK signal. The 8 bits or 16 bits data stream is preceded by a logical ²0² dummy bit. Irrespective of the condition of the EWEN or EWDS instruction, the READ command is always valid and independent of these two instructions. After the data word has been read the internal address will be automatically incremented by 1 allowing the next consecutive data word to be read out without entering further address data. The address will wrap around with CS High until CS returns to LOW. ERAL The ERAL instruction erases the entire 64´16 or 128´8 memory cells to logical ²1² state in the programming enable mode. After the erase-all instruction set has been issued, the data erase feature is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signal for the erase-all operation, so the SK clock is not required. During the internal erase-all operation, we can verify the busy/ready status if CS is high. The DO pin will remain low but when the operation is over, the DO pin will return to high and further instruction can be executed. EWEN/EWDS WRAL The EWEN/EWDS instruction will enable or disable the programming capabilities. At both the power on and power off state the device automatically entered the disable mode. Before a WRITE, ERASE, WRAL or ERAL instruction is given, the programming enable instruction EWEN must be issued, otherwise the ERASE/WRITE instruction is invalid. After the EWEN instruction is issued, the programming enable condition remains until power is turned off or a EWDS instruction is given. No data can be written into the device in the programming disabled state. By so doing, the internal memory data can be protected. Rev. 2.00 The WRAL instruction writes data into the entire 64´16 or 128´8 memory cells in the programming enable mode. After the write-all instruction set has been issued, the data writing is activated by the falling edge of CS. Since the internal auto-timing generator provides all timing signals for the write-all operation, so the SK clock is not required. During the internal write-all operation, we can verify the busy/ready status if CS is high. The DO pin will remain low but when the operation is over the DO pin will return to high and further instruction can be executed. 4 May 6, 2010 HT93LC46 Timing Diagrams READ tC D S C S S K (1 ) 1 S ta r t b it D I A N 0 A 0 tH H ig h - Z D O 0 D X D 0 Z H ig h - Z D X * * A d d r e s s p o in te r a u to m a tic a lly c y c le s to th e n e x t w o r d M o d e (X 1 6 ) A N A 5 A 6 D X D 1 5 D 7 (X 8 ) EWEN/EWDS C S S ta n d b y S K D I 0 (1 ) S ta r t b it 0 1 1 = E W E N 0 0 = E W D S WRITE tC C S D S v e r ify S ta n d b y S K D I 0 (1 ) S ta r t b it 1 A N A N -1 A N -2 A 1 A 0 D X D 0 tS H ig h - Z D O Z re a d y b u s y tP tH V R ERASE tC C S D S v e r ify S ta n d b y S K D I D O Rev. 2.00 1 (1 ) S ta r t b it 1 A N A N -1 A N -2 A 1 A 0 tS H ig h - Z tP 5 b u s y tH V Z re a d y R May 6, 2010 HT93LC46 ERAL tC C S D S v e r ify S ta n d b y S K 0 (1 ) S ta r t b it D I 0 1 0 tS H ig h - Z D O tP tH V Z re a d y b u s y R WRAL tC C S D S v e r ify S ta n d b y S K 0 (1 ) S ta r t b it D I 0 0 1 D X D 0 tS H ig h - Z D O b u s y tP tH V Z re a d y R Instruction Set Summary Instruction Comments Start bit Op Code Address ORG=0 ORG=1 X8 X16 Data ORG=0 ORG=1 X8 X16 READ Read data 1 10 A6~A0 A5~A0 D7~D0 D15~D0 ERASE Erase data 1 11 A6~A0 A5~A0 ¾ WRITE Write data 1 01 A6~A0 A5~A0 D7~D0 D15~D0 EWEN Erase/Write Enable 1 00 11XXXXX 11XXXX ¾ EWDS Erase/Write Disable 1 00 00XXXXX 00XXXX ¾ ERAL Erase All 1 00 10XXXXX 10XXXX ¾ WRAL Write All 1 00 01XXXXX 01XXXX D7~D0 D15~D0 Note: ²X² stands for ²don¢t care² Data should be written to the EEPROM in the format (8-bit or 16-bit mode) in which it is to be read. Rev. 2.00 6 May 6, 2010 HT93LC46 Package Information 8-pin DIP (300mil) Outline Dimensions A 8 5 B 1 4 H C D I G E F Symbol Nom. Max. A 0.355 ¾ 0.375 B 0.240 ¾ 0.260 C 0.125 ¾ 0.135 D 0.125 ¾ 0.145 E 0.016 ¾ 0.020 0.070 F 0.050 ¾ G ¾ 0.100 ¾ H 0.295 ¾ 0.315 I ¾ 0.375 ¾ Symbol A Rev. 2.00 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 9.02 ¾ 9.53 B 6.10 ¾ 6.60 C 3.18 ¾ 3.43 D 3.18 ¾ 3.68 E 0.41 ¾ 0.51 F 1.27 ¾ 1.78 G ¾ 2.54 ¾ H 7.49 ¾ 8.00 I ¾ 9.53 ¾ 7 May 6, 2010 HT93LC46 8-pin SOP (150mil) Outline Dimensions 5 8 A B 4 1 C C ' G H D E a F · MS-012 Symbol Nom. Max. A 0.228 ¾ 0.244 B 0.150 ¾ 0.157 C 0.012 ¾ 0.020 C¢ 0.188 ¾ 0.197 D ¾ ¾ 0.069 E ¾ 0.050 ¾ F 0.004 ¾ 0.010 G 0.016 ¾ 0.050 H 0.007 ¾ 0.010 a 0° ¾ 8° Symbol A Rev. 2.00 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 5.79 ¾ 6.20 B 3.81 ¾ 3.99 C 0.30 ¾ 0.51 C¢ 4.78 ¾ 5.00 D ¾ ¾ 1.75 E ¾ 1.27 ¾ F 0.10 ¾ 0.25 G 0.41 ¾ 1.27 H 0.18 ¾ 0.25 a 0° ¾ 8° 8 May 6, 2010 HT93LC46 8-pin TSSOP Outline Dimensions 8 5 E 1 1 4 E D A L A 2 e R 0 .1 0 A 1 B C L 1 y q (4 C O R N E R S ) Symbol Min. Nom. Max. A 0.041 ¾ 0.047 A1 0.002 ¾ 0.006 A2 0.031 ¾ 0.041 B ¾ 0.010 ¾ C 0.004 ¾ 0.006 D 0.114 ¾ 0.122 E 0.244 ¾ 0.260 E1 0.169 ¾ 0.177 e ¾ 0.026 ¾ L 0.020 ¾ 0.028 L1 0.035 ¾ 0.043 y ¾ ¾ 0.004 q 0° ¾ 8° Symbol Rev. 2.00 Dimensions in inch Dimensions in mm Min. Nom. Max. A 1.05 ¾ 1.20 A1 0.05 ¾ 0.15 A2 0.80 ¾ 1.05 B ¾ 0.25 ¾ C 0.11 ¾ 0.15 D 2.90 ¾ 3.10 E 6.20 ¾ 6.60 E1 4.30 ¾ 4.50 e ¾ 0.65 ¾ L 0.50 ¾ 0.70 L1 0.90 ¾ 1.10 y ¾ ¾ 0.10 q 0° ¾ 8° 9 May 6, 2010 HT93LC46 Product Tape and Reel Specifications Reel Dimensions D T 2 A C B T 1 SOP 8N, TSSOP 8L Symbol Description A Reel Outer Diameter Dimensions in mm 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter 13.0+0.5/-0.2 D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.00 2.0±0.5 12.8+0.3/-0.2 18.2±0.2 10 May 6, 2010 HT93LC46 Carrier Tape Dimensions P 0 D P 1 t E F W C D 1 P B 0 K 0 A 0 R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . SOP 8N Symbol Description Dimensions in mm 12.0+0.3/-0.1 W Carrier Tape Width P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 5.5±0.1 D Perforation Diameter 1.55±0.10 D1 Cavity Hole Diameter 1.50+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.4±0.1 B0 Cavity Width 5.2±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness C Cover Tape Width 0.30±0.05 9.3±0.1 TSSOP 8L Symbol Description W Carrier Tape Width P Cavity Pitch E Perforation Position Dimensions in mm 12.0+0.3/-0.1 8.0±0.1 1.75±0.10 F Cavity to Perforation (Width Direction) D Perforation Diameter 1.5+0.1/-0.0 D1 Cavity Hole Diameter 1.5+0.1/-0.0 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 7.0±0.1 B0 Cavity Width 3.6±0.1 K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.00 5.5±0.5 1.6±0.1 0.300±0.013 9.3±0.1 11 May 6, 2010 HT93LC46 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.00 12 May 6, 2010