ON LC87F17C8A Lc87f17c8a Datasheet

LC87F17C8A
CMOS LSI
8-bit Microcontroller with
USB Full-Speed Host/Device Controller
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128K-byte Flash ROM / 8192-byte RAM / 48-pin
Feature
 USB 2.0 Full Speed Host/Device Controller  2 ports
 Digital Audio Interface
 Infrared Remote Control Receiver
 12-bit ADC  12 channels
 USB Voltage Regulator Integrated
 Power-ON Reset/Low-Voltage Detect Reset
Function Descriptions
P24/INT7/SCK4
P23/INT4/SI4
P22/INT4/SO4
P21/INT4
P20/INT4/INT6
P07/AN7/T7O/LRCK
P06/AN6/T6O/BCLK
P05/AN5/CKO/SDAT
P04/AN4/LRCK_IN
32
31
30
29
28
27
26
25
OWP0
UBD-
33
34
35
36
UBD+
SQFP48(7X7)
37
24
P03/AN3/BCLK_IN
38
23
P02/AN2/SDAT_IN
39
22
P01/AN1
40
21
41
20
P00/AN0/SDATI
VSS2
42
19
VDD2
18
PWM0/MCLKO
LC87F17C8A
43
10
11
12
P12/SCK0
P13/SO1/SM1CK
9
P10/SO0
8
VDD1
P11/SI0/SB0
7
CF2
2
1
6
P14/SI1/SB1/SM1DA
CF1
13
5
P15/SCK1/SM0DO/SM1DO
48
4
14
VSS1
P16/T1PWML/SM0DA
47
XT2/AN11
P17/T1PWMH/BUZ/SM0CK
15
3
PWM1/MCLKI
16
46
XT1/AN10
17
45
44
P73/INT3/T0IN/RMIN
RES
1) Ports
- I/O ports
31
- USB ports 4 (UAD+, UAD–, UBD+, UBD–)
- Power supply pins 6 (VSS1 to 3, VDD1 to 3)
2) Timers  7 channels
- Timer 0 : 16-bit timer/counter with 2 capture registers.
- Timer 1 : 16-bit timer/counter that supports PWM/toggle output
- Timer 4 : 8-bit timer with a 6-bit prescaler
- Timer 5 : 8-bit timer with a 6-bit prescaler
- Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
- Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
- Base timer for Watch (32.768kHz crystal oscillation)
UAD3) SIO  5 channels
UAD+
- SIO0 : Synchronous serial interface
VDD3
VSS3
Automatic continuous data transmission
UFILT
AFILT
- SIO1 : 8-bit asynchronous/synchronous serial interface
P32/INT5
- SIO4 : CRC16 calculator circuit built in
P31/SCRX/INT5
2
P30/SCTX/INT5
- SMIIC0 : Single-master I C/8-bit synchronous SIO
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
- SMIIC1 : Single-master I2C/8-bit synchronous SIO
P72/INT2/T0IN
4) Full Duplex UART
- SCUART2 : 8-level receive FIFO buffer
5) PWM: Variable frequency 12-bit PWM  2 channels
6) USB Controller
- Host
: Supports Full-Speed and Low-Speed
- Device : Supports up to 9 endpoints. Full-Speed.
7) Digital Audio Interface
- fs : 8kHz/11.025kHz/12kHz/16kHz/22.05kHz/24kHz/32kHz/44.1kHz/48kHz/96kHz
- Left justified/right justified/ I2S format selectable
8) Infrared Remote Controller Receiver
- Supports data encoding systems such as PPM and Manchester encoding.
Pin Assignment
(Top view)
Application
 iPod/iPhone Docking Station
* iPod and iPhone are trademarks of Apple Inc., registered in the U.S. and other countries.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 36 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November 2014 - Rev. 0
1
Publication Order Number :
LC87F17C8A/D
LC87F17C8A
■ Ports
 I/O ports
 USB ports
 Dedicated oscillator ports
 Input-only port (also used for the oscillator)
 PLL filter pins
 Reset pin
 Debugger-dedicated pin
 Power supply pins
31 (P00 to P07, P10 to P17, P20 to P24, P30 to P32,
P70 to P73, PWM0, PWM1, XT2)
4 (UAD+, UAD–, UBD+, UBD–)
2 (CF1, CF2)
1 (XT1)
2 (UFILT, AFILT)
1 (RES)
1 (OWP0)
6 (VSS1 to 3, VDD1 to 3)
■ Timers
 Timer 0 : 16-bit timer/counter with 2 capture registers
Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)  2 channels
Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter
(with two 8-bit capture registers)
Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3 : 16-bit counter (with two 16-bit capture registers)
 Timer 1 : 16-bit timer/counter that supports PWM/toggle output
Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle output) + 8-bit timer/counter with an 8-bit prescaler
(with toggle output)
Mode 1 : 8-bit PWM with an 8-bit prescaler  2 channels
Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle output)
(Toggle output also possible from low-order 8 bits.)
Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle output)
(Low-order 8 bits can be used as a PWM output.)
 Timer 4 : 8-bit timer with a 6-bit prescaler
 Timer 5 : 8-bit timer with a 6-bit prescaler
 Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle output)
 Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle output)
 Base timer
<1> The clock can be selected from among a subclock (32.768 kHz crystal oscillator), low-speed RC
oscillator clock, system clock, and timer 0 prescaler output.
<2> Interrupts programmable in 5 different time schemes.
■ Serial
Interfaces
 SIO0 : Synchronous serial interface
<1> LSB first/MSB first selectable
<2> Transfer clock cycle : 4/3 to 512/3 tCYC
<3> Continuous automatic data transmission (1 to 256 bits can be specified in 1-bit units)
(Suspension and resumption of data transfer possible in 1-byte units)
 SIO1 : 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clock)
Mode 1 : Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrate)
Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clock)
Mode 3 : Bus mode 2 (start detection, 8 data bits, stop detection)
 SIO4 : Synchronous serial interface
<1> LSB first/MSB first selectable
<2> Transfer clock cycle : 4/3 to 1020/3 tCYC
<3> Continuous automatic data transmission (1 to 8192 bytes can be specified in 1-byte units)
(Suspension and resumption of data transmission possible in 1-byte units or in word units)
<4> Clock polarity can be selected.
<5> CRC16 calculator circuit built- in
 SMIIC0 : Single-master I2C/8-bit synchronous SIO
Mode 0 : Communication in single-master mode.
Mode 1 : 8-bit synchronous serial I/O (data MSB first)
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LC87F17C8A
 SMIIC1 : Single-master I2C/8-bit synchronous SIO
Mode 0 : Communication in single-master mode.
Mode 1 : 8-bit synchronous serial I/O (data MSB first)
■ Full
Duplex UART
 SCUART2
<1> Data length : 7/8 bits selectable
<2> Stop bits
: 1/2 bits selectable
<3> Parity bits
: None/even parity/odd parity selectable
<4> Baudrate
: 8/3 to 8192/3 tCYC
<5> LSB first/MSB first mode selectable
<6> Capable of Smart card interface
<7> 8-level receive FIFO buffer
■16-bit
Cyclic Redundancy Check (CRC) Calculator
<1> User-programmable CRC polynomial equation
<2> 1 to 256 bytes can be specified
<3> LSB first/MSB first selectable
■ AD
Converter: 12 bits × 12 channels
■ PWM: Variable
■ Infrared
frequency 12-bit PWM × 2 channels
Remote Control Receiver Circuit
<1> Noise rejection function (noise filter time constant: Approx. 120s when the 32.768 kHz crystal oscillator
is selected as the reference clock)
<2> Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding.
<3> X'tal HOLD mode release function
■ USB
Interface
 Host Controller × 2 ports
<1> Supports Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) operation.
<2> Supports four transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer).
 Device Controller
<1> Supports Full-Speed operation.
<2> Supports up to 9 endpoints
EP0
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
Transfer
Control

-
-
-
-
-
-
-
-
Type
Bulk
-








Interrupt
-








Isochronous
-








64
64
64
64
64
64
64
1023
1023
Endpoint
Max. payload
■ Audio
Interface
<1> Sampling frequencies (fs) : 8 kHz/11.025 kHz/12 kHz/16 kHz/22.05 kHz/24 kHz/32 kHz/44.1 kHz/48 kHz/96kHz
<2> Master clock : 256 fs/384 fs
<3> Bit clock
: 48 fs/64 fs
<4> Data bit length : 16 bits/18 bits/20 bits/24 bits
<5> LSB first/MSB first selectable.
<6> Left justified/right justified/I2S format selectable
■ Watchdog Timer
 Internal counter watchdog timer
<1> Capable of generating an internal reset on an overflow of the timer running on the low-speed RC
oscillator clock, or subclock.
<2> Operation in HALT/HOLD mode can be selected from among “continue count operation,” “suspend
operation,” and “retain the count value.”
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LC87F17C8A
■ Clock
Output Function
<1> Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock
selected as the system clock.
<2> Can output the source oscillator clock for the subclock.
■ Interrupts
 49 sources, 10 vectors
<1> Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt
request of the level equal to or lower than the current interrupt level is not accepted.
<2> When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the
highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt
into the lowest vector address is given priority.
No.
Vector
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/UHC-A bus active/UHC-B bus active/USB bus active/remote control receive
4
0001BH
H or L
INT3/INT5/base timer/AIF asynchronous counter
5
00023H
H or L
T0H/INT6/UHC-A device connected, disconnected, resumed/SMIIC1
6
0002BH
H or L
T1L/T1H/INT7/AIF start/SMIIC0/UHC-B device connected, disconnected, resumed/
AIF FIFO empty
7
00033H
H or L
SIO0/USB bus reset/USB suspend/SCUART2 receive completed/SCUART2 receive FIFO full
8
0003BH
H or L
SIO1/SIO4/USB endpoint/USB-SOF/
9
00043H
H or L
ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC-STALL
10
0004BH
H or L
Port 0/PWM0/PWM1/T4/T5/UHC-SOF/CRC
SCUART2 buffer empty/SCUART2 transmission completed/AIF end
 Priority levels X > H > L
 When interrupts of the same level occur at the same time, the interrupt with the lowest vector address is given
priority.
■ Subroutine
Stack Levels : Up to 4096 levels (The stack is allocated in RAM.)
■ High-speed
Multiplication/Division Instructions
 16 bits × 8 bits (5 tCYC execution time)
 24 bits × 16 bits (12 tCYC execution time)
 16 bits ÷ 8 bits (8 tCYC execution time)
 24 bits ÷ 16 bits (12 tCYC execution time)
■ Oscillator
Circuit and PLL
 Medium-speed RC oscillator circuit (internal) : For system clock (approx. 1 MHz)
 Low-speed RC oscillator circuit (internal)
: For system clock, timer, and watchdog timer (approx. 30 kHz)
 CF oscillator circuit
: For system clock
 Crystal oscillator circuit
: For system clock and time-of-day clock
 PLL circuit (internal)
: For USB interface (see Fig. 5) and audio interface (see Fig. 6)
■ Internal
Reset Functions
 Power-on reset (POR) function
<1> POR is activated at power-on.
<2> POR release voltage can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V,
and 4.35V) by setting options.
 Low voltage detection reset (LVD) function
<1> LVD and POR functions are combined to generate resets when power is turned on and when power
voltage falls below a threshold level.
<2> The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V,
2.51V, 2.81V, 3.79V, and 4.28V) can be selected by setting options.
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LC87F17C8A
■ Standby
Function
 HALT mode : Halts instruction execution while allowing the peripheral circuits to continue operation.
(1) Oscillators do not stop automatically.
(2) There are three ways of releasing HOLD mode.
<1> Setting the reset pin to a low level.
<2> Generating a reset signal by watchdog timer or low-voltage detection
<3> Occurrence of an interrupt
 HOLD mode : Suspends instruction execution and operation of the peripheral circuits.
(1) The PLL, CF, RC and crystal oscillators automatically stop operation.
Note : Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in
standby mode is also controlled.
(2) There are five ways of releasing HOLD mode.
<1> Setting the reset pin to a low level
<2> Generating a reset signal by the watchdog timer or low-voltage detection
<3> Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins
* INT0 and INT1 HOLD mode release is available only when level detection is configured.
<4> Establishing an interrupt source at port 0
<5> Establishing an bus active interrupt source in the USB host control circuit
 X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the base
timer and infrared remote control receiver circuit.
(1) The PLL, CF and RC oscillators automatically stop operation.
Note : Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in
standby mode is also controlled.
Note : The low-speed RC oscillator retains the state that is established on entry into X'tal HOLD mode
if the base timer is running with the low-speed RC oscillator selected as the base timer input
clock source.
(2) The state of crystal oscillator established when the X'tal HOLD mode is entered is retained.
(3) There are seven ways of releasing X'tal HOLD mode.
<1> Setting the reset pin to a low level
<2> Generating a reset signal by the watchdog timer or low-voltage detection
<3> Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins
* INT0 and INT1 X’tal HOLD mode release is available only when level detection is configured.
<4> Establishing an interrupt source at port 0
<5> Establishing an interrupt source in the base timer circuit
<6> Establishing an interrupt source in the infrared remote control receiver circuit
<7> Establishing an bus active interrupt source in the USB host control circuit
■ Package
Form
 SQFP48(7×7)
Pb-Free and Halogen Free product
■ Development Tools
 On-chip debugger : TCB87-Type C (1-wire communication cable) + LC87F17C8A
■ Flash
ROM Programming Board
Package
Programming Board
SQFP48 (7×7)
W87F55256SQ
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LC87F17C8A
■ Flash
ROM Programmer
Maker
Flash Support Group
Company (FSG)
Single
Model
Supported Version
Device
AF9709C
Rev. 03.28 or later
87F128JU
(Note 2)
LC87F17C8A
AF9101/AF9103 (main unit)
Flash Support Group
Company (FSG)
Onboard
(FSG model)
+
single/ganged
SIB87 Type C (interface driver)
Our company (Note 1)
(Our company model)
Single/ganged
Our company
SKK/SKK Type C
(SanyoFWS)
Application version
1.08 and later
Onboard
SKK-DBG Type C
Chip data version
single/ganged
(SanyoFWS)
2.47 and later
LC87F17C8
(Further information on the AF series)
Flash Support Group Company (TOA ELECTRONICS, Inc.)
Phone: 053-459-1050
E-mail: sales@j- fsg.co.jp
Note 1 : PC-less standalone onboard programming is possible using the FSG onboard programmer
(AF9101/AF9103) and the serial interface driver (SIB87 Type C) provided by our company in pair.
Note 2 : Dedicated programming device and program are required depending on the programming conditions.
Contact our company or FSG if you have any questions or difficulties regarding this matter.
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LC87F17C8A
Package Dimensions
unit : mm
SPQFP48 7x7 / SQFP48
CASE 131AJ
ISSUE A
0.5 0.2
9.0 0.2
9.0 0.2
48
7.0 0.1
7.0 0.1
1 2
0.5
0.15 0.05
0.18
0.10
(1.5)
0 to 10
0.1 0.1
1.7 MAX
(0.75)
0.10
SOLDERING FOOTPRINT*
GENERIC
MARKING DIAGRAM*
8.40
XXXXXXXX
YDD
8.40
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
DD = Additional Traceability Data
XXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
0.28
may or may not be present.
1.00
0.50
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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LC87F17C8A
37
38
39
40
41
42
43
44
45
46
47
48
LC87F17C8A
24
23
22
21
20
19
18
17
16
15
14
13
P03/AN3/BCLK_IN
P02/AN2/SDAT_IN
P01/AN1
P00/AN0/SDATI
VSS2
VDD2
PWM0/MCLKO
PWM1/MCLKI
P17/T1PWMH/BUZ/SM0CK
P16/T1PWML/SM0DA
P15/SCK1/SM0DO/SM1DO
P14/SI1/SB1/SM1DA
P73/INT3/T0IN/RMIN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1/SM1CK
1
2
3
4
5
6
7
8
9
10
11
12
UADUAD+
VDD3
VSS3
UFILT
AFILT
P32/INT5
P31/SCRX/INT5
P30/SCTX/INT5
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
36
35
34
33
32
31
30
29
28
27
26
25
UBD+
UBDOWP0
P24/IINT7/SCK4
P23/INT4/SI4
P22/INT4/SO4
P21/INT4
P20/INT4/INT6
P07/AN7/T7O/LRCK
P06/AN6/T6O/BCLK
P05/AN5/CKO/SDAT
P04/AN4/LRCK_IN
Pin Assignment
Top view
SQFP48(7×7) (Pb-Free and Halogen Free product)
SQFP48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NAME
P73/INT3/T0IN/RMIN
RES
SQFP48
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1/SM1CK
P14/SI1/SB1/SM1DA
P15/SCK1/SM0DO/SM1DO
P16/T1PWML/SM0DA
P17/T1PWMH/BUZ/SM0CK
PWM1/MCLKI
PWM0/MCLKO
VDD2
VSS2
P00/AN0/SDATI
P01/AN1
P02/AN2/SDAT_IN
P03/AN3/BCLK_IN
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NAME
P04/AN4/LRCK_IN
P05/AN5/CKO/SDAT
P06/AN6/T6O/BCLK
P07/AN7/T7O/LRCK
P20/INT4/INT6
P21/INT4
P22/INT4/SO4
P23/INT4/SI4
P24/INT7/SCK4
OWP0
UBD
UBD+
UAD
UAD+
VDD3
VSS3
UFILT
AFILT
P32/INT5
P31/SCURX/INT5
P30/SCUTX/INT5
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
LC87F17C8A
System Block Diagram
Interrupt control
Standby control
ROM
CF
USB PLL
RC
Clock
generator
X’tal
PC
RES
Reset circuit
(LVD/POR)
ACC
Reset control
WDT
PLA
IR
B register
C register
SIO0
Bus interface
SIO1
Port 0
SIO4
Port 1
PSW
SMIIC0
Port 2
RAR
SMIIC1
Port 3
RAM
Timer 0
Port 7
Stack pointer
Timer 1
INT0 to INT7
Noise filter
Watchdog timer
Timer 4
SCUART2
Timer 5
Audio interface
Timer 6
ADC
Timer 7
USB host
Base timer
USB device
PWM0
IFR control
receiver circuit
PWM1
CRC
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ALU
On-chip debugger
LC87F17C8A
Pin Description
Pin Name
I/O
Description
Option
VSS1, VSS2,
VSS3
-
power supply
No
VDD1, VDD2
-
+power supply
No
VDD3
-
USB reference voltage
Yes
Port 0
I/O
 8-bit I/O port
Yes
 I/O can be specified in 1-bit units
P00 to P07
 Pull-up resistors can be turned on and off in 1-bit units.
 HOLD release input
 Port 0 interrupt input
 Pin functions
AD converter input port : AN0 to AN7 (P00 to P07)
P00 : audio interface SDAT input
P02 : audio through SDAT input
P03 : audio through BCLK input
P04 : audio through LRCK input
P05 : System clock output / audio interface SDAT I/O
P06 : Timer 6 toggle output / audio interface BCLK I/O
P07 : Timer 7 toggle output / audio interface LRCK I/O
Port 1
I/O
 8-bit I/O port
Yes
 I/O can be specified in 1-bit units
P10 to P17
 Pull-up resistors can be turned on and off in 1-bit units.
 Pin functions
P10 : SIO0 data output
P11 : SIO0 data input / bus I/O
P12 : SIO0 clock I/O
P13 : SIO1 data output / SMIIC1 clock I/O
P14 : SIO1 data input / bus I/O / SMIIC1 bus I/O / data input
P15 : SIO1 clock I/O / SMIIC0 data output (used in 3-wire SIO mode) /
SMIIC1 data output (used in 3-wire SIO mode)
P16 : Timer 1 PWML output / SMIIC0 bus I/O / data input
P17 : Timer 1 PWMH output / buzzer output / SMIIC0 clock I/O
Port 2
P20 to P24
I/O
 5-bit I/O port
Yes
 I/O can be specified in 1-bit units
 Pull-up resistors can be turned on and off in 1-bit units.
 Pin functions
P20 to P23 : INT4 input / HOLD release input / timer 1 event input /
timer 0L capture input / timer 0H capture input
P20 : INT6 input / timer 0L capture 1 input
P22 : SIO4 data I/O
P23 : SIO4 data I/O
P24 : INT7 input / timer 0H capture 1 input / SIO4 clock I/O
Interrupt acknowledge types
Rising
Falling
INT4
Enable
Enable
INT6
Enable
INT7
Enable
Rising &
H Level
L Level
Enable
Disable
Disable
Enable
Enable
Disable
Disable
Enable
Enable
Disable
Disable
Falling
Continued on next page.
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10
LC87F17C8A
Continued from preceding page.
Pin Name
Port 3
I/O
I/O
Description
Option
 3-bit I/O port
Yes
 I/O can be specified in 1-bit units
P30 to P32
 Pull-up resistors can be turned on and off in 1-bit units.
 Pin functions
P30 to P32 : INT5 input / HOLD release input / timer 1 event input /
timer 0L capture input / timer 0H capture input
P30 : SCUART2 transmit
P31 : SCUART2 receive
Interrupt acknowledge types
INT5
Port 7
I/O
Rising
Falling
Enable
Enable
Rising &
Falling
Enable
H Level
L Level
Disable
Disable
 4-bit I/O port
No
 I/O can be specified in 1-bit units
P70 to P73
 Pull-up resistors can be turned on and off in 1-bit units.
 Pin functions
P70 : INT0 input / HOLD release input / timer 0L capture input
P71 : INT1 input / HOLD release input / timer 0H capture input
P72 : INT2 input / HOLD release input / timer 0 event input /
timer 0L capture input / high-speed clock counter input
P73 : INT3 input (input with noise filter) / timer 0 event input /
timer 0H capture input / infrared remote control receiver input
AD converter input port: AN8 (P70), AN9 (P71)
Interrupt acknowledge types
PWM0
I/O
PWM1
Rising
Falling
INT0
Enable
Enable
INT1
Enable
INT2
INT3
Rising &
H Level
L Level
Disable
Enable
Enable
Enable
Disable
Enable
Enable
Enable
Enable
Enable
Disable
Disable
Enable
Enable
Enable
Disable
Disable
Falling
No
PWM0 and PWM1 output port
General-purpose input port
 Pin functions
PWM0 : Audio interface master clock output
PWM1 : Audio interface master clock input
UAD
I/O
USB-A port data I/O pin
No
I/O
USB-B port data I/O pin
No
UAD+
UBD
UBD+
UFILT
I/O
USB interface PLL filter circuit connection pin (see Fig.5)
No
AFILT
I/O
Audio interface PLL filter circuit connection pin (see Fig.6)
No
RES
I/O
External reset input / internal reset output
No
XT1
I
 32.768 kHz crystal resonator input
No
 Pin functions
General-purpose input port
AD converter input port: AN10
XT2
I/O
No
 32.768 kHz crystal resonator output
 Pin functions
General-purpose I/O port
AD converter input port: AN11
CF1
I
Ceramic/crystal resonator input
No
CF2
O
Ceramic/crystal resonator output
No
OWP0
I/O
Dedicated debugger port
No
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11
LC87F17C8A
On-chip Debugger Pin Treatment
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87
On-chip Debugger Installation Manual."
Recommended Unused Pin Treatment
Recommended Unused Pin Treatment
Pin Name
Board
Software
P00 to P07
Open
Set output low.
P10 to P17
Open
Set output low.
P20 to P24
Open
Set output low.
P30 to P32
Open
Set output low.
P70 to P73
Open
Set output low.
PWM0, PWM1
Open
Set output low.
UAD+, UAD
Open
Set output low.
UBD+, UBD
Open
Set output low.
XT1
Pull-down with a resistor of 100kΩ or lower.
-
XT2
Open
Set output low.
OWP0
Pull-down with a 100kΩ resistor.
-
Port Output Types
The table below lists the type of port output and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in output mode.
Port Name
P00 to P07
Option Selected
Option Type
in Units of
1 bit
P10 to P17
P20 to P24
Output Type
Pull-up Resistor
1
CMOS
Programmable
2
N-channel open drain
Programmable
P30 to P32
P70
-
No
N-channel open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
PWM0, PWM1
-
No
CMOS
No
UAD+, UAD
-
No
CMOS
No
XT1
-
No
Input only
No
XT2
-
No
32.768kHz crystal resonator output
No
UBD+, UBD
(N-channel open drain when in
general-purpose output mode)
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12
LC87F17C8A
User Option Table
Option Name
Port output type
Program start
address
USB regulator
Option to be
1 bit
P10 to P17
○
1 bit
P20 to P24
○
1 bit
P30 to P32
○
1 bit
-
○
-
USB regulator
USB regulator
(HALT mode)
function
Power-on reset
function
Detection function
Detection level
Power-on reset level
○
-
○
-
○
-
○
○
○
-
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13
Option Selection
in Units of
○
(HOLD mode)
detection reset
Option Selected
P00 to P07
USB regulator
Low-voltage
Flash-ROM Version
Applied on
CMOS
N-channel open drain
CMOS
N-channel open drain
CMOS
N-channel open drain
CMOS
N-channel open drain
00000h
1FE00h
Use
Non-use
Use
Non-use
Use
Non-use
Enable : Use
Disable : Non-use
-
7 levels
-
8 levels
LC87F17C8A
USB Reference Power Option
When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the
reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can
be switched by selecting an option. The procedure for making the option selection is described below.
(1)
Option settings
Reference voltage circuit state
(2)
(3)
(4)
USB regulator
Use
Use
Use
Non-use
USB regulator at HOLD mode
Use
Non-use
Non-use
Non-use
USB regulator at HALT mode
Use
Non-use
Use
Non-use
Normal mode
Active
Active
Active
Inactive
HOLD mode
Active
Inactive
Inactive
Inactive
HALT mode
Active
Inactive
Active
Inactive
• When the USB reference voltage circuit is made inactive, the level of the reference voltage for the USB port
output is equal to VDD1.
• Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
• When the reference voltage circuit is activated, the current drain increases by approximately 100µA compared
with when the reference voltage circuit is inactive.
Example 1 : VDD1=VDD2=3.3V
• Inactivating the reference voltage circuit (selection (4)).
• Connecting VDD3 to VDD1 and VDD2.
IC
Power supply
3.3V
UAD+
/UBD+
VDD1
UAD/UBD-
VDD2
VDD3
To USB connector
27 to 33
UFILT
100
VSS1 VSS2 VSS3
2.2F
Example 2 : VDD1=VDD2=5.0V
• Activating the reference voltage circuit (selection (1)).
• Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS.
IC
UAD+
/UBD+
VDD1
Power supply
5V
2.2F
VDD2
UAD/UBD-
VDD3
UFILT
27 to 33
To USB connector
100
VSS1 VSS2 VSS3
2.2F
Note : Do not apply the voltage of more than 3.6V to UAD+, UAD, UBD+
and UBD when the reference voltage circuit is active.
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14
LC87F17C8A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
VDD max
VDD1, VDD2, VDD3
Input voltage
VI(1)
XT1, CF1, RES
Input/output
VIO(1)
Ports 0, 1, 2, 3, 7
Conditions
VDD[V]
Maximum supply
VDD1=VDD2=VDD3
voltage
voltage
PWM0, PWM1,
min
typ
max
unit
0.3
+6.5
0.3
VDD+0.3
0.3
VDD+0.3
V
XT2
Peak output
IOPH(1)
Ports 0, 1, 2
current
• When CMOS output
type is selected
10
• Per 1 applicable pin
IOPH(2)
PWM0, PWM1
• Per 1 applicable pin
IOPH(3)
Port 3
• When CMOS output
P71 to P73
type is selected
20
5
• Per 1 applicable pin
High level output current
Average
IOMH(1)
Ports 0, 1, 2
output current
• When CMOS output
type is selected
(Note 1-1)
7.5
• Per 1 applicable pin
IOMH(2)
IOMH(3)
PWM0, PWM1
Per 1 applicable pin
Port 3
• When CMOS output
P71 to P73
type is selected
15
3
• Per 1 applicable pin
Total output
IOAH(1)
Ports 0, 2
current
IOAH(2)
IOAH(3)
IOAH(4)
IOAH(5)
Peak output
Total current of all
applicable pins
IOPL(1)
current
Port 1
Total current of all
PWM0, PWM1
applicable pins
Ports 0, 1, 2
Total current of all
PWM0, PWM1
applicable pins
Port 3
Total current of all
P71 to P73
applicable pins
UAD+, UAD
Total current of all
UBD+, UBD
applicable pins
P02 to P07
Per 1 applicable pin
25
25
45
10
50
mA
Ports 1, 2
20
PWM0, PWM1
IOPL(2)
P00, P01
Per 1 applicable pin
IOPL(3)
Ports 3, 7
Per 1 applicable pin
30
10
XT2
Low level output current
Average
IOML(1)
P02 to P07
output current
Ports 1, 2
(Note 1-1)
PWM0, PWM1
IOML(2)
IOML(3)
Per 1 applicable pin
15
P00, P01
Per 1 applicable pin
Ports 3, 7
Per 1 applicable pin
20
7.5
XT2
Total output
IOAL(1)
Ports 0, 2
current
Total current of all
45
applicable pins
IOAL(2)
IOAL(3)
IOAL(4)
IOAL(5)
Port 1
Total current of all
PWM0, PWM1
applicable pins
Ports 0, 1, 2
Total current of all
PWM0, PWM1
applicable pins
Ports 3, 7
Total current of all
XT2
applicable pins
UAD+, UAD
Total current of all
UBD+, UBD
applicable pins
45
80
15
50
Note 1-1 : The average output current is an average of current values measured over 100ms intervals.
Continued on next page.
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15
LC87F17C8A
Continued from preceding page.
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Allowable power
Pd max
SQFP48(77)
min
typ
max
Ta=40 to +85°C
140
dissipation
Operating ambient
Topr
Temperature
Storage ambient
unit
40
+85
55
+125
mW
°C
Tstg
temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Conditions at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Operating
VDD(1)
VDD1=VDD2=VDD3
supply voltage
0.245s ≤ tCYC ≤ 200s
0.245s ≤ tCYC ≤ 0.383s
(Note 2-1)
USB circuit active.
min
typ
max
unit
3.0
5.5
3.0
5.5
2.7
5.5
2.0
5.5
0.490s ≤ tCYC ≤ 200s
Except for onboard
programming mode
Memory retention
VHD
VDD1=VDD2=VDD3
supply voltage
High level
are retained in HOLD mode
VIH(1)
input voltage
Low level
RAM and register contents
Ports 0, 1, 2, 3, 7
2.7 to 5.5
PWM0, PWM1
VIH(2)
XT1, XT2, CF1, RES
VIL(1)
Ports 1, 2, 3, 7
input voltage
VIL(2)
VIL(3)
Port 0
PWM0, PWM1
VIL(4)
VIL(5)
Instruction
cycle time
(Note 2-2)
XT1, XT2, CF1, RES
tCYC
USB circuit active.
Except for onboard
programming mode
0.3VDD
+0.7
VDD
2.7 to 5.5
0.75VDD
VDD
4.0 to 5.5
VSS
2.7 to 4.0
VSS
4.0 to 5.5
VSS
2.7 to 4.0
VSS
0.2VDD
2.7 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.245
200
3.0 to 5.5
0.245
0.383
2.7 to 5.5
0.490
200
V
0.1VDD
+0.4
0.2VDD
0.15VDD
+0.4
s
Note 2-1 : VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2 : Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF
at a division ratio of 1/2.
Continued on next page.
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16
LC87F17C8A
Continued from preceding page.
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
External
FEXCF(1)
CF1
min
typ
max
unit
• CF2 pin open
• System clock frequency
system clock
division ratio =1/1
frequency
3.0 to 5.5
0.1
12
• External system clock
duty =50±5%
MHz
• CF2 pin open
• System clock frequency
division ratio =1/1
2.7 to 5.5
0.1
6
• External system clock
duty =50±5%
Oscillation
FmCF
CF1, CF2
12MHz ceramic oscillation
frequency range
mode
(Note 2-3)
See Fig. 1.
FmRC
3.0 to 5.5
MHz
Internal medium-speed
RC oscillation
FmSRC
Internal low-speed RC
oscillation
FsX'tal
XT1, XT2
12
2.7 to 5.5
0.5
1.0
2.0
2.7 to 5.5
15
30
60
32.768kHz crystal
oscillation mode
kHz
2.7 to 5.5
32.768
See Fig. 2.
Note 2-3 : See Tables 1 and 2 for the oscillation constants.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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17
LC87F17C8A
Electrical Characteristics at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
High level input
current
Low level input
current
High level output
voltage
Symbol
IIH(1)
Pin/Remarks
Ports 0, 1, 2, 3, 7
RES
PWM0, PWM1
IIH(2)
XT1, XT2
IIH(3)
CF1
IIL(1)
Ports 0, 1, 2, 3, 7
RES
PWM0, PWM1
IIL(2)
XT1, XT2
IIL(3)
CF1
VOH(1)
Ports 0, 1, 2, 3
P71 to P73
Output disabled
Pull-up resistor off
VIN=VSS
(Including output Tr's off
leakage current)
Input port configuration
VIN=VSS
VIN=VSS
VDD [V]
min
typ
max
unit
2.7 to 5.5
1
2.7 to 5.5
1
2.7 to 5.5
15
2.7 to 5.5
1
2.7 to 5.5
1
2.7 to 5.5
15
4.5 to 5.5
VDD1
VOH(2)
IOH=0.4mA
3.0 to 5.5
VDD0.4
VOH(3)
IOH=0.2mA
2.7 to 5.5
VDD0.4
IOH=10mA
4.5 to 5.5
VDD1.5
IOH=1.6mA
3.0 to 5.5
VDD0.4
IOH=1mA
2.7 to 5.5
VDD0.4
IOL=30mA
4.5 to 5.5
1.5
VOL(2)
IOL=5mA
3.0 to 5.5
0.4
VOL(3)
IOL=2.5mA
2.7 to 5.5
0.4
IOL=10mA
4.5 to 5.5
1.5
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.7 to 5.5
0.4
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.7 to 5.5
0.4
VOH=0.9VDD
4.5 to 5.5
15
35
80
2.7 to 4.5
18
50
150
VOH(5)
PWM0, PWM1
P05 to P07
(Note 3-1)
VOH(6)
VOL(1)
VOL(4)
VOL(5)
P00, P01
Ports 0, 1, 2
PWM0, PWM1
XT2
VOL(6)
VOL(7)
Ports 3, 7
VOL(8)
Pull-up resistance
Output disabled
Pull-up resistor off
VIN=VDD
(Including output Tr's off
leakage current)
Input port configuration
VIN=VDD
VIN=VDD
IOH=1mA
VOH(4)
Low level output
voltage
Conditions
Rpu(1)
Ports 0, 1, 2, 3, 7
V
Rpu(2)
Hysteresis voltage
VHYS
Pin capacitance
CP
RES
Ports 1, 2, 3, 7
All pins
A
For pins other than those
under test :
VIN=VSS
f=1MHz
Ta=25°C
k
2.7 to 5.5
0.1VDD
V
2.7 to 5.5
10
pF
Note 3-1 : When the CKO system clock output function (P05) or the audio interface output function (P05 to P07)
is used.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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18
LC87F17C8A
Serial I/O Characteristics at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Specification
Pin/
Conditions
Remarks
SCK0(P12)
VDD [V]
See Fig. 8.
pulse width
typ
max
unit
2
1
pulse width
High level
min
tSCKH(1)
1
tSCKHA(1a)
• Continuous data transmission/
reception mode
• USB, AIF, SIO4, CRC not used
4
at the same time.
• See Fig. 8.
Input clock
• (Note 4-1-2)
tSCKHA(1b)
• Continuous data transmission/
reception mode
2.7 to 5.5
tCYC
• USB used at the same time
7
• AIF, SIO4, CRC not used at the
same time.
• See Fig. 8.
• (Note 4-1-2)
tSCKHA(1c)
• Continuous data transmission/
reception mode
• USB, AIF, SIO4, CRC used at
9
the same time.
• See Fig. 8.
Serial clock
• (Note 4-1-2)
Frequency
Low level
tSCK(2)
tSCKL(2)
pulse width
High level
SCK0(P12)
• When CMOS output type is
4/3
selected.
1/2
• See Fig. 8.
tSCK
tSCKH(2)
1/2
pulse width
tSCKHA(2a)
• Continuous data transmission/
reception mode
• USB, AIF, SIO4, CRC not used
tSCKH(2)
at the same time.
+2tCYC
• When CMOS output type is
tSCKH(2)
+
(10/3)tCYC
Output clock
selected.
• See Fig. 8.
tSCKHA(2b)
• Continuous data transmission/
reception mode
2.7 to 5.5
• USB used at the same time
• AIF, SIO4, CRC not used at the
tSCKH(2)
+2tCYC
same time.
• When CMOS output type is
tSCKH(2)
+
tCYC
(19/3)tCYC
selected.
• See Fig. 8.
tSCKHA(2c)
• Continuous data transmission/
reception mode
• USB, AIF, SIO4, CRC used at
the same time
• When CMOS output type is
tSCKH(2)
+2tCYC
tSCKH(2)
+
(25/3)tCYC
selected.
• See Fig. 8.
Note 4-1-1 : These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-1-2 : In an application where the serial clock input is to be used in continuous data transmission/reception
mode, the time from SI0RUN being set when serial clock is high to the falling edge of the first serial
clock must be longer than tSCKHA.
Continued on next page.
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19
LC87F17C8A
Continued from preceding page.
Symbol
tsDI(1)
time
Specification
Pin/
Conditions
Remarks
SB0(P11),
SI0(P11)
VDD [V]
Data hold time
Output
to rising edge of SIOCLK
tdDO(1)
typ
max
unit
0.03
2.7 to 5.5
thDI(1)
delay time
min
• Must be specified with respect
• See Fig. 8.
Input clock
Serial output
Data setup
0.03
SO0(P10),
SB0(P11)
• Continuous data transmission/
(1/3)tCYC
reception mode
+0.05
• (Note 4-1-3)
tdDO(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
tdDO(3)
Output clock
Serial input
Parameter
+0.05
2.7 to 5.5
(Note 4-1-3)
s
1tCYC
(1/3)tCYC
+0.05
Note 4-1-3 : Must be specified with respect to falling edge of SIOCLK. Must be defined as the time up to the
beginning of output state change in open drain output mode. See Fig. 8.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Pin/
Remarks
SCK1(P15)
Specification
Conditions
VDD [V]
See Fig. 8.
2.7 to 5.5
pulse width
High level
Frequency
Low level
SCK1(P15)
• When CMOS output type is
2
selected.
tSCKL(4)
• See Fig. 8.
1/2
2.7 to 5.5
tSCK
tSCKH(4)
1/2
Serial input
SB1(P14),
SI1(P14)
Data hold time
• Must be specified with
respect to rising edge of
SIOCLK.
thDI(2)
0.03
2.7 to 5.5
0.03
• See Fig. 8.
Output delay
time
Serial output
tsDI(2)
tdDO(4)
unit
1
pulse width
Data setup time
max
1
pulse width
High level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
pulse width
Output clock
Serial clock
Parameter
SO1(P13),
SB1(P14)
• Must be specified with
respect to falling edge of
s
SIOCLK.
• Must be specified as the
time up to the beginning of
2.7 to 5.5
(1/2)tCYC
+0.05
output state change in open
drain output mode.
• See Fig. 8.
Note 4-2-1 : These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
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20
LC87F17C8A
3. SIO4 Serial I/O Characteristics (Note 4-3-1)
Parameter
Symbol
Frequency
tSCK(5)
Low level
tSCKL(5)
Specification
Pin/
Conditions
Remarks
SCK4(P24)
VDD [V]
See Fig. 8.
pulse width
typ
max
unit
2
1
pulse width
High level
min
tSCKH(5)
1
tSCKHA(5a)
• USB, SIO0 continuous transfer
mode, AIF, CRC not used at
4
the same time.
• See Fig. 8.
Input clock
• (Note 4-3-2)
tSCKHA(5b)
• USB used at the same time.
• SIO0 continuous transfer
2.7 to 5.5
tCYC
mode, AIF, CRC not used at
7
the same time.
• See Fig. 8.
• (Note 4-3-2)
tSCKHA(5c)
• USB, SIO0 continuous transfer
mode used at the same time.
• AIF, CRC not used at the
10
same time.
• See Fig. 8.
Serial clock
• (Note 4-3-2)
Frequency
tSCK(6)
Low level
tSCKL(6)
pulse width
High level
pulse width
SCK4(P24)
• When CMOS output type is
4/3
selected.
1/2
• See Fig. 8.
tSCK
tSCKH(6)
tSCKHA(6a)
1/2
• USB, SIO0 continuous transfer
mode, AIF, CRC not used at
tSCKH(6)
the same time.
• When CMOS output type is
Output clock
selected.
tSCKH(6)
+
+
(5/3)tCYC
(10/3)tCYC
tSCKH(6)
tSCKH(6)
• See Fig. 8.
tSCKHA(6b)
• USB used at the same time.
• SIO0 continuous transfer
mode, AIF, CRC not used at
the same time.
• When CMOS output type is
2.7 to 5.5
+
+
(5/3)tCYC
(19/3)tCYC
tSCKH(6)
tSCKH(6)
tCYC
selected.
• See Fig. 8.
tSCKHA(6c)
• USB, SIO0 continuous transfer
mode used at the same time
• AIF, CRC not used at the
same time.
• When CMOS output type is
+
+
(5/3)tCYC
(28/3)tCYC
selected.
• See Fig. 8.
Note 4-3-1 : These specifications are theoretical values. Margins must be allowed according to the actual
operating conditions.
Note 4-3-2 : In an application where the serial clock input is to be used, the time from SI4RUN being set when
serial clock is high to the falling edge of the first serial clock must be longer than tSCKHA when
continuous data transmission/reception is started.
Continued on next page.
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21
LC87F17C8A
Continued from preceding page.
Serial input
Parameter
Data setup time
tsDI(3)
Data hold time
thDI(3)
Specification
Pin/
Conditions
Remarks
SO4(P22),
SI4(P23)
VDD [V]
min
• Must be specified with respect
typ
max
unit
0.03
to rising edge of SIOCLK.
• See Fig. 8.
2.7 to 5.5
0.03
Output delay
Serial output
Symbol
tdDO(5)
time
SO4(P22),
SI4(P23)
• Must be specified with respect
s
to falling edge of SIOCLK.
• Must be specified as the time up
to the beginning of output state
(1/3)tCYC
2.7 to 5.5
+0.05
change in open drain output
mode
• See Fig. 8.
4-1. SMIIC0/SMIIC1 Simple SIO Mode I/O Characteristics (Note 4-4-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Input clock
tSCK(7)
Low level
tSCKL(7)
SM0CK(P17),
See Fig. 8.
Frequency
2.7 to 5.5
Low level
tSCKL(8)
2/3
SM0CK(P17),
SM1CK(P13)
• When CMOS output type
4/3
is selected.
• See Fig. 8.
1/2
2.7 to 5.5
tSCK
tSCKH(8)
1/2
pulse width
Serial input
Data setup time
Data hold time
thDI(4)
SM0DA(P16),
SM1DA(P14)
• Must be specified with
time
tdDO(6)
SIOCLK.
SM0DA(P16),
SM0DO(P15),
SM1DA(P14),
SM1DO(P15)
0.03
respect to rising edge of
2.7 to 5.5
• See Fig. 8.
Output delay
Serial output
tsDI(4)
unit
2/3
pulse width
High level
max
tCYC
tSCKH(7)
tSCK(8)
typ
4/3
pulse width
High level
min
SM1CK(P13)
pulse width
Output clock
Serial clock
VDD [V]
Frequency
0.03
• Must be specified with
s
respect to falling edge of
SIOCLK.
• Must be specified as the
time to the beginning of
2.7 to 5.5
(1/3)tCYC
+0.05
output state change.
• See Fig. 8.
Note 4-4-1 : These specifications are theoretical values. Margins must be allowed according to the actual
operating conditions.
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22
LC87F17C8A
4-2. SMIIC0/SMIIC1 I2C Mode I/O Characteristics (Note 4-5-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Input clock
tSCL
Low level
tSCLL
SM0CK(P17),
See Fig. 10.
2.7 to 5.5
tSCLx
Low level
tSCLLx
2.5
SM0CK(P17),
Must be specified as the time
SM1CK(P13)
up to the beginning of output
state change.
10
1/2
2.7 to 5.5
tSCL
tSCLHx
1/2
pulse width
tsp
SM0CK, SM0DA,
SM0CK(P17),
SM1CK, SM1DA pin
SM0DA(P16),
input spike
SM1CK(P13),
tBUF
2.7 to 5.5
1
Tfilt
SM0CK(P17),
See Fig. 10.
SM0DA(P16),
input
Bus relinquish
and stop
See Fig. 10.
SM1DA(P14)
suppression time
time between start
unit
2
pulse width
HIghlevel
max
Tfilt
tSCLH
Frequency
typ
5
pulse width
High level
min
SM1CK(P13)
pulse width
Output clock
Serial clock
VDD [V]
Frequency
SM1CK(P13),
2.5
Tfilt
SM1DA(P14)
tBUFx
• Standard clock mode
• Must be specified as the time
2.7 to 5.5
Output
up to the beginning of output
5.5
state change.
s
• High-speed clock mode
• Must be specified as the time
1.6
up to the beginning of output
state change.
Start, restart
tHD;STA
SM0CK(P17),
• When SMIIC register control
SM0DA(P16),
bit SHDS=0
time
SM1CK(P13),
• See Fig. 10.
SM1DA(P14)
• When SMIIC register control
input
condition hold
2.0
Tfilt
bit SHDS=1
2.5
• See Fig. 10.
tHD;STAx
• Standard clock mode
• Must be specified as the time
2.7 to 5.5
4.1
Output
up to the beginning of output
state change.
s
• High-speed clock mode
• Must be specified as the time
1.0
up to the beginning of output
state change.
SM0CK(P17),
See Fig. 10.
SM0DA(P16),
SM1CK(P13),
1.0
Tfilt
SM1DA(P14)
tSU;STAx
• Standard clock mode
• Must be specified as the time
up to the beginning of output
Output
setup time
tSU;STA
input
Restart condition
2.7 to 5.5
5.5
state change.
s
• High-speed clock mode
• Must be specified as the time
up to the beginning of output
1.6
state change.
Continued on next page.
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23
LC87F17C8A
Continued from preceding page.
Specification
Parameter
Symbol
Pin/Remarks
tSU;STO
SM0CK(P17),
Conditions
VDD [V]
setup time
min
typ
max
unit
See Fig. 10.
SM0DA(P16),
input
Stop condition
SM1CK(P13),
1.0
Tfilt
SM1DA(P14)
tSU;STOx
• Standard clock mode
• Must be specified as the time
2.7 to 5.5
Output
up to the beginning of output
4.9
state change.
s
• High-speed clock mode
• Must be specified as the time
1.1
up to the beginning of output
state change.
tHD;DAT
SM0CK(P17),
SM1CK(P13),
0
SM1DA(P14)
tHD;DATx
Must be specified as the time up
2.7 to 5.5
Tfilt
Output
to the beginning of output state
change.
tSU;DAT
SM0CK(P17),
1
1.5
See Fig. 10.
SM0DA(P16),
Input
Data setup time
See Fig. 10.
SM0DA(P16),
Input
Data hold time
SM1CK(P13),
1
SM1DA(P14)
tSU;DATx
Must be specified as the time up
2.7 to 5.5
Output
to the beginning of output state
Tfilt
1tSCL-
change.
1.5Tfilt
Note 4-5-1 : These specifications are theoretical values. Margins must be allowed according to the actual
operating conditions.
Note 4-5-2 : The value of Tfilt is determined by bits 7 and 6 (BRP1 and BRP0) of the SMIC0BRG/SMIC1BRG
register and the system clock frequency.
BRP1
BRP0
Tfilt
0
0
(1/3) tCYC×1
0
1
(1/3) tCYC×2
1
0
(1/3) tCYC×3
1
1
(1/3) tCYC×4
Set the value of the BRP1 and BRP0 bits so that the value of Tfilt falls within the following value
range :
250 ns ≥ Tfilt > 140 ns
Note 4-5-3: For standard clock mode operation, set up the SMIC0BRG/SMIC1BRG register so that the following
conditions are satisfied :
250 ns ≥ Tfilt > 140 ns
BRDQ (bit5) = 1
SCL frequency value ≤ 100 kHz
For high-speed clock mode operation, set up the SMIC0BRG/SMIC1BRG register so that the
following conditions are satisfied :
250 ns ≥ Tfilt > 140 ns
BRDQ (bit5) = 0
SCL frequency value ≤ 400 kHz
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24
LC87F17C8A
Pulse Input Conditions at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
High/low level
tPIH(1)
INT0(P70),
pulse width
tPIL(1)
INT1(P71),
INT2(P72),
INT4(P20 to P23),
min
typ
max
unit
• Interrupt source flag can be
set.
• Event inputs for timer 0/1
are enabled.
2.7 to 5.5
1
2.7 to 5.5
2
2.7 to 5.5
64
2.7 to 5.5
256
2.7 to 5.5
4
2.7 to 5.5
200
INT5(P30 to P32),
INT6(P20),
INT7(P24)
tPIH(2)
INT3(P73) when
tPIL(2)
noisefilter time constant
is 1/1.
• Interrupt source flag can be
set.
• Event inputs for timer 0 are
tCYC
enabled.
tPIH(3)
INT3(P73) when
tPIL(3)
noisefilter time constant
• Interrupt source flag can be
set.
is 1/32.
• Event inputs for timer 0 are
tPIH(4)
INT3(P73) when
• Interrupt source flag can be
tPIL(4)
noisefilter time constant
enabled.
set.
is 1/128.
• Event inputs for timer 0 are
RMIN(P73)
Recognized as a signal by
enabled.
tPIL(5)
infrared remote control
receiver circuit
tPIL(6)
RES
Resetting is enabled.
RMCK
(Note 5-1)
s
Note 5-1 : Denotes the reference frequency of the infrared remote control receiver circuit (1tCYC to 128tCYC or
source oscillation frequency of the subclock)
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25
LC87F17C8A
AD Converter Characteristics at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
<12-bit AD Converter Mode>
Specification
Parameter
Symbol
Pin/Remarks
N
AN0(P00)
Conditions
VDD [V]
Resolution
Absolute
ET
accuracy
Conversion time
TCAD
(Note 6-1)
AN8(P70)
AN9(P71)
See conversion time
AN10(XT1)
current
max
unit
12
bit
3.0 to 5.5
±16
4.0 to 5.5
32
115
3.0 to 5.5
64
115
3.00 to 5.5
VSS
VDD
LSB
calculation formulas.
(Note 6-2)
VAIN
voltage range
Analog port input
typ
3.0 to 5.5
to AN7(P07)
AN11(XT2)
Analog input
min
IAINH
VAIN=VDD
3.0 to 5.5
IAINL
VAIN=VSS
3.0 to 5.5
s
V
1
A
1
<8-bit AD Converter Mode>
Specification
Parameter
Symbol
Pin/Remarks
Resolution
N
AN0(P00)
Absolute accuracy
ET
Conversion time
TCAD
Conditions
VDD [V]
Analog input
input current
typ
3.0 to 5.5
to AN7(P07)
max
unit
8
bit
(Note 6-1)
3.0 to 5.5
AN9(P71)
See conversion time
4.0 to 5.5
20
90
AN10(XT1)
calculation formulas.
AN11(XT2)
(Note 6-2)
3.0 to 5.5
40
90
3.0 to 5.5
VSS
VDD
AN8(P70)
VAIN
voltage range
A Analog port
min
IAINH
VAIN=VDD
3.0 to 5.5
IAINL
VAIN=VSS
3.0 to 5.5
±1.5
LSB
s
V
1
A
1
Conversion time calculation formulas :
12-bits AD Converter Mode : TCAD (Conversion time) = ((52/(AD division ratio))+2) × (1/3) × tCYC
8-bits AD Converter Mode : TCAD (Conversion time) = ((32/(AD division ratio))+2) × (1/3) × tCYC
<Recommended Operating Conditions>
External
Supply Voltage
System Clock
Cycle Time
AD Frequency
Conversion Time (TCAD) [μs]
Oscillator
Range
Division
tCYC [ns]
Division Ratio
12-bit AD
8-bit AD
FmCF [MHz]
VDD [V]
4.0 to 5.5
(SYSDIV)
1/1
250
1/8
34.8
21.5
3.0 to 5.5
1/1
250
1/16
69.5
42.8
12
(ADDIV)
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy
must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to
the analog input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process
until the time the conversion result register is loaded with a complete digital conversion value
corresponding to the analog input value.
The conversion time is doubled in the following cases :
● The AD conversion is carried out in the 12-bit AD conversion mode for the first time after a system
reset.
● The AD conversion is carried out for the first time after the AD conversion mode is switched from
8-bit to 12-bit AD conversion mode.
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26
LC87F17C8A
Power-on Reset (POR) Characteristics at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Conditions
Option
selected voltage
POR release voltage
PORRL
Select from option
(Note 7-1)
Detection voltage
POUKS
unknown state
Power supply rise
min
typ
1.67V
1.55
1.67
1.79
1.97V
1.85
1.97
2.09
2.07V
1.95
2.07
2.19
2.37V
2.25
2.37
2.49
2.57V
2.45
2.57
2.69
2.87V
2.75
2.87
2.99
3.86V
3.73
3.86
3.99
4.35V
4.21
4.35
4.49
0.7
0.95
See Fig. 12
(Note 7-2)
PORIS
time
max
Power supply rise time from
100
VDD=0V to 1.6V
unit
V
ms
Note 7-1 : The POR release level can be selected out of 8 levels only when LDV reset function is disabled.
Note 7-2 : POR is in unknown state before transistors start operation.
Low Voltage Detection (LVD) Characteristics
at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Conditions
Option
selected voltage
LVD reset voltage
LVDET
(Note 8-2)
LVD hysteresis
Select from option.
LVUKS
Low voltage detection
minimum width
1.91
2.01
(Note 8-1)
2.01V
1.91
2.01
2.11
(Note 8-3)
2.31V
2.21
2.31
2.41
2.51V
2.41
2.51
2.61
2.81V
2.71
2.81
2.91
3.79V
3.69
3.79
3.89
4.28V
4.18
4.28
4.38
1.91V
55
2.01V
55
2.31V
55
2.51V
55
2.81V
55
3.79V
60
4.28V
65
unit
V
mV
See Fig. 13.
(Note 8-4)
TLVDW
max
1.81
LVHYS
unknown state
typ
1.91V
See Fig. 13.
width
Detection voltage
min
0.7
0.95
V
LVDET-0.5V
See Fig. 14.
0.2
ms
(Reply sensitivity)
Note8-1 : The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled.
Note8-2 : LVD reset voltage specification values do not include hysteresis voltage.
Note8-3 : LVD reset voltage may exceed its specification values when port output state changes and/or when a
large current flows through port.
Note8-4 : LVD is in an unknown state before transistors start operation.
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27
LC87F17C8A
Consumption Current Characteristics at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
Specification
Pin/
Conditions
Remarks
VDD[V]
• FmCF=12MHz ceramic oscillation mode
consumption
VDD1
=VDD2
current
=VDD3
• System clock set to 12MHz side
• FsX'tal=32.768kHz crystal oscillation mode
(Note 9-1)
• Internal PLL oscillation stopped
(Note 9-2)
• Internal low-/medium-speed RC oscillation
stopped
• USB circuit stopped
min
typ
max
4.5 to 5.5
9.8
18
3.0 to 3.6
5.7
11
4.5 to 5.5
17
30
3.0 to 3.6
8.5
16
4.5 to 5.5
6.7
12
3.0 to 3.6
4.2
7.1
2.7 to 3.0
3.5
5.8
4.5 to 5.5
0.44
1.4
3.0 to 3.6
0.29
0.87
2.7 to 3.0
0.26
0.75
4.5 to 5.5
28
153
3.0 to 3.6
18
80
2.7 to 3.0
16
66
4.5 to 5.5
45
160
3.0 to 3.6
18
74
2.7 to 3.0
14
58
4.5 to 5.5
4.0
7.0
unit
• 1/1 frequency division ratio
IDDOP(2)
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation mode active
• Internal low-/medium-speed RC oscillation
stopped
• USB circuit active
mA
• 1/1 frequency division ratio
IDDOP(3)
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
• Internal low-/medium-speed RC oscillation
stopped
• 1/2 frequency division ratio
IDDOP(4)
• External oscillation FmCF stopped
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to internal medium-speed
RC oscillation
• Internal low-speed RC oscillation stopped
• 1/2 frequency division ratio
IDDOP(5)
• External oscillation FsX'tal /FmCF stopped
• System clock set to internal low-speed RC
oscillation
• Internal medium-speed RC oscillation stopped
• 1/1 frequency division ratio
IDDOP(6)
• External oscillation FmCF stopped
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low-/medium-speed RC oscillation
stopped
• 1/2 frequency division ratio
HALT mode
consumption
current
(Note 9-1)
(Note 9-2)
IDDHALT(1)
A
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation stopped
mA
• Internal low-/medium-speed RC oscillation
stopped
3.0 to 3.6
• USB circuit stopped
2.2
3.8
• 1/1 frequency division ratio
Note 9-1 : The consumption current value do not include current that flows into the output transistors and internal
pull-up resistors.
Note 9-2 : The consumption current values do not include operational current of LVD (Low Voltage Detection)
function if not specified.
Continued on next page.
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28
LC87F17C8A
Continued from preceding page.
Parameter
Symbol
HALT mode
IDDHALT(2)
Specification
Pin/
Conditions
Remarks
typ
max
4.5 to 5.5
11
19
3.0 to 3.6
4.9
9.1
4.5 to 5.5
2.5
4.5
3.0 to 3.6
1.3
2.3
2.7 to 3.0
1.1
1.8
4.5 to 5.5
0.16
0.56
3.0 to 3.6
0.09
0.27
2.7 to 3.0
0.07
0.21
4.5 to 5.5
7.2
111
3.0 to 3.6
4.0
56
2.7 to 3.0
3.4
46
4.5 to 5.5
30
141
3.0 to 3.6
8.4
63
2.7 to 3.0
5.8
48
• HOLD mode
4.5 to 5.5
0.30
91
• CF1=VDD or open
3.0 to 3.6
0.22
46
2.7 to 3.0
0.21
38
4.5 to 5.5
3.3
95
3.0 to 3.6
2.5
49
2.7 to 3.0
2.3
41
4.5 to 5.5
0.88
95
3.0 to 3.6
0.47
47
2.7 to 3.0
0.42
39
VDD[V]
• HALT mode
consumption
VDD1
=VDD2
current
=VDD3
• FsX'tal=32.768kHz crystal oscillation mode
min
unit
• FmCF=12MHz ceramic oscillation mode
(Note 9-1)
• System clock set to 12MHz side
(Note 9-2)
• Internal PLL oscillation active
• Internal low-/medium-speed RC oscillation
stopped
• USB circuit active
•1/1 frequency division ratio
IDDHALT(3)
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
mA
• Internal low-/medium-speed RC oscillation
stopped
• 1/2 frequency division ratio
IDDHALT(4)
• HALT mode
• External oscillation FmCF stopped
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to internal medium-speed
RC oscillation
• Internal low-speed RC oscillation stopped
•1/2 frequency division ratio
IDDHALT(5)
• HALT mode
• External oscillation FsX'tal /FmCF stopped
• System clock set to internal low-speed RC
oscillation
• Internal medium-speed RC oscillation
stopped.
• 1/1 frequency division ratio
IDDHALT(6)
• HALT mode
• External oscillation FmCF stopped
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low-/medium-speed RC oscillation
stopped.
• 1/2 frequency division ratio
HOLD mode
IDDHOLD(1)
consumption
current
(External clock mode)
(Note 9-1)
(Note 9-2
IDDHOLD(2)
• HOLD mode
• LVD option selected
• CF1=VDD or open
(External clock mode)
IDDHOLD(3)
• HOLD mode
• Internal timer type watchdog timer active
A
(Internal low-speed RC oscillation circuit
active)
• CF1=VDD or open
(External clock mode)
Note 9-1 : Values of the consumption current do not include current that flows into the output transistors and
internal pull-up resistors.
Note 9- 2: The consumption current values do not include operational current of LVD (Low Voltage Detection)
function if not specified.
Continued on next page.
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29
LC87F17C8A
Continued from preceding page.
Parameter
X'tal HOLD
IDDHOLD(4)
Specification
Pin/
Symbol
Conditions
Remarks
mode
VDD1
=VDD2
consumption
=VDD3
VDD[V]
• X'tal HOLD mode
• CF1=VDD or open
(External clock mode)
current
• FsX'tal=32.768kHz crystal oscillation mode
(Note 9-1)
IDDHOLD(5)
(Note 9-2
• X'tal HOLD mode
• CF1=VDD or open
(External clock mode)
• FmSRC=30kHz internal low-speed RC
oscillation mode
min
typ
max
4.5 to 5.5
26
135
3.0 to 3.6
6.1
60
2.7 to 3.0
3.8
46
4.5 to 5.5
0.94
95
3.0 to 3.6
0.51
47
2.7 to 3.0
0.44
39
unit
A
Note 9-1 : Values of the consumption current do not include current that flows into the output transistors and
internal pull-up resistors.
Note 9-2 : The consumption current values do not include operational current of LVD (Low Voltage Detection)
function if not specified.
USB Characteristics and Timing at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Conditions
Parameter
Symbol
Pin/Remarks
min
typ
max
unit
High level output
VOH(USB)
• 15k±5% to GND
2.8
3.6
V
Low level output
VOL(USB)
• 1.5k±5% to 3.6V
0.0
0.3
V
Output signal crossover voltage
VCRS
1.3
2.0
V
Differential input sensitivity
VDI
• |(UAD+)(UAD)|
0.2
• |(UBD+)(UBD)|
V
Differential input common mode range
VCM
0.8
2.5
V
High level input
VIH(USB)
2.0
3.6
V
Low level input
VIL(USB)
0.0
0.8
V
Rise time (full-speed)
tFR
CL=50pF
4
20
ns
Fall time (full-speed)
tFF
CL=50pF
4
20
ns
Rise time (low-speed)
tLR
CL=200 to 600pF
75
300
ns
Fall time (low-speed)
tLF
CL=200 to 600pF
75
300
ns
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1= VSS2 = VSS3= 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Onboard
IDDFW(1)
programming
VDD1
in the microcontroller block
current
Programming time
tFW(1)
tFW(2)
min
typ
max
unit
• Excluding power dissipation
3.0 to 5.5
• Erase operation
• Write operation
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30
5
10
mA
20
30
ms
40
60
s
3.0 to 5.5
LC87F17C8A
Main System Clock Oscillation
The characteristics of a sample main system clock oscillator circuit shown in Table 1 are measured using an
our oscillation characteristics evaluation board and external components with circuit constant values with
which the resonator vendor confirmed normal and stable oscillation.
Table 1 shows the characteristics of a oscillator circuit when USB host function is not used. If USB host
function is to be used, it is absolutely recommended to use a resonator that satisfies the precision and stability
according to the USB standards (500ppm)
Table 1
Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator
Circuit Constant
Nominal
Vendor Name
Frequency
Resonator Name
Oscillation
Operating
C1
C2
Rd1
[pF]
[pF]
[]
(33)
(33)
470
Voltage Range
Stabilization Time
[V]
typ
max
[ms]
[ms]
0.1
0.5
Remarks
C1 and C2
12MHz
MURATA
CSTCE12M0GH5L**-R0
3.0 to 5.5
integrated
SMD type
The oscillation stabilization time is required for the oscillator to get stabilized in the following cases (see Figure 4):
• Until
oscillation is stabilized after VDD goes above the operating voltage lower limit
•
Until oscillation is stabilized after the instruction for starting the main clock oscillator circuit is executed
•
Until oscillation is stabilized after HOLD mode is released.
•
Until oscillation is stabilized after X'tal HOLD mode is released with CFSTOP (OCR register, bit 0) set to 0
and oscillation is started.
Subsystem Clock Oscillation
Table 2 shows the characteristics of a sample subsystem clock oscillator circuit that are measured using an our
oscillation characteristics evaluation board and external components with circuit constant values with which
the resonator vendor confirmed normal and stable oscillation.
Table 2
Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator
Nominal
Vendor Name
Frequency
Circuit Constant
Resonator
Name
Oscillation
Operating
C3
C4
Rf
Rd2
[pF]
[pF]
[]
[]
18
18
Open
680k
Voltage Range
[V]
Stabilization Time
typ
max
[s]
[s]
1.1
3.0
Remarks
Applicable CL
32.768kHz
EPSON TOYOCOM
MC-306
2.7 to 5.5
value=12.5pF
SMD type
The oscillation stabilization time is required for the oscillator to get stabilized in the following cases (see Figure 4) :
• Until oscillation is stabilized after the instruction for starting the subclock oscillator circuit is executed
• Until oscillation is stabilized after HOLD mode is released with EXTOSC (OCR register, bit 6) set to 1 and
oscillation is started.
Note : The components that are involved in oscillation should be placed as close to the IC and to one another as
possible because they are vulnerable to the influences of the circuit pattern.
CF1
XT1
CF2
Rf
Rd1
C1
C3
C2
Rd2
C4
X’tal
CF
Figure 1
XT2
CF Oscillator Circuit
Figure 2
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31
Crystal Oscillator Circuit
LC87F17C8A
0.5VDD
Figure 3 AC Timing Measurement Point
VDD
Operating VDD lower limit
Power supply
GND
Reset time
RES
Internal
medium-speed
RC oscillation
tmsCF
CF1,CF2
tmsX’tal
XT1,XT2
Execute oscillation enable instruction
Operating mode
Instruction execution
Reset
Unknown
Reset Time and Oscillation Stabilization Time
HOLD release signal
HOLD release signal valid
Internal
medium-speed
RC oscillation
tmsCF
CF1,CF2
tmsX’tal
* If operation is enabled before
entry into HOLD mode
XT1,XT2
Operating mode
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time
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32
LC87F17C8A
UFILT
When using the internal PLL circuit to generate the
48MHz clock for USB, it is necessary to connect a filter
circuit as shown in the left figure to the UFILT pin.
After PLL is set, stabilization time of 20ms or longer
must be secured.
Rd
100
+
Cd
 2.2F
Figure 5
External Filter Circuit for the Internal USB-dedicated PLL Circuit
AFILT
+
-
Figure 6
To generate the master clock for the audio
interface using the internal PLL circuit, it is
necessary to connect a filter circuit as shown
in the left figure to the AFILT pin.
Rd
150
+ Cp
1F
-
Cd
4.7F
External Filter Circuit for Audio Interface (Used with Internal PLL Circuit)
VDD
RRES
RES
CRES
Note :
The external circuit differs depending on which of the
power-on reset and low-voltage reset functions is to be
used. Refer to the section on the reset functions in the user's
manual.
Figure 7 Sample Reset Circuit
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33
LC87F17C8A
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transfer
period (SIO0, 4 only)
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transfer
period (SIO0, 4 only)
tSCKHA
tSCKL
SIOCLK:
thDI
tsDI
DATAIN:
tdDO
DATAOUT:
Figure 8 Serial I/O Waveform
tPIL
tPIH
Figure 9 Pulse Input Timing Waveform
P
SDA
S
S
r
P
tBUF
tHD;STA
tR
tF
tHD;STA
tsp
SCK
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
S : Start condition
P : Stop condition
Sr : Restart condition
Figure 10
I2C Timing
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34
tSU;STO
LC87F17C8A
Voh
tr
D+
tr
90%
90%
Vcrs
10%
Vol
10%
D
Figure 11 USB Data Signal Timing and Voltage Levels
(a)
POR release
voltage
(b)
VDD
Reset period
100 s or longer
Reset period
Reset unknown state
(POUKS)
RES
Figure 12
Sample Waveforms for POR-only (LVD deselected) Operation (Reset pin : Pull-up resistor PRES only)
• The
POR function generates a reset only when the power is turned on starting at the VSS level.
stable reset will be generated if power is turned on again if the power level does not go down to the VSS
level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function as
explained below or implement an external reset circuit.
• A reset is generated only when power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 100 s or longer.
• No
LVD hysteresis
width
(LVHYS)
LVD release
voltage
(LVDET+LVHY)
VDD
Reset period
Reset
period
Reset period
LVD detection voltage
(LVDET)
Reset unknown
state
RES
Figure 13
Sample Waveforms for POR+LVD Operation (Reset pin : Pull-up Resistor PRES Only)
• A reset is generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent repetitions of reset release and entry cycles near the
detection level.
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35
LC87F17C8A
VDD
LVD reset voltage
LVD detection voltage
LVDET-0.5V
TLVDW
VSS
Figure 14
Minimum Low Voltage Detection Width (Sample Temporary Power Interruption/Fluctuation Waveform )
ORDERING INFORMATION
Device
LC87F17C8AUWA-2H
Package
SPQFT48 7x7 / SQFP48
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
2500 / Tray JEDEC
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
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directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
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