Freescale MCF5372L Microprocessor data sheet Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
MCF5373DS
Rev. 0.3, 04/2006
MCF5373 ColdFire®
Microprocessor Data Sheet
Supports MCF5372L, MCF5372, MCF5373L, & MCF5373
by: Microcontroller Division
The MCF537x devices are a family of highly-integrated
32-bit microprocessors based on the Version 3 ColdFire
microarchitecture. All MCF537x devices contain a
32-Kbyte internal SRAM, a Fast Ethernet controller, a
2-bank SDR/DDR SDRAM controller, a 16-channel
DMA controller, up to three UARTs, a queued SPI, as
well as other peripherals that enable the MCF537x
family for use in general purpose industrial control
applications. Optional peripherals include USB host and
On-the-Go controllers and cryptography hardware
accelerators.
Table of Contents
1
2
3
4
5
6
MCF537x Family Configurations .........................2
Ordering Information ...........................................3
Signal Descriptions..............................................3
Mechanicals and Pinouts ....................................8
Preliminary Electrical Characteristics ................14
Revision History ................................................40
This document provides an overview of the MCF537x
microprocessor family, focusing on its highly diverse
feature set. It was written from the perspective of the
MCF5373L device. However, it also pertains to the
MCF5372L, MCF5372, and MCF5373. See the
following section for a summary of differences between
the various devices of the MCF537x family.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
• Preliminary
MCF537x Family Configurations
1
MCF537x Family Configurations
The following table compares the various device derivatives available within the MCF537x family.
Table 1. MCF537x Family Configurations
Module
MCF5372 MCF5372L MCF5373 MCF5373L
ColdFire Version 3 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
x
x
x
x
Core (System) Clock
up to
180 MHz
up to
240 MHz
up to
180 MHz
up to
240 MHz
Peripheral and External Bus Clock
(Core clock ÷ 3)
up to
60 MHz
up to
80 MHz
up to
60 MHz
up to
80 MHz
Performance (Dhrystone/2.1 MIPS)
up to 158
up to 211
up to 158
up to 211
Instruction/Data Cache
16 Kbytes
Static RAM (SRAM)
32 Kbytes
SDR/DDR SDRAM Controller
x
x
x
x
USB 2.0 Host
—
x
—
x
USB 2.0 On-the-Go
—
x
—
x
Synchronous Serial Interface (SSI)
x
x
x
x
Fast Ethernet Controller (FEC)
x
x
x
x
Cryptography Hardware Accelerators
—
—
x
x
UARTs
3
3
3
3
I2C
x
x
x
x
QSPI
x
x
x
x
PWM Module
—
x
—
x
Real Time Clock
x
x
x
x
32-bit DMA Timers
4
4
4
4
Watchdog Timer (WDT)
x
x
x
x
Periodic Interrupt Timers (PIT)
4
4
4
4
Edge Port Module (EPORT)
x
x
x
x
Interrupt Controllers (INTC)
2
2
2
2
16-channel Direct Memory Access (DMA)
x
x
x
x
FlexBus External Interface
x
x
x
x
up to 46
up to 62
up to 46
up to 62
x
x
x
x
160 QFP
196
MAPBGA
160 QFP
196
MAPBGA
General Purpose I/O (GPIO)
JTAG - IEEE® 1149.1 Test Access Port
Package
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
2
Preliminary
Freescale Semiconductor
Ordering Information
2
Ordering Information
Table 2. Orderable Part Numbers
3
Freescale Part
Number
Description
Speed
Temperature
MCF5372CAB180
MCF5372 RISC Microprocessor, 160 QFP
180 MHz
–40° to +85° C
MCF5372LCVM240
MCF5372 RISC Microprocessor, 196 MAPBGA
240 MHz
–40° to +85° C
MCF5373CAB180
MCF5373 RISC Microprocessor, 160 QFP
180 MHz
–40° to +85° C
MCF5373LCVM240
MCF5373 RISC Microprocessor, 256 MAPBGA
240 MHz
–40° to +85° C
Signal Descriptions
The following table lists all the MCF537x pins grouped by function. The “Dir” column is the direction for
the primary function of the pin only. Refer to Section 4, “Mechanicals and Pinouts,” for package diagrams.
For a more detailed discussion of the MCF537x signals, consult the MCF5373 Reference Manual
(MCF5373RM).
NOTE
In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A23), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.
Table 3. MCF5372/3 Signal Information and Muxing
Signal Name
GPIO
Alternate 1
Alternate 2
Dir.1
MCF5372
MCF5373
160 QFP
MCF5372L
MCF5373L
196 MAPBGA
Reset
RESET2
—
—
—
I
95
K13
RSTOUT
—
—
—
O
86
L12
Clock
EXTAL
—
—
—
I
91
L14
2
XTAL
—
—
—
O
93
K14
EXTAL32K
—
—
—
I
—
P13
XTAL32K
—
—
—
O
—
N13
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
3
Signal Descriptions
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate 1
Alternate 2
Dir.1
MCF5372
MCF5373
160 QFP
MCF5372L
MCF5373L
196 MAPBGA
FB_CLK
—
—
—
O
40
N1
Mode Selection
RCON2
—
—
—
I
72
P8
DRAMSEL
—
—
—
I
92
J11
FlexBus
A[23:22]
—
FB_CS[5:4]
—
O
134, 133
A9, B9
A[21:16]
—
—
—
O
132–127
C9, D9, A10,
B10, C10, D10
A[15:14]
—
SD_BA[1:0]
—
O
126, 123
A11, B11
A[13:11]
—
SD_A[13:11]
—
O
120–118
C11, A12, B12
A10
—
—
—
O
11
A13
A[9:0]
—
SD_A[9:0]
—
O
116–107
A14, B14, B13,
C12, D11, C14,
C13, D14–D12
D[31:16]
—
SD_D[31:16]3
—
O
27–34, 46–53
J2, J1, K4–K1,
L4, L3, N2, P1,
P2, N3, L5, P3,
N4, P4
D[15:1]
—
FB_D[31:17]3
—
O
16–23, 57–63
F2, F1, G4–G1,
H4, H3, L6, M6,
N6, P6, L7, M7,
N7
D02
—
FB_D[16]3
—
O
64
P7
BE/BWE[3:0]
PBE[3:0]
SD_DQM[3:0]
—
O
26, 54, 24, 56
J3, M5, H2, P5
OE
PBUSCTL3
—
—
O
66
M8
TA2
PBUSCTL2
—
—
I
106
E14
R/W
PBUSCTL1
—
—
O
65
L8
TS
PBUSCTL0
DACK0
—
O
12
E2
Chip Selects
FB_CS[5:4]
PCS[5:4]
—
—
O
—
D8, C8
FB_CS[3:2]
PCS[3:2]
—
—
O
—
B8, A8
FB_CS1
PCS1
—
—
O
135
D7
FB_CS0
—
—
—
O
136
C7
SDRAM Controller
SD_A10
—
—
—
O
43
M2
SD_CKE
—
—
—
O
14
F4
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
4
Preliminary
Freescale Semiconductor
Signal Descriptions
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate 1
Alternate 2
Dir.1
MCF5372
MCF5373
160 QFP
MCF5372L
MCF5373L
196 MAPBGA
SD_CLK
—
—
—
O
37
L1
SD_CLK
—
—
—
O
38
M1
SD_CS0
—
—
—
O
15
F3
SD_DQS3
—
—
—
O
25
H1
SD_DQS2
—
—
—
O
55
N5
SD_SCAS
—
—
—
O
44
M3
SD_SRAS
—
—
—
O
45
M4
SD_SDR_DQS
—
—
—
O
35
L2
SD_WE
—
—
—
O
13
E1
External Interrupts Port4
IRQ72
PIRQ72
—
—
I
102
F13
IRQ62
PIRQ62
USBHOST_
VBUS_EN2
—
I
—
F12
IRQ52
PIRQ52
USBHOST_
VBUS_OC2
—
I
—
F11
IRQ42
PIRQ42
SSI_MCLK2
—
I
101
G14
IRQ32
PIRQ32
—
—
I
—
G13
IRQ22
PIRQ22
USB_CLKIN2
—
I
—
G12
IRQ12
PIRQ12
DREQ12
SSI_CLKIN
I
100
G11
FEC
FEC_MDC
PFECI2C3
I2C_SCL2
—
O
4
B1
FEC_MDIO
PFECI2C2
I2C_SDA2
—
I/O
3
A1
FEC_COL
PFECH7
—
—
I
144
B6
FEC_CRS
PFECH6
—
—
I
145
A6
FEC_RXCLK
PFECH5
—
—
I
146
A5
FEC_RXDV
PFECH4
—
—
I
147
B5
FEC_RXD[3:0]
PFECH[3:0]
—
—
I
148–151
C5, D5, A4, B4
FEC_RXER
PFECL7
—
—
I
152
C4
FEC_TXCLK
PFECL6
—
—
I
153
A3
FEC_TXEN
PFECL5
—
—
O
154
B3
FEC_TXER
PFECL4
—
—
O
155
A2
FEC_TXD[3:0]
PFECL[3:0]
—
—
O
157, 158, 1, 2
D4, C3, B2, C2
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
5
Signal Descriptions
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate 1
Alternate 2
Dir.1
MCF5372
MCF5373
160 QFP
MCF5372L
MCF5373L
196 MAPBGA
USB Host & USB On-the-Go
USBOTG_M
—
—
—
I/O
—
H14
USBOTG_P
—
—
—
I/O
—
H13
USBHOST_M
—
—
—
I/O
—
J13
USBHOST_P
—
—
—
I/O
—
J12
PWM
PWM7
PPWM7
—
—
I/O
—
E13
PWM5
PPWM5
—
—
I/O
—
E12
PWM3
PPWM3
DT3OUT
DT3IN
I/O
—
E11
PWM1
PPWM1
DT2OUT
DT2IN
I/O
—
F14
SSI
The SSI signals do not have dedicated bond pads. Please refer to the following pins for muxing: IRQ4 for SSI_MCLK,
IRQ1 for SSI_CLKIN, U1CTS for SSI_BCLK, U1RTS for SSI_FS, U1RXD for SSI_RXD, and U1TXD for SSI_TXD
I2C
I2C_SCL2
PFECI2C1
—
U2TXD
I/O
—
E3
I2C_SDA2
PFECI2C0
—
U2RXD
I/O
—
E4
DMA
DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:
TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.
QSPI
QSPI_CS2
PQSPI5
U2RTS
—
O
78
N12
QSPI_CS1
PQSPI4
PWM7
USBOTG_
PU_EN
O
—
M12
QSPI_CS0
PQSPI3
PWM5
—
O
—
M11
QSPI_CLK
PQSPI2
I2C_SCL2
—
O
77
P12
QSPI_DIN
PQSPI1
U2CTS
—
I
75
P11
QSPI_DOUT
PQSPI0
I2C_SDA2
—
O
76
N11
UARTs
U1CTS
PUARTL7
SSI_BCLK
—
I
143
C6
U1RTS
PUARTL6
SSI_FS
—
O
142
D6
U1TXD
PUARTL5
SSI_TXD2
—
O
141
A7
U1RXD
PUARTL4
SSI_RXD2
—
I
140
B7
U0CTS
PUARTL3
—
—
I
85
M14
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
6
Preliminary
Freescale Semiconductor
Signal Descriptions
Table 3. MCF5372/3 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate 1
Alternate 2
Dir.1
MCF5372
MCF5373
160 QFP
MCF5372L
MCF5373L
196 MAPBGA
U0RTS
PUARTL2
—
—
O
84
M13
U0TXD
PUARTL1
—
—
O
83
N14
U0RXD
PUARTL0
—
—
I
80
P14
Note: The UART2 signals are multiplexed on the QSPI, DMA Timers, and I2C pins.
DMA Timers
DT3IN
PTIMER3
DT3OUT
U2RXD
I
8
D1
DT2IN
PTIMER2
DT2OUT
U2TXD
I
7
C1
DT1IN
PTIMER1
DT1OUT
DACK1
I
6
D2
DT0OUT
DREQ02
I
5
D3
DT0IN
PTIMER0
BDM/JTAG5
JTAG_EN6
—
—
—
I
96
G10
—
TRST2
—
I
88
K11
PSTCLK
—
TCLK2
—
O
70
N8
BKPT
—
TMS2
—
I
87
L13
DSI
—
TDI2
—
I
90
K12
DSO
—
TDO
—
O
74
L11
DDATA[3:0]
—
—
—
O
—
L9, M9, N9, P9
PST[3:0]
—
—
—
O
—
L10, M10, N10,
P10
ALLPST
—
—
—
O
73
—
—
I
124
E10
DSCLK
Test
TEST6
—
—
Power Supplies
EVDD
—
—
—
9, 69, 71, 81, 94,
103, 139, 160
E6, E7, F5–F7,
G5, H10, J8,
K8–K9
IVDD
—
—
—
36, 79, 97, 125,
156
E5, J9, K5, K10
PLL_VDD
—
—
—
99
J10
SD_VDD
—
—
—
11, 39, 41, 67,
105, 121, 137
E8–E9, F8–F10,
J4–J7, H5, K6,
K7
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
7
Mechanicals and Pinouts
Table 3. MCF5372/3 Signal Information and Muxing (continued)
MCF5372
MCF5373
160 QFP
MCF5372L
MCF5373L
196 MAPBGA
—
—
H12
—
—
10, 42, 68, 82,
89, 104, 122,
138, 159
G6–G9, H6–H9
—
—
—
98
H11
—
—
—
—
J14
Signal Name
GPIO
Alternate 1
Alternate 2
USBOTG_VDD
—
—
VSS
—
PLL_VSS
USBHOST_VSS
Dir.1
NOTES:
1
Refers to pin’s primary function.
2 Pull-up enabled internally on this signal for this mode.
3
Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by
negating the DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.
4 GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the
alternate functions.
5 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for
assigning these pins.
6 Pull-down enabled internally on this signal for this mode.
4
Mechanicals and Pinouts
This section contains drawings showing the pinout and the packaging and mechanical characteristics of
the MCF537x devices.
NOTE
The mechanical drawings are the latest revisions at the time of publication
of this document. The most up-to-date mechanical drawings can be found at
the product summary page located at http://www.freescale.com/coldfire.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
8
Preliminary
Freescale Semiconductor
Mechanicals and Pinouts
4.1
Pinout—196 MAPBGA
The pinout for the MCF5373LCVM240 and MCF5372LCVM240 packages are shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
FEC_
MDIO
FEC_
TXER
FEC_
TXCLK
FEC_
RXD1
FEC_
RXCLK
FEC_
CRS
U1TXD
FB_CS2
A23
A19
A15
A12
A10
A9
A
B
FEC_
MDC
FEC_
TXD1
FEC_
TXEN
FEC_
RXD0
FEC_
RXDV
FEC_
COL
U1RXD
FB_CS3
A22/
A18
A14
A11
A7
A8
B
C
DT2IN
FEC_
TXD0
FEC_
TXD2
FEC_
RXER
FEC_
RXD3
U1CTS
FB_CS0 FB_CS4
A21
A17
A13
A6
A3
A4
C
D
DT3IN
DT1IN
DT0IN
FEC_
TXD3
FEC_
RXD2
U1RTS
FB_CS1 FB_CS5
A20
A16
A5
A0
A1
A2
D
E
SD_WE
TS
I2C_SCL I2C_SDA
IVDD
EVDD
EVDD
SD_VDD SD_VDD
TEST
PWM3
PWM5
PWM7
TA
E
F
D14
D15
SD_CS0
SD_CKE
EVDD
EVDD
EVDD
SD_VDD SD_VDD SD_VDD
IRQ5
IRQ6
IRQ7
PWM1
F
G
D10
D11
D12
D13
EVDD
VSS
VSS
VSS
VSS
JTAG_
EN
IRQ1
IRQ2
IRQ3
IRQ4
G
H
SD_
DQS3
BE/
BWE1
D8
D9
SD_VDD
VSS
VSS
VSS
VSS
EVDD
PLL_
VSS
USBOTG
_VDD
USB
OTG_P
USB
OTG_M
H
J
D30
D31
BE/
BWE3
EVDD
IVDD
PLL_
VDD
DRAM
SEL
USB
USB
USBHOST
J
HOST_P HOST_M
_VSS
K
D26
D27
D28
D29
IVDD
EVDD
EVDD
IVDD
TRST/
DSCLK
TDI/DSI
RESET
XTAL
K
L
SD_CLK
SD_DR_
DQS
D24
D25
D19
D7
D3
R/W
DDATA3
PST3
TDO/
DSO
RSTOUT
TMS/
BKPT
EXTAL
L
SD_CAS
SD_RAS
BE/
BWE2
D6
D2
OE
DDATA2
PST2
QSPI_
CS0
QSPI_
CS1
U0RTS
U0CTS
M
TCLK/
DDATA1
PSTCLK
PST1
QSPI_
DOUT
QSPI_
CS2
XTAL
32K
U0TXD
N
P
M SD_CLK SD_A10
SD_VDD SD_VDD SD_VDD SD_VDD
SD_VDD SD_VDD
N
FB_CLK
D23
D20
D17
SD_
DQS2
D5
D1
P
D22
D21
D18
D16
BE/
BWE0
D4
D0
RCON
DDATA0
PST0
QSPI_
DIN
QSPI_
CLK
EXTAL
32K
U0RXD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 1. MCF5373LCVM240 Pinout Top View (196 MAPBGA)
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
9
Mechanicals and Pinouts
4.2
Package Dimensions—196 MAPBGA
Figure 2 shows the MCF5373LCVM240 and MCF5372LCVM240 package dimensions.
NOTES:
1. Dimensions are in millimeters.
2. Interpret dimensions and tolerances
per ASME Y14.5M, 1994.
3. Dimension B is measured at the
maximum solder ball diameter,
parallel to datum plane Z.
4. Datum Z (seating plane) is defined
by the spherical crowns of the solder
balls.
5. Parallelism measurement shall
exclude any effect of mark on top
surface of package.
D
X
Laser mark for pin 1
identification in
this area
Y
M
K
Millimeters
DIM Min Max
E
A
A1
A2
b
D
E
e
S
1.32 1.75
0.27 0.47
1.18 REF
0.35 0.65
15.00 BSC
15.00 BSC
1.00 BSC
0.50 BSC
M
Top View
0.20
13X
e
S
14 13 12 11 10
9
6
5
4
3
2
Metalized mark for
pin 1 identification
in this area
1
A
B
C
13X
5
D
S
E
e
F
A
0.30 Z
A2
G
H
J
K
L
M
A1
Z
0.15 Z
4
Detail K
Rotated 90 ° Clockwise
N
P
3
196X
b
0.30 Z X Y
0.10 Z
Bottom View
View M-M
Figure 2. 196 MAPBGA Package Dimensions (Case No. 1128A-01)
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
10
Preliminary
Freescale Semiconductor
Mechanicals and Pinouts
4.3
Pinout—160 QFP
A18
A17
A16
A15
IVDD
TEST
A14
VSS
SD_VDD
EVDD
VSS
SD_VDD
FB_CS0
FB_CS1
A23/FB_CS5
A22/FB_CS4
A21
A20
A19
FEC_RXD2
FEC_RXD3
FEC_RXDV
FEC_RXCLK
FEC_CRS
FEC_COL
U1CTS
U1RTS
U1TXD
U1RXD
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
TA
SD_VDD
VSS
EVDD
IRQ7
IRQ4
IRQ1
PLL_VDD
PLL_VSS
IVDD
JTAG_EN
RESET
EVDD
XTAL
DRAMSEL
EXTAL
TDI/DSI
VSS
TRST/DSCLK
TMS/BKPT
RSTOUT
U0CTS
U0RTS
U0TXD
VSS
EVDD
D2
D1
D0
R/W
OE
SD_VDD
VSS
EVDD
TCLK/PSTCLK
EVDD
RCON
ALL_PST
TDO/DSO
QSPI_DIN
QSPI_DOUT
QSPI_CLK
QSPI_CS2
IVDD
U0RXD
D17
D16
BE/BWE2
SD_DQS0/2
BE/BWE0
D7
D6
D5
D4
D3
SD_VDD
VSS
SD_A10
SD_CAS
SD_RAS
D23
D22
D21
D20
D19
D18
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SD_WE
SD_CKE
SD_CS0
D15
D14
D13
D12
D11
D10
D9
D8
BE/BWE1
SD_DQS1/3
BE/BWE3
D31
D30
D29
D28
D27
D26
D25
D24
SD_DR_DQS
IVDD
SD_CLK
SD_CLK
SD_VDD
FB_CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
•
FEC_TXD1
FEC_TXD0
FEC_MDIO
FEC_MDC
DT0IN
DT1IN
DT2IN
DT3IN
EVDD
VSS
SD_VDD
TS
160 EVDD
159 VSS
158 FEC_TXD2
157 FEC_TXD3
156 IVDD
155 FEC_TXER
154 FEC_TXEN
153 FEC_TXCLK
152 FEC_RXER
151 FEC_RXD0
150 FEC_RXD1
The pinout for the MCF5372CAB180 and MCF5373CAB180 packages is shown below.
Figure 3. MCF5372CAB180 and MCF5373CAB180 Pinout Top View (160 QFP)
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
11
Mechanicals and Pinouts
4.4
Package Dimensions—160 QFP
Figure 4 and Figure 5 show the MCF5372CAB180 and MCF5373CAB180 package dimensions.
Top View
Figure 4. 160QFP Package Dimensions (Sheet 1 of 2)
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
12
Preliminary
Freescale Semiconductor
Mechanicals and Pinouts
Figure 5. 160QFP Package Dimensions (Sheet 2 of 2)
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
13
Preliminary Electrical Characteristics
5
Preliminary Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5373
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5373.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however
for production silicon these specifications will be met. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this MCU document supersede any values
found in the module specifications.
5.1
Maximum Ratings
Table 4. Absolute Maximum Ratings1, 2
Rating
Symbol
Value
Unit
Core Supply Voltage
IVDD
– 0.5 to +2.0
V
CMOS Pad Supply Voltage
EVDD
– 0.3 to +4.0
V
DDR/Memory Pad Supply Voltage
SDVDD
– 0.3 to +4.0
V
PLL Supply Voltage
PLLVDD
– 0.3 to +2.0
V
VIN
– 0.3 to +3.6
V
ID
25
mA
TA
(TL - TH)
– 40 to +85
°C
Tstg
– 55 to +150
°C
Digital Input Voltage 3
Instantaneous Maximum Current
Single pin limit (applies to all pins) 3, 4, 5
Operating Temperature Range (Packaged)
Storage Temperature Range
NOTES:
1
Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.”
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is
not guaranteed. Continued operation at these levels may affect device reliability or cause
permanent damage to the device.
2 This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid application of
any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,
either VSS or EVDD).
3 Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
then use the larger of the two values.
4
All functional non-supply pins are internally clamped to VSS and EVDD.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
14
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
5
5.2
Power supply must maintain regulation within operating EVDD range during instantaneous
and operating maximum current conditions. If positive injection current (Vin > EVDD) is greater
than IDD, the injection current may flow out of EVDD and could result in external power supply
going out of regulation. Insure external EVDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power (ex; no
clock). Power supply must maintain regulation within operating EVDD range during
instantaneous and operating maximum current conditions.
Thermal Characteristics
Table 5. Thermal Characteristics
Characteristic
Symbol
256MBGA
196MBGA
160QFP
Unit
Junction to ambient, natural convection
Four layer board
(2s2p)
θJMA
261,2
321,2
401,2
°C/W
Junction to ambient (@200 ft/min)
Four layer board
(2s2p)
θJMA
231,2
291,2
361,2
°C/W
Junction to board
θJB
153
203
253
°C/W
Junction to case
θJC
104
104
104
°C/W
Junction to top of package
Ψjt
21,5
21,5
21,5
°C/W
Maximum operating junction temperature
Tj
105
105
105
oC
NOTES:
1 θ
JMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJmA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction
temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device
junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt
parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
2 Per JEDEC JESD51-6 with the board horizontal.
3
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in °C can be obtained from:
T J = T A + ( P D × Θ JMA )
Eqn. 1
Where:
TA
= Ambient Temperature, °C
QJMA
= Package Thermal Resistance, Junction-to-Ambient, °C/W
PD
= PINT + PI/O
PINT
= IDD × IVDD, Watts - Chip Internal Power
PI/O
= Power Dissipation on Input and Output Pins — User Determined
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
15
Preliminary Electrical Characteristics
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if
PI/O is neglected) is:
K
P D = --------------------------------( T J + 273°C )
Eqn. 2
Solving equations 1 and 2 for K gives:
2
K = P D × ( T A × 273°C ) + Q JMA × P D
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
5.3
ESD Protection
Table 6. ESD Protection Characteristics1, 2
Characteristics
ESD Target for Human Body Model
Symbol
Value
Units
HBM
2000
V
NOTES:
1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 7. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
Core Supply Voltage
IVDD
1.4
1.6
V
PLL Supply Voltage
PLLVDD
1.4
1.6
V
EVDD
3.0
3.6
V
Mobile DDR/Bus Pad Supply Voltage
SDVDD
1.65
1.95
V
DDR/Bus Pad Supply Voltage
SDVDD
2.25
2.75
V
SDR/Bus Pad Supply Voltage
SDVDD
3.0
3.6
V
USBVDD
3.0
3.6
V
CMOS Input High Voltage
EVIH
2
EVDD + 0.05
V
CMOS Input Low Voltage
EVIL
-0.05
0.8
V
Mobile DDR/Bus Input High Voltage
SDVIH
TBD
SDVDD + 0.05
V
Mobile DDR/Bus Input Low Voltage
SDVIL
-0.05
TBD
V
DDR/Bus Input High Voltage
SDVIH
2
SDVDD + 0.05
V
DDR/Bus Input Low Voltage
SDVIL
-0.05
0.8
V
CMOS Pad Supply Voltage
USB Supply Voltage
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
16
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 7. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
Iin
-1.0
1.0
µA
CMOS Output High Voltage
IOH = –5.0 mA
EVOH
EVDD - 0.4
—
V
CMOS Output Low Voltage
IOL = 5.0 mA
EVOL
—
0.4
V
DDR/Bus Output High Voltage
IOH = –5.0 mA
SDVOH
SDVDD - 0.4
—
V
DDR/Bus Output Low Voltage
IOL = 5.0 mA
SDVOL
—
0.4
V
IAPU
-10
-130
µA
—
—
7
7
Input Leakage Current
Vin = VDD or VSS, Input-only pins
Weak Internal Pull-Up Device Current, tested at VIL Max.1
2
Cin
Input Capacitance
All input-only pins
All input/output (three-state) pins
pF
NOTES:
1 Refer to the signals section for pins having weak internal pull-up devices.
2 This parameter is characterized before qualification rather than 100% tested.
5.4.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins.
The filter shown in Figure 6 should be connected between the board VDD and the PLLVDD pins. The
resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible.
10 Ω
Board VDD
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 6. System PLL VDD Power Filter
5.4.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in
Figure 7 should be connected between the board EVDD or IVDD and each of the USBVDD pins. The
resistor and capacitors should be placed as close to the dedicated USBVDD pin as possible.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
17
Preliminary Electrical Characteristics
0Ω
Board EVDD/IVDD
USB VDD Pin
10 µF
0.1 µF
GND
Figure 7. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also
recommended in parallel with those shown.
5.4.3
Supply Voltage Sequencing and Separation Cautions
DC Power Supply Voltage
Figure 8 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SDVDD), PLL VDD
(PLLVDD), and Core VDD (IVDD).
EVDD, SDVDD, USBVDD
3.3V
Supplies Stable
2.5V
1.5V
SDVDD (2.5V/1.8V)
IVDD, PLLVDD
1
2
0
Time
Notes:
1. IVDD should not exceed EVDD, SDVDD or PLLVDD by more than
0.4 V at any time, including power-up.
2. Recommended that IVDD/PLLVDD should track EVDD/SDVDD up to
0.9 V, then separate for completion of ramps.
3. Input voltage must not be greater than the supply voltage (EVDD, SDVDD,
IVDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
4. Use 1 ms or slower rise time for all supplies.
Figure 8. Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences.
Both SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
18
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
5.4.3.1
Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, then the sense circuits in the I/O pads will cause all
pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on
how long after EVDD/SDVDD powers up before IVDD must powered up. IVDD should not lead the EVDD,
SDVDD or PLLVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal
ESD protection diodes. The rise times on the power supplies should be slower than 1 µs to avoid turning
on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1. Use 1 µs or slower rise time for all supplies.
2. IVDD/PLLVDD and EVDD/SDVDD should track up to 0.9 V, then separate for the completion of
ramps with EVDD/SD VDD going to the higher external voltages. One way to accomplish this is to
use a low drop-out voltage regulator.
5.4.3.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers
to be in a high impedance state. There is no limit on how long after IVDD and PLLVDD power down before
EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more
than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There
are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IVDD/PLLVDD to 0 V.
2. Drop EVDD/SDVDD supplies.
5.5
Power Consumption Specifications
Estimated maximum RUN mode power consumption measurements are shown in the below figure.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
19
Preliminary Electrical Characteristics
Estimated Power Consumption vs. Core Frequency
Power Consumption (mW)
300
250
200
150
100
50
0
0
40
80
120
160
200
240
Core Frequency (MHz)
Figure 9. Estimated Maximum RUN Mode Power Consumption
Table 8 lists estimated maximum power and current consumption for the device in various operating
modes.
Table 8. Estimated Maximum Power Consumption Specifications
Characteristic
Symbol
Run Mode - Total Power Dissipation
Static
Dynamic
Core Operating Supply Current 1
Run Mode
Typical
Max
Unit
—
—
—
250
5.74
244
mW
mW
mW
—
TBD
mA
—
—
—
144
96
1
mA
mA
mA
IDD
Pad Operating Supply Current
Run Mode (application dependent)
Wait Mode
Stop Mode
EIDD
NOTES:
1 Current measured at maximum system clock frequency, all modules active, and default drive
strength with matching load.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
20
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
5.6
Oscillator and PLL Electrical Characteristics
Table 9. PLL Electrical Characteristics
Num
1
Characteristic
PLL Reference Frequency Range
Crystal reference
External reference
Symbol
Min.
Value
Max.
Value
Unit
fref_crystal
fref_ext
TBD
TBD
16
16
MHz
MHz
fsys
fsys/3
TBD
TBD
240
80
MHz
MHz
tcst
—
10
ms
2
Core frequency
CLKOUT Frequency1
3
Crystal Start-up Time2, 3
4
EXTAL Input High Voltage
Crystal Mode4
All other modes (External, Limp)
VIHEXT
VIHEXT
TBD
TBD
TBD
TBD
V
V
EXTAL Input Low Voltage
Crystal Mode4
All other modes (External, Limp)
VILEXT
VILEXT
TBD
TBD
TBD
TBD
V
V
5
30
pF
tlpll
—
1
ms
tdc
40
60
%
5
6
7
8
XTAL Load Capacitance2
PLL Lock Time
Duty Cycle of
2, 5
reference 2
NOTES:
1 All internal registers retain data at 0 Hz.
2 This parameter is guaranteed by characterization before qualification rather than 100% tested.
3 Proper PC board layout procedures must be followed to achieve specifications.
4 This parameter is guaranteed by design rather than 100% tested.
5
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in
the synthesizer control register (SYNCR).
5.7
External Interface Timing Characteristics
Table 10 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings
listed in Table 10 are shown in Figure 11 and Figure 12.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
21
Preliminary Electrical Characteristics
* The timings are also valid for inputs sampled on the negative clock edge.
1.5V
FB_CLK (80MHz)
TSETUP
THOLD
Input Setup And Hold
Invalid
1.5V
Valid
1.5V
Invalid
trise
Input Rise Time
Vh = VIH
Vl = VIL
tfall
Input Fall Time
FB_CLK
Vh = VIH
Vl = VIL
B4
B5
Inputs
Figure 10. General Input Timing Requirements
5.7.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to
slave-only devices up to a maximum bus frequency of 80MHz. It can be directly connected to
asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or
other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple
chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects
(FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory
interfaces. Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte
(8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common
ROM/flash memories.
5.7.1.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the system clock.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
22
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 10. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
—
80
Mhz
fsys/3
tFBCK
—
12.5
ns
tcyc
Frequency of Operation
FB1
Clock Period (FB_CLK)
FB2
Address, Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)
tFBCHDCV
—
7.0
ns
1
FB3
Address, Data, and Control Output Hold (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)
tFBCHDCI
1
—
ns
1, 2
FB4
Data Input Setup
tDVFBCH
3.5
—
ns
FB5
Data Input Hold
tDIFBCH
0
—
ns
FB6
Transfer Acknowledge (TA) Input Setup
tCVFBCH
4
—
ns
FB7
Transfer Acknowledge (TA) Input Hold
tCIFBCH
0
—
ns
FB8
Address Output Valid (A[23:0])
tFBCHAV
—
6.0
ns
FB9
Address Output Hold (A[23:0])
tFBCHAI
1
—
ns
3
NOTES:
1 Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.8.2, “DDR SDRAM AC Timing
Characteristics” for SD_CS[3:0] timing.
2
The FlexBus supports programming an extension of the address hold. Please consult the MCF5373 Reference
Manual for more information.
3 These specs are used when the A[23:0] signals are configured as 23-bit, non-muxed FlexBus address signals.
FB_CLK
FB1
FB3
A[23:0]
A[23:0]
FB2
D[31:0]
FB5
DATA
R/W
FB4
TS
FB_CSn
BE/BWEn
FB7
OE
FB6
TA
Figure 11. FlexBus Read Timing.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
23
Preliminary Electrical Characteristics
FB_CLK
FB1
FB3
A[23:0]
FB2
FB3
D[31:0]
R/W
TS
FB_CSn
BE/BWEn
FB7
OE
FB6
TA
Figure 12. Flexbus Write Timing
5.8
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.8.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read
cycles. The device’s SDRAM controller is a DDR controller that has an SDR mode. Because it is designed
to support DDR, a DQS pulse must still be supplied to device for each data beat of an SDR read. Te
processor accomplishes this by asserting a signal named SD_DQS during read cycles. Care must be taken
during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal
and its usage.
Table 11. SDR Timing Specifications
Symbol
Characteristic
Symbol
Frequency of Operation
Min
Max
Unit
Notes
TBD
80
Mhz
1
ns
2
SD_CLK
3
SD1
Clock Period
tSDCK
12.5
TBD
SD2
Clock Skew
tSDSK
—
TBD
SD3
Pulse Width High
tSDCKH
0.45
0.55
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
24
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 11. SDR Timing Specifications (continued)
Symbol
Characteristic
Symbol
Min
Max
Unit
Notes
tSDCKH
0.45
0.55
SD_CLK
4
SD4
Pulse Width Low
SD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
tSDCHACV
—
0.5 × SD_CLK
+ 1.0
ns
SD6
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
ns
SD7
SD_SDR_DQS Output Valid
tDQSOV
—
Self timed
ns
5
SD8
SD_DQS[3:0] input setup relative to SD_CLK
tDQVSDCH
0.25 ×
SD_CLK
0.40 × SD_CLK
ns
6
SD9
SD_DQS[3:2] input hold relative to SD_CLK
tDQISDCH
SD10
Data (D[31:0]) Input Setup relative to SD_CLK (reference
only)
tDVSDCH
0.25 ×
SD_CLK
—
ns
SD11
Data Input Hold relative to SD_CLK (reference only)
tDISDCH
1.0
—
ns
SD12
Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid
tSDCHDMV
—
0.75 × SD_CLK
+ 0.5
ns
SD13
Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
tSDCHDMI
1.5
—
ns
Does not apply. 0.5×SD_CLK fixed
width.
7
8
NOTES:
1 The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.
Please see the PLL chapter of the MCF5373 Reference Manual for more information on setting the SDRAM clock rate.
2 SD_CLK is one SDRAM clock in (ns).
3 Pulse width high plus pulse width low cannot exceed min and max clock period.
4 Pulse width high plus pulse width low cannot exceed min and max clock period.
5 SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat.
6 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data
beat.
7 The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
8 Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup
spec is just provided as guidance.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
25
Preliminary Electrical Characteristics
SD3
SD1
SD2
SD_CLK0
SD4
SD2
SD_CLK1
SD6
SD_CSn
SD_RAS
SD_CAS
SD_WE
CMD
SD5
A[23:0]
SD_BA[1:0]
ROW
COL
SD12
SDDM
SD13
WD1
D[31:0]
WD2
WD3
WD4
Figure 13. SDR Write Timing
SD2
SD1
SD_CLK0
SD2
SD_CLK1
SD_CSn,
SD_RAS,
SD_CAS,
SD_WE
A[23:0],
SD_BA[1:0]
SD6
CMD
3/4 MCLK
Reference
SD5
ROW
COL
tDQS
SDDM
SD7
SD_DQS
(Measured at Output Pin)
Board Delay
SD_DDQS
SD9
(Measured at Input Pin)
SD8
Board Delay
Delayed
SD_CLK
SD10
D[31:0]
from
Memories
WD1
NOTE: Data driven from memories relative
to delayed memory clock.
WD2
WD3
WD4
SD11
Figure 14. SDR Read Timing
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
26
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
5.8.2
DDR SDRAM AC Timing Characteristics
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to
properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte
lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early
board design. Please contact your local Freescale representative if questions develop.
Table 12. DDR Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
tDDCK
80
TBD
Mhz
1
DD1
Clock Period
tDDSK
TBD
12.5
ns
2
DD2
Pulse Width High
tDDCKH
0.45
0.55
SD_CLK
3
DD3
Pulse Width Low
tDDCKL
0.45
0.55
SD_CLK
3
DD4
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
tSDCHACV
—
0.5 × SD_CLK
+ 1.0
ns
4
DD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
ns
DD6
Write Command to first DQS Latching Transition
tCMDVDQ
—
1.25
SD_CLK
DD7
Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
tDQDMV
1.5
—
ns
DD8
Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
tDQDMI
1.0
—
ns
7
DD9
Input Data Skew Relative to DQS (Input Setup)
tDVDQ
—
1
ns
8
tDIDQ
0.25 × SD_CLK
+ 0.5ns
—
ns
9
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH
0.5
—
ns
DD12 DQS input read preamble width
tDQRPRE
0.9
1.1
SD_CLK
DD13 DQS input read postamble width
tDQRPST
0.4
0.6
SD_CLK
DD14 DQS output write preamble width
tDQWPRE
0.25
DD15 DQS output write postamble width
tDQWPST
0.4
DD10 Input Data Hold Relative to DQS.
5
6
SD_CLK
0.6
SD_CLK
NOTES:
1
The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.
2
SD_CLK is one SDRAM clock in (ns).
3 Pulse width high plus pulse width low cannot exceed min and max clock period.
4 Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process,
temperature, and voltage variations.
5 This specification relates to the required input setup time of today’s DDR memories. Rigoletto’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
6
The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data
beats will be valid for each subsequent DQS edge.
7 This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
27
Preliminary Electrical Characteristics
8
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).
9
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line
becomes invalid.
SD_CLK
VIX
VMP
VIX
VID
SD_CLK
Figure 15. SD_CLK and SD_CLK crossover timing
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
DD4
A[13:0]
DD6
ROW
COL
DD7
DM3/DM2
DD8
SD_DQS3/SD_DQS2
DD7
WD1 WD2 WD3 WD4
D[31:24]/D[23:16]
DD8
Figure 16. DDR Write Timing
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
28
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
CL=2
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
CL=2.5
DD4
A[13:0]
ROW
COL
DD9
DQS Read
Preamble
CL = 2
SD_DQS3/SD_DQS2
DQS Read
Postamble
DD10
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
DQS Read
DQS Read
Preamble
Postamble
CL = 2.5
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 17. DDR Read Timing
5.9
General Purpose I/O Timing
Table 13. GPIO Timing1
Num
Characteristic
Symbol
Min
Max
Unit
G1
FB_CLK High to GPIO Output Valid
tCHPOV
—
10
ns
G2
FB_CLK High to GPIO Output Invalid
tCHPOI
1.5
—
ns
G3
GPIO Input Valid to FB_CLK High
tPVCH
9
—
ns
G4
FB_CLK High to GPIO Input Invalid
tCHPI
1.5
—
ns
NOTES:
1 GPIO pins include: IRQn, PWM, UART, and Timer pins.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
29
Preliminary Electrical Characteristics
FB_CLK
G2
G1
GPIO Outputs
G3
G4
GPIO Inputs
Figure 18. GPIO Timing
5.10 Reset and Configuration Override Timing
Table 14. Reset and Configuration Override Timing
Num
Characteristic
Symbol
Min
Max
Unit
R1
RESET Input valid to FB_CLK High
tRVCH
9
—
ns
R2
FB_CLK High to RESET Input invalid
tCHRI
1.5
—
ns
R3
RESET Input valid Time 1
tRIVT
5
—
tCYC
R4
FB_CLK High to RSTOUT Valid
tCHROV
—
10
ns
R5
RSTOUT valid to Config. Overrides valid
tROVCV
0
—
ns
R6
Configuration Override Setup Time to RSTOUT invalid
tCOS
20
—
tCYC
R7
Configuration Override Hold Time after RSTOUT invalid
tCOH
0
—
ns
R8
RSTOUT invalid to Configuration Override High Impedance
tROICZ
—
1
tCYC
NOTES:
1 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.
FB_CLK
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides*:
(RCON, Override pins])
Figure 19. RESET and Configuration Override Timing
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
30
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
NOTE
Refer to the CCM chapter of the MCF5373 Reference Manual for more
information.
5.11 USB On-The-Go
The MCF5373 device is compliant with industry standard USB 2.0 specification.
5.12 SSI Timing Specifications
The following figure and table lists the specifications for the SSI module.
S1
S2
S3
SSI_BCLK
S4
S5
SSI_MCLK
STFS
S6
S7
SSI_TXD (Output)
STFS
S6
SSI_RXD (Input)
Note: SSI External. Continous clock Synchronous mode only
Figure 20. SSI External Continous Clock Timing Diagram
Table 15. SSI Timing
1.8 +/- 0.10V
Num
Description
Unit
Minimum
Maximum
S1
SSI_BCLK clock period
1/(64fs)1
49
ns
S2
SSI_BCK high-level time
35
—
ns
S3
SSI_BCK low-level time
35
—
ns
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
31
Preliminary Electrical Characteristics
Table 15. SSI Timing (continued)
1.8 +/- 0.10V
Num
Description
Unit
Minimum
Maximum
S4
SSI_BCK rising edge to SSI_MCLK edge
10
—
ns
S5
SSI_MCLK edge to SSI_BCLK rising edge
10
—
ns
S6
SSI_TXD/SSI_RXD data set-up time
10
—
ns
S7
SSI_TXD/SSI_RXD data hold time
10
—
ns
NOTES:
1
fs is the sampling frequency. SSI_BCLK can be operated upto 512 times the sampling frequency to a max frequency of 49.152MHz
5.13 I2C Input/Output Timing Specifications
Table 16 lists specifications for the I2C input timing parameters shown in Figure 21.
Table 16. I2C Input Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2
—
tcyc
I2
Clock low period
8
—
tcyc
I3
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
1
ms
I4
Data hold time
0
—
ns
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
1
ms
I6
Clock high time
4
—
tcyc
I7
Data setup time
0
—
ns
I8
Start condition setup time (for repeated start condition only)
2
—
tcyc
I9
Stop condition setup time
2
—
tcyc
Table 17 lists specifications for the I2C output timing parameters shown in Figure 21.
Table 17. I2C Output Timing Specifications between SCL and SDA
Num
I11
Characteristic
Min
Max
Units
Start condition hold time
6
—
tcyc
I2
1
Clock low period
10
—
tcyc
I3
2
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
—
µs
I4 1
Data hold time
7
—
tcyc
I5 3
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
3
ns
I6
1
Clock high time
10
—
tcyc
I7
1
Data setup time
2
—
tcyc
I8 1
Start condition setup time (for repeated start condition only)
20
—
tcyc
I9 1
Stop condition setup time
10
—
tcyc
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
32
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
NOTES:
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 17. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers
given in Table 17 are minimum values.
2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively
drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance
and pull-up resistor values.
3 Specified at a nominal 50-pF load.
Figure 21 shows timing for the values in Table 17 and Table 16.
I5
I6
I2
I2C_SCL
I1
I4
I7
I8
I9
I3
I2C_SDA
Figure 21. I2C Input/Output Timings
5.14 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
5.14.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV,
FEC_RXER, and FEC_RXCLK)
The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FEC_RXCLK frequency.
Table 18 lists MII receive channel timings.
Table 18. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup
5
—
ns
M2
FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold
5
—
ns
M3
FEC_RXCLK pulse width high
35%
65%
FEC_RXCLK period
M4
FEC_RXCLK pulse width low
35%
65%
FEC_RXCLK period
Figure 22 shows MII receive signal timings listed in Table 18.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
33
Preliminary Electrical Characteristics
M3
FEC_RXCLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RXDV
FEC_RXER
M1
M2
Figure 22. MII Receive Signal Timing Diagram
5.14.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN,
FEC_TXER, FEC_TXCLK)
Table 19 lists MII transmit channel timings.
The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FEC_TXCLK frequency.
The transmit outputs (FEC_TXD[3:0], FEC_TXEN, FEC_TXER) can be programmed to transition from
either the rising or falling edge of FEC_TXCLK, and the timing is the same in either case. This options
allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Table 19. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid
5
—
ns
M6
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid
—
25
ns
M7
FEC_TXCLK pulse width high
35%
65%
FEC_TXCLK period
M8
FEC_TXCLK pulse width low
35%
65%
FEC_TXCLK period
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
34
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
Figure 23 shows MII transmit signal timings listed in Table 19.
M7
FEC_TXCLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TXEN
FEC_TXER
M6
Figure 23. MII Transmit Signal Timing Diagram
5.14.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 20 lists MII asynchronous inputs signal timing.
Table 20. MII Async Inputs Signal Timing
Num
M9
Characteristic
Min
Max
Unit
1.5
—
FEC_TXCLK period
FEC_CRS, FEC_COL minimum pulse width
Figure 24 shows MII asynchronous input timings listed in Table 20.
FEC_CRS
FEC_COL
M9
Figure 24. MII Async Inputs Timing Diagram
5.14.4 MII Serial Management Channel Timing (FEC_MDIO and
FEC_MDC)
Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum
MDC frequency of 2.5 MHz.
Table 21. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11
FEC_MDC falling edge to FEC_MDIO output valid (max prop delay)
—
25
ns
M12
FEC_MDIO (input) to FEC_MDC rising edge setup
10
—
ns
M13
FEC_MDIO (input) to FEC_MDC rising edge hold
0
—
ns
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
35
Preliminary Electrical Characteristics
Table 21. MII Serial Management Channel Timing (continued)
Num
Characteristic
Min
Max
Unit
M14
FEC_MDC pulse width high
40% 60% FEC_MDC period
M15
FEC_MDC pulse width low
40% 60% FEC_MDC period
Figure 25 shows MII serial management channel timings listed in Table 21.
M14
M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 25. MII Serial Management Channel Timing Diagram
5.15 32-Bit Timer Module Timing Specifications
Table 22 lists timer module AC timings.
Table 22. Timer Module AC Timing Specifications
Name
Characteristic
Unit
Min
Max
T1
DT0IN / DT1IN / DT2IN / DT3IN cycle time
3
—
tCYC
T2
DT0IN / DT1IN / DT2IN / DT3IN pulse width
1
—
tCYC
5.16 QSPI Electrical Specifications
Table 23 lists QSPI timings.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
36
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 23. QSPI Modules AC Timing Specifications
Name
Characteristic
Min
Max
Unit
QS1
QSPI_CS[3:0] to QSPI_CLK
1
510
tCYC
QS2
QSPI_CLK high to QSPI_DOUT valid.
—
10
ns
QS3
QSPI_CLK high to QSPI_DOUT invalid. (Output hold)
2
—
ns
QS4
QSPI_DIN to QSPI_CLK (Input setup)
9
—
ns
QS5
QSPI_DIN to QSPI_CLK (Input hold)
9
—
ns
The values in Table 23 correspond to Figure 26.
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QS3
QS4
QS5
QSPI_DIN
Figure 26. QSPI Timing
5.17 JTAG and Boundary Scan Timing
Table 24. JTAG and Boundary Scan Timing
Characteristics1
Num
Symbol
Min
Max
Unit
J1
TCLK Frequency of Operation
fJCYC
DC
1/4
fsys/3
J2
TCLK Cycle Period
tJCYC
4
—
tCYC
J3
TCLK Clock Pulse Width
tJCW
26
—
ns
J4
TCLK Rise and Fall Times
tJCRF
0
3
ns
J5
Boundary Scan Input Data Setup Time to TCLK Rise
tBSDST
4
—
ns
J6
Boundary Scan Input Data Hold Time after TCLK Rise
tBSDHT
26
—
ns
J7
TCLK Low to Boundary Scan Output Data Valid
tBSDV
0
33
ns
J8
TCLK Low to Boundary Scan Output High Z
tBSDZ
0
33
ns
J9
TMS, TDI Input Data Setup Time to TCLK Rise
tTAPBST
4
—
ns
J10
TMS, TDI Input Data Hold Time after TCLK Rise
tTAPBHT
10
—
ns
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
37
Preliminary Electrical Characteristics
Table 24. JTAG and Boundary Scan Timing (continued)
Characteristics1
Num
Symbol
Min
Max
Unit
J11
TCLK Low to TDO Data Valid
tTDODV
0
26
ns
J12
TCLK Low to TDO High Z
tTDODZ
0
8
ns
J13
TRST Assert Time
tTRSTAT
100
—
ns
J14
TRST Setup Time (Negation) to TCLK High
tTRSTST
10
—
ns
NOTES:
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
1
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 27. Test Clock Input Timing
TCLK
VIL
VIH
J5
Data Inputs
J6
Input Data Valid
J7
Data Outputs
Output Data Valid
J8
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 28. Boundary Scan (JTAG) Timing
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
38
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
TCLK
VIL
VIH
J9
TDI
TMS
J10
Input Data Valid
J11
TDO
Output Data Valid
J12
TDO
J11
TDO
Output Data Valid
Figure 29. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 30. TRST Timing
5.18 Debug AC Timing Specifications
Table 25 lists specifications for the debug AC timing parameters shown in Figure 32.
Table 25. Debug AC Timing Specification
Num
Characteristic
Units
Min
Max
DE0
PSTCLK cycle time
—
0.3
tcyc
DE1
PST valid to PSTCLK high
4
—
ns
DE2
PSTCLK high to PST invalid
1.5
—
ns
DE3
DSCLK cycle time
5
—
tcyc
DE4
DSI valid to DSCLK high
1
—
tcyc
DE51
DSCLK high to DSO invalid
4
—
tcyc
DE6
BKPT input data setup time to FB_CLK high
4
—
ns
DE7
FB_CLK high to BKPT invalid
0
—
ns
NOTES:
1 DSCLK and DSI are synchronized internally. DE4 is measured from the synchronized DSCLK input
relative to the rising edge of FB_CLK.
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
Freescale Semiconductor
Preliminary
39
Revision History
Figure 31 shows real-time trace timing for the values in Table 25.
PSTCLK
DE0
DE1
DE2
PST[3:0]
DDATA[3:0]
Figure 31. Real-Time Trace AC Timing
Figure 32 shows BDM serial port AC timing and BKPT pin timing for the values in Table 25.
FB_CLK
DE6
BKPT
DE7
DE5
DSCLK
DE3
Current
DSI
Next
DE4
DSO
Past
Current
Figure 32. BDM Serial Port AC Timing
6
Revision History
Table 26. MCF5373DS Document Revision History
Rev. No.
0
Substantive Changes
Date of Release
• Initial release.
11/2005
0.1
• Swapped pin locations PLL_VSS (J11->H11) and DRAMSEL
(H11->J11) in Table 3. Figure 1 is correct.
12/2005
0.2
• Added not to Section 4, “Mechanicals and Pinouts.”
• Added “top view” and “bottom view” where appropriate in mechanical
drawings and pinout figures.
• Figure 10: Corrected “FB_CLK (75MHz)” label to “FB_CLK (80MHz)”
3/2006
0.3
• Changed 160QFP pinouts in Figure 3 and Table 3: Removed IRQ3
pin, shifted pins 89–99 up one pin to 90–100. Pin 89 is now VSS.
• Table 3: Rearranged GPIO signal names for FEC pins.
• Removed ULPI specifications as the device does not support ULPI.
4/2006
MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
40
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MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3
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MCF5373DS
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