ISSI IS42S83200A-75TL 256 mb synchronous dram Datasheet

IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
ISSI
256 Mb Synchronous DRAM
November 2005
®
DESCRIPTION
IS42S83200A is a synchronous 256Mb SDRAM and is
organized as 4-bank x 8,388,608-word x 8-bit; and
IS42S16160A is organized as 4-bank x 4,194,304-word x
16-bit. All inputs and outputs are referenced to the rising
edge of CLK.
IS42S83200A and IS42S16160A achieve very
high speed clock rates up to 166MHz, and are
suitable for main memories or graphic
memories in computer systems.
FEATURES
IS42S83200A/16160A
ITEM
tCLK
Clock Cycle Time
-7
-75
-
10
Unit
ns
7
7.5
ns
42
45
45
15
20
-
20
-
ns
ns
ns
5
60
5.4
63
5.4
ns
67.5
ns
IS42S83200A
-
-
110
mA
IS42S16160A
130
130
-
mA
3
3
3
mA
-6
CL=2
CL=3
(Min.)
tRAS Active to Precharge Command Period (Min.)
(Min.)
tRCD Row to Column Delay
tAC
Access Time from CLK
(Max.)
tRC
Ref /Active Command Period
(Min.)
Icc1
Operation Current (Single Bank)
(Max.)
Icc6
Self Refresh Current
CL=2
CL=3
(Max.) -6,-7,-75
-
6
6
- Single 3.3V ±0.3V power supply
- Max. Clock frequency:
-6:166MHz<3-3-3>
-7:143MHz<3-3-3>
-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (IS42S16160A)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 8192 refresh cycles /64ms(4 banks concurrent refresh)
- LVTTL Interface
- Row address A0-12 /Column address A0-9(x8) / A0-8(x16)
- Package: 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
- Lead-free available
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
1
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
PIN CONFIGURATION (TOP VIEW)
x8
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
2
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
400mil x 875mil 54pin 0.8mm pitch TSOP(II)
x16
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
DQM, DQMU/L
A0-12
BA0,1
Vdd
VddQ
Vss
VssQ
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
: Output Disable / Write Mask
: Address Input
: Bank Address Input
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
BLOCK DIAGRAM
DQ0-7
I/O Buffer
Memory Array
Memory Array
Memory Array
8192x1024x8
Cell Array
8192x1024x8
Cell Array
Memory Array
8192x1024x8
Cell Array
8192x1024x8
Cell Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
A0-12
BA0,1
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
Note:This figure shows the IS42S83200A
The IS42S16160A configuration is 8192x512x16 of cell array and DQ0-15
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
3
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
PIN FUNCTION
Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
CKE
Input
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
/CS
Input
Chip Select:
When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
Input
A0-12 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12.
The Column Address is specified by A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Input
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
CLK
A0-12
BA0,1
DQ0-7(x8),
DQ0-15(x16)
DQM(x8),
DQMU/L(x16)
Vdd, Vss
VddQ, VssQ
4
Input / Output Data In and Data out are referenced to the rising edge of CLK.
Input
Power Supply
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Power Supply for the memory array and peripheral circuitry.
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
BASIC FUNCTIONS
The IS42S83200A/16160A provides basic
functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh.
Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals,
/CS, CKE and A10 are used as chip select, refresh opt ion,
and precharge option, respectively .
To know the detailed definition of commands,
please see the command truth table.
CLK
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @ refresh command
A10
Precharge Option @ precharge or read/write command
define basic command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.
First output data appears after /CAS latency. When A10 =H at this command,
the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total
data length to be written is set by burst length. When A10 =H at this command,
the bank is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This com­
mand also terminates burst read / write operation. When A10 =H at this
command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank
address are generated internally. After this command, the banks are
precharged automatically.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
5
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
CKE
n-1
CKE
n
/CS
/RAS
/CAS
A10
/AP
A0-9,
11-12
Deselect
DESEL
H
X
H
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
L
X
Precharge All Banks
PREA
H
X
L
L
H
L
X
H
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with
Auto-Precharge
WRITEA
H
X
L
H
L
L
V
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
L
V
Column Address Entry
& Read with
Auto-Precharge
READA
H
X
L
H
L
H
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Burst Terminate
TBST
H
X
L
H
H
L
X
X
X
Mode Register Set
MRS
H
X
L
L
L
L
L
L
V
/WE BA0,1
note
1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-9,11-12=L, A0-A6 =Mode Address
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
FUNCTION TRUTH TABLE
Current State
IDLE
ROW
ACTIVE
/CS
/RAS
/CAS
/WE
Address
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
Op-Code,
REFA
Auto-Refresh*5
L
L
L
L
Mode-Add
MRS
Mode Register Set*5
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
NOP
L
H
L
H
BA, CA, A10
READ / READA
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst
L
H
L
H
BA, CA, A10
READ
Action
READ / WRITE ILLEGAL*2
Bank Active, Latch RA
NOP*4
Begin Read, Latch CA,
Determine Auto-Precharge
Begin Write, Latch CA,
Determine Auto-Precharge
Terminate Burst, Latch CA,
READ / READA Begin New Read, Determine
Auto-Precharge*3
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine AutoPrecharge*3
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
Command
Bank Active / ILLEGAL*2
Terminate Burst, Precharge
7
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
FUNCTION TRUTH TABLE (continued)
Current State
WRITE
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
8
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Terminate Burst, Latch CA,
READ / READA Begin Read, Determine AutoPrecharge*3
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine AutoPrecharge*3
Bank Active / ILLEGAL*2
Terminate Burst, Precharge
READ / READA ILLEGAL
WRITE /
WRITEA
ILLEGAL
Bank Active / ILLEGAL*2
ILLEGAL*2
READ / READA ILLEGAL
WRITE /
WRITEA
ILLEGAL
Bank Active / ILLEGAL*2
ILLEGAL*2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
WRITE RE-
L
H
L
X
BA, CA, A10
COVERING
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
PRE CHARGING
ROW
ACTIVATING
Address
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
Command
Action
READ / WRITE ILLEGAL*2
ILLEGAL*2
NOP*4 (Idle after tRP)
REFA
ILLEGAL
MRS
ILLEGAL
READ / WRITE ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
READ / WRITE ILLEGAL*2
9
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
H
X
X
X
X
DESEL
NOP (Idle after tRC)
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
L
H
H
H
X
NOP
NOP (Idle after tRSC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
REFRESHING
MODE
REGISTER
SETTING
Address
Command
Action
READ / WRITE ILLEGAL
READ / WRITE ILLEGAL
Op-Code,
Mode-Add
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
FUNCTION TRUTH TABLE (continued)
Current State
SELFREFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
ANY STATE
other than
listed above
CKE CKE
/CS
/RAS /CAS
/WE
Add
X
X
X
INVALID
X
X
X
X
Exit Self-Refresh (Idle after tRC)
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Power Down)
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State =Power Down
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle*3
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CLK Suspend
n-1
n
H
X
X
X
L
H
H
L
H
L
Action
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be
satisfied before any command other than EXIT.
2. Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
11
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MODE
REGISTER
SET
MRS
REFA
AUTO
REFRESH
IDLE
CKEL
CLK
SUSPEND
CKEH
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
TERM
TERM
READ
WRITE
WRITE
SUSPEND
WRITEA
CKEL
WRITE
CKEH
READA
READ
READ
WRITE
READA
WRITEA
POWER
APPLIED
READ
SUSPEND
CKEH
WRITEA
WRITEA
SUSPEND
CKEL
READA
CKEL
CKEL
WRITEA
READA
CKEH
CKEH
POWER
ON
PRE
PRE
PRE
READA
SUSPEND
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
POWER ON SEQUENCE
MODE REGISTER
Before starting normal operation, the following
power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
Burst Length, Burst Type and /CAS Latency can
be programmed by setting the mode register
1. Apply power and start clock. Attempt to maintain
CKE high, DQM high and NOP condition at the
inputs.
when all banks are in idle state. After tRSC from a
MRS command, the SDRAM is ready for new
®
(MRS). The mode register stores these data until
the next MRS command, which may be issued
command.
2. Maintain stable power, stable clock, and NOP
input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE
or PREA)
4. After all banks become idle state (after tRP),
issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize
the mode register.
CLK
/CS
After these sequence, the SDRAM is idle state and
ready for normal operation.
/RAS
/CAS
/WE
BA0,1 A12-A0
BA0 BA1 A12 A11 A10 A9
0
LATENCY
MODE
0
0
0
CL
000
001
010
011
100
101
110
111
0
SW
SW
0
1
A8
A7
0
0
A6
A5
A4
LTMODE
A3
A2
BT
Burst Write
Single Write
/CAS LATENCY
R
R
2
3
R
R
R
R
A1
V
A0
BL
BURST
LENGTH
BL
000
001
010
011
100
101
110
111
BURST
TYPE
0
1
BT=0
1
2
4
8
R
R
R
Full Page
BT=1
1
2
4
8
R
R
R
R
SEQUENTIAL
INTERLEAVED
R: Reserved for Future Use
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
13
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
CLK
Command
Read
Write
Y
Y
Address
Q1
Q0
DQ
Q2
D1
D0
Q3
D2
D3
/CAS Latency
CL= 3
BL= 4
Burst Length
Burst Length
Burst Type
Initial Address BL
Column Addressing
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
Sequential
Interleaved
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
-
14
-
1
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
OPERATIONAL DESCRIPTION
BANK ACTIVATE
READ
The SDRAM has four independent banks. Each bank
is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-12. The minimum activation interval between one bank and the other bank is tRRD.Multiple
banks can be active state concurrently by issuing mul­
tiple ACT commands.
After tRCD from the bank activation, a READ
command can be issued. 1st output data is available after the /CAS Latency from the READ, fol­
lowed by (BL -1) consecutive data when the Burst
Length is BL. The start address is specified by
A0-9(X8), A0-8(X16) , and the address sequence of
burst data is defined by the Burst Type.
A READ command may be applied to any
active bank, so the row precharge time (tRP) can be
hidden behind continuous output data by
interleaving the multiple banks. When A10 is high
at a READ command, the auto-precharge
(READA) is performed. Any command (READ,
WRITE, PRE, TBST, ACT) to the same bank is
inhibited till the internal precharge is complete.
The internal precharge starts at BL after READA.
The next ACT command can be issued after (BL
PRECHARGE
The PRE command deactivates the bank indicated
by BA0,1. When multiple banks are active, the
precharge all command (PREA, PRE + A10=H) is
available to deactivate them at the same time.
After tRP from the precharge, an ACT command to the
same bank can be issued.BA0-1 are “DON’T CARE”
in this case.
+ tRP) from the previous READA.
In any case, tRCD+BL ≥ tRASmin must be met.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
ACT
ACT
tRRD
READ
PRE
tRCD
ACT
tRP
A0-9,11-12
Xa
Xb
Yb
A10
Xa
Xb
0
BA0-1
00
01
01
DQ
Xa
1
Xa
00
Qb0
Qb1
Qb2
Qb3
Precharge All
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
15
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Multi Bank Interleaving Read (CL=2, BL=4)
CLK
Command
READ
ACT
ACT
READ PRE
tRCD
tRCD
ACT
tRP
A0-9,11-12
Xa
Ya
Xb
Yb
A10
Xa
0
Xb
0
0
Xa
BA0-1
00
00
01
01
00
00
Qa2
Qa3
DQ
Qa0
Qa1
Xa
Qb0
Qb1
Qb2
Qb3
Read with Auto-Precharge (CL=2, BL=4)
CLK
Command
READ
ACT
ACT
BL
tRCD
tRP
A0-9,11-12
Xa
Ya
Xa
A10
Xa
1
Xa
BA0-1
00
00
00
DQ
Qa0
Qa1
Qa2
Qa3
internal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK
Command
READ
ACT
tRCD
DQ
CL=2
DQ
CL=3
ACT
BL
Qa0
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
internal precharge starts
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
WRITE
A WRITE command can be issued to any active bank.
The start address is specified by A0-9(x8), A0-8(x16).
1st input data is set at the same cycle as the WRITE.
The consecutive data length to be write is defined
by the Burst Length. The address sequence of
burst data is defined by Burst Type. Minmum delay
time of a WRITE command after an ACT command to
the same bank is tRCD. From the last input data to the
PRE command , the write recovery time (tWR) is
required. When A10 is high at a WRITE command ,
auto-precharge (WRITEA) is performed. Any com­
mand (READ,WRITE,PRE,ACT,TBST) to the same
bank is inhibited till the internal precharge is complete.
The internal precharge starts at tWR after the last input
data cycle . The next ACT command can be issued
after (BL+tWR-1+tRP) from the previous WRITEA. In
any case, tRCD+BL+tWR-1 ≥ tRASmin must be met.
Write (BL=4)
CLK
Command
ACT
PRE
Write
BL
tRCD
A0-9,11-12
Xa
Ya
A10
Xa
0
BA0-1
00
00
ACT
tRP
Xa
0
Xa
00
tWR
Da0
DQ
Da1
Da2
Da3
Write with Auto-Precharge (BL=4)
CLK
Command
Write
ACT
ACT
BL
tRCD
tRP
A0-9,11-12
Xa
Ya
Xa
A10
Xa
1
Xa
BA0-1
00
00
00
tWR
DQ
Da0
Da1
Da2
Da3
internal precharge starts
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
17
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed
READ to READ interval is minimum 1 CLK..
Read interrupted by Read (CL=2, BL=4)
CLK
Command
READ
A0-9,11-12
Ya
Yb
Yc
A10
0
0
0
BA0-1
00
00
10
Qa1
Qa2
READ READ
DQ
Qa0
Qb0
Qc0
Qc1
Qc2
Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the
DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled
automatically 2 cycle after WRITE assertion.
Read interrupted by Write (CL=2, BL=4)
CLK
Command
ACT
READ
Write
A0-9,11-12
Xa
Ya
Ya
A10
Xa
0
0
BA0-1
00
00
00
DQM
DQ
Qa0
Da0
Da1
Output disable by DQM
18
Da2
Da3
by WRITE
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge
of the same bank . READ to PRE interval is minimum 1
CLK. A PRE command to output disable latency is
equivalent to the /CAS Latency. As a result, READ to
PRE interval determines valid data length to be output.
The figure below shows examples of BL=4.
Read interrupted by Precharge (BL=4)
CLK
Command
DQ
Command
PRE
READ
Q0
READ
Q1
Q2
PRE
CL=2
DQ
Command
Q0
READ PRE
DQ
Command
Q0
PRE
READ
DQ
Command
Q1
READ
Q0
Q1
Q0
Q1
Q2
PRE
CL=3
DQ
Command
READ PRE
DQ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
Q0
19
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
[Read Interrupted by Burst Terminate]
Similarly to the precharge, a burst terminate command
can interrupt the burst read operation and disable the
data output. The terminated bank remains active.
READ to TBST interval is minimum 1 CLK. A TBST
command to output disable latency is equivalent to
the /CAS Latency.
Read interrupted by Terminate (BL=4)
CLK
Command
READ
DQ
Command
TBST
Q0
READ
Q1
Q2
TBST
CL=2
DQ
Command
Q0
READ TBST
DQ
Command
Q0
TBST
READ
DQ
Command
Q1
READ
Q0
Q1
Q0
Q1
Q2
TBST
CL=3
DQ
Command
DQ
20
READ TBST
Q0
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to
WRITE interval is minimum 1 CLK.
Write interrupted by Write (BL=4)
CLK
Command
Write
Write
Write
A0-9,11-12
Ya
Yb
Yc
A10
0
0
0
BA0-1
00
00
10
DQ
Da0
Db0
Dc0
Da2
Da1
Dc1
Dc2
Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"don't care".
Write interrupted by Read (CL=2, BL=4)
CLK
Command
ACT
Write
READ
A0-9,11-12
Xa
Ya
Yb
A10
Xa
0
0
BA0-1
00
00
00
DQ
Da0
Da1
Qb0
Qb1
Qb2
Qb3
don't care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
21
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is
required from the last data to PRE command. During write recovery, data inputs must be masked by DQM.
Write interrupted by Precharge (BL=4)
CLK
Command
ACT
Write
ACT
PRE
tRP
A0-9,11-12
Xa
Ya
A10
0
0
0
0
BA0-1
00
00
00
00
Xa
DQM
tWR
DQ
Da0
Da1
[Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation.In this case, the write recovery time is not
required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write interrupted by Terminate (BL=4)
CLK
Command
ACT
Write
A0-9,11-12
Xa
Ya
Yb
A10
0
0
0
BA0-1
00
00
00
DQ
22
Da0
TBST
Da1
Write
Db0
Db1
Db2
Db3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
[Write with Auto-Precharge Interrupted by Write or Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command
can be issued after(BL+tWR-1+ tRP) from the WRITEA. Auto-precharge interruption by a command to the
same bank is inhibited.
WRITEA interrupted by WRITE to another bank (BL=4)
CLK
Command
Write
ACT
Write
BL
A0-9,11-12
Ya
tRP
Xa
Yb
tWR
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da0
Da1
auto-precharge
Db0
Db1
Db2
Db3
interrupted
activate
WRITEA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
Write
Read
ACT
BL
A0-9,11-12
Ya
tRP
Xa
Yb
tWR
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da0
Da1
auto-precharge
Qb0
interrupted
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
Qb1
Qb2
Qb3
activate
23
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
[Read with Auto-Precharge Interrupted by Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command
can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same
bank is inhibited.
READA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
Read
Read
ACT
BL
tRP
Ya
Yb
Xa
A10
1
0
Xa
BA0-1
00
10
00
A0-9,11-12
Qa0
DQ
auto-precharge
Qa1
interrupted
Qb0
Qb1
Qb2
Qb3
activate
[Full Page Burst]
Full page burst length is available for only the sequential burst type. Full page burst read or write is
repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read
or write with auto-precharge command is illegal.
[Single Write]
When single write mode is set, burst length for write is always one, independently of Burst Length defined
by (A2-0).
24
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA
(/CS= /RAS= /CAS= L, /WE= /CKE= H) command.
The refresh address is generated internally. 8192
REFA cycles within 64ms refresh 256M bit memory
cells. The auto-refresh is performed on 4 banks
concurrently. Before performing an auto-refresh, all
banks must be in the idle state. Auto-refresh to autorefresh interval is minimum tRFC. Any command must
not be supplied to the device before tRFC from the
REFA command.
Auto-Refresh
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
minimum tRFC
A0-12
BA0-1
Auto Refresh on All Banks
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
Auto Refresh on All Banks
25
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
SELF REFRESH
Self-refresh mode is entered by issuing a REFS
command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once the self-refresh is initiated, it is maintained as
long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and the only enabled input .
All other inputs including CLK are disabled and
ignored, so that power consumption due to synchro­
nous inputs is saved. To exit the self-refresh, supply­
ing stable CLK inputs, asserting DESEL or NOP com­
mand and then asserting CKE=H. After tRFC from the
1st CLK egde following CKE=H, all banks are in the
idle state and a new command can be issued, but
DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK
NOP
/CS
/RAS
/CAS
/WE
CKE
new command
A0-12
X
BA0-1
00
Self Refresh Entry
26
Self Refresh Exit
minimum tRFC
for recovery
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
CLK SUSPEND
CKE controls the internal CLK at the following cycle.
Figure below shows how CKE works. By negating CKE,
the next internal CLK is suspended. The purpose of
CLK suspend is power down, output suspend or input
suspend. CKE is a synchronous input except during
the self-refresh mode. CLK suspend can be performed
either when the banks are active or idle. A command
at the suspended cycle is ignored.
ext.CLK
tIH
tIS
tIH
tIS
CKE
int.CLK
Power Down by CKE
CLK
Standby Power Down
CKE
Command
PRE
NOP NOP NOP
Active Power Down
CKE
Command
ACT
NOP NOP NOP
DQ Suspend by CKE
CLK
CKE
Command
DQ
Read
Write
D0
D1
D2
D3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
Q0
Q1
Q2
Q3
27
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
DQM CONTROL
DQM is a dual function signal defined as the data mask
for writes and the output disable for reads. During writes,
DQM(U,L) masks input data word by word. DQM(U,L)
to write mask latency is 0. During reads, DQM(U,L)
forces output to Hi-Z word by word. DQM(U,L) to output
Hi-Z latency is 2.
DQM Function
CLK
Command
Write
Read
DQMU/L
DQ
D0
D2
D3
masked by DQMU/L=H
28
Q0
Q1
Q3
disabled by DQMU/L=H
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 - 4.6
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 - 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 - 4.6
V
VO
Output Voltage
with respect to VssQ
-0.5 - 4.6
V
IO
Output Current
Pd
Power Dissipation
Topr
Operating Temperature
Tstg
Storage Temperature
Ta = 25˚C
50
mA
1000
mW
0 - 70
˚C
-65 - 150
˚C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 - 70 ˚C ,unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ.
Max.
Unit
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VddQ
Supply Voltage for output
3.0
3.3
3.6
V
VssQ
Supply Voltage for output
0
0
0
V
VIH*1
High-Level Input Voltage all inputs
VddQ +0.3
V
VIL*2
Low-level Input Voltage all inputs
2.0
-0.3
0.8
V
NOTES:
1. VIH (max) = VDDQ + 2.0V for a pulse width of < 3ns.
2. VIL (min) = -2.0V for a pulse width of < 3ns.
3. All voltages referenced to VSS/VSSQ.
CAPACITANCE
(Ta=0 -70˚C,Vdd=VddQ=3.3± 0 . 3 V , V s s = V s s Q = 0 V , u n l e s s o t h e r w i s e n o t e d )
Symbol
Parameter
CI(A)
Input Capacitance, address pin
CI(C)
Input Capacitance, contorl pin
CI(K)
Input Capacitance, CLK pin
CI/O
Input Capacitance, I/O pin
Test Condition
@ 1MHz
1.4V bias
200mV swing
Vcc=3.3V
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
Limits (min.)
Limits (max.)
-6 /-7
-75
Unit
2.5
3.8
5.0
pF
2.5
3.8
5.0
pF
2.5
3.5
4.0
pF
4.0
6.5
6.5
pF
29
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
ITEM
Organization
Symbol
Operating current
Icc1
Precharge Standby
current in Non-Power
down mode
Precharge Standby
current in Power down
mode
Active Standby current
tRC=min, tCLK=min
BL=1,IOL=0mA
Limits (max.)
-6
Unit
-7
-75
-
110
mA
x8
-
x16
130
130
-
mA
Note
1
Icc2N
CKE=VILmax
tCLK=15ns
x8/x16
20
20
20
mA
2,3
Icc2NS
CKE=VIHmin
CLK=VILmax(fixed)
x8/x16
15
15
15
mA
2,4
Icc2P
CKE=VIHmin
tCLK=15ns(Note)
x8/x16
2
2
2
mA
Icc2PS
CKE=VIHmin
tCLK=VILmax(fixed)
x8/x16
2
2
2
mA
Icc3N
CKE=/CS=VIHmin
tCLK=15ns(Note)
x8/x16
30
30
30
mA
3,5
Icc3NS
CKE=VIHmin
tCLK=VILmax(fixed)
x8/x16
20
20
20
mA
4,5
-
-
150
mA
2
x8
Burst current
Icc4
All Bank Active
tCLK = min
BL=4, CL=3, IOL=0mA
Auto-refresh current
Icc5
tRC=min, tCLK=min
Self-refresh current
Icc6
CKE < 0.2V
x8/x16
5
x16
160
160
-
mA
x8/x16
160
160
160
mA
3
3
3
mA
-6,-7,-75
NOTE:
1.address are changed 3 times during tRC , only 1 bank is active & all other banks are idle
2.all banks are idle
3.input signals are changed one time during 3x tCLK
4.input signals are stable
5.all banks are active
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Symbol
Parameter
Limits
Test Conditions
Min.
30
unit
Max.
VOH (DC)
High-Level Output Voltage (DC)
IOH=-2mA
2.4
-
VOL (DC)
Low-level Output Voltage (DC)
IOL= 2mA
-
0.4
V
IOZ
Off-state Output Current
Q floating VO=0 -- VddQ
-10
10
µA
II
Input Current
VIH = 0 -- VddQ +0.3V
-10
10
µA
V
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
AC TIMING REQUIREMENTS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Input Pulse Levels:0.8V-2.0V
Input Timing Measurement Level:1.4V
Limits
Unit
-75
-7
Min. Max. Min. Max. Min. Max.
-6
Parameter
Symbol
tCLK
CLK cycle time
CL=2
-
-
10
ns
CL=3
6
7
7.5
ns
tCH
CLK High pulse width
2
2.5
2.5
ns
tCL
CLK Low pulse width
2
2.5
2.5
ns
tT
Transition time of CLK
1
tIS
Input Setup time
(all inputs)
1.8
1.8
1.8
ns
tIH
Input Hold time
(all inputs)
1
1
1
ns
tRC
Row Cycle time
60
63
67.5
ns
tRFC
tRCD
Refresh Cycle Time
Row to Column Delay
60
70
75
ns
15
20
20
ns
tRAS
Row Active time
42 120K
45
120K 45
tRP
Row Precharge time
15
20
20
ns
tWR
Write Recovery time
12
14
15
ns
tRRD
Act to Act Delay time
12
14
15
ns
tRSC
Mode Register Set Cycle time
12
14
15
ns
tREF
Refresh Interval time
10
7.8
1
10
7.8
CLK
1.4V
DQ
1.4V
1
10
120K
7.8
ns
ns
us
Any AC timing is referenced
to the input signal passing
through 1.4V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
31
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
SWITCHING CHARACTERISTICS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Limits
Symbol
Parameter
-6
Min.
tAC
tOH
Access time from CLK
Output Hold time
from CLK
-75
-7
Max. Min.
Max.
Min.
CL=2
CL=3
5.4
5
CL=2
CL=3
Unit Note
Max.
6
ns
5.4
ns
3
ns
2.5
2.7
3
ns
0
0
ns
tOLZ
Delay time , output lowimpedance from CLK
0
tOHZ
Delay time , output highimpedance from CLK
2.5
5
2.7
5.4
3
5.4
*1
ns
NOTE:
1. If clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter.
Output Load Condition
CLK
VOUT
1.4V
50pF
1.4V
DQ
Output Timing Measurement
Reference Point
CLK
1.4V
tOLZ
DQ
1.4V
tAC
32
tOH
tOHZ
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Burst Write (Single Bank) [BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRP
tRAS
/RAS
tRCD
tRCD
/CAS
tWR
tWR
/WE
CKE
DQM
A0-9,11
X
A10
X
X
A12
X
X
BA0,1
0
DQ
Y
0
D0
ACT#0
X
0
D0
WRITE#0
D0
0
D0
Y
0
D0
PRE#0
ACT#0
0
D0
WRITE#0
D0
D0
PRE#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
33
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Burst Write (Multi Bank) [BL=4]
0
1
2
3
5
4
6
8
7
9
10
11
12
13
14
15
16
CLK
tRC
tRC
/CS
tRAS
tRP
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
tWR
tWR
/WE
CKE
DQM
A0-9,11
X
A10
X
X
X
X
A12
X
X
X
X
BA0,1
0
DQ
Y
X
0
1
D0
D0
Y
D0
ACT#0 WRITE#0
ACT#1
D0
X
1
0
D1
D1
PRE#0
D1
0
0
D1
D0
ACT#0
WRITEA#1
(Auto-Precharge)
Y
X
1
D0
D0
0
D0
WRITE#0
PRE#0
ACT#1
Italic paramater shows minimum case
34
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Burst Read (Single Bank) [CL=2, BL=4]
0
1
2
3
4
5
7
6
9
8
10
11
12
13
14
15
16
CLK
tRC
/CS
tRP
tRAS
tRAS
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
X
A12
X
X
BA0,1
0
Y
X
0
DQ
0
Q0
ACT#0
READ#0
Q0
Q0
PRE#0
Y
0
0
Q0
0
Q0
ACT#0
READ#0
Q0
Q0
Q0
PRE#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
35
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Burst Read (Multi Bank) [CL=2, BL=4]
0
1
2
4
3
5
7
6
9
8
10
11
12
13
14
15
16
CLK
tRC
tRC
/CS
tRRD
tRAS
/RAS
tRCD
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
X
X
X
A12
X
X
X
X
BA0,1
0
Y
X
0
Y
1
DQ
X
1
Q0
Q0
Q0
0
Q0
ACT#0 READA#0
ACT#1
Y
0
Q1
Q1
ACT#0
READA#1
X
Q1
1
Q1
Q0
READ#0
0
Q0
Q0
Q0
PRE#0
ACT#1
Italic paramater shows minimum case
36
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Write Interrupted by Write [BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
X
A10
X
X
X
A12
X
X
X
BA0,1
0
DQ
Y
X
0
1
D0
D0
ACT#0 WRITE#0
ACT#1
Y
Y
0
D0
D0
Y
1
D0
D1
X
0
D1
D1
WRITE#0 WRITEA#1
interrupt
interrupt
same bank other bank
D0
0
D0
WRITE#0
interrupt
other bank
D0
1
D0
PRE#0
ACT#1
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
37
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Read Interrupted by Read [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
X
X
A12
X
X
X
BA0,1
0
Y
0
X
Y
1
DQ
1
Q0
ACT#0 READ#0
ACT#1
Y
Q0
Y
1
Q0
Q1
X
0
Q1
Q1
READ#1 READA#1
interrupt
interrupt
other bank same bank
Q1
1
Q1
READ#0
interrupt
other bank
Q0
Q0
Q0
Q0
ACT#1
Italic paramater shows minimum case
38
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4]
0
1
2
4
3
5
6
7
9
8
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
X
X
A10
X
X
A12
X
X
BA0,1
0
1
DQ
Y
Y
Y
0
1
1
D0
ACT#0
D0
WRITE#0
Q1
READ#1
Q1
D1
1
D1
WRITE#1
D1
D1
PRE#1
ACT#1
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
39
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Write / Read Terminated by Precharge [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRP
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
X
A10
X
X
X
A12
X
X
X
BA0,1
0
DQ
Y
0
D0
ACT#0
X
0
0
Y
0
D0
WRITE#0
X
0
Q0
PRE#0 ACT#0
Terminate
READ#0
0
Q0
PRE#0
Terminate
ACT#0
Italic paramater shows minimum case
40
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Write / Read Terminated by Burst Terminate [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
Y
Y
Y
0
0
0
D0
ACT#0
D0
WRITE#0 TBST
Q0
Q0
READ#0 TBST
D0
0
D0
WRITE#0
D0
D0
PRE#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
41
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Single Write Burst Read [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
Y
Y
0
0
D0
ACT#0 WRITE#0
Q0
Q0
Q0
Q0
READ#0
Italic paramater shows minimum case
42
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Power-Up Sequence and Intialize
CLK
200µs
/CS
tRP
tRFC
tRFC
tRSC
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
MA
X
A10
0
X
A12
0
X
BA0,1
0
0
DQ
NOP
Power On
PRE ALL
REFA
REFA
REFA
MRS
ACT#0
Minimum 8 REFA cycles
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
43
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Auto Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
Y
0
D0
PRE ALL
REFA
ACT#0
D0
D0
D0
WRITE#0
All banks must be idle before REFA is issued.
Italic paramater shows minimum case
44
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Self Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
PRE ALL Self Refresh Entry
Self Refresh Exit
ACT#0
All banks must be idle before REFS is issued.
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
45
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
CLK Suspension [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
Y
Y
0
0
D0
D0
D0
ACT#0 WRITE#0 internal CLK
suspended
D0
Q0
READ#0
Q0
Q0
Q0
internal CLK
suspended
Italic paramater shows minimum case
46
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
Power Down
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
PRE ALL
ACT#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
47
IS42S83200A
IS42S16160A
ISSI
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency
Speed (ns)
Order Part No.
Package
166 MHz
6
IS42S16160A-6T
54-pin TSOP-II
143 MHz
7
IS42S16160A-7T
54-pin TSOP-II
133 MHz
7.5
IS42S83200A-75T
54-pin TSOP-II
Commercial Range: 0°C to +70°C, Lead-free
Frequency
48
Speed (ns)
Order Part No.
Package
166 MHz
6
IS42S16160A-6TL
54-pin TSOP-II
143 MHz
7
IS42S16160A-7TL
54-pin TSOP-II
133 MHz
7.5
IS42S83200A-75TL
54-pin TSOP-II
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
ISSI
®
PACKAGING INFORMATION
Plastic TSOP 54–Pin, 86-Pin
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
E
E1
measured from the bottom of the
package.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
N/2
1
D
SEATING PLANE
A
ZD
b
e
Plastic TSOP (T - Type II)
Millimeters
Inches
Min
Max
Min
Max
Symbol
Ref. Std.
No. Leads (N)
A
A1
A2
b
C
D
E1
E
e
L
L1
ZD
α
—
1.20
0.05 0.15
—
—
0.30 0.45
0.12 0.21
22.02 22.42
10.03 10.29
11.56 11.96
0.80 BSC
0.40 0.60
—
—
0.71 REF
0°
8°
54
—
0.047
0.002 0.006
—
—
0.012 0.018
0.005 0.0083
0.867 0.8827
0.395 0.405
0.455 0.471
0.031 BSC
0.016 0.024
—
—
0°
8°
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/28/02
L
α
A1
C
Plastic TSOP (T - Type II)
Millimeters
Inches
Symbol Min Max
Min
Max
Ref. Std.
No. Leads (N)
86
A
A1
A2
b
C
D
E1
E
e
L
L1
ZD
α
—
1.20
0.05 0.15
0.95 1.05
0.17 0.27
0.12 0.21
22.02 22.42
10.16 BSC
11.56 11.96
0.50 BSC
0.40 0.60
0.80 REF
0.61 REF
0°
8°
—
0.047
0.002 0.006
0.037 0.041
0.007 0.011
0.005 0.008
0.867 0.8827
0.400 BSC
0.455 0.471
0.020 BSC
0.016 0.024
0.031 REF
0.024 BSC
0°
8°
1