ON LE2464RDXA 64 kb i2c cmos serial eeprom Datasheet

LE2464RDXA
64 kb I2C CMOS Serial EEPROM
Overview
The LE2464RDXA is two-wire serial interface EEPROM (Electrically
Erasable and Programmable ROM). This device realizes high speed and a high
level reliability by high performance CMOS EEPROM technology. This
device is compatible with I2C memory protocol, therefore it is best suited for
application that requires re-writable nonvolatile parameter memory.
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Function
 Capacity : 64k bits (8k  8 bits)
 Single supply voltage : 1.7 V to 3.6 V
 Operating temperature : 40ºC to +85ºC
 Interface : Two wire serial interface (I2C Bus*)
WLCSP6, 0.80x1.20
 Operating clock frequency : 400 kHz (Fast), 1000 kHz (Fast-Plus)
 Low Power consumption

: Standby : 2 µA (max.)
: Active (Read, 400 kHz) : 0.5 mA (max.)
Active (Read, 1000 kHz) : 2.0 mA (max.)
 Automatic page write mode : 32 Bytes
 Read mode : Sequential Read and random read
 Slave Address : Slave address in 7 bit format is 054 (S2 = 1, S1 = 0, S0 = 0)
 Erase/Write cycles : 106 cycles (Page Write)
 Data Retention : 20 years
 Pull-up resistance: 5 kΩ (typ.) on WP pin with a built-in pull-up resister
 High reliability : Adopts proprietary symmetric memory array configuration (USP6947325)
Hardware write protect feature
Noise filters connected to SCL and SDA pins
Incorporates a feature to prohibit write operations under low voltage conditions.
 Package : LE2464RDXA WLP6(0.801.20) 0.33mm height
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Symbol
Conditions
Supply voltage
DC input voltage
Over-shoot voltage
Storage temperature
Tstg
Ratings
Unit
0.5 to +4.6
V
0.5 to VDD+0.5
V
1.0 to VDD+1.0
V
65 to +150
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
August 2016 - Rev. 1
1
Publication Order Number :
LE2464RDXA/D
LE2464RDXA
Recommended Operating Conditions
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Operating supply voltage
1.7
3.6
V
Operating temperature
40
+85
C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
DC Electrical Characteristics
Spec.
Parameter
Symbol
Conditions
Unit
min
typ
max
f = 400 kHz, VDD=VDD Max
0.5
f = 1000 kHz, VDD=VDD Max
2.0
Supply current at reading
ICC1
Supply current at writing
ICC2
Standby current
ISB
Input leakage current
ILI
VIN=VSS to VDD, VDD=VDD Max
Output leakage current
ILO
VIN=VSS to VDD, VDD=VDD Max
Input Low voltage
VIL
Input High voltage
VIH
f = 1000 kHz / 400 kHz,
mA
3.0
mA
2
µA
2.0
+2.0
µA
2.0
+2.0
µA
VDD  0.3
V
tWC=5ms, VDD=VDD Max
WP=VDD2=VDD
VIN=VDD or VSS
VDD  0.7
VOL2
Output Low voltage
VOL1
V
IOL = 1.0 mA, VDD = 1.7 V
IOL = 1.2 mA, VDD = 2.0 V
IOL = 2.1 mA, VDD = 2.0 V
IOL = 3.0 mA, VDD = 2.5 V
0.2
V
0.4
V
Capacitance at Ta=25C, f=1MHz
Parameter
Symbol
Conditions
max
Unit
In/Output pin capacitance
CI/O
VI/O = 0 V (SDA)
10
pF
Input pin capacitance
CI
VIN = 0 V
10
pF
Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices.
Pull-up resistance (WP) at Ta = 40 to 85 C
Parameter
Pull up resistance
Symbol
R
Conditions
Resistance between WP to VDD2
min
4000
typ
max
Unit
5500
7000

Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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2
LE2464RDXA
Fast-Plus (1000 kHz)
Spec.
Parameter
Symbol
Unit
min
typ
max
Slave mode SCL clock frequency
fSCLS
0
SCL clock low time
tLOW
500
1000
ns
SCL clock high time
tHIGH
300
ns
SDA output delay time
tAA
50
450
kHz
ns
SDA data output hold time
tDH
50
ns
Start condition setup time
tSU.STA
250
ns
Start condition hold time
tHD.STA
250
ns
Data in setup time
tSU.DAT
50
ns
Data in hold time
tHD.DAT
0
ns
Stop condition setup time
tSU.STO
250
ns
SCL SDA rise time
tR
120
ns
SCL SDA fall time
tF
120
ns
Bus release time
tBUF
Noise suppression time
tSP
50
ns
Write time
tWC
5
ms
500
ns
Fast (400 kHz)
Spec.
Parameter
Symbol
Unit
min
typ
Slave mode SCL clock frequency
fSCLS
0
SCL clock low time
tLOW
1200
SCL clock high time
tHIGH
600
SDA output delay time
tAA
100
SDA data output hold time
tDH
100
max
400
kHz
ns
ns
900
ns
ns
Start condition setup time
tSU.STA
600
ns
Start condition hold time
tHD.STA
600
ns
Data in setup time
tSU.DAT
100
ns
Data in hold time
tHD.DAT
0
ns
Stop condition setup time
tSU.STO
600
ns
SCL SDA rise time
tR
300
SCL SDA fall time
tF
Bus release time
tBUF
Noise suppression time
tSP
50
ns
Write time
tWC
5
ms
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3
300
ns
1200
ns
ns
LE2464RDXA
Standard (100 kHz)
Spec.
Parameter
Symbol
Unit
min
typ
max
Slave mode SCL clock frequency
fSCLS
0
SCL clock low time
tLOW
4700
ns
SCL clock high time
tHIGH
4000
ns
SDA output delay time
tAA
100
100
3500
kHz
ns
SDA data output hold time
tDH
100
ns
Start condition setup time
tSU.STA
4700
ns
Start condition hold time
tHD.STA
4000
ns
Data in setup time
tSU.DAT
250
ns
Data in hold time
tHD.DAT
0
ns
Stop condition setup time
tSU.STO
4000
ns
SCL SDA rise time
tR
1000
SCL SDA fall time
tF
300
Bus release time
tBUF
Noise suppression time
tSP
50
ns
Write time
tWC
5
ms
AC measurement condition
Input pulse level
0.2  VDD to 0.8  VDD
Input pulse rise / fall time
20 ns
Output timing reference level
0.5  VDD
Output load
100 pF
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4
4700
ns
ns
ns
LE2464RDXA
Package Dimensions
unit : mm
WLCSP6, 0.80x1.20
CASE 567HM
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A B
E
PIN A1
REFERENCE
D
0.05 C
2X
0.05 C
2X
DIM
A
A1
b
D
E
e
TOP VIEW
A
0.05 C
A1
RECOMMENDED
SOLDERING FOOTPRINT*
0.08 C
NOTE 3
6X
C
SIDE VIEW
SEATING
PLANE
0.40
PITCH
A1
PACKAGE
OUTLINE
e
b
0.05 C A B
0.03 C
MILLIMETERS
MIN
MAX
0.33
0.03
0.13
0.15
0.25
0.80 BSC
1.20 BSC
0.40 BSC
6X
e
0.20
B
0.40
PITCH
A
1
2
DIMENSIONS: MILLIMETERS
3
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
LE2464RDXA
Pin Assignment
Top View
Ball side View
2
VDD2
VSS
SDA
SDA
VSS
VDD2
2
1
VDD
WP
SCL
SCL
WP
VDD
1
A
B
C
C
B
A
Pin Descriptions
PIN.A1
VDD
PIN.A2
VDD2
Power supply
Power supply for WP pin Pull-up
PIN.B1
WP
Write protect
PIN.B2
VSS
Ground
PIN.C1
SCL
Serial clock input
PIN.C2
SDA
Serial data input/output
Block Diagram
VDD2
Write controller
igh voltage generator
X decoder
SCL
Serial controller
WP
EEPROM Array
Y decoder & Sense
SDA
Serial-Parallel converter
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LE2464RDXA
Bus timing
tHIGH
tF
tLOW
tR
tSP
SCL
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tSP
SDA/IN
tAA
tBUF
tDH
SDA/OUT
Write timing
tWC
SCL
D0
SDA
Write Data
Acknowledge
Stop
condition
Start
condition
Pin Function
SCL (Serial clock)
The SCL signal is used to control serial input data timing. The SCL is used to latch input data synchronously
at the rising edge and read output data synchronously at the falling edge.
SDA (Serial input / output data)
The SDA pin is bidirectional for serial data transfer. It is an open-drain structure that needs to be pulled up by
resistor.
WP (Write protect)
When the WP input is high, write protection is enabled. When WP input is either low or floating, write
protection is disabled. The read operation is always activated irrespective of the WP pin status.
VDD2 (Power supply for WP pin pull-up)
VDD2 pin is for the pull-up power supply to WP pin. Voltage impression of 0.5 V to VDD +0.5 V is permitted
like other pins about the pin voltage.
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LE2464RDXA
Functional Description
The device supports the I2C protocol. Any device that sends data on to the bus is defined to be a transmitter,
and any device that reads the data to a receiver. The device that controls the data transfer is known as the
bus master, and the other as the slave device.
1) Start Condition
A Start condition needs to start the EEPROM operation, it is to set falling edge of the SDA while the SCL
is stable in the high status.
2) Stop Condition
A Start condition is identified by rising edge of the SDA signal while the SCL is stable in the high status.
The device becomes the standby mode from a Read operation by a Stop condition. In a write sequence,
a stop condition is trigger to terminate the write data inputs and it is trigger to start the internal write cycle.
After the internally write cycle time which is specified as tWC, the device enters a standby mode.
tSU.STA
tSU.STO
tHD.STA
SCL
SDA
Stop
condition
Start
condition
3) Data Input
During data input, the device latches the SDA on the rising edge of the SCL. For correct the operation,
The SDA must be stable during the rising edge of the SCL.
tSU.DAT
tHD.DAT
SCL
SDA
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8
LE2464RDXA
4) Acknowledge Bit (ACK)
The Acknowledge Bit is used to indicate a successful byte data transfer. The receiver sends a zero to
acknowledge that it has received each word (Device Code, Slave Address etc) from the transmitter.
SCL
(From Transmitter)
8
1
9
SDA
(From Transmitter)
SDA
(EEPROM output)
Acknowledge
Bit output
Start
condition
tAA
tDH
5) Device addressing
To transmit between the bus master and slave device (EEPROM), the master must send a Start condition
to the EEPROM. The device address word of the EEPROM consists of 4-bit Device Code, 3-bit Slave
Device address code and 1-bit read/write code. By sending these, it becomes possible to communicate
between the bus master and the EEPROM.
The upper 4-bit of the device address word are called the Device Code, the Device Code of the EEPROM
uses 1010b fixed code. This device has the 3-bit of the Slave Device address as the Slave address (S0,
S1, S2). The value of Slave address are fixed S0 = 0, S1 = 0, and S2 = 1.
When the Device Code is received on the SDA, the device only responds if Slave address pin tied to VDD
or VSS is the same as the Slave address signal input. The 8th bit is the read/write bit. The bit is set to 1 for
Read operation and 0 for Write operation. If a match occurs on the Device Code, the corresponding
device gives an acknowledgement on SDA during the 9th bit time. If device does not match the Device
Code, it deselects itself from the bus, and goes into the Standby mode. Use the Random Read command
when you execute reading after the slave device was switched.
Memory
Address
Device Code
1
0
1
0
S2
S1
S0
R/W
LSB
MSB
Device address word
S2 = 1, S1 = 0, S0 = 0
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LE2464RDXA
6) EEPROM Write Operation
6)-1. Byte Write
The write operation requires a 7-bit device address word with the 8th bit = 0 (write). Then the EEPROM
sends acknowledgement 0 at the 9th clock cycle. After these, the EEPROM receives word address (A15
to A8), and the EEPROM outputs acknowledgement 0. And then, the EEPROM receives word address
(A7 to A0), and the EEPROM outputs acknowledgement 0. Then the EEPROM receives 8-bit write data,
the EEPROM outputs acknowledgement 0 after receipt of write data. If the EEPROM receives a stop
condition, the EEPROM enters an internally timed (tWC) write cycle and terminates receipt of inputs until
completion of the write cycle.
A A A A A A
A9 A8
15 14 13 12 11 10
1 0 1 0
ACK
R/W
Data
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
ACK
ACK
Stop
SDA
Start
Word Address
ACK
A15 to A13: Don’t Care
Access from master device
6)-2. Page Write
The Page write allows up to 32 bytes to be written in a single write cycle. The page write is the same
sequence as the byte write except for inputting the more write data. The page write is initiated by a start
condition, device code, device address, memory address(n) and write data(n) with every 9th bit
acknowledgement. The device enters the page write operation if this device receives more write
data(n+1) instead of receiving a stop condition. The page address (A0 to A4) bits are automatically
incremented on receiving write data(n+1). The device can continue to receive write data up to 32 bytes. If
the page address bits reaches the last address of the page, the page address bits will roll over to the first
address of the same page and previous write data will be overwritten. After these, if the device receives a
stop condition, the device enters an internally timed (tWC×(n+x)) write cycle and terminates receipt of
inputs until completion of the write cycle.
1 0 1 0 S2 S1 S0 W
Data(n)
A A A A A A
A9 A8
15 14 13 12 11 10
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
ACK
ACK
ACK
ACK
R/W
Data(n+x)
Data(n+1)
·····
D7 D6 ~ D1 D0
ACK
ACK
D7 D6 ~ D1 D0
ACK
D7 D6 ~ D1 D0
D7 D6 ~ D1 D0
ACK
Stop
SDA
Start
Word Address(n)
ACK
A15 to A13: Don’t Care
Access from master device
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LE2464RDXA
6)-3. Acknowledge Polling
The Acknowledge Polling operation is used to show if the EEPROM is in an internally timed write cycle or
not. This operation is initiated by the stop condition after inputting write data. This requires the 8-bit
device address word with the 8th bit = 0 (write) following the start condition during an internally timed write
cycle. If the EEPROM is busy with the internal write cycle, no acknowledge will be returned. If the
EEPROM has terminated the internal write cycle, it responds with an acknowledge. The terminated write
cycle of the EEPROM can be known by this operation.
1 0 1 0 S2 S1 S0 W
During Write
1 0 1 0 S2 S1 S0 W
NO ACK
NO ACK
R/W
No Write
Start
Start
SDA
Start
During Write
R/W
1 0 1 0 S2 S1 S0 W
······
ACK
R/W
Access from master device
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LE2464RDXA
7) EEPROM Read Operation
7)-1. Current Address Read
The device has an internal address counter. It maintains that last address during the last read or write
operation, with incremented by one. The current address read accesses the address kept by the internal
address counter. After receiving a start condition and the device address word with the 8th bit = 1 (Read),
the EEPROM outputs the 8-bit current address data from following acknowledgement 0. If the EEPROM
receives acknowledgement 1 and a following stop condition, the EEPROM stops the read operation and
is returned to a standby mode. In case the EEPROM has accessed the last address of the last page at
previous read operation, the current address will roll over and returns to zero address. In case EEPROM
has accessed the last address of the last page at previous write operation, the current address roll over
within page addressing and returns to the first address in the same page.
The current address is valid while power is on. After power on, the current address will be reset (all 0).
Note: After the page write operation, the current address is the specified memory address in the last page
write, if the write data is more than 32-bytes.
Start
SDA
1 0 1
0 S2 S1 S0 R
D7 D6 D5 D4 D3 D2 D1 D0
Stop
Data (n+1)
Device Address
NO ACK
ACK
R/W
Access from master device
7)-2. Random Read
The random read requires a dummy write to set read address. The EEPROM receives a start condition
and the device address word with the 8th bit = 0 (write), the memory address. The EEPROM outputs
acknowledgement 0 after receiving memory address then enters a current address read with receiving a
start condition. The EEPROM outputs the read data of the address which was defined in the dummy write
operation. After receiving no acknowledgement and a following stop condition, the EEPROM stops the
random read operation and returns to a standby mode.
Word Address(n)
A A A A A A A9 A8
15 14 13 12 11 10
A7 A6 A5 A4 A3 A2 A1 A0
ACK
ACK
ACK
R/W
Dummy Write
Device Address
Data(n)
1 0 1 0 S2 S1 S0 R
ACK
D7 D6 ~ D1 D0
ACK
Stop
1 0 1 0 S2 S1 S0 W
Start
SDA
Start
Device Address
NO ACK
R/W
Current Read
A15 to A13: Don’t Care
Access from master device
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LE2464RDXA
7)-3. Sequential Read
The sequential read operation is initiated by either a current address read or random read. If the
EEPROM receives acknowledgement 0 after 8-bit read data, the read address is incremented and the
next 8-bit read data outputs. The current address will roll over and returns address zero if it reaches the
last address of the last page. The sequential read can be continued after roll over. The sequential read is
terminated if the EEPROM receives no acknowledgement and a following stop condition.
1 0 1
0
Data(n)
R
D7 D6 ~ D1 D0
ACK
Data(n+1)
Data(n+2)
D7 D6 ~ D1 D0
D7 D6 ~ D1 D0
ACK
ACK
ACK
R/W
Data(n+x)
D7 D6 ~ D1 D0
ACK
Stop
SDA
Start
Device Address
NO ACK
Access from master device
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LE2464RDXA
Application Notes
1) Software reset function
Software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is
executed in order to avoid erroneous operation after power-on and to reset while the command input
sequence. During the dummy clock input period, the SDA bus must be opened (set to high by a pull-up
resistor). Since it is possible for the ACK output and read data to be output from the EEPROM during
the dummy clock period, forcibly entering H will result in an overcurrent flow.
Note that this software reset function does not work during the internal write cycle.
Dummy clock x 9
1
SCL
8
2
9
SDA
Start
Condition
Start
Condition
2) Pull-up resistor of SDA pin
Due to the demands of the I2C bus protocol function, the SDA pin must be connected to a pull-up resistor
(with a resistance from several k to several tens of k) without fail. The appropriate value must be
selected for this resistance (RPU) on the basis of the VIL and IIL of the microcontroller and other devices
controlling this product as well as the VOL – IOL characteristics of the product. Generally, when the
resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the
operating current consumption will increase.
RPU maximum value
The maximum resistance must be set in such a
way that the bus potential, which is determined
by the sum total (IL) of the input leaks of the
devices connected to the SDA bus and by RPU,
can completely satisfy the input high level (VIH
min) of the microcontroller and EEPROM.
However, a resistance value that satisfies SDA
rise time tR and fall time tF must be set.
RPU
EEPROM
Master
Device
IL
SDA
CBUS
IL
RPU maximum value = (VDD  VIH) / IL
Example: When VDD = 3.0 V and IL = 2 A
RPU maximum value = (3.0 V  3.0 V  0.8) / 2 A = 300 k
RPU minimum value
A resistance corresponding to the low-level output voltage (VOL max) of EEPROM must be set.
RPU minimum value = (VDD  VOL) / IOL
Example: When VDD = 3.0 V, VOL = 0.4 V and IOL = 1 mA
RPU minimum value = (3.0 V  0.4) / 1 mA = 2.6 k
Recommended RPU setting
RPU is set to strike a good balance between the operating frequency requirements and power
consumption. If it is assumed that the SDA load capacitance is 50 pF and the SDA output data strobe
time is 500 ns, RPU will be about RPU = 500 ns/50 pF = 10 k.
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LE2464RDXA
3) Precautions when turning on the power
This product contains a power-on reset circuit for preventing the inadvertent writing of data when the
power is turned on. The following conditions must be met in order to ensure stable operation of this
circuit. No data guarantees are given in the event of an instantaneous power failure during the internal
write operation.
symbol
tRISE
tOFF
Vbot
Parameter
Spec.
Typ.
–
–
–
Min.
–
10
–
Power rise time
Power off time
Power bottom voltage
Max.
100
–
0.2
Unit
ms
ms
V
tRISE
VDD
tOFF
Vbot
0V
Notes:
1) The SDA pin must be set to high and the SCL pin to low or high.
2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state.
A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during
power rise
After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins
set to high.
VDD
VDD
tLOW
SCL
SCL
SDA
SDA
tSU.DAT
tDH
tSU.DAT
B. If it is not possible to satisfy the instruction 2 in Note above
After the power has stabilized, software reset must be executed.
C. If it is not possible to satisfy the instructions both 1 and 2 in Note above
After the power has stabilized, the steps in A must be executed, then software reset must be executed.
4) Noise filter for the SCL and SDA pins
This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 100 ns or
less are not recognized because of this function.
5) Function to inhibit writing when supply voltage is low
This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the
guaranteed operating supply voltage range. The data is protected by ensuring that write operations are
not started at voltages (typ.) of 1.3 V and below.
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LE2464RDXA
6) Notes on write protect operation
This product prohibits all memory array writing when the WP pin is high. To ensure full write protection,
the WP is set high for all periods from the start condition to the stop condition, and the conditions below
must be satisfied.
symbol
tSU.WP
tHD.WP
WP
Parameter
Min.
600
600
WP Setup time
WP Hold time
Spec.
Typ.
–
–
Max.
–
–
tHD.WP
tSU.WP
SCL
SDA
Stop Condition
Start Condition
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16
Unit
ns
ns
LE2464RDXA
MARKING INFORMATION
LE2464RDXA WLP6(0.80x1.20)
Part ID : 64R
Lot Number : 3digits
64R
Lot
ORDERING INFORMATION
Device
LE2464RDXATDG
Package
Shipping (Qty / Packing)
WLCSP6, 0.80x1.20
(Pb-Free / Halogen Free)
5000 / Tape & Reel
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
* I2C Bus is a trademark of Philips Corporation.
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