PHILIPS GTL16612DGG 18-bit gtl/gtl to lvttl/ttl bidirectional universal translator (3-state) Datasheet

INTEGRATED CIRCUITS
GTL16612
18-bit GTL/GTL+ to LVTTL/TTL
bidirectional universal translator (3-State)
Product data
Supersedes data of 2000 Jun 19
Philips
Semiconductors
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
FEATURES
GTL16612
DESCRIPTION
• 18-bit bidirectional bus interface
• Translates between GTL/GTL+ logic levels (B ports) and
The GTL16612 is a high-performance BiCMOS product designed for
VCC operation at 3.3 V with I/O compatibility up to 5 V.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).
LVTTL/TTL logic levels (A ports)
• 5 V I/O tolerant on the LVTTL/TTL side (A ports)
• No bus current loading when LVTTL/TTL output is tied to 5 V bus
• 3-State buffers
• Output capability: +64 mA/-32 mA on the LVTTL/TTL side
(A ports); +40 mA on the GTL/GTL+ side (B ports)
• TTL input levels on control pins
• Power-up reset
• Power-up 3-State
• Positive edge triggered clock inputs
• Latch-up protection exceeds 500 mA per JESD78
• ESD protection exceeds 2000 V HBM per JESD22-A114,
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA.
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
QUICK REFERENCE DATA
SYMBOL
TYPICAL
CONDITIONS
Tamb = 25 °C
PARAMETER
UNIT
3.3 V
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50 pF
CIN
Input capacitance (Control pins)
VI = 0 V or VCC
CI/O
I/O pin capacitance
Outputs disabled; VI/O = 0 V or VCC
8
pF
ICCZ
Total supply current
Outputs disabled
12
mA
1.9
ns
4
pF
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DWG NUMBER
56-Pin Plastic SSOP
-40 to +85 °C
GTL16612DL
SOT371-1
56-Pin Plastic TSSOP
-40 to +85 °C
GTL16612DGG
SOT364-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2002 Dec 13
2
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
PIN CONFIGURATION
PIN DESCRIPTION
OEAB
1
56
CEAB
LEAB
2
55
CPAB
A0
3
54
B0
GND
4
53
GND
A1
5
52
B1
A2
6
51
B2
VCC
7
50
NC
A3
8
49
B3
A4
9
48
B4
B5
A5
10
47
GND
11
46
GND
A6
12
45
B6
A7
13
44
B7
A8
14
43
B8
A9
15
42
B9
A10
16
41
B10
A11
17
40
B11
GND
18
39
GND
A12
19
38
B12
A13
20
37
B13
A14
21
36
B14
VCC
22
35
VREF
A15
23
34
B15
B16
A16
24
33
GND
25
32
GND
A17
26
31
B17
OEBA
27
30
CPBA
LEBA
28
29
CEBA
SW00485
2002 Dec 13
GTL16612
3
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1, 27
OEAB/OEBA
A-to-B/ B-to-A Output enable
input (active Low)
29, 56
CEBA/CEAB
B-to-A/A-to-B clock enable
2, 28
LEAB/LEBA
A-to-B/B-to-A Latch enable input
55,30
CPAB/CPBA
A-to-B/B-to-A Clock input
(active rising edge)
3, 5, 6, 8, 9, 10,
12, 13, 14, 15,
16, 17, 19, 20,
21, 23, 24, 26
A0-A17
Data inputs/outputs (A side)
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
38, 37, 36, 34,
33, 31
B0-B17
Data inputs/outputs (B side)
4, 11, 18, 25,
32, 39, 46, 53
GND
Ground (0 V)
7, 22
VCC
Positive supply voltage
35
VREF
GTL reference voltage
50
NC
No connection
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
LOGIC SYMBOL (Positive Logic)
OEAB
CEAB
CPAB
LEAB
LEBA
CPBA
CEBA
OEBA
1
56
55
2
28
30
29
27
CE
A0
3
1D
54
B0
C1
CLK
CE
1D
C1
CLK
To 17 other channels
SW00254
FUNCTION TABLE
INPUTS
CEAB1
OEAB1
LEAB1
CPAB1
A
OUTPUT
B
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X
BO2
H
L
L
X
X
BO2
L
L
L
↑
L
L
L
L
L
↑
H
H
L
L
L
H
X
BO2
L
L
L
L
X
BO3
X = Don’t care
H = High voltage level
L = Low voltage level
↑ = Low to High
Z = High impedance “off” state
1. A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CPBA, and CEBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established, provided that CPAB was Low before LEAB went Low.
2002 Dec 13
4
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
ABSOLUTE MAXIMUM RATINGS 1, 2
SYMBOL
VCC
PARAMETER
CONDITIONS
RATING
UNIT
-0.5 to +4.6
V
VI < 0
-50
mA
A port
-0.5 to +7.0
B port
-0.5 to +4.6
VO < 0; A port
-50
mA
Output in Off or High state; A port
-0.5 to +7.0
V
Output in Off or High state; B port
-0.5 to +4.6
V
A port
128
mA
B port
80
mA
A port
-64
mA
-65 to +150
°C
DC supply voltage
IIK
DC input diode current
VI
DC input voltage3
IOK
DC output diode current
VO
DC output voltage3
IOL
Current into any output in the LOW state
IOH
Current into any output in the HIGH state
Tstg
Storage temperature range
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
3.3 V RANGE LIMITS
SYMBOL
PARAMETER
VCC
DC supply voltage
VTT
Termination voltage
VREF
Input voltage
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
IOH
HIGH-level output current
IOL
LOW-level output current
2002 Dec 13
UNIT
MIN
MAX
3.0
3.6
GTL
1.14
1.26
GTL+
1.35
1.65
GTL
0.74
0.87
GTL+
0.9
1.10
B port
0
VTT
Except B port
0
5.5
B port
VREF+50 mV
Except B port
2.0
GTL reference voltage
VI
Tamb
TEST CONDITIONS
V
V
V
V
V
B port
VREF-50 mV
Except A port
0.8
A port
-32
B port
40
A port
64
V
mA
mA
Operating free-air temperature range
-40
5
+85
°C
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
DC ELECTRICAL CHARACTERISTICS (3.3 V "0.3 V RANGE)
LIMITS
SYMBOL
PARAMETER
Temp = -40 to +85 °C
TEST CONDITIONS
MIN
VIK
Input clamp voltage
VOH
High-level output voltage
VCC = 3.0 V; IIK = -18 mA
VCC = 3.0 to 3.6 V; IOH = -100 µA
A port
VCC = 3.0 V; IOH = -32 mA
VCC
2.0
2.3
0.25
0.4
VCC = 3.0 V; IOL = 32 mA
0.3
0.5
VCC = 3.0 V; IOL = 64 mA
0.4
0.55
0.4
0.5
VCC = 3.6 V; VI = 5.5 V
I/O Data pins4
A port
VCC = 3.6 V; VI = 0
IOFF
Output off current
VCC = 0 V; VI or VO = 0 to 4.5 V
20
0.5
10
0.1
-5
0.1
130
VCC = 3 V; VI = 2.0 V
-75
-140
Current into an output in the
High state when VO > VCC
VO = 5.5 V; VCC = 3.0 V
Power up/down 3-State
output current3
VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC
OE = Don’t care
A port
V
µ
µA
µA
µ
±5
µA
±100
µA
µ
µA
10
125
µA
1.0
±100
µA
Outputs high
5.0
9.0
Outputs low
10.5
18.5
6.0
11.5
Outputs high
9.7
17.5
Outputs low
7.0
12.0
VCC = 3 V to 3.6 V; One input at VCC-0.6 V,
Other inputs at VCC or GND
0.04
0.2
A-Port
ICCL
ICCZ5
VCC = 3.6 V
Disabled
VI = GND or VCC, IO = 0
mA
B-Port
ICCL
∆ICC
0.1
75
IEX
ICCH
10
VCC = 3 V; VI = 0.8 V
Bus Hold current, A outputs
ICCH
±1
0.1
B port
IHOLD
IPU/PD
0.1
Control pins
VCC = 0 or 3.6 V; VI = 5.5 V
VCC = 3.6 V; VI = VTT or GND
V
V
B port
VCC = 3.6 V; VI = VCC
UNIT
V
A port
VCC = 3.6 V; VI = VCC or GND
Input leakage current
-1.2
0.2
VCC = 3.0 V; IOL = 40 mA
II
-0.85
0.07
VCC = 3.0 V; IOL = 16 mA
Low-level output voltage
MAX
VCC-0.2
VCC = 3.0 V; IOL = 100 µA
VOL
TYP1
Additional supply current per
input pin2
mA
NOTES:
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. This is the increase in supply current for each LVTTL input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 msec. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V
a transition time of 100 µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground.
2002 Dec 13
6
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
AC CHARACTERISTICS (A PORT)
GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 Ω; Tamb = -40 to +85 °C.
GTL16612 An Port
SYMBOL
PARAMETER
GTL
GTL+
VCC = 3.3 V ±0.3 V
VCC = 3.3 V ±0.3 V
VREF = 0.8 V
VREF = 1.0 V
UNIT
WAVEFORM
MIN
TYP1
MAX
MIN
TYP1
MAX
tPLH
Bn to An
2
1.6
3.0
5.0
1.6
3.0
5.0
ns
tPHL
Bn to An
2
3.0
4.9
6.3
3.0
4.9
6.3
ns
tPLH
LEBA to An
3
1.6
2.7
4.2
1.6
2.7
4.2
ns
tPHL
LEBA to An
3
1.6
2.8
4.3
1.6
2.8
4.3
ns
tPLH
CPBA to An
1
1.9
3.4
4.7
1.9
3.4
4.7
ns
tPHL
CPBA to An
1
1.8
3.8
5.2
1.8
3.8
5.2
ns
tPZH
OEBA to An
5
1.5
2.6
4.2
1.5
2.6
4.2
ns
tPHZ
OEBA to An
5
1.4
2.9
4.8
1.4
2.9
4.8
ns
tPZL
OEBA to An
6
1.3
2.4
3.8
1.3
2.4
3.8
ns
tPLZ
OEBA to An
6
1.2
2.2
3.5
1.2
2.2
3.5
ns
NOTE:
1. Typical values are at VCC = 3.3 V, Tamb = +25 °C.
AC CHARACTERISTICS (B PORT)
GND = 0 V; tr = tf = 2.5 ns; CL = 30 pF; RL = 25 Ω; Tamb = -40 to +85 °C.
GTL16612 Bn Port
SYMBOL
PARAMETER
GTL
GTL+
VCC = 3.3 V ±0.3 V
VCC = 3.3 V ±0.3 V
VREF = 0.8 V
VREF = 1.0 V
UNIT
WAVEFORM
MIN
TYP1
MAX
MIN
TYP1
MAX
tPLH
An to Bn
2
1.4
2.4
3.7
1.3
2.4
3.7
ns
tPHL
An to Bn
2
1.3
2.5
4.0
1.4
2.6
4.2
ns
tPLH
LEAB to Bn
3
1.7
3.0
4.4
1.8
3.0
4.6
ns
tPHL
LEAB to Bn
3
2.1
3.5
5.4
2.3
3.6
5.5
ns
tPLH
CPAB to Bn
1
1.8
3.1
4.5
1.9
3.1
4.8
ns
tPHL
CPAB to Bn
1
2.3
3.6
5.4
2.4
3.8
5.8
ns
tPLH
OEAB to Bn
7
1.1
2.1
3.3
1.4
2.0
3.5
ns
tPHL
OEAB to Bn
7
1.6
2.8
4.4
1.0
2.9
4.5
ns
NOTE:
1. Typical values are at VCC = 3.3 V, Tamb = +25 °C.
2002 Dec 13
7
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
AC SETUP REQUIREMENTS (3.3 V ±0.3 V RANGE)
A Port: GND = 0 V; Input tr = tf = 2.5 ns; CL = 50 pF; RL = 500 Ω; Tamb = -40 to +85 °C; VREF = 0.8 V or 1.0 V.
B Port: GND = 0 V; Input tr = tf = 2.5 ns; CL = 30 pF; RL = 25 Ω; VREF = 0.8 V or 1.0 V.
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3 V ±0.3 V
MIN
ts(H)
UNIT
MAX
Setup time, High or Low
Bn to CPBA
4
1.5
ns
4
1.5
ns
Setup time, High or Low
An to CPAB
4
2.0
ns
4
3.0
ns
Hold time, High or Low
Bn to CPBA, or An to CPAB
4
1.0
ns
4
1.0
ns
Setup time, High or Low
Bn to LEBA, or An to LEAB
4
1.0
ns
4
1.0
ns
Hold time, High or Low
Bn to LEBA, or An to LEAB
4
1.5
ns
4
1.5
ns
Setup time, High or Low
CEAB to CPAB, or CEBA to CPBA
4
1.0
ns
4
1.0
ns
Hold time, High or Low
CEAB to CPAB, or CEBA to CPBA
4
1.5
ns
4
1.0
ns
2.0
ns
tw(L)
Pulse width, High or Low
CPBA or CPAB
4
4
2.0
ns
tw(H)
Pulse width, High
LEBA or LEAB
3
1.5
ns
ts(L)
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
tw(H)
2002 Dec 13
8
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
AC WAVEFORMS
VM = 1.5 V at VCC w 3.0 V. VM = 1.5 V for A ports and control pins; VM = 0.8 V for B ports in GTL mode; VM = 1.0 V for B ports in GTL+ mode.
VX = VOL + 0.3 V at VCC w 3.0 V.
VY = VOH - 0.3 V at VCC w 3.0 V.
1/fMAX
CPBA or
CPAB
VM
3.0 V or VCC,
whichever is
less
VM
tPZH
tW(H)
tPHL
tPLH
VM
VM
0V
tW(L)
3.0 V or VCC,
whichever is
less
OEBA
tPHZ
VOH
VOH
An or Bn
VY
VM
An or Bn
VM
VM
VOL
SW00223
SW00181
Waveform 1. Propagation delay, clock input to output, clock
pulse width, and maximum clock frequency
VM
An or Bn
Waveform 5. 3-State output enable time to high level
and output disable time from high level
3.0V or VCC,
whichever is
less
VM
3.0 V or VCC,
whichever is
less
OEBA
VM
VM
0V
tPLH
tPHL
tPZL
tPLZ
VOH
An or Bn
VM
An or Bn
VM
VX
VM
VOL
VOL
SW00224
SW00176
Waveform 2. Propagation delay, transparent mode
VM
LEAB or
LEBA
3.0V or VCC,
whichever is
less
VM
VM
Waveform 6. 3-State output enable time to low level
and output disable time from low level
3.0 V or VCC,
whichever is
less
OEAB
VM
VM
0V
tW(H)
tPLH
tPLH
tPHL
tPHL
VOH
Bn
An or Bn
VM
VM
SW00495
SW00177
Propagation delay, enable to output,
and enable pulse width
ÉÉÉ
ÉÉÉÉ
ÉÉÉ ÉÉÉÉ
An or Bn
CEAB or CEBA
VM
VM
VM
tS(H)
th(H)
CPAB or CPBA,
LEAB or LEBA
VM
tS(L)
Waveform 7.
ÉÉÉ
ÉÉÉ
3.0 V or VCC,
whichever is
less
VM
0V
th(L)
VM
3.0 V or VCC,
whichever is
less
0V
SW00222
Waveform 4. Data setup and hold times
2002 Dec 13
VM
VOL
VOL
Waveform 3.
VM
9
Output enable time on open collector output
with pullup
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
TEST CIRCUIT
6.0 V or VCC x 2
VCC
Open
PULSE
GENERATOR
VOUT
VIN
RL =
500 Ω
GND
tW
90%
NEGATIVE
PULSE
VM
RT
VM
10%
D.U.T.
VIN
90%
10%
0V
CL
tTHL (tF)
RL =
500 Ω
tTLH (tR)
tTLH (tR)
90%
Test Circuit for A Outputs
POSITIVE
PULSE
tTHL (tF)
VIN
90%
VM
VM
10%
1.2 V
10%
tW
0V
25 Ω
FROM OUTPUT
UNDER TEST
TEST POINT
CL = 30 pF
(INCLUDES PROBE AND JIG CAPACITANCE)
Load Circuit for B Outputs
SWITCH POSITION
TEST
SWITCH
tPLZ/tPZL
6V
tPLH/tPHL
Open
tPHZ/tPZH
GND
DEFINITIONS
INPUT PULSE REQUIREMENTS
RL = Load resistor; see AC CHARACTERISTICS for value.
FAMILY
CL = Load capacitance includes jig and probe capacitance:
See AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
74GTL16
Amplitude
Rep. Rate
tW
tR
tF
3.0 V or VCC
whichever
is less
v10 MHz 500 ns v2.5 ns v2.5 ns
SW00255
2002 Dec 13
10
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
2002 Dec 13
11
GTL16612
SOT364-1
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
REVISION HISTORY
Rev
Date
GTL16612
Description
_4
20021213
Product data (9397 750 10862); ECN 853-2166 29245 of 03 December 2002
Modifications:
• New package release.
_3
20000619
Product data (9397 750 07217); ECN 853-2166 23903 of 19 June 2000.
2002 Dec 13
12
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
Data sheet status
Level
Data sheet status[1]
Product
status[2] [3]
Definitions
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
 Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 12-02
For sales offices addresses send e-mail to:
[email protected].
Document order number:
Philips
Semiconductors
2002 Dec 13
13
9397 750 10862