1CY74FCT163952 Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT163952 CY74FCT163H952 16-Bit Registered Transceivers SCCS048A - March 1997 - Revised November 2000 Features Functional Description • Low power, pin-compatible replacement for LCX and LPT families • 5V tolerant inputs and outputs • 24 mA balanced drive outputs • Power-off disable outputs permit live insertion • Edge-rate control circuitry for reduced noise • FCT-C speed at 4.4 ns • Latch-up performance exceeds JEDEC standard no. 17 • Typical output skew < 250 ps • Industrial temperature range of –40˚C to +85˚C • TSSOP (19.6-mil pitch) or SSOP (25-mil pitch) • Typical Volp (ground bounce) performance exceeds Mil Std 883D • VCC = 2.7V to 3.6V • ESD (HBM) > 2000V CY74FCT163H952 • Bus hold on data inputs • Eliminates the need for external pull-up or pull-down resistors • Devices with bus hold are not recommended for translating rail-to-rail CMOS signals to 3.3V logic levels These 16-bit registered transceivers are high-speed, low-power devices. 16-bit operation is achieved by connecting the control lines of the two 8-bit registered transceivers together. For data flow from bus A-to-B, CEAB must be LOW to allow data to be stored when CLKAB transitions from LOW-to-HIGH. The stored data will be present on the output when OEAB is LOW. Control of data from B-to-A is similar and is controlled by using the CEBA, CLKBA, and OEBA inputs. The outputs are 24-mA balanced output drivers with current limiting resistors to reduce the need for external terminating resistors and provide for minimal undershoot and reduced ground bounce. The CY74FCT163H952 has “bus hold” on the data inputs, which retains the input’s last state whenever the source driving the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs. The CY74FCT163952 is designed with inputs and outputs capable of being driven by 5.0V buses, allowing its use in mixed voltage systems as a translator. The outputs are also designed with a power off disable feature enabling its use in applications requiring live insertion. Pin Configuration Logic Block Diagrams; CY74FCT163952, CY74FCT163H952 SSOP/TSSOP Top View 1 OEAB 2 CEBA 1 CEBA 1 CLKBA 2 CLKBA 1 OEAB 2 OEAB 1 CEAB 2 CEAB 1 CLKAB 1A1 C CE D 1B1 2A1 1 OEBA 3 4 54 53 1 CEBA 5 52 1B1 1A2 VCC 6 51 1B2 7 50 VCC 1A3 8 9 49 48 1B3 47 46 45 1B5 GND 1A6 10 11 12 1A7 13 44 1B7 1A8 14 43 1B8 2A1 15 42 2B1 2A2 16 17 41 40 2B2 GND 2A4 18 39 GND 19 38 2B4 2A5 20 21 37 36 2B5 2A6 VCC 22 35 VCC 2A7 23 34 2B7 2A8 24 25 33 32 2B8 GND 2 CEAB 26 31 2 CEBA 2 CLKAB 27 30 2 CLKBA 2 OEAB 28 29 2 OEBA GND 1A1 2 OEBA C CE D 56 55 1 CEAB 2 CLKAB 1 OEBA 1 2 1 CLKAB 1A4 C CE D 1A5 2B1 C CE D 2A3 TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS Copyright 1 CLKBA GND 1B4 GND 1B6 2B3 2B6 GND © 2000, Texas Instruments Incorporated CY74FCT163952 CY74FCT163H952 Maximum Ratings[5, 6] Pin Description Name Description OEAB A-to-B Output Enable Input (Active LOW) (Above which the useful life may be impaired. For user guidelines, not tested.) OEBA B-to-A Output Enable Input (Active LOW) Storage Temperature ..................................–55°C to +125°C CEAB A-to-B Clock Enable Input (Active LOW) CEBA B-to-A Clock Enable Input (Active LOW) Ambient Temperature with Power Applied .............................................–55°C to +125°C CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input A A-to-B Data Inputs or B-to-A Three-State Outputs[1] B B-to-A Data Inputs or A-to-B Three-State Outputs[1] Supply Voltage Range......................................0.5V to +4.6V DC Input Voltage ............................................–0.5V to +7.0V DC Output Voltage .........................................–0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin) ........................ –60 to +120 mA Power Dissipation.......................................................... 1.0W Function Table[2, 3] For A-to-B (Symmetric with B-to-A) Operating Range Inputs Outputs CEAB CLKAB OEAB A B H X L X B[4] X L L X B[4] L L L L H H H X Z L L X X Range Industrial Ambient Temperature VCC –40°C to +85°C 2.7V to 3.6V Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Description Test Conditions All Inputs Min. Typ.[7] 2.0 Max. Unit 5.5 V 0.8 V VIH Input HIGH Voltage VIL Input LOW Voltage VH Input Hysteresis[8] VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –1.2 V IIH Input HIGH Current VCC=Max., VI=5.5 ±1 µA IIL Input LOW Current VCC=Max., VI=GND ±1 µA IOZH High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=5.5V ±1 µA IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND ±1 µA IOS Short Circuit Current[9] VCC=Max., VOUT=GND –240 mA IOFF Power-Off Disable VCC=0V, VOUT≤4.5V ±100 µA ICC Quiescent Power Supply Current VIN≤0.2V, VIN>VCC–0.2V VCC=Max. 0.1 10 µA ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VIN=VCC–0.6V[10] VCC=Max. 2.0 30 µA 100 –0.7 –60 –135 mV Notes: 1. On the CY74FCT163H952, these pins have bus hold. 2. A-to-B data flow is shown: B-to-A data flow is similar but uses, CEBA, CLKBA, and OEBA. 3. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. = LOW-to-HIGH Transition. Z = HIGH Impedance. 4. Level of B before the indicated steady-state input conditions were established. 5. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature. 6. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground, 7. Typical values are at VCC=3.3V, TA = +25˚C ambient. 8. This parameter is specified but not tested. 9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 10. Per TTL driven input; all other inputs at VCC or GND. 2 CY74FCT163952 CY74FCT163H952 Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Description VIH Input HIGH Voltage VIL Input LOW Voltage Test Conditions Min. All Inputs Typ.[7] Max. 2.0 [8] VH Input Hysteresis VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA IIH Input HIGH Current VCC=Max., VI=VCC IIL Input LOW Current VCC V 0.8 V 100 [11] IBBH IBBL Bus Hold Sustain Current on Bus Hold Input VCC=Min. IBHHO IBHLO Bus Hold Overdrive Current on Bus Hold Input[11] VCC=Max., VI=1.5V IOZH High Impedance Output Current (Three-State Output pins) IOZL Unit mV –0.7 – 1.2 V ±100 µA ±100 µA VI=2.0V –50 µA VI=0.8V +50 µA ±500 µA VCC=Max., VOUT=VCC ±1 µA High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND ±1 µA IOS Short Circuit Current[9] VCC=Max., VOUT=GND –240 mA IOFF Power-Off Disable VCC=0V, VOUT≤4.5V ±100 µA ICC Quiescent Power Supply Current VIN≤0.2V VCC VIN>VCC–0.2V VCC=Max. +40 µA ∆ICC Quiescent Power supply Current (TTL inputs HIGH) VIN=VCC–0.6V[10] VCC=Max. +350 µA –60 –135 Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Description Test Conditions Min. Typ.[7] Max. Unit IODL Output LOW Dynamic Current[9] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V 50 90 200 mA IODH Output HIGH Dynamic Current[9] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V –36 –60 –110 mA VOH Output HIGH Voltage VCC=Min., IOH= –0.1 mA VOL Output LOW Voltage VCC–0.2 V VCC=Min., IOH= –8 mA 2.4[12] 3.0 V VCC=3.0V, IOH= –24 mA 2.0 3.0 V VCC=Min., IOL= 0.1mA 0.2 VCC=Min., IOL= 24 mA 0.3 V 0.55 Notes: 11. Pins with bus hold are described in Pin Description. 12. VOH=VCC–0.6 V at rated current Capacitance[8](TA = +25˚C, f = 1.0 MHz) Parameter Description Test Conditions Typ.[7] Max. Unit CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF 3 CY74FCT163952 CY74FCT163H952 Power Supply Characteristics Parameter Description Test Conditions Typ.[7] Max. Unit ICCD Dynamic Power Supply Current[13] VCC=Max., One Input Toggling, VIN=VCC or 50% Duty Cycle, VIN=GND Outputs Open, OE=GND 50 75 µA/MHz IC Total Power Supply Current[14] VCC=Max., f1=10 MHz, 50% VIN=VCC or Duty Cycle, Outputs Open, One VIN=GND Bit Toggling, OE=GND VIN=VCC–0.6V or VIN=GND 0.5 0.8 mA 0.5 0.8 mA VCC=Max., f1=2.5 MHz, 50% VIN=VCC or Duty Cycle, Outputs Open, Six- VIN=GND teen Bits Toggling, OE=GND VIN=VCC–0.6V or VIN=GND 2.0 3.0[15] mA 2.0 3.3[15] mA Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[16,17] CY74FCT163952A Parameter Description CY74FCT163952C CY74FCT163H952C Min. Max. Min. Max. Unit Fig. No.[18] tPLH tPHL Propagation Delay Data to Output 1.5 4.8 1.5 4.4 ns 1, 3 tPZH tPZL Output Enable Time 1.5 6.2 1.5 5.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time 1.5 5.6 1.5 5.2 ns 1, 7, 8 tSU Set-Up Time, HIGH or LOW A, B to CLKAB, CLKBA 2.5 — 2.5 — ns 4 tH Hold Time, HIGH or LOW A, B to CLKAB, CLKBA 2.0 — 1.5 — ns 4 tSU Set-Up Time, HIGH or LOW CEAB, CEBA to CLKAB, CLKBA 3.0 — 3.0 — ns 4 tH Hold Time, HIGH or LOW CEAB, CEBA to CLKAB, CLKBA 2.0 — 2.0 — ns 4 tW Pulse Width, HIGH or LOW CLKAB or CLKBA[19] 3.0 — 3.0 — ns 5 tSK(O) Output Skew[19] 0.5 ns — 0.5 Notes: 13. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 14. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 15. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 16. Minimum limits are specified but not tested on Propagation Delays. 17. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%. 18. See “Parameter Measurement Information” in the General Information section. 19. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design. 4 CY74FCT163952 CY74FCT163H952 Ordering Information CY74FCT163952 Speed (ns) 4.1 4.8 Ordering Code Package Name Package Type CY74FCT163952CPACT Z48 48-Lead (240-Mil) TSSOP CY74FCT163952CPVC/PVCT O48 48-Lead (300-Mil) SSOP CY74FCT163952APVC/PVCT O48 48-Lead (300-Mil) SSOP Operating Range Industrial Industrial Ordering Information CY74FCT163H952 Speed (ns) 4.1 Ordering Code Package Name Package Type 74FCT163H952CPACT Z48 48-Lead (240-Mil) TSSOP CY74FCT163H952CPVC O48 48-Lead (300-Mil) SSOP 74FCT163H952CPVCT O48 48-Lead (300-Mil) SSOP Package Diagrams 56-Lead Shrunk Small Outline Package O56 5 Operating Range Industrial CY74FCT163952 CY74FCT163H952 Package Diagrams 56-Lead Thin Shrunk Small Outline Package Z56 6 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74FCT163H952CPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI 74FCT163H952CPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) CY74FCT163952CPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI CY74FCT163952CPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI CY74FCT163952CPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI CY74FCT163952CPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI CY74FCT163H952CPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI CY74FCT163H952CPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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