ISSI ® IS63LV1024 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT SEPTEMBER 2000 FEATURES DESCRIPTION • High-speed access times: 8, 10, 12 and 15 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 3.3V power supply • Packages available: – 32-pin 300-mil SOJ – 32-pin 400-mil SOJ – 32-pin TSOP (Type II) The ISSI IS63LV1024 is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM in revolutionary pinout. The IS63LV1024 is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) with CMOS input levels. The IS63LV1024 operates from a single 3.3V power supply and all inputs are TTL-compatible. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K X 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE OE CONTROL CIRCUIT WE ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. H 10/02/00 1 ISSI IS63LV1024 PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOJ 32-Pin TSOP (Type II) (T) A0 1 32 A16 A1 2 31 A15 A2 3 30 A14 A3 4 29 A13 CE 5 28 OE I/O0 6 27 I/O7 I/O1 7 26 I/O6 Vcc 8 25 GND GND 9 24 Vcc I/O2 10 23 I/O5 I/O3 11 22 I/O4 WE 12 21 A12 A4 13 20 A11 A5 14 19 A10 A6 15 18 A9 A7 16 17 A8 PIN DESCRIPTIONS A0 A1 A2 A3 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A4 A5 A6 A7 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ® A16 A15 A14 A13 OE I/o7 I/O6 GND Vcc I/O5 I/O4 A12 A11 A10 A9 A8 TRUTH TABLE WE A0-A16 Address Inputs Mode CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Bidirectional Ports Not Selected X (Power-down) Output Disabled H Read H Write L Vcc Power GND Ground CE OE H X High-Z ISB1, ISB2 L L L H L X High-Z DOUT DIN ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 I/O Operation Vcc Current ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation Value –0.5 to Vcc + 0.5 –55 to +125 –65 to +150 1.0 Unit V °C °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. H 10/02/00 ISSI IS63LV1024 ® OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 0.3V 3.3V ± 0.15V DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VCC Com. Ind. –1 –5 1 5 µA ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. –1 –5 1 5 µA Notes: 1. VIL = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 ns Min. Max. -10 ns Min. Max. -12 ns Min. Max. -15 ns Min. Max. Symbol Parameter Test Conditions Unit ICC1 Vcc Operating Supply Current VCC = Max., CE = VIL IOUT = 0 mA, f = Max. Com. Ind. — — 160 170 — — 150 160 — — 130 140 — — 120 130 mA ISB TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE ≥ VIH, f = Max Com. Ind. — — 55 55 — — 45 45 — — 40 40 — — 35 35 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. — — 25 30 — — 25 30 — — 25 30 — — 25 30 mA ISB2 CMOS Standby Current VCC = Max., CE ≤ VCC – 0.2V, Com. Ind. — — 5 10 — — 5 10 — — 5 10 — — 5 10 mA (CMOS Inputs) VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. H 10/02/00 3 ISSI IS63LV1024 ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -8 ns Min. Max. Parameter -10 ns Min. Max. -12 ns Min. Max. -15 ns Min. Max. Unit tRC Read Cycle Time 8 — 10 — 12 — 15 — ns tAA Address Access Time — 8 — 10 — 12 — 15 ns tOHA Output Hold Time 2 — 2 — 3 — 3 — ns tACE CE Access Time — 8 — 10 — 12 — 15 ns tDOE OE Access Time — 4 — 5 — 6 — 7 ns tLZOE(2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns (2) tHZOE OE to High-Z Output 0 4 0 5 0 6 0 7 ns (2) tLZCE CE to Low-Z Output 3 — 3 — 3 — 3 — ns tHZCE(2) CE to High-Z Output 0 4 0 5 0 6 0 7 ns tPU CE to Power Up Time 0 — 0 — 0 — 0 — ns tPD CE to Power Down Time — 8 — 10 — 12 — 15 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1 output loading specified in Figure 1. 2. Tested with the C2 load in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1a and 1b AC TEST LOADS 317 Ω ZOUT = 50 Ω 3.3V OUTPUT OUTPUT 50 Ω 5 pF Including jig and scope VT = 1.5V Figure 1 4 351 Ω Figure 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. H 10/02/00 ISSI IS63LV1024 ® AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t ACE t HZCE t LZCE DOUT HIGH-Z DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. H 10/02/00 5 ISSI IS63LV1024 ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol -8 ns Min. Max. Parameter -10 ns Min. Max. -12 ns Min. Max. -15 ns Min. Max. Unit tWC Write Cycle Time 8 — 10 — 12 — 15 — ns tSCE CE to Write End 7 — 7 — 8 — 10 — ns tAW Address Setup Time to Write End 8 — 8 — 8 — 10 — ns tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — 0 — ns t WE Pulse Width (OE High) 7 — 7 — 8 — 10 — ns t WE Pulse Width (OE Low) 8 — 10 — 12 — 15 — ns tSD Data Setup to Write End 5 — 5 — 6 — 7 — ns PWE1(1) PWE2(2) tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns (2) tHZWE WE LOW to High-Z Output — 4 — 5 — 6 — 7 ns (2) tLZWE WE HIGH to Low-Z Output 3 — 3 — 3 — 3 — ns Notes: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. AC WAVEFORMS WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. H 10/02/00 ISSI IS63LV1024 ® WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CE_WR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA DOUT t HZWE DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE • VIH. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. H 10/02/00 7 ISSI IS63LV1024 ORDERING INFORMATION Commercial Range: 0°C to +70°C Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package Speed (ns) Order Part No. Package 8 IS63LV1024-8T IS63LV1024-8J IS63LV1024-8K TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ 8 IS63LV1024-8TI IS63LV1024-8JI IS63LV1024-8KI TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ 10 IS63LV1024-10T IS63LV1024-10J IS63LV1024-10K TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ 10 IS63LV1024-10TI IS63LV1024-10JI IS63LV1024-10KI TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ 12 IS63LV1024-12T IS63LV1024-12J IS63LV1024-12K TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ 12 IS63LV1024-12TI IS63LV1024-12JI IS63LV1024-12KI TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ 15 IS63LV1024-15T IS63LV1024-15J IS63LV1024-15K TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ 15 IS63LV1024-15TI IS63LV1024-15JI IS63LV1024-15KI TSOP (Type II) 300-mil Plastic SOJ 400-mil Plastic SOJ ISSI ® ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 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