LS3N165 P-CHANNEL MOSFET The LS3N165 is a monolithic dual enhancement mode P-Channel Mosfet FEATURES DIRECT REPLACEMENT FOR INTERSIL LS3N165 ABSOLUTE MAXIMUM RATINGS1@ 25°C (unless otherwise noted) Maximum Temperatures The hermetically sealed TO-78 package is well suited Storage Temperature ‐65°C to +200°C for high reliability and harsh environment applications. Operating Junction Temperature ‐55°C to +150°C Lead Temperature (Soldering, 10 sec.) +300°C (See Packaging Information). Maximum Power Dissipation Continuous Power Dissipation (one side) 300mW LS3N165 Features: Total Derating above 25°C 4.2 mW/°C MAXIMUM CURRENT Very high Input Impedance Drain Current 50mA Low Capacitance MAXIMUM VOLTAGES High Gain High Gate Breakdown Voltage Drain to Gate or Drain to Source2 ‐40V Low Threshold Voltage Peak Gate to Source3 ±125V Gate‐Gate Voltage ±80V LS3N165 ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL CHARACTERISTIC MIN TYP. MAX UNITS CONDITIONS IGSSR Gate Reverse Leakage Current ‐‐ ‐‐ 10 VGS = ‐0V IGSSF Gate Forward Current ‐‐ ‐‐ ‐10 VGS = ‐40V pA TA= +125°C ‐‐ ‐‐ ‐25 IDSS Drain to Source Leakage Current ‐‐ ‐‐ ‐200 VDS = ‐20V ISDS Source to Drain Leakage Current ‐‐ ‐‐ ‐400 VSD = ‐20V VDB = 0 ID(on) Drain Current “On” ‐5.0 ‐‐ ‐30 mA VDS = ‐15V, VGS = ‐10V VGS(th) Gate to Source Threshold Voltage ‐2.0 ‐‐ ‐5.0 V VDS = ‐15V, ID = ‐10µA ‐2.0 ‐‐ ‐5.0 VDS = VGS , ID = ‐10µA rDS(on) Drain to Source “On” Resistance ‐‐ ‐‐ 300 Ω VGS = ‐20V, ID = ‐100µA gfs Forward Transconductance 1500 ‐‐ 3000 µS VDS = ‐15V, ID = ‐10mA , f = 1kHz The LS3N165 is a dual enhancement mode P-Channel Mosfet and is ideal for space constrained applications and those requiring tight electrical matching. gos Ciss Crss Coss RE(Yfs) Click To Buy Output Admittance ‐‐ ‐‐ 300 Input Capacitance ‐‐ ‐‐ 3 Reverse Transfer Capacitance ‐‐ ‐‐ 0.7 Output Capacitance ‐‐ ‐‐ 3.0 Common Source Forward 1200 ‐‐ ‐‐ Transconductance MATCHING CHARACTERISTICS LS3N165 SYMBOL LIMITS CHARACTERISTIC MIN MAX Yfs1/Yfs2 Forward Transconductance Ratio 0.90 1.0 VGS1‐2 Gate Source Threshold Voltage ‐‐ 100 Differential ∆VGS1‐2/∆T Gate Source Threshold Voltage ‐‐ 100 Differential Change with Temperature pF VDS = ‐15V, ID = ‐10mA , f = 1MHz4 µS VDS = ‐15V, ID = ‐10mA , f = 100MHz4 UNITS ns mV CONDITIONS VDS = ‐15V, ID = ‐500µA , f = MHz4 VDS = ‐15V, ID = ‐500µA µV/°C VDS = ‐15V, ID = ‐500µA TA = ‐55°C to = +25°C SWITCHING CIRCUIT Note 1 ‐ Absolute maximum ratingsTEST are limiting values above which LS3N165 serviceability may be impaired. * Note 2 – Per Transistor Note 3 – Device must not be tested at ±125V more than once or longer than 300ms. d i f l 00% d Available Packages: Device Schematic SWITCHING WAVEFORM & TEST CIRCUIT TO-78 (Bottom View) LS3N165 in TO-72 LS3N165 in bare die. Please contact Micross for full package and die dimensions Tel: +44 1603 788967 Email: [email protected] Web: http://www.micross.com/distribution *To avoid possible damage to the device while wiring, testing, or in actual operation, follow these procedures: To avoid the build‐up of static charge, the leads of the devices should remain shorted together with a metal ring except when being tested or used. Avoid unnecessary handling. Pick up devices by the case instead of the leads. Do not insert or remove devices from circuits with the power on, as transient voltages may cause permanant damage to the devices. Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.