Fairchild GTLP8T306 8-bit lvttl/gtlp bus transceiver Datasheet

Revised April 2000
GTLP8T306
8-Bit LVTTL/GTLP Bus Transceiver
General Description
Features
The GTLP8T306 is an 8-bit bus transceiver that provides
LVTTL to GTLP signal level translation. The device provides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTLP
logic levels. High speed backplane operation is a direct
result of GTLP’s reduced output swing (<1V), reduced input
threshold levels and output edge rate control. The edge
rate control minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
■ Bidirectional interface between GTL/GTLP and LVTTL
logic levels
Fairchild’s GTLP has internal output edge-rate control and
is process, voltage, and temperature (PVT) compensated.
Its function is similar to BTL and GTL but with different output levels and receiver thresholds. The GTLP output LOW
level is typically less than 0.5V, the output HIGH level is
1.5V and the receiver threshold is 1.0V.
■ Output Edge Rate Control to minimize noise on the
GTLP port
■ Power up/down/off high impedance for live insertion
■ Standard 245 function
■ CMOS technology for low power dissipation
■ 5V tolerant inputs and outputs on the A-Port
■ Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs
■ LVTTL compatible driver and control inputs
■ Flow through pinout optimizes PCB layout
■ Open drain on GTLP to support wired-or connection
■ A-Port source/sink −24 mA/+24 mA
■ B-Port sink 50 mA
■ Recommended Operating Temperature −40°C to +85°C
Ordering Code:
Order Number
Package Number
Package Description
GTLP8T306MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2000 Fairchild Semiconductor Corporation
Connection Diagram
DS500051
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GTLP8T306 8-Bit LVTTL/GTLP Bus Transceiver
September 1997
GTLP8T306
Pin Descriptions
Pin Names
Truth Table
Description
Inputs
Output
OE
Output Enable (Active LOW)
OE
T/R
T/R
Transmit/Receive Input
H
X
A0–A7
Side A Inputs or 3-STATE Outputs
L
L
Bus B Data to Bus A
B0–B7
Side B Inputs or 3-STATE Outputs
L
H
Bus A Data to Bus B
VREF
GTLP Reference Voltage
HIGH Z on Bus A and Bus B
Functional Description
The GTLP8T306 is an 8-bit transceiver providing the standard 245 functionality that supports both GTL and GTLP signal
levels.
Data polarity is non-inverting and the data flow direction is controlled by the T/R pin. The outputs are enabled to allow data
through the device when OE is LOW otherwise both the A and B ports are placed in a HIGH impedance state.
Logic Diagram
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2
Supply Voltage (VCC)
−0.5V to 7.0V
DC Input Voltage (VI)
−0.5V to +7.0V
Recommended Operating
Conditions (Note 3)
Outputs 3-STATE
Outputs Active (Note 2)
DC Output Sink Current into A-Port
IOL
Bus Termination Voltage (VTT)
−0.5V to +7.0V
−0.5V to 7.0V
48 mA
−48 mA
+50 mA
ESD Rating
Storage Temperature (TSTG)
+24 mA
A-Port
+50 mA
B-Port
−40°C to +85°C
Operating Temperature (TA)
DC Output Diode Current (IOK)
−50 mA
−24 mA
A-Port
−50 mA
VO > VCC
0V to 5.5V
LOW Level Output Current (IOL)
100 mA
VO < 0V
1.14V to 1.26V
and control pins
DC Input Diode Current (IIK)
VI < 0V
1.35V to 1.65V
GTL
HIGH Level Output Current (IOH)
DC Output Sink Current into B-Port
in the LOW State, IOL
GTLP
Input Voltage (VI) on A-Port
DC Output Source Current from
A-Port IOH
3.15V to 3.45V
Supply Voltage VCC
DC Output Voltage (VO)
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
>2000V
−65°C to +150°C
Note 2: IO Absolute Maximum Rating must be observed.
Note 3: Unused inputs must be held high or low.
3
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GTLP8T306
Absolute Maximum Ratings(Note 1)
GTLP8T306
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted).
Symbol
VIH
VIL
Test Conditions
Min
B-Port
VREF +0.05
Others
2.0
B-Port
0.0
Typ
(Note 4)
VTT
GTLP
1.0
GTL
0.8
VIK
VOH
VOL
A-Port
A-Port
B-Port
II
VCC = 3.15V
II = −18 mA
VCC = Min to Max
(Note 5)
IOH = −100 µA
VCC −0.2
VCC = 3.15V
IOH = −12 mA
2.4
IOH = −24 mA
2.0
V
VCC = 3.15V
IOL = 24 mA
0.5
VCC = 3.15V
IOL = 40 mA
0.4
IOL = 50 mA
0.55
V
VCC = 3.45V
VI = 5.5V
20
VI = 0V
−20
Control Pins
VCC = 3.45V
VI = 5.5V
5
VI = 0V
−5
VI = VTT
5
VI = 0
−5
100
VI or VO = 0 to 4.5V
II (Hold)
A-Port
VCC = 3.15V
VI = 0.8V
75
VI = 2.0V
−20
A-Port
VCC = 3.45V
B-Port
V
µA
µA
µA
µA
µA
VO = 3.45V
20
VO = 1.5V
5
A-Port
VCC = 3.45V
VO = 0
−20
B-Port
VCC = 3.45V
VO = 0.55
−5
A or B Ports
VCC = 3.45V
Outputs HIGH
7
18
Outputs LOW
8
20
VI = V CC or GND
Outputs Disabled
8
20
One Input at VCC–0.6V
0
1
IO = 0
ICC
A-Port and
VCC = 3.45V
(Note 6)
Control Pins
A or Control Inputs at
VCC or GND
CIN
Control Pins
VI = VCC or 0
5
A-Port
VI = VCC or 0
7
B-Port
VI = VCC or 0
9
µA
µA
mA
mA
Note 4: All typical values are VCC = 3.3V and T A= 25°C.
Note 5: For conditions shown as Min, use the appropriate value specified under recommended operating conditions.
Note 6: This is the increase in supply current for each input that is at the specified LVTTL voltage level rather than VCC or GND.
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V
V
0.2
VCC = 0
ICC
V
IOL = 100 µA
A-Port
IOZL
V
−1.2
IOFF
IOZH
V
0.8
VCC = Min to Max
(Note 5)
VCC = 3.45V
V
VREF −0.05
A-Port
B-Port
Units
V
Others
VREF
Max
4
pF
Over recommended range of supply voltage and operating free air-temperature, VREF = 1.0V (unless otherwise noted).
CL = 30 pF for B-Port and CL = 50 pF for A-Port.
Symbol
tPLH
From (Input)
To (Output)
Min
Typ
(Note 7)
Max
An
Bn
1.0
4.0
7.5
1.0
5.1
7.5
1.0
5.8
8.3
1.0
4.9
8.3
ns
tPHL
tPLH
Units
Bn
An
ns
tPHL
tRISE
Transition Time, B Outputs (20% to 80%)
2.6
ns
tFALL
Transition Time, B Outputs (20% to 80%)
2.6
ns
tRISE
Transition Time, A Outputs (10% to 90%)
2.5
ns
tFALL
Transition Time, A Outputs (10% to 90%)
tPZH, tPZL
2.5
OE
An
4.5
9.5
1.0
4.9
9.5
1.0
5.4
9.5
1.0
6.0
9.5
ns
tPHZ, tPLZ
tPLH
ns
1.0
OE
Bn
ns
tPHL
Note 7: All typical values are at VCC = 3.3V and TA = 25°C.
5
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GTLP8T306
AC Electrical Characteristics
GTLP8T306
Test Circuit and Timing Waveforms
Test Circuit for A Outputs
Test Circuit for B Outputs
Voltage Waveforms Enable and Disable Times
A-Port
Voltage Waveforms Pulse Duration
(VM = VCC/2 for A-Port and 1.0 for B-Port)
Voltage Waveforms Propagation Delay and Setup and Hold Times
(VM = VCC/2 for A-Port and 1.0 for B-Port)
Note A: CL includes probes and Jig capacitance.
Note B: For B-Port, CL = 30 pF is used for worst case.
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GTLP8T306 8-Bit LVTTL/GTLP Bus Transceiver
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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