EL5128 ® Data Sheet May 4, 2007 Dual VCOM Amplifier & Gamma Reference Buffer The EL5128 integrates two VCOM amplifiers with a single gamma reference buffer. Operating on supplies ranging from 5V to 15V, while consuming only 2.0mA, the EL5128 has a bandwidth of 12MHz (-3dB) and provides common mode input ability beyond the supply rails, as well as rail-to-rail output capability. This enables the amplifier to offer maximum dynamic range at any supply voltage. The EL5128 also features fast slewing and settling times, as well as a high output drive capability of 30mA (sink and source). The EL5128 is targeted at TFT-LCD applications, including notebook panels, monitors, and LCD-TVs. It is available in the 10 Ld MSOP package and is specified for operation over the -40°C to +85°C temperature range. Pinout VINA- 2 - + + - VINA+ 3 VS+ 4 • Dual VCOM amplifier • Single gamma reference buffer • 12MHz -3dB bandwidth • Supply voltage = 4.5V to 16.5V • Low supply current = 2.0mA • High slew rate = 10V/µs • Unity-gain stable • Beyond the rails input capability • Rail-to-rail output swing • Ultra-small package • Pb-Free Plus Anneal Available (RoHS Compliant) • TFT-LCD drive circuits • Notebook displays 10 VOUTB • LCD desktop monitors 9 VINB- • LCD-TVs 8 VINB+ Ordering Information 7 VS- VINC 5 Features Applications EL5128 (10 LD MSOP) TOP VIEW VOUTA 1 FN7000.3 6 VOUTC PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL5128CY 2 - 10 Ld MSOP MDP0043 (3.0mm) EL5128CY-T7 2 7” 10 Ld MSOP MDP0043 (3.0mm) EL5128CY-T13 2 13” 10 Ld MSOP MDP0043 (3.0mm) EL5128CYZ (Note) BAAAA - 10 Ld MSOP MDP0043 (3.0mm) (Pb-free) EL5128CYZ-T7 (Note) BAAAA 7” 10 Ld MSOP MDP0043 (3.0mm) (Pb-free) EL5128CYZ-T13 BAAAA (Note) 13” 10 Ld MSOP MDP0043 (3.0mm) (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5128 Absolute Maximum Ratings (TA = +25°C) Thermal information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS + 0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . 30mA Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = +25°C Unless Otherwise Specified Electrical Specifications PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT 12 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V 2 TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 0V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range (VCOM amps) CMRR Common-Mode Rejection Ratio (VCOM amps) for VIN from -5.5V to +5.5V 50 70 dB AVOL Open-Loop Gain -4.5V ≤ VOUT ≤ +4.5V (VCOM amps) 75 95 dB AV Voltage Gain -4.5V ≤ VOUT ≤ +4.5V -5.5 µV/°C 50 +5.5 0.995 nA V 1.005 V/V -4.85 V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = 5mA ISC IOUT -4.92 4.85 4.92 V Short Circuit Current ±120 mA Output Current ±30 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V 60 IS Supply Current (per amplifier) No load 660 1000 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 2) -4.0V ≤ VOUT ≤ +4.0V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product RL = 10kΩ, CL = 10pF (VCOM amps) 8 MHz PM Phase Margin RL = 10kΩ, CL = 10pF (VCOM amps) 50 ° CS Channel Separation f = 5MHz 75 dB NOTES: 1. Measured over operating temperature range. 2. Slew rate is measured on rising and falling edges. 2 FN7000.3 May 4, 2007 EL5128 VS+ = +5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = +25°C Unless Otherwise Specified Electrical Specifications PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT 10 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V 2 TCVOS Average Offset Voltage Drift (Note 3) 5 IB Input Bias Current VCM = 2.5V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio for VIN from -0.5V to +5.5V 45 66 dB AVOL Open-Loop Gain 0.5V ≤ VOUT ≤+ 4.5V 75 95 dB AV Voltage Gain 0.5V ≤ VOUT ≤+ 4.5V 0.995 -0.5 µV/°C 50 +5.5 nA V 1.005 V/V 150 mV OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA ISC IOUT 80 4.85 4.92 V Short Circuit Current ±120 mA Output Current ±30 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V 60 IS Supply Current (per amplifier) No load 660 1000 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 4) 1V ≤ VOUT ≤ 4V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product RL = 10kΩ, CL = 10pF 8 MHz PM Phase Margin RL = 10kΩ, CL = 10pF 50 ° CS Channel Separation f = 5MHz 75 dB NOTES: 3. Measured over operating temperature range. 4. Slew rate is measured on rising and falling edges. 3 FN7000.3 May 4, 2007 EL5128 VS+ = +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = +25°C Unless Otherwise Specified Electrical Specifications PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT 14 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 7.5V 2 TCVOS Average Offset Voltage Drift (Note 5) 5 IB Input Bias Current VCM = 7.5V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio for VIN from -0.5V to +15.5V 53 72 dB AVOL Open-Loop Gain 0.5V ≤ VOUT ≤ 14.5V 75 95 dB AV Voltage Gain 0.5V ≤ VOUT ≤ 14.5V 0.995 -0.5 µV/°C 50 +15.5 nA V 1.005 V/V 150 mV OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA ISC IOUT 80 14.85 14.92 V Short Circuit Current ±120 mA Output Current ±30 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V 60 IS Supply Current (per amplifier) No load 660 1000 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 6) 1V ≤ VOUT ≤ 14V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product RL = 10kΩ, CL = 10pF 8 MHz PM Phase Margin RL = 10kΩ, CL = 10pF 50 ° CS Channel Separation f = 5MHz 75 dB NOTES: 5. Measured over operating temperature range. 6. Slew rate is measured on rising and falling edges. 4 FN7000.3 May 4, 2007 EL5128 Typical Performance Curves 70 21 VS=±5V VS=±5V 5 0 -5 0 50 100 2.0 0.0 -2.0 150 -50 DIE TEMPERATURE (°C) 0 50 100 150 DIE TEMPERATURE (°C) FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE -4.91 VS=±5V IOUT=5mA 4.96 4.95 4.94 OUTPUT LOW VOLTAGE (V) 4.97 OUTPUT HIGH VOLTAGE (V) 19 FIGURE 2. INPUT OFFSET VOLTAGE DRIFT INPUT BIAS CURRENT (nA) INPUT OFFSET VOLTAGE (mV) FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION -50 17 INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C) INPUT OFFSET VOLTAGE (mV) 10 15 1 12 8 10 6 4 2 -0 -2 -4 0 -6 0 -8 10 -10 200 13 20 11 400 30 9 600 40 7 800 50 5 1000 TYPICAL PRODUCTION DISTRIBUTION 60 3 1200 VS=±5V QUANTITY (AMPLIFIERS) TYPICAL PRODUCTION DISTRIBUTION VS=±5V 1600 T =25°C A 1400 -12 QUANTITY (AMPLIFIERS) 1800 -4.92 VS=±5V IOUT=-5mA -4.93 -4.94 -4.95 -4.96 -4.97 4.93 -50 0 50 100 150 DIE TEMPERATURE (°C) FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE 5 -50 0 50 100 150 DIE TEMPERATURE (°C) FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE FN7000.3 May 4, 2007 EL5128 Typical Performance Curves (Continued) VS=±5V RL=10kΩ 10.40 SLEW RATE (V/µs) OPEN-LOOP GAIN (dB) 100 90 80 VS=±5V 10.35 10.30 10.25 -50 0 50 100 150 0 -50 FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE 150 100 FIGURE 8. SLEW RATE vs TEMPERATURE 700 VS=±5V TA=25°C 0.55 SUPPLY CURRENT PER AMPLIFIER (µA) SUPPLY CURRENT (mA) 50 DIE TEMPERATURE (°C) DIE TEMPERATURE (°C) 0.5 600 500 400 0.45 300 -50 0 50 100 150 0 200 5 -80 50 -130 GAIN 0 -180 VS=±5V, TA=25°C RL=10kΩ to GND CL=12pF to GND 100 1K 10K 100K 1M 10M -230 100M FREQUENCY (Hz) FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUENCY 6 MAGNITUDE (NORMALIZED) (dB) -30 PHASE PHASE (°) GAIN (dB) FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE 20 100 -50 10 20 15 SUPPLY VOLTAGE (V) FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE 150 10 5 DIE TEMPERATURE (°C) 10kΩ 0 1kΩ 560Ω -5 -10 150Ω CL=10pF AV=1 VS=±5V -15 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS RL FN7000.3 May 4, 2007 EL5128 Typical Performance Curves (Continued) 200 RL=10kΩ AV=1 10 VS=±5V OUTPUT IMPEDANCE (Ω) MAGNITUDE (NORMALIZED) (dB) 20 12pF 0 50pF -10 100pF -20 1000pF -30 100K 1M 160 120 80 40 0 10K 100M 10M AV=1 VS=±5V TA=25°C FIGURE 14. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY 12 80 10 60 8 CMRR (dB) MAXIMUM OUTPUT SWING (VP-P) 10M FREQUENCY (Hz) FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS CL 6 4 2 VS=±5V TA=25°C AV=1 RL=10kΩ CL=12pF DISTORTION <1% 0 10K 40 20 VS=±5V TA=25°C 100K 1M 0 100 10M 1K FREQUENCY (Hz) 80 VOLTAGE NOISE (nV/√Hz) 40 20 VS=±5V TA=25°C 1K 1M 10M 600 PSRR- 0 100 100K FIGURE 16. CMRR vs FREQUENCY PSRR+ 60 10K FREQUENCY (Hz) FIGURE 15. MAXIMUM OUTPUT SWING vs FREQUENCY PSRR (dB) 1M 100K FREQUENCY (Hz) 10K 100K 1M FREQUENCY (Hz) FIGURE 17. PSRR vs FREQUENCY 7 10M 100 10 1 100 1K 10K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 18. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY FN7000.3 May 4, 2007 EL5128 Typical Performance Curves (Continued) -60 0.010 0.009 0.007 X-TALK (dB) THD+ N (%) 0.008 0.006 0.005 0.004 VS=±5V RL=10kΩ AV=1 VIN=1VRMS 0.003 0.002 MEASURED CHANNEL A TO B VS=±5V R =10kΩ -80 AL =1 V VIN=220mVRMS -100 -120 0.001 1K 10K -140 1K 100K 10K FIGURE 19. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1M 6M V =±5V 90 AS =1 V RL=10kΩ VIN=±50mV 70 T =25°C A FIGURE 20. CHANNEL SEPARATION vs FREQUENCY RESPONSE STEP SIZE (V) OVERSHOOT (%) 100K FREQUENCY (Hz) FREQUENCY (Hz) 50 30 4 VS=±5V AV=1 3 RL=10kΩ 2 CL=12pF TA=25°C 1 0.1% 0 -1 -2 0.1% -3 -4 10 10 100 1K LOAD CAPACITANCE (pF) FIGURE 21. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 1V 1µs 0 200 400 600 800 SETTLING TIME (ns) FIGURE 22. SETTLING TIME vs STEP SIZE 50mV 200ns VS=±5V TA=25°C AV=1 RL=10kΩ CL=12pF VS=±5V TA=25°C AV=1 RL=10kΩ CL=12pF FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE 8 FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE FN7000.3 May 4, 2007 EL5128 Pin Descriptions PIN NUMBER PIN NAME 1 VOUTA PIN FUNCTION EQUIVALENT CIRCUIT Amplifier A Output VS+ GND VS- CIRCUIT 1 2 VINA- Amplifier A Inverting Input VS+ VS- CIRCUIT 2 3 VINA+ Amplifier A Non-Inverting Input (Reference Circuit 2) 4 VS+ Positive Power Supply 5 VINC Amplifier C (Reference Circuit 2) 6 VOUTC Amplifier C Output (Reference Circuit 2) 7 VS- 8 VINB+ Amplifier B Non-Inverting Input (Reference Circuit 2) 9 VINB- Amplifier B Inverting Input (Reference Circuit 2) 10 VOUTB Amplifier B Output (Reference Circuit 1) Negative Power Supply 9 FN7000.3 May 4, 2007 EL5128 Applications Information diodes placed in the input stage of the device begin to conduct and over-voltage damage could occur. Product Description The EL5128 voltage feedback amplifier/buffer combination is fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability, it is unity gain stable, and has low power consumption (500µA per amplifier). These features make the EL5128 ideal for a wide range of general-purpose applications. Connected in voltage follower mode and driving a load of 10kΩ and 12pF, the EL5128 has a -3dB bandwidth of 12MHz while maintaining a 10V/µs slew rate. 1V 1V Operating Voltage, Input, and Output The EL5128 is specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5128 specifications are stable over both the full supply range and operating temperatures of -40°C to +85°C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The input common-mode voltage range of the amplifiers extends 500mV beyond the supply rails. The output swings of the EL5128 typically extend to within 80mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 25 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from ±5V supply with a 10kΩ load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P. INPUT VS=±5V AV=1 TA=25°C VIN=10VP-P 100µs VS=±2.5V TA=25°C AV=1 VIN=6VP-P FIGURE 26. OPERATION WITH BEYOND-THE-RAILS INPUT Short Circuit Current Limit The EL5128 will limit the short circuit current to ±120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±30mA. This limit is set by the design of the internal metal interconnects. Driving Capacitive Loads The EL5128 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The amplifiers drive 10pF loads in parallel with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a “snubber” circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150Ω and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. OUTPUT Power Dissipation FIGURE 25. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT Output Phase Reversal The EL5128 is immune to phase reversal as long as the input voltage is limited from (VS-) -0.5V to (VS+) +0.5V. Figure 26 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection 10 With the high-output drive capability of the EL5128 amplifier, it is possible to exceed the 125°C “absolute-maximum junction temperature” under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX - T AMAX P DMAX = --------------------------------------------Θ JA FN7000.3 May 4, 2007 EL5128 where: JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD • TJMAX = Maximum junction temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = Σi × [ V S × I SMAX + ( V S + - V OUT i ) × I LOAD i ] POWER DISSIPATION (W) • TAMAX= Maximum ambient temperature 0.6 0.5 486mW 0.4 M SO P1 20 0 6°° CC// W W θ JJAA = 0.3 0.2 0.1 0 0 when sourcing, and: P DMAX = Σi × [ V S × I SMAX + ( V OUT i - V S - ) × I LOAD i ] 25 75 85 50 100 125 AMBIENT TEMPERATURE (°C) FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE when sinking. JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD where: 1 • VS = Total supply voltage • ISMAX = Maximum supply current per amplifier • VOUTi = Maximum output voltage of the application • ILOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figures 27 and 28 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves in Figures 27 and 28. POWER DISSIPATION (W) 0.9 870mW 0.8 0.7 θ M JA = 0.6 11 0.5 SO 5° P1 0 C/ W 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Power Supply Bypassing and Printed Circuit Board Layout The EL5128 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1µF ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7µF tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. 11 FN7000.3 May 4, 2007 EL5128 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3° ±3° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN7000.3 May 4, 2007