iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 1/13
FEATURES
APPLICATIONS
♦ 8-/12-fold level shift to 5 V output voltage
♦ Safe low output state with single errors
♦ Schmitt trigger inputs with two-stage pull-down current for
enhanced noise immunity with limited power dissipation
♦ Inputs compatible with TTL and CMOS levels
(1.8 V to 3.3 V to 5 V)
♦ Current-limited and short-circuit-proof push-pull output stages
♦ Push-pull current sources for driving FETs
♦ Surge voltage-proof outputs up to 18 V
♦ Ground and supply voltage monitor
♦ Protective ESD circuitry
♦ Temperature range from -40 to 125 °C
♦ Operation of 5 V logic level
N-FETs from 3.3 V systems
PACKAGES
QFN24
(iC-MFL)
QFN28
(iC-MFLT)
BLOCK DIAGRAM
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
IN8
OUT8
EN
iC-MFL
VCC
Copyright © 2008 iC-Haus
Supply- and
Ground Monitor
GNDR
GND
http://www.ichaus.com
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 2/13
DESCRIPTION
iC-MFL / iC-MFLT is a monolithically integrated,
8/12-channel level adjustment device which drives
N-channel FETs. The internal circuit blocks have
been designed in such a way that with single errors, such as open pins (VCC, GND, GNDR) or
the short-circuiting of two outputs, iC-MFL’s output
stages switch to a predefined, safe low state. Externally connected N-channel FET are thus shut down
safely in the event of a single error.
The inputs of the eight/twelve channels consist of
a Schmitt trigger with a pull-down current source
and are compatible with TTL and CMOS levels (1.8
to 5 V). The eight/twelve channels have a currentlimited push-pull output stage and a pull-down resistor at the output. The output stages supply an output
signal of 5 V and are enabled by a high signal at pin
EN. Furthermore, all stages can handle surge voltage pulses (max. 18 V, pulse width < 100 ms, max.
2 % duty cycle) at the output.
iC-MFL monitors the supply voltage at VCC pin and
the voltages at the two ground pins GND and GNDR.
The pins GND and GNDR must be connected together externally in order to guarantee the safe low
state of the output stages in the event of error.
Should the supply voltage at VCC undershoot a predefined threshold, the voltage monitor causes the
outputs to be actively tied to GND via the lowside
transistors. If the supply voltage ceases to be applied
to VCC, the outputs are tied to GNDR by pull-down
resistors.
If the connection between the ground potential and
the GND pin is disrupted, the highside and lowside
transistors of the output stages are shut down and
the outputs tied to GNDR via the pull-down resistors.
If on the other hand the connection between ground
potential and the GNDR pin is disrupted, only the
output stage highside transistors are shut down; the
outputs are then actively tied to GND via the lowside
transistors.
Open inputs IN1...8/12 and EN are actively tied to
GND by pull-down currents. The pull-down currents
have two stages in order to limit power dissipation
with enhanced noise immunity.
When two outputs of different logic states are short
circuited, the driving capability of the lowside driver
predominates, keeping the connected N-channel
FETs in a safe shutdown state.
The device is protected against destruction by ESD.
PACKAGES
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 3/13
PIN CONFIGURATION QFN24
4 mm x 4 mm to JEDEC MO220
PIN FUNCTIONS
No. Name Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OUT1
GNDR
VCC
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
EN
GND
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
TP
5 V Output channel 1
(n.c.)
(n.c.)
Ground (Resistor)
5 V Supply Voltage
Input channel 1
Input channel 2
Input channel 3
Input channel 4
Input channel 5
Input channel 6
Input channel 7
Input channel 8
(n.c.)
Enable Input
(n.c.)
Ground
5 V Output channel 8
5 V Output channel 7
5 V Output channel 6
5 V Output channel 5
5 V Output channel 4
5 V Output channel 3
5 V Output channel 2
Thermal-Pad
The Thermal Pad is to be connected to a ground plane on the PCB. Connections between GND, GNDR and the
ground plane should be conciled to system FMEA aspects.
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 4/13
PIN FUNCTIONS
No. Name Function
PIN CONFIGURATION QFN28
5 mm x 5 mm to JEDEC MO220
28
27
26
25
24
23
22
1
21
2
20
3
19
MFLT
4
18
code...
...
5
6
17
16
15
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OUT2
OUT1
GNDR
VCC
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
EN
GND
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
TP
5 V Output channel 2
5 V Output channel 1
Ground (Resistor)
5 V Supply Voltage
Input channel 1
Input channel 2
Input channel 3
Input channel 4
Input channel 5
Input channel 6
Input channel 7
Input channel 8
Input channel 9
Input channel 10
Input channel 11
Input channel 12
Enable Input
Ground
5 V Output channel 12
5 V Output channel 11
5 V Output channel 10
5 V Output channel 9
5 V Output channel 8
5 V Output channel 7
5 V Output channel 6
5 V Output channel 5
5 V Output channel 4
5 V Output channel 3
Thermal-Pad
The Thermal Pad is to be connected to a ground plane on the PCB. Connections between GND, GNDR and the
ground plane should be conciled to system FMEA aspects.
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 5/13
ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 VCC
Supply Voltage
-0.3
6
V
G002 V()
Voltage at OUT1...8/12
-0.3
6
V
G003 Vp()
Peak Voltage at OUT1...8/12
-0.3
18
V
G004 V()
Voltage at IN1...8/12, EN
-0.3
6
V
G005 V(GNDR)
Voltage at GNDR referenced to GND
-0.3
0.3
V
G006 V(GND)
Voltage at GND referenced to GNDR
-0.3
0.3
V
G007 Imx()
Current in OUT1...8/12, IN1...8/12, EN
-10
10
mA
G008 Imx()
Current in OUT1...8/12
-10
120
mA
G009 Imx()
Current in VCC, GND
-50
50
mA
G010 Imx()
Current in GND, GNDR
t < 100 ms, duty cycle < 2 %
-100
10
mA
G011 Vd()
ESD susceptibility
HBM 100 pF discharged through 1.5 kΩ
2
kV
G012 Tj
Operating Junction Temperature
-40
150
°C
G013 Ts
Storage Temperature Range
-55
125
°C
t < 100 ms, duty cycle < 2 %
t < 100 ms, duty cycle < 2 %
THERMAL DATA
Operating Conditions: VCC = 5 V ±10 %
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
T01
Ta
Operating Ambient Temperature Range
T02
Rthja
Thermal Resistance Chip/Ambient
-40
SMD assembly, no additional cooling areas.
All voltages are referenced to ground unless otherwise stated.
All currents into the device pins are positive; all currents out of the device pins are negative.
Typ.
Max.
125
°C
75
K/W
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 6/13
ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC = 5 V ±10 %, Tj = -40...125 °C unless otherwise stated
Item
No.
Symbol
Parameter
Conditions
Tj
°C
Fig.
Unit
Min.
Typ.
Max.
4.5
5
5.5
V
7
10
mA
mA
Total Device
001
002
003
004
005
VCC
Permissible Supply Voltage
I(VCC)
Supply Current in VCC
(No load)
iC-MFL
iC-MFLT
1.5
I(VCC)
Error Current in VCC
VCC = 5 V, one output at 18 V
-50
mA
I(GND)
Current in GND
(No load)
iC-MFL
iC-MFLT
-6
-9
mA
mA
(No load, all OUTx = hi)
iC-MFL
iC-MFLT
-4
-6
-0.3
mA
mA
20
100
mA
18
V
-3
-0.4
V
I(GNDR)
Current in GNDR
Current Driver OUT1...8/12
101 I(OUTx)
Current in I(OUTx)
V() = 18 V
VCC = 5 V
102
U(OUTx)
permitted voltage
103
Vc()lo
Clamp Voltage lo referenced to
I() = -10 mA
the lower voltage of GND, GNDR
T < 100 ms, duty cycle < 2 %
104
Vs()hi
Saturation Voltage hi referenced
to VCC
Vs()hi = VCC – V();
I() = -0.5 mA
I() = -2 mA
0.2
0.8
V
V
0.2
0.8
V
V
70
kΩ
105
Vs()lo
Saturation Voltage lo referenced
to GND
I() = 0.5 mA
I() = 2 mA
106
Rpd()
Pull-Down Resistor at OUTx
referenced to GNDR
V(GND) > Vtr(GND)
107
Isc()lo
Short circuit current lo
108
Isc()hi
Short circuit current hi
109
Vsh()
Output Voltage at short circuit of At two different input signals hi
two outputs
and lo
12
30
V() = 0.8 V...VCC
2
3.6
6
mA
V() = 0...VCC – 0.8 V
-6
-3
-2
mA
1.1
V
Input IN1...8/12, EN
201
Vc()hi
Clamp Voltage hi
202
Vc()lo
Clamp Voltage lo referenced to
I() = -10 mA
the lower voltage of GND, GNDR
I() = 10 mA
-3
-0.4
V
203
Vt()hi
Threshold Voltage hi
1.1
1.4
V
204
Vt()lo
Threshold Voltage lo
0.8
1.1
V
205
Vt()hys
Input Hysteresis
Vt()hys = Vt()hi – Vt()lo
200
400
mV
206
Ipd1()
Pull-Down Current 1
0.4 V < V() < Vt()hi
4
150
225
350
µA
207
Ipd2()
Pull-Down Current 2
V() > 1.4 V
4
20
45
70
µA
208
Cin()
Input Capacitance
209
Ileak()
Input Leakage Current
VCC = 0 V, V() = 0...5.5 V
6
V
20
pF
-10
10
µA
V
Supply Monitor
301
VCCon
Turn-On Threshold VCC
3.7
4.4
302
VCCoff
Turn-Off Threshold VCC
Decreasing voltage VCC
3.2
4.1
V
303
VCChys
Hysteresis
VCChys = VCCon – VCCoff
100
600
mV
270
mV
200
Ground Monitor GND, GNDR
401
Vtg()hi
Threshold Voltage hi GND Moni- Referenced to GNDR
tor
402
Vtg()lo
Threshold Voltage lo GND Moni- Referenced to GNDR
tor
50
403
Vtg()hys
Hysteresis
5
404
Vtr()hi
Threshold Voltage hi GNDR Mon- Referenced to GND
itor
405
Vtr()lo
Threshold Voltage lo GNDR Mon- Referenced to GND
itor
Vt()hys = Vt()hi - Vt()lo
50
mV
80
mV
270
mv
mV
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 7/13
ELECTRICAL CHARACTERISTICS
Operating Conditions: VCC = 5 V ±10 %, Tj = -40...125 °C unless otherwise stated
Item
No.
406
Symbol
Vtr()hys
Parameter
Conditions
Hysteresis
Vt()hys = Vt()hi - Vt()lo
Propagation Delay, INx, EN →
OUTx
({INx, EN}lo → hi) → 90 % OUTx,
({INx, EN}hi → lo) → 10 % OUTx,
no Cl()
Tj
°C
Fig.
Unit
Min.
Typ.
Max.
5
80
mV
40
200
ns
Timing
501
tp(OUTx)
1
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 8/13
ELECTRICAL CHARACTERISTICS: Diagrams
V(INx, EN)
Vt()hi
Vt()lo
0
t
V(OUTx)
V()hi
0.9 V()hi
0.1 V()hi
0
t
tp(OUTx)
tp(OUTx)
Figure 1: Propagation delays
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 9/13
DESCRIPTION OF FUNCTIONS
Output characteristic of the lowside transistor
The lowside output transistors at the eight/twelve channels demonstrate a resistive behavior with low voltage
V(OUTx) and behave as a current sink with finite output resistance with higher voltages.
I(OUTx)
rent remains high until Vt()hi (Electrical Characteristics
No. 203); above this threshold the device switches to
a lower pull-down current. If the voltage falls below
Vt()lo (Electrical Characteristics No. 204), the device
switches back to a higher pull-down current.
I(OUTx)
[mA]
[mA]
VCC − V(OUTx)
3.6
1
3
4
5
[V]
−400Ω
−400Ω
V(OUTx)
1
2
2
3
4
5
−3
[V]
Figure 2: Output characteristic of the lowside transistor at OUTx
Output characteristic for the highside transistor
The highside output transistors at the eight/twelve
channels demonstrate a resistive behavior with low
voltage (VCC – V(OUTx)) and behave as a current
source with finite output resistance with higher voltages.
Figure 3: Output characteristic of the highside transistor at OUTx
Ipd()
V() increasing
Ipd1()
Ipd2()
V() decreasing
Pull-down currents
In order to enhance noise immunity with limited power
dissipation at inputs INx and EN the pull-down currents at these pins have two stages. With a rise in
voltage at input pins INx and EN the pull-down cur-
Vt()lo
Vt()hi
V()
Figure 4: Pull-down currents at INx and EN
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 10/13
DETECTING SINGLE ERRORS
If single errors are detected, safety-relevant applications require externally connected switching transistors
to be specifically shut down. Single errors can occur
when a pin is open (due to a disconnected bonding
wire or a bad solder connection, for example) or when
two pins are short-circuited.
I(OUTx)
[µA]
150
−30 kΩ
When two output of different logic levels are shortcircuited, the driving capability of the lowside driver will
predominate, keeping the connected N-channel FETs
in a safe shutdown state.
With open pins VCC, GND or GNDR iC-MFL switches
the output stages to a safe, predefined low state via
pull-down resistors or pull-down current sources at the
inputs, subsequently shutting down any externally connected N-channel FETs.
I(OUTx)
[µA]
V(OUTx)
1
2
3
4
[V]
5
Figure 6: Output characteristic at OUTx with open
GND pin
Loss of GND potential
If ground potential is not longer applied to GND, the
output stages are shut down and the outputs tied to
GNDR via internal pull-down resistors with a typical
value of 30 kΩ.
150
I(OUTx)
[mA]
3.6
−30kΩ
V(OUTx)
1
2
3
4
5
[V]
Figure 5: Output characteristic at OUTx with disconnected VCC supply
Loss of VCC potential
If the supply voltage is disconnected from VCC pin, the
outputs are tied to GNDR via internal pull-down resistors of typically 30 kΩ which form a passive path from
the gate of an external switching transistor to ground.
A further increase of output current may occur due to
self-supply effects via the output of the iC, as indicated
by the arrows in Figure 5.
V(OUTx)
1
2
3
4
5
[V]
Figure 7: Output characteristic at OUTx with open
GNDR pin
Loss of GNDR potential
If ground potential is no longer applied to the GNDRpin, the output stage highside drivers are shut down
and the outputs actively tied to GND via the lowside
drivers.
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 11/13
OUTPUT VOLTAGE SURGE PROTECTION
An internal protective circuitry allows for short overvoltage pulses of up to 18 V at the output stages. Puls
duration and duty cycle must be less than 100 ms and
2 % respectively for absolute maximum ratings.
to ground via the output resistor which has a typical
value of 150 Ω.
I(OUTx)
[mA]
80
I(OUTx)
[mA]
60
80
−150Ω
40
60
20
−150 Ω
40
V(OUTx)
20
−3 mA
3.6 mA
5
10
15
[V]
18
V(OUTx)
5
10
15
18
[V]
Figure 8: Surge output characteristic at OUTx
with Vin = low
The output characteristic in Figure 8 corresponds to
that of the lowside driver as shown in Figure 2 for an
output voltage V(OUTx) of up to VCC potential. At
higher output voltage, the excess current is diverted
Figure 9: Surge output characteristic at OUTx
with Vin = high
The output characteristic in Figure 9 corresponds to
that of the highside driver as shown in Figure 3 for
an output voltage V(OUTx) of up to VCC potential. At
higher output voltage, the excess current is diverted to
ground via the output resistor which has a typical value
of 150 Ω.
APPLICATION NOTES
Driving an N-channel MOSFET
One typical field of application for iC-MFL is in the operation of 5 V logic level N-FETs with microprocessor
output signals of 1.8 to 5 V, as shown in Figure 10.
24V
3.3 V
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
IN8
OUT8
CL
VCC
3.3 V
0V
Microcontroller
RL
T1
EN
GND
iC-MFL
5V
VCC
Supply- and
Ground Monitor
GNDR
GND
Figure 10: Driving an N-channel MOSFET
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 12/13
This specification is for a newly developed product. iC-Haus therefore reserves the right to change or update, without notice, any information contained herein,
design and specification; and to discontinue or limit production or distribution of any product versions. Please contact iC-Haus to ascertain the current data.
Copying – even as an excerpt – is only permitted with iC-Haus approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions
in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of
merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which
information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or
areas of applications of the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued
annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in
Hanover (Hannover-Messe).
We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
iC-MFL / iC-MFLT
8-/12-FOLD FAIL-SAFE LOGIC N-FET DRIVER
Rev C1, Page 13/13
ORDERING INFORMATION
Type
Package
Order Designation
iC-MFL
QFN24
QFN24
iC-MFL QFN24
iC-MFLT QFN28
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
Appointed local distributors: http://www.ichaus.de/support_distributors.php