Fairchild DM74S182 Look-ahead carry generator Datasheet

Revised March 2000
DM74S182
Look-Ahead Carry Generator
General Description
These circuits are high-speed, look-ahead carry generators, capable of anticipating a carry across four binary
adders or groups of adders. They are cascadable to perform full look-ahead across n-bit adders. Carry, generatecarry, and propagate-carry functions are provided as
shown in the pin designation table.
When used in conjunction with the 181 arithmetic logic unit,
these generators provide high-speed carry look-ahead
capability for any word length. Each DM74S182 generates
the look-ahead (anticipated carry) across a group of four
ALU’s and, in addition, other carry look-ahead circuits may
be employed to anticipate carry across sections of four
look-ahead packages up to n-bits. The method of cascading circuits to perform multi-level look-ahead is illustrated
under typical application data.
Carry input and output of the ALU’s are in their true form,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, out-
puts, generate, and propagate) of the look-ahead generators are implemented in the compatible forms for direct
connection to the ALU. Reinterpretations of carry functions,
as explained on the 181 data sheet are also applicable to
and compatible with the look-ahead generator. Positive
logic equations for the DM74S182 are:
Cn + x = G0 + P0 Cn
Cn + y = G1 + P1 G0 + P1 P0 Cn
Cn + z = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 Cn
G = G3 (P3 + G2) (P3 + P2 + G1)
(P3 + P2 + P1 + G0)
P = P3 P2 P1 P0
Features
■ Typical propagation delay time 7 ns
■ Typical power dissipation 260 mW
Ordering Code:
Order Number
DM74S182N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Pin Designations
Designation
Pin Nos.
Function
G0, G1, G2, G3
3, 1, 14, 5
Active LOW
P0, P1, P2, P3
4, 2, 15, 6
Carry Generate Inputs
Active LOW
Carry Propagate Inputs
Cn
13
Carry Input
Cn + x, Cn + y,
12, 11, 9
Carry Outputs
Cn + z
G
10
Active LOW
Carry Generate Output
P
7
Active LOW
Carry Propagate Output
© 2000 Fairchild Semiconductor Corporation
DS006474
VCC
16
Supply Voltage
GND
8
Ground
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DM74S182 Look-Ahead Carry Generator
August 1986
DM74S182
Logic Diagram
VCC = PIN 16
GND = PIN 8
Typical Application
64-Bit ALU, Full-Carry Look Ahead in Three Levels
A and B inputs, and F outputs of 181 are not shown.
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2
Supply Voltage
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
7V
Input Voltage
5.5V
0°C to +70°C
Operating Free Air Temperature Range
−65°C to +150°C
Storage Temperature Range
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
4.75
5
5.25
V
LOW Level Input Voltage
0.8
V
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
VIL
2
V
IOH
HIGH Level Output Current
−1
mA
IOL
LOW Level Output Current
20
mA
TA
Free Air Operating Temperature
70
°C
0
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
VOH
HIGH Level
VCC = Min, IOH = Max
Output Voltage
VIL = Max, VIH = Min
LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min, VIL = Max
VOL
Min
2.7
Typ
(Note 2)
Max
Units
−1.2
V
3.4
V
0.5
V
II
Input Current @ Max Input Voltage VCC = Max, VI = 5.5V
1
mA
IIH
HIGH Level
VCC = Max
P0, P1 or G3
200
µA
Input Current
VI = 2.7V
P3
100
P2
150
IIL
Cn
50
G0, G2
350
G1
400
LOW Level
VCC = Max
P0, P1 or G3
−8
Input Current
VI = 0.5V
P3
−4
P2
−6
Cn
−2
G0, G2
−14
−16
G1
VCC = Max (Note 3)
IOS
Short Circuit Output Current
ICCH
Supply Current with Outputs HIGH VCC = Max (Note 4)
ICCL
Supply Currents with Outputs LOW VCC = Max (Note 5)
mA
−40
−100
mA
39
55
mA
69
109
mA
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4: ICCH is measured with all outputs OPEN, inputs P3 and G3 at 4.5V, and all other inputs grounded.
Note 5: ICCL is measured with all outputs OPEN, inputs G0, G1, and G2 at 4.5V, and all other inputs grounded.
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DM74S182
Absolute Maximum Ratings(Note 1)
DM74S182
Switching Characteristics
at VCC = 5V and TA = 25°C
RL = 280Ω
Symbol
Parameter
From (Input)
To (Output)
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
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CL = 15 pF
Min
CL = 50 pF
Max
Min
Units
Min
GN or PN to Cn + x, y, z
7
10
ns
GN or PN to Cn + x, y, z
7
11
ns
GN or PN to G
7.5
11
ns
GN or PN to G
10.5
14
ns
PN to P
6.5
10
ns
PN to P
10
14
ns
Cn to to Cn + x, y, z
10
13
ns
Cn to to Cn + x, y, z
10.5
14
ns
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DM74S182 Look-Ahead Carry Generator
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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