256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb B-die 64bit Non-ECC INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM DDR2 Unbuffered SODIMM Ordering Information Part Number Density Organization Component Composition Number of Rank Height M470T3354BG(Z)3-CD5/CC 256MB 32Mx64 32Mx16(K4T51163QB)*4 1 30mm M470T3354BG(Z)0-CD5/CC 256MB 32Mx64 32Mx16(K4T51163QB)*4 1 30mm M470T3354BZ3-LD5/CC 256MB 32Mx64 32Mx16(K4T51163QB)*4 1 30mm M470T3354BZ0-LD5/CC 256MB 32Mx64 32Mx16(K4T51163QB)*4 1 30mm M470T6554BG(Z)3-CD5/CC 512MB 64Mx64 32Mx16(K4T51163QB)*8 2 30mm M470T6554BG(Z)0-CD5/CC 512MB 64Mx64 32Mx16(K4T51163QB)*8 2 30mm M470T6554BZ3-LD5/CC 512MB 64Mx64 32Mx16(K4T51163QB)*8 2 30mm M470T6554BZ0-LD5/CC 512MB 64Mx64 32Mx16(K4T51163QB)*8 2 30mm M470T2953BS(Y)3-CD5/CC 1GB 128Mx64 64Mx8(K4T51083QB)*16 2 30mm M470T2953BS(Y)0-CD5/CC 1GB 128Mx64 64Mx8(K4T51083QB)*16 2 30mm M470T2953BY3-LD5/CC 1GB 128Mx64 64Mx8(K4T51083QB)*16 2 30mm M470T2953BY0-LD5/CC 1GB 128Mx64 64Mx8(K4T51083QB)*16 2 30mm Note: “Z” and “Y” of Part number(11th digit) stand for Lead-free products. Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products. Features • Performance range D5(DDR2-533) CC(DDR2-400) Unit Speed@CL3 400 400 Mbps Speed@CL4 533 400 Mbps CL-tRCD-tRP 4-4-4 3-3-3 CK • JEDEC standard 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin • 4 Banks • Posted CAS • Programmable CAS Latency: 3, 4, 5 • Programmable Additive Latency: 0, 1 , 2 , 3 and 4 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination • Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C - support High Temperature Self-Refresh rate enable feature • Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16 • All of Lead-free products are compliant for RoHS Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 64Mx8(512Mb) based Module A0-A13 A0-A9 BA0-BA1 A10 32Mx16(512Mb) based Module A0-A12 A0-A9 BA0-BA1 A10 Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Pin Configurations (Front side/Back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47 5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS 7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS 157 DQ48 158 DQ52 DQ53 9 VSS 10 DM0 59 VSS 60 VSS 109 WE 110 S0 159 DQ49 160 11 DQS0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS 13 14 DQ6 63 CAS 114 ODT0 163 CK1 65 66 115 NC/S1 116 A13 165 NC, TEST VSS 164 DQ7 DQ29 VSS 113 16 DQ25 VSS 64 15 DQS0 VSS 166 CK1 17 DQ2 18 VSS 67 DM3 68 DQS3 117 VDD 118 VDD 167 DQS6 168 VSS 19 20 DQ12 69 121 122 171 DQS6 VSS 170 72 NC VSS 169 71 NC/ODT1 VSS 120 DQ13 DQS3 VSS 119 22 NC VSS 70 21 DQ3 VSS DM6 VSS 23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 26 DQ27 VSS 76 DQ31 VSS 125 DQ37 VSS 175 177 DQ51 VSS 176 127 DQ33 VSS 126 28 DM1 VSS 75 27 DQ9 VSS DQ55 VSS 29 DQS1 30 CK0 79 80 DQS4 130 DQ56 180 DQ60 32 CK0 81 131 DQS4 132 DM4 VSS 179 DQS1 NC/CKE1 VDD 129 31 CKE0 VDD 181 DQ57 182 DQ61 77 78 82 128 172 178 33 VSS 34 VSS 83 NC 84 NC 133 VSS 134 DQ38 183 VSS 184 VSS 35 DQ10 36 DQ14 85 86 DQ34 136 DQS7 DQ15 87 88 137 DQ35 138 187 DM7 VSS 186 38 DQ39 VSS 185 DQ11 NC VDD 135 37 BA2 VDD 188 DQS7 39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS 41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63 45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS5 195 SDA 196 VSS 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 49 DQS2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 Note : NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules. Pin Description Pin Name Function CK0,CK1 Clock Inputs, positive line CK0,CK1 Clock Inputs, negative line CKE0,CKE1 Clock Enables Pin Name SDA SA1,SA0 Function SPD Data Input/Output SPD address DQ0~DQ63 Data Input/Output DM0~DM7 Data Masks RAS Row Address Strobe CAS Column Address Strobe DQS0~DQS7 Data strobes WE Write Enable DQS0~DQS7 Data strobes complement S0,S1 Chip Selects TEST A0~A9, A11~A13 A10/AP BA0,BA1 ODT0,ODT1 SCL Logic Analyzer specific test pin (No connect on So-DIMM) Address Inputs VDD Core and I/O Power Address Input/Autoprecharge VSS Ground VREF Input/Output Reference SDRAM Bank Address On-die termination control Serial Presence Detect(SPD) Clock Input VDDSPD NC SPD Power Spare pins, No connect Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Input/Output Functional Description Symbol Type Function CK0-CK1 CK0-CK1 Input The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK . A Delay Locked Loop (DLL) circuit is driven from the clock input and output timing for read operations is synchronized to the input clock. CKE0-CKE1 Input Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low, By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refesh mode. S0-S1 Input Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0, Rank 1 is selected by S1. Ranks are also called “Physical banks”. RAS, CAS, WE Input When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE define the operation to be executed by the SDRAM. BA0~BA1 Input Selects which DDR2 SDRAM internal bank is activated. ODT0~ODT1 Input Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM Extended Mode Register Set (EMRS). A0~A9, A10/AP, A11~A13 Input During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. DQ0~DQ63 In/Out Data Input/Output pins. DM0~DM7 Input The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DQS0~DQS7 DQS0~DQS7 In/Out The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. VDD,VDD SPD,VSS Supply Power supplies for core, I/O, Serial Presence Detect, and ground for the module. SDA In/Out This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected to VDD to act as a pull up. SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up. SA0~SA1 Input Address pins used to select the Serial Presence Detect base address. TEST In/Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SO-DIMMs). Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Functional Block Diagram: 512MB, 64Mx64 Module(Populated as 2 rank of x16 DDR2 SDRAMs) M470T6554BG(Z)3/M470T6554BG(Z)0 3Ω + 5% ODT1 ODT0 CKE1 CKE0 S1 S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS CS C K LDQS E LDM I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 O D T LDQS CS C K LDQS E LDM I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 O D T LDQS CS C K LDQS E LDM I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 O D T LDQS CS C K LDQS E LDM I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 O D T DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQS6 DQS6 DM6 DQS7 DQS7 DM7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS CS C K LDQS E LDM I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 O D T LDQS CS C K LDQS E LDM I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 O D T LDQS CS C K LDQS E LDM I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 O D T LDQS CS C K LDQS E LDM I/O 0 I/O 1 D7 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 O D T 3Ω + 5% BA0 - BA1 DDR2 SDRAMs D0 - D7 A0 - A13 DDR2 SDRAMs D0 - D7 RAS DDR2 SDRAMs D0 - D7 CAS DDR2 SDRAMs D0 - D7 WE DDR2 SDRAMs D0 - D7 SCL SA0 SA1 SCL A0 SPD A1 A2 SDA WP * Clock Wiring VDDSPD Serial PD VREF DDR2 SDRAMs D0 - D7 VDD DDR2 SDRAMs D0 - D7, VDD and VDDQ VSS DDR2 SDRAMs D0 - D7, SPD Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 4 DDR2 SDRAMs 4 DDR2 SDRAMs * Wire per Clock Loading Table/Wiring Diagrams Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms ± 5%. Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Functional Block Diagram: 256MB, 32Mx64 Module(Populated as 1 rank of x16 DDR2 SDRAMs) M470T3354BG(Z)3/M470T3354BG(Z)0 3Ω + 5% CKE0 ODT0 S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS CS O D LDQS T LDM I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E LDQS CS O D LDQS T LDM I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 3Ω BA0 - BA1 DDR2 SDRAMs D0 - D3 A0 - A13 DDR2 SDRAMs D0 - D3 RAS DDR2 SDRAMs D0 - D3 CAS DDR2 SDRAMs D0 - D3 WE DDR2 SDRAMs D0 - D3 DQS4 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7 SCL SA0 SA1 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SCL A0 SPD A1 A2 LDQS CS O D LDQS T LDM I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E LDQS CS O D LDQS T LDM I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E SDA WP * Clock Wiring VDDSPD Serial PD Clock Input DDR2 SDRAMs VREF DDR2 SDRAMs D0 - D3 *CK0/CK0 *CK1/CK1 2 DDR2 SDRAMs 2 DDR2 SDRAMs VDD DDR2 SDRAMs D0 - D3, VDD and VDDQ VSS DDR2 SDRAMs D0 - D3, SPD * Wire per Clock Loading Table/Wiring Diagrams Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms ± 5%. Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Functional Block Diagram: 1GB, 128Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs) M470T2953BS(Y)3/M470T2953BS(Y)0 3Ω + 5% CKE1 ODT1 S1 CKE0 ODT0 S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 CS0 O D T 0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS0 O DQS DQS D DM T 0 I/O 8 I/O 9 D1 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 0 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 C K E 0 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS0 O DQS D DQS T DM 0 I/O 8 I/O 9 D3 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 0 D0 CS0 O D T 0 D2 C K E 0 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS1 O D T 1 D8 CS1 O DQS DQS D DM T 1 I/O 8 I/O 9 D9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 C K E 1 CS1 O D T 1 C K E 1 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS4 DQS4 DM4 C K E 1 DQS5 DQS5 DM5 DQS6 DQS6 DM6 D10 CS1 O DQS D DQS T DM 1 I/O 8 I/O 9 D11 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS7 DQS7 DM7 C K E 1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS0 O D T 0 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS DQS DM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS0 O D T 0 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS0 O D T 0 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS DQS DM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS0 O D T 0 C K E 0 D4 C K E 0 D5 C K E 0 D6 C K E 0 D7 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS1 O D T 1 DQS DQS DM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS1 O D T 1 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS1 O D T 1 DQS DQS DM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS1 O D T 1 C K E 1 D12 C K E 1 D13 C K E 1 D14 C K E 1 D15 * Clock Wiring 10Ω + 5% BA0 - BA1 DDR2 SDRAMs D0 - D15 A0 - A13 DDR2 SDRAMs D0 - D15 RAS DDR2 SDRAMs D0 - D15 CAS DDR2 SDRAMs D0 - D15 WE DDR2 SDRAMs D0 - D15 SCL SA0 SA1 VDDSPD Serial PD VREF DDR2 SDRAMs D0 - D15 VDD DDR2 SDRAMs D0 - D15, VDD and VDDQ VSS DDR2 SDRAMs D0 - D15, SPD SCL A0 SPD A1 A2 WP SDA Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 8 DDR2 SDRAMs 8 DDR2 SDRAMs * Wire per Clock Loading Table/Wiring Diagrams Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%. Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Absolute Maximum DC Ratings Symbol Rating Units Notes Voltage on VDD pin relative to VSS - 1.0 V ~ 2.3 V V 1 VDDQ Voltage on VDDQ pin relative to VSS - 0.5 V ~ 2.3 V V 1 VDDL Voltage on VDDL pin relative to VSS - 0.5 V ~ 2.3 V V 1 Voltage on any pin relative to VSS - 0.5 V ~ 2.3 V V 1 -55 to +100 °C 1, 2 VDD VIN, VOUT TSTG Parameter Storage Temperature Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC Operating Conditions (SSTL - 1.8) Symbol Parameter Rating Min. Typ. Max. 1.7 1.8 1.9 Units Notes VDD Supply Voltage VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 4 VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 4 VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 1,2 Termination Voltage VREF-0.04 VREF VREF+0.04 V 3 VTT V Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together. Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Operating Temperature Condition Symbol Parameter Rating Units Notes TOPER Operating Temperature 0 to 95 °C 1, 2, 3 Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported. 3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. Input DC Logic Level Symbol Parameter Min. Max. Units VIH(DC) DC input logic high VREF + 0.125 VDDQ + 0.3 V VIL(DC) DC input logic low - 0.3 VREF - 0.125 V Max. Units Notes Input AC Logic Level Symbol Parameter Min. VIH(AC) AC input logic high VREF + 0.250 - V VIL(AC) AC input logic low - VREF - 0.250 V Notes AC Input Test Conditions Symbol VREF VSWING(MAX) SLEW Condition Input reference voltage Value Units Notes 0.5 * VDDQ V 1 Input signal maximum peak to peak swing 1.0 V 1 Input signal minimum slew rate 1.0 V/ns 2, 3 Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions. VDDQ VIH(AC) min VIH(DC) min VSWING(MAX) VREF VIL(DC) max VIL(AC) max delta TF Falling Slew = delta TR VREF - VIL(AC) max delta TF Rising Slew = VSS VIH(AC) min - VREF delta TR < AC Input Test Signal Waveform > Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM IDD Specification Parameters Definition (IDD values are for full operating range of Voltage and Temperature) Symbol Proposed Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA IDD2P Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0mA mA Slow PDN Exit MRS(12) = 1mA mA IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA IDD5B Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions Normal mA Low Power mA Notes mA Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Operating Current Table(1-1) (TA=0oC, VDD= 1.9V) M470T6554BG(Z)3/M470T6554BG(Z)0 : 64Mx64 512MB Module Symbol CD5 (DDR533@CL=4) LD5 (DDR533@CL=4) CCC (DDR400@CL=3) LCC (DDR400@CL=3) Unit IDD0 760 460 720 460 mA IDD1 860 560 760 520 mA IDD2P 64 64 64 64 mA IDD2Q 200 200 200 200 mA mA IDD2N 240 200 240 200 IDD3P-F 240 120 240 120 mA IDD3P-S 120 120 120 120 mA IDD3N 560 260 520 260 mA IDD4W 1,200 700 1,000 700 mA IDD4R 1,100 700 940 700 mA IDD5B 1,060 860 1,000 860 mA IDD6 44 40 44 40 mA IDD7 1,840 1,060 1,760 1,060 mA Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. M470T3354BG(Z)3/M470T3354BG(Z)0 : 32Mx64 256MB Module Symbol CD5 (DDR533@CL=4) LD5 (DDR533@CL=4) CCC (DDR400@CL=3) LCC (DDR400@CL=3) Unit IDD0 480 360 460 360 mA mA IDD1 580 460 500 420 IDD2P 32 32 32 32 mA IDD2Q 100 100 100 100 mA IDD2N 120 100 120 100 mA IDD3P-F 120 60 120 60 mA IDD3P-S 60 60 60 60 mA IDD3N 280 160 260 160 mA IDD4W 920 600 740 520 mA IDD4R 820 600 680 520 mA IDD5B 780 760 740 760 mA IDD6 22 20 22 20 mA IDD7 1,560 960 1,500 960 mA Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Operating Current Table(1-2) (TA=0oC, VDD= 1.9V) M470T2953BS(Y)3/M470T2953BS(Y)0 : 128Mx64 1GB Module Symbol CD5 (DDR533@CL=4) LD5 (DDR533@CL=4) CCC (DDR400@CL=3) LCC (DDR400@CL=3) Unit IDD0 1,360 760 1,280 760 mA IDD1 1,440 920 1,320 840 mA IDD2P 128 128 128 128 mA IDD2Q 400 400 400 400 mA IDD2N 480 400 480 400 mA IDD3P-F 480 240 480 240 mA IDD3P-S 240 240 240 240 mA IDD3N 1,120 520 1,040 520 mA IDD4W 2,160 1,160 1,680 1,000 mA IDD4R 2,000 1,160 1,680 1,000 mA IDD5B 2,120 1,720 2,000 1,720 mA IDD6 88 80 88 80 mA IDD7 2,760 1,960 2,680 1,960 mA Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC) Parameter Non-ECC Min Symbol Input capacitance, CK and CK Input capacitance, CKE , CS, Addr, RAS, CAS, WE Input/output capacitance, DQ, DM, DQS, DQS Max M470T6554BG(Z)3 M470T6554BG(Z)0 Min Max M470T3354BG(Z)3 M470T3354BG(Z)0 Min Max M470T2953BS(Y)3 M470T2953BS(Y)0 CCK - 32 - 24 - 48 CI - 34 - 34 - 42 CIO - 10 - 6 - 10 Units pF * DM is internally loaded to match DQ and DQS identically. Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM (0 °C < TCASE < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V) Refresh Parameters by Device Density Parameter Symbol Refresh to active/Refresh command time tRFC Average periodic refresh interval tREFI 256Mb 512Mb 1Gb 2Gb 4Gb Units 75 105 127.5 195 tbd ns 0 °C ≤ TCASE ≤ 85°C 7.8 7.8 7.8 7.8 7.8 µs 85 °C < TCASE ≤ 95°C 3.9 3.9 3.9 3.9 3.9 µs Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin Speed DDR2-533(D5) Bin (CL - tRCD - tRP) Parameter DDR2-400(CC) 4-4-4 3-3-3 Units min max min max tCK, CL=3 5 8 5 8 ns tCK, CL=4 3.75 8 5 8 ns - - - - ns tCK, CL=5 tRCD 15 15 ns tRP 15 15 ns tRC 55 55 ns tRAS 40 70000 40 70000 ns Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Parameter Symbol DDR2-533 DDR2-400 min max min max Units DQ output access time from CK/CK tAC -500 +500 -600 +600 ps DQS output access time from CK/CK tDQSCK -450 +450 -500 +500 ps CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK CK half period tHP min(tCL, tCH) x min(tCL, tCH) x ps Clock cycle time, CL=x tCK 3750 8000 5000 8000 ps DQ and DM input hold time tDH 225 x 275 x ps DQ and DM input setup time tDS 100 x 150 x ps Control & Address input pulse width for each input tIPW 0.6 x 0.6 x tCK DQ and DM input pulse width for each input tDIPW 0.35 x 0.35 x tCK Data-out high-impedance time from CK/CK tHZ DQS low-impedance time from CK/CK tLZ(DQS) DQ low-impedance time from CK/CK x tAC max x tAC max ps tAC min tAC max tAC min tAC max ps tLZ(DQ) 2* tACmin tAC max 2* tACmin tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ x 300 x 350 ps DQ hold skew factor tQHS x 400 x 450 ps DQ/DQS output hold time from DQS tQH tHP - tQHS x tHP - tQHS x ps Write command to first DQS latching transition tDQSS WL-0.25 WL+0.25 WL-0.25 WL+0.25 tCK DQS input high pulse width tDQSH 0.35 x 0.35 x tCK DQS input low pulse width tDQSL 0.35 x 0.35 x tCK DQS falling edge to CK setup time tDSS 0.2 x 0.2 x tCK DQS falling edge hold time from CK tDSH 0.2 x 0.2 x tCK Mode register set command cycle time tMRD 2 x 2 x tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write preamble tWPRE 0.35 x 0.35 x tCK Address and control input hold time tIH 375 x 475 x ps Address and control input setup time tIS 250 x 350 x ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Active to active command period for 1KB page size products tRRD 7.5 x 7.5 x ns Active to active command period for 2KB page size products tRRD 10 x 10 x ns Four Activate Window for 1KB page size products tFAW 37.5 37.5 Four Activate Window for 2KB page size products tFAW 50 50 ns CAS to CAS command delay tCCD 2 2 tCK Write recovery time tWR 15 x 15 x ns Auto precharge write recovery + precharge time tDAL tWR+tRP x tWR+tRP x tCK Internal write to read command delay tWTR 7.5 x 10 x ns Internal read to precharge command delay tRTP 7.5 7.5 Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns Exit self refresh to a read command tXSRD 200 200 tCK Exit precharge power down to any non-read command tXP 2 x 2 x tCK Exit active power down to read command tXARD 2 x 2 x tCK Exit active power down to read command (Slow exit, Lower power) tXARDS 6 - AL 6 - AL Notes ns ns tCK Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs Parameter Symbol CKE minimum pulse width (high and low pulse width) tCKE ODT turn-on delay tAOND ODT turn-on tAON ODT turn-on(Power-Down mode) tAONPD ODT turn-off delay tAOFD DDR2 SDRAM DDR2-533 min DDR2-400 max 3 min max 3 Units tCK 2 2 2 2 tCK tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns tAC(min)+2 2tCK+tAC( max)+1 tAC(min)+2 2tCK+tAC (max)+1 ns 2.5 2.5 2.5 2.5 tCK tAC(min) tAC(max)+ 0.6 tAC(min) tAC(max)+ 0.6 ns 2.5tCK+ tAC(max)+1 ns ODT turn-off tAOF ODT turn-off (Power-Down mode) tAOFPD ODT to power down entry latency tANPD 3 3 tCK ODT power down exit latency tAXPD 8 8 tCK OCD drive mode output delay tOIT 0 Minimum time clocks remains ON after CKE asynchronously tDelay drops LOW tAC(min)+2 tIS+tCK +tIH 2.5tCK+ tAC(min)+2 tAC(max)+1 12 0 tIS+tCK +tIH Notes 12 ns ns Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Physical Dimensions: 32Mbx16 based 64Mx64 Module(2 Rank) M470T6554BG(Z)3/M470T6554BG(Z)0 67.60 mm 3.8 mm Max a 1 b 11.40 199 30.00 20.00 4.00 ± 0.10 6.00 2.00 1.1 mm Max 47.40 16.25 63.00 2 200 30.00 SPD a 67.60 mm DETAIL a BACK SIDE FRONT SIDE 4.00 ± 0.10 1.0 ± 0.05 1.0 ± 0.05 2.55 1.50 ± 0.10 1.80 ± 0.10 4.00 ± 0.10 0.20 ± 0.15 4.20 2.70 ± 0.10 DETAIL b 2.40 ± 0.10 4.20 0.60 0.45 ± 0.03 The used device is 32M x16 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51163QB Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Physical Dimensions: 32Mbx16 based 32Mx64 Module(1 Rank) M470T3354BG(Z)3/M470T3354BG(Z)0 67.60 mm 2.45 mm Max a 1 b 11.40 199 30.00 20.00 4.00 ± 0.10 6.00 SPD 2.00 47.40 1.1 mm Max 16.25 63.00 2 200 30.00 a 67.60 mm DETAIL a BACK SIDE FRONT SIDE 4.00 ± 0.10 1.0 ± 0.05 1.0 ± 0.05 2.55 1.50 ± 0.10 1.80 ± 0.10 4.00 ± 0.10 0.20 ± 0.15 4.20 2.70 ± 0.10 DETAIL b 2.40 ± 0.10 4.20 0.60 0.45 ± 0.03 The used device is 32M x16 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51163QB Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Physical Dimensions: 64Mbx8 based 128Mx64 Module(2 Ranks) M470T2953BS(Y)3/M470T2953BS(Y)0 67.60 mm 3.8 mm max 2.00 a 1 b 11.40 199 30.00 20.00 4.00 ± 0.10 6.00 SPD 47.40 16.25 1.1mm max 63.00 2 200 30.00 a 67.60 mm DETAIL a BACK SIDE FRONT SIDE 4.00 ± 0.10 1.0 ± 0.05 1.0 ± 0.05 2.55 1.50 ± 0.10 1.80 ± 0.10 4.00 ± 0.10 0.20 ± 0.15 4.20 2.70 ± 0.10 DETAIL b 2.40 ± 0.10 4.20 0.60 0.45 ± 0.03 The used device is 64M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QB Rev. 1.5 Aug. 2005 256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM Revision History Revision 1.0 (Jan. 2004) - Initial Release Revision 1.1 (Jun. 2004) - Added lead-free part number in the ordering information - Changed IDD2P Revision 1.2 (Jul. 2004) - Added current values and part number of low power product Revision 1.3 (Feb. 2005) - Added the detail information for mechanical dimension Revision 1.4 (Mar. 2005) - Changed 1GB Functional Block Diagram Revision 1.5 (Aug. 2005) - Changed the IDD Specification Parameters Definition Rev. 1.5 Aug. 2005