OPA129 OPA OPA 129 129 SBOS026A – JANUARY 1994 – REVISED APRIL 2007 Ultra-Low Bias Current Difet® OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● ● ● ULTRA-LOW BIAS CURRENT: 100fA max LOW OFFSET: 2mV max LOW DRIFT: 10µV/°C max HIGH OPEN-LOOP GAIN: 94dB min LOW NOISE: 15nV/√Hz at 10kHz PLASTIC DIP AND SO PACKAGES PHOTODETECTOR PREAMPS CHROMATOGRAPHY ELECTROMETER AMPLIFIERS MASS SPECTROMETERS pH PROBE AMPLIFIERS ION GAGE MEASUREMENT Substrate DESCRIPTION 8 The OPA129 is an ultra-low bias current monolithic operational amplifier offered in an 8-pin PDIP and SO-8 package. Using advanced geometry dielectrically-isolated FET (Difet®) inputs, this monolithic amplifier achieves a high performance level. Difet fabrication eliminates isolation-junction leakage current—the main contributor to input bias current with conventional monolithic FETs. This reduces input bias current by a factor of 10 to 100. Very low input bias current can be achieved without resorting to small-geometry FETs or CMOS designs which can suffer from much larger offset voltage, voltage noise, drift, and poor power-supply rejection. The OPA129 special pinout eliminates leakage current that occurs with other op amps. Pins 1 and 4 have no internal connection, allowing circuit board guard traces— even with the surface-mount package version. OPA129 is available in 8-pin DIP and SO packages, specified for operation from –40°C to +85°C. 7 V+ –In 2 3 +In Noise-Free Cascode 6 Output 30kΩ 30kΩ 5 V– Simplified Circuit Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Difet is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright © 1994–2007, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com SPECIFICATIONS ELECTRICAL At VS = ±15V and TA = +25°C, unless otherwise noted. Pin 8 connected to ground. OPA129PB, UB PARAMETER CONDITION MIN TYP OPA129P, U MAX MIN ±30 ±100 Doubles every 10°C TYP MAX UNITS * * ±250 fA INPUT BIAS CURRENT(1) vs Temperature VCM = 0V INPUT OFFSET CURRENT VCM = 0V ±30 VCM = 0V VS = ±5V to ±18V ±0.5 ±3 ±3 f = 10Hz f = 100Hz f = 1kHz f = 10kHz fB = 0.1Hz to 10Hz f = 10kHz 85 28 17 15 4 0.1 * * * * * * nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVPP fA/√Hz 1013 || 1 1015 || 2 * * Ω || pF Ω || pF OFFSET VOLTAGE Input Offset Voltage vs Temperature Supply Rejection NOISE Voltage Current INPUT IMPEDANCE Differential Common-Mode VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate Settling Time: 0.1% 0.01% Overload Recovery, 50% Overdrive(2) RATED OUTPUT Voltage Output Current Output Load Capacitance Stability Short-Circuit Current POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent TEMPERATURE Specification Operating Storage Thermal Resistance DIP-8 SO-8 * ±2 ±10 ±100 ±1 ±5 * fA ±5 * mV µV/°C µV/V VIN = ±10V ±10 80 ±12 118 * * * * V dB RL ≥ 2kΩ 94 120 * * dB 1 1 47 2.5 * * * * MHz kHz V/µs * * * µs µs µs * * * * * V mA pF mA * * V V mA * * * °C °C °C 20Vp-p, RL = 2kΩ VO = ±10V, RL = 2kΩ G = –1, RL = 2kΩ, 10V Step 5 10 5 G = –1 RL = 2kΩ VO = ±12V Gain = +1 ±12 ±6 ±5 IO = 0mA Ambient Temperature Ambient Temperature ±13 ±10 1000 ±35 ±15 1.2 –40 –40 –40 * * ±55 * ±18 1.8 * +85 +125 +125 * * * * θJA, Junction-to-Ambient 90 100 * * °C/W °C/W NOTES: (1) High-speed automated test. (2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. 2 OPA129 www.ti.com SBOS026A PACKAGE INFORMATION(1) ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ...................................................................... ±18V Differential Input Voltage ............................................................ V– to V+ Input Voltage Range .................................................................... V– to V+ Storage Temperature Range ......................................... –40°C to +125°C Operating Temperature Range ...................................... –40°C to +125°C Output Short Circuit Duration(1) .................................................................. Continuous Junction Temperature (TJ) ............................................................ +150°C PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA129P OPA129PB OPA129U OPA129UB DIP-8 DIP-8 SO-8 SO-8 P P D D NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com. NOTE: (1) Short circuit may be to power supply common at +25°C ambient. CONNECTION DIAGRAM ELECTROSTATIC DISCHARGE SENSITIVITY Top View Any integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. DIP/SO NC 1 –In 2 8 Substrate 7 V+ OPA +In 3 6 Output NC 4 5 V– NC: No internal connection. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. TYPICAL PERFORMANCE CURVES At TA = +25°C, +15VDC, unless otherwise noted. OPEN-LOOP FREQUENCY RESPONSE POWER SUPPLY REJECTION vs FREQUENCY 140 45 Gain 100 θ 80 Phase Margin ≈90° 60 40 90 135 20 0 Pulse Shift (degrees) Voltage Gain (dB) 120 Power Supply Rejection (dB) 140 180 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 100 80 +PSRR 60 –PSRR 40 20 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) OPA129 SBOS026A 120 www.ti.com 3 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, +15VDC, unless otherwise noted. COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE COMMON-MODE REJECTION vs FREQUENCY 140 Common-Mode Rejection (dB) Common-Mode Rejection (dB) 120 110 100 90 80 120 100 80 60 40 20 0 70 15 10 5 0 10 5 1 15 10k 100k 1M BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 10M 10 Normalized Bias and Offset Current Bias and Offset Current (fA) 1k BIAS AND OFFSET CURRENT vs TEMPERATURE 10pA 1pA IB and IOS 100 10 1 1 0.1 0.01 –50 –25 0 25 50 75 100 125 –15 Ambient Temperature (°C) –10 –5 5 0 10 15 Common-Mode Voltage (V) FULL-POWER OUTPUT vs FREQUENCY INPUT VOLTAGE NOISE SPECTRAL DENSITY 30 Output Voltage (VPP) 1k Voltage Density (nV/√Hz) 100 Frequency (Hz) 100pA 100 20 10 0 10 1 10 100 1k 10k 100k 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) 4 10 Common-Mode Voltage (V) OPA129 www.ti.com SBOS026A TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, +15VDC, unless otherwise noted. 3 3 2 2 1 Gain Bandwidth (MHz) 4 Slew Rate (V/µs) Gain Bandwidth (MHz) 4 1 0 –50 –25 0 25 50 75 100 6 2 4 +Slew –Slew 1 0 0 125 5 10 Ambient Temperature (°C) 15 20 Supply Voltage (±VCC) SUPPLY CURRENT vs TEMPERATURE OPEN-LOOP GAIN, PSR AND CMR vs TEMPERATURE 2.0 130 PSR, CMR, Voltage Gain (dB) Supply Current (mA) 2 GBW 0 0 –75 3 Slew Rate (v/µs) GAIN BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE 1.5 1.0 0.5 0 120 A OL CMR 110 100 PSR 90 –75 –50 –25 0 25 50 75 100 125 –75 –50 Ambient Temperature (°C) –25 0 25 50 75 100 125 Ambient Temperature (°C) SMALL SIGNAL TRANSIENT RESPONSE LARGE SIGNAL TRANSIENT RESPONSE 10 Output Voltage (mV) Output Voltage (V) 80 0 –10 5V 0 5µs 25 0 –40 0 50 1µs 20mV –80 2 4 6 8 10 Time (µs) Time (µs) OPA129 SBOS026A 40 www.ti.com 5 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, +15VDC, unless otherwise noted. COMMON-MODE INPUT RANGE vs SUPPLY VOLTAGE BIAS CURRENT vs ADDITIONAL POWER DISSIPATION 100pA 10pA Bias Current (fA) Common-Mode Voltage (+V) 15 10 5 100 10 0 1 0 5 10 15 20 0 APPLICATIONS INFORMATION NON-STANDARD PINOUT The OPA129 uses a non-standard pinout to achieve lowest possible input bias current. The negative power supply is connected to pin 5—see Figure 1. This is done to reduce the leakage current from the V- supply (pin 4 on conventional op amps) to the op amp input terminals. With this new pinout, sensitive inputs are separated from both power supply pins. RF V+ RIN VIN 2 3 7 OPA129 6 VOUT 5 V+ V– 470kΩ 220Ω 50 100 150 200 250 300 350 Additional Power Dissipation (mW) Supply Voltage (±VCC) 470kΩ 0.1µF V– FIGURE 1. Offset Adjust Circuit. OFFSET VOLTAGE TRIM The OPA129 has no conventional offset trim connections. Pin 1, next to the critical inverting input, has no internal connection. This eliminates a source of leakage current and allows guarding of the input terminals. Pin 1 and pin 4, next to the two input pins, have no internal connection. This allows an optimized circuit board layout with guarding—see the Circuit Board Layout section. 6 1pA Due to its laser-trimmed input stage, most applications do not require external offset voltage trimming. If trimming is required, the circuit shown in Figure 1 can be used. Power supply voltages are divided down, filtered and applied to the non-inverting input. The circuit shown is sensitive to variation in the supply voltages. Regulation can be added, if needed. GUARDING AND SHIELDING Ultra-low input bias current op amps require precautions to achieve best performance. Leakage current on the surface of circuit board can exceed the input bias current of the amplifier. For example, a circuit board resistance of 1012Ω from a power supply pin to an input pin produces a current of 15pA—more than 100 times the input bias current of the op amp. To minimize surface leakage, a guard trace should completely surround the input terminals and other circuitry connecting to the inputs of the op amp. The DIP package should have a guard trace on both sides of the circuit board. The guard ring should be driven by a circuit node equal in potential to the op amp inputs—see Figure 2. The substrate, pin 8, should also be connected to the circuit board guard to assure that the amplifier is fully surrounded by the guard potential. This minimizes leakage current and noise pick-up. Careful shielding is required to reduce noise pickup. Shielding near feedback components may also help reduce noise pick-up. Triboelectric effects (friction-generated charge) can be a troublesome source of errors. Vibration of the circuit board, input connectors and input cables can cause noise and drift. Make the assembly as rigid as possible. Attach cables to avoid motion and vibration. Special low noise or low leakage cables may help reduce noise and leakage current. Keep all input connections as short possible. Surface-mount components may reduce circuit board size and allow a more rigid assembly. OPA129 www.ti.com SBOS026A CIRCUIT BOARD LAYOUT The OPA129 uses a new pinout for ultra low input bias current. Pin 1 and pin 4 have no internal connection. This allows ample circuit board space for a guard ring surrounding the op amp input pins—even with the tiny SO-8 surfacemount package. Figure 3 shows suggested circuit board layouts. The guard ring should be connected to pin 8 (substrate) as shown. It should be driven by a circuit node equal in potential to the input terminals of the op amp—see Figure 2 for common circuit configurations. TESTING Accurately testing the OPA129 is extremely difficult due to its high performance. Ordinary test equipment may not be able to resolve the amplifier’s extremely low bias current. Inaccurate bias current measurements can be due to: 1. Test socket leakage. 2. Unclean package. 3. Humidity or dew point condensations. 4. Circuit contamination from fingerprints or anti-static treatment chemicals. 5. Test ambient temperature. 6. Load power dissipation. 7. Mechanical stress. 8. Electrostatic and electromagnetic interference. (A) Non-Inverting RF 2 6 Out 2 Current Input 3 7 6 OPA129 Output 5 8 VO = –IIN • RF VO = –10V/nA V– FIGURE 4. Current-to-Voltage Converter. 500Ω 9.5kΩ V+ Guard 8 2 7 6 OPA129 3 1VDC Output 5 V– pH Probe RS ≈ 500MΩ 50mV Out FIGURE 5. High Impedance (1015Ω) Amplifier. 1011Ω RF 8 3 V+ Out 8 2 In In 18kΩ CF 10pF 6 3 2kΩ V+ IIN (B) Buffer 8 2 1000MΩ (C) Inverting ∆Q 3 7 Output 6 OPA129 VOUT 5 In Low frequency cutoff = V– 1/(2πR C ) = 0.16Hz F F 2 6 Out 3 VOUT = –∆Q/CF 8 FIGURE 6. Piezoelectric Transducer Charge Amplifier. Guard top and bottom of board. ~1pF to prevent gain peaking FIGURE 2. Connection of Input Guard. 1 8 V+ V0 1010 Ω Connect to proper circuit node, depending on circuit configuration (see Figure 2). 4 5 2 (A) DIP package 1 8 V0 5 3 Connect to proper circuit node, depending on circuit configuration (see Figure 2). 0.1µF V– FIGURE 3. Suggested Board Layout for Input Guard. OPA129 6 5 0.1µF Output 5 x 109V/W –15V (B) SOIC package Circuit must be well shielded. FIGURE 7. Sensitive Photodiode Amplifier. OPA129 SBOS026A 8 7 V+ 4 +15V Guard Pin photodiode HP 5082-4204 V– www.ti.com 7 PACKAGE OPTION ADDENDUM www.ti.com 24-Feb-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) OPA129P OBSOLETE PDIP P 8 TBD Call TI Call TI OPA129PB OBSOLETE PDIP P 8 TBD Call TI Call TI OPA129U ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UB ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UB/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UB/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UBE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UBG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA129UE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device OPA129UB/2K5 Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA129UB/2K5 SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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