STMicroelectronics LIS331DL Mems motion sensor 3-axis - â±2g/â±8g smart digital output -nano-accelerometer Datasheet

LIS331DL
MEMS motion sensor
3-axis - ±2g/±8g smart digital output “nano” accelerometer
Features
■
2.16 V to 3.6 V supply voltage
■
1.8 V compatible IOs
■
<1 mW power consumption
■
±2g / ±8g dynamically selectable full-scale
■
I2C/SPI digital output interface
■
Programmable interrupt generator
■
Embedded click and double click recognition
■
Embedded free-fall and motion detection
■
Embedded high pass filter
■
Embedded self test
■
10000 g high shock survivability
■
ECOPACK® RoHS
process developed by ST to produce inertial
sensors and actuators in silicon.
and “Green” compliant
(see Section 9)
The IC interface is manufactured using a CMOS
process that allows to design a dedicated circuit
which is trimmed to better match the sensing
element characteristics.
The LIS331DL has dynamically user selectable
full scales of ±2g/±8g and it is capable of
measuring accelerations with an output data rate
of 100 Hz or 400 Hz.
Applications
■
Free-Fall detection
■
Motion activated functions
■
Gaming and virtual reality input devices
■
Vibration monitoring and compensation
Description
The LIS331DL, belonging to the “nano” family of
ST motion sensors, is the smallest consumer lowpower three axes linear accelerometer. The
device features digital I2C/SPI serial interface
standard output and smart embedded functions.
The sensing element, capable of detecting the
acceleration, is manufactured using a dedicated
Table 1.
LGA 16 (3x3x1 mm)
A self-test capability allows the user to check the
functioning of the sensor in the final application.
The device may be configured to generate inertial
wake-up/free-fall interrupt signals when a
programmable acceleration threshold is crossed
at least in one of the three axes. Thresholds and
timing of interrupt generators are programmable
by the end user on the fly.
The LIS331DL is available in plastic Land Grid
Array package (LGA) and it is guaranteed to
operate over an extended temperature range from
-40 °C to +85 °C.
Device summary
Order code
Temp range [°C]
Package
Packing
LIS331DL
-40 to +85
LGA
Tray
LIS331DLTR
-40 to +85
LGA
Tape and reel
April 2008
Rev 3
1/42
www.st.com
42
Contents
LIS331DL
Contents
1
2
3
4
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2
I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.2
Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.3
Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.4
Click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
5
2.3.1
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1
5.2
2/42
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.1
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.2
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.3
SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
LIS331DL
Contents
6
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
7.1
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2
CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3
CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4
CTRL_REG3 [interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 26
7.5
HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.6
STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.7
OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8
OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.9
OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.10
FF_WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.11
FF_WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.12
FF_WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.13
FF_WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.14
FF_WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.15
FF_WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.16
FF_WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.17
FF_WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.18
CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.19
CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.20
CLICK_THSY_X (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.21
CLICK_THSZ (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.22
CLICK_TimeLimit (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.23
CLICK_Latency (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.24
CLICK_Window (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1
Mechanical characteristics at 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2
Mechanical characteristics derived from measurement in the -40 °C to +85
°C temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.3
Electrical characteristics at 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3/42
Contents
LIS331DL
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4/42
LIS331DL
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C slave timing diagram (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LIS331DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
X axis Zero-g level at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
X axis Sensitivity at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Y axis Zero-g level at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Y axis Sensitivity at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Z axis Zero-g level at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Z axis Sensitivity at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
X axis Zero-g level change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
X axis Sensitivity change vs. temperature at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Y axis Zero-g level change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Y axis Sensitivity change vs. temperature at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Z axis Zero-g level change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Z axis Sensitivity change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Current consumption in normal mode at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
LGA 16: Mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5/42
List of tables
LIS331DL
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
6/42
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mechanical characteristics @ Vdd=2.5 V, T= 25 °C unless otherwise noted . . . . . . . . . . . . 7
Electrical characteristics @ Vdd=2.5 V, T= 25 °C unless otherwise noted. . . . . . . . . . . . . . 8
SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 17
Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 17
Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
High pass filter cut-off frequency configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data Signal on INT1(2) pad control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
OUT_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
OUT_Y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
OUT_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FF_WU_CFG_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FF_WU_CFG_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FF_WU_SRC_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FF_WU_SRC_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FF_WU_THS_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FF_WU_THS_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FF_WU_DURATION_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FF_WU_DURATION_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FF_WU_CFG_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FF_WU_CFG_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FF_WU_SRC_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FF_WU_SRC_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FF_WU_THS_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FF_WU_THS_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FF_WU_DURATION_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FF_WU_DURATION_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CLICK_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CLICK_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Click interrupt configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LIS331DL
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
List of tables
CLICK_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CLICK_THSY_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CLICK_THSY_X description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CLICK_THSZ register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CLICK_THSZ description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CLICK_TimeLimit register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CLICK_Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CLICK_Window register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7/42
Block diagram and pin description
LIS331DL
1
Block diagram and pin description
1.1
Block diagram
Figure 1.
Block diagram
X+
Y+
CHARGE
AMPLIFIER
Z+
a
MUX
CS
SCL/SPC
I2C
A/D
CONVERTER
CONTROL LOGIC
SDA/SDO/SDI
SPI
Z-
SDO
YX-
SELF TEST
1.2
REFERENCE
TRIMMING
CIRCUITS
CONTROL LOGIC
CLOCK
Pin description
Figure 2.
Pin connection
Z
X
1
1
13
9
Y
5
(TOP VIEW)
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
8/42
INT 1
&
INTERRUPT GEN.
(BOTTOM VIEW)
INT 2
LIS331DL
Block diagram and pin description
Table 2.
Pin description
Pin#
Name
Function
1
Vdd_IO
Power supply for I/O pins
2
NC
Internally Not Connected
3
NC
Internally Not Connected
4
SCL
SPC
I2C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
5
GND
0V supply
6
SDA
SDI
SDO
I2C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
7
SDO
SA0
SPI Serial Data Output (SDO)
I2C less significant bit of the device address (SA0)
8
CS
9
INT 2
Inertial interrupt 2
10
Reserved
Connect to GND
11
INT 1
Inertial interrupt 1
12
GND
0V supply
13
GND
0V supply
14
Vdd
Power supply
15
Reserved
16
GND
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
Connect to Vdd
0V supply
9/42
Mechanical and electrical specifications
LIS331DL
2
Mechanical and electrical specifications
2.1
Mechanical characteristics
Table 3.
Mechanical characteristics @ Vdd=2.5 V, T= 25 °C unless otherwise noted(1)
Symbol
FS
Measurement range(3)
So
Sensitivity
TCSo
Sensitivity change vs
temperature
TyOff
Typical zero-g level offset
accuracy(4),(5)
TCOff
NL
Vst
Min.
Typ.(2)
FS bit set to 0
±2.0
±2.3
FS bit set to 1
±8.0
±9.2
FS bit set to 0
16.2
18
19.8
FS bit set to 1
64.8
72
79.2
Parameter
Test conditions
Max.
Unit
g
mg/digit
FS bit set to 0
±0.01
%/°C
FS bit set to 0
±40
mg
FS bit set to 1
±60
mg
Zero-g level change vs
temperature
Max delta from 25 °C
±0.5
mg/°C
Non linearity
Best fit straight line
±0.5
% FS
Self test output
change(6),(7),(8)
BW
System bandwidth(9)
Top
Operating temperature range
Wh
Product weight
FS bit set to 0
STP bit used
X axis
-3
-19
-32
LSb
FS bit set to 0
STP bit used
Y axis
3
19
32
LSb
FS bit set to 0
STP bit used
Z axis
-3
-19
-32
LSb
ODR/2
-40
Hz
+85
20
°C
mgram
1. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.
2. Typical specifications are not guaranteed
3. Verified by wafer level test and measurement of initial offset and sensitivity
4. Typical zero-g level offset value after MSL3 preconditioning
5. Offset can be eliminated by enabling the built-in high pass filter
6. If STM bit is used values change in sign for all axes
7. Self Test output changes with the power supply. “Self test output change” is defined as OUTPUT[LSb](Self-test bit on CTRL_REG1=1)
-OUTPUT[LSb](Self-test bit on CTRL_REG1=0). 1LSb=4.6g/256 at 8bit representation, ±2.3 g Full-Scale
8. Output data reach 99% of final value after 3/ODR when enabling Self-Test mode due to device filtering
9. ODR is output data rate. Refer to Table 4 for specifications
10/42
LIS331DL
Mechanical and electrical specifications
2.2
Electrical characteristics
Table 4.
Electrical characteristics @ Vdd=2.5 V, T= 25 °C unless otherwise noted(1)
Symbol
Vdd
Vdd_IO
Idd
IddPdn
Min.
Typ.(2)
Max.
Unit
Supply voltage
2.16
2.5
3.6
V
I/O pins supply voltage(3)
1.71
Vdd+0.1
V
0.3
0.4
mA
1
5
µA
Parameter
Supply current
ODR=100 Hz
Current consumption in
power-down mode
VIH
Digital high level input voltage
VIL
Digital low level input voltage
VOH
High level output voltage
VOL
Low level output voltage
ODR
Output data rate
BW
Test conditions
0.8*Vdd_IO
0.2*Vdd_IO
0.9*Vdd_IO
DR=0
100
DR=1
400
Top
Operating temperature range
V
Hz
(5)
Turn-on time
V
V
0.1*Vdd_IO
System bandwidth(4)
Ton
V
ODR/2
Hz
3/ODR
s
-40
+85
°C
1. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.
2. Typical specification are not guaranteed
3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
4. Filter cut-off frequency
5. Time to obtain valid data after exiting Power-Down mode
11/42
Mechanical and electrical specifications
LIS331DL
2.3
Communication interface characteristics
2.3.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and top.
Table 5.
SPI slave timing values
Value(1)
Symbol
Parameter
Unit
Min
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
8
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
Max
100
ns
10
MHz
ns
50
6
SDO output disable time
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production
Figure 3.
CS
SPI slave timing diagram (2)
(3)
(3)
tc(SPC)
tsu(CS)
SPC
(3)
(3)
tsu(SI)
SDI
(3)
th(SI)
LSB IN
MSB IN
tv(SO)
SDO
th(CS)
(3)
tdis(SO)
th(SO)
MSB OUT
LSB OUT
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port
3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors
12/42
(3)
(3)
LIS331DL
Mechanical and electrical specifications
I2C - Inter IC control interface
2.3.2
Subject to general operating conditions for Vdd and top.
I2C slave timing values
Table 6.
I2C Standard mode(1)
Symbol
I2C Fast mode (1)
Parameter
f(SCL)
Unit
SCL clock frequency
Min
Max
Min
Max
0
100
0
400
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0(2)
KHz
µs
ns
3.45
0(2)
0.9
tr(SDA) tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb (3)
300
tf(SDA) tf(SCL)
SDA and SCL fall time
300
20 + 0.1Cb (3)
300
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
µs
ns
µs
tw(SP:SR)
Bus free time between STOP
and START condition
1. Data based on standard I2C protocol requirement, not tested in production
2. A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL
3. Cb = total capacitance of one bus line, in pF
Figure 4.
I2C slave timing diagram (4)
REPEATED
START
START
tsu(SR)
tw(SP:SR)
SDA
tf(SDA)
tsu(SDA)
tr(SDA)
START
th(SDA)
tsu(SP)
STOP
SCL
th(ST)
tw(SCLL)
tw(SCLH)
tr(SCL)
tf(SCL)
4. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports
13/42
Mechanical and electrical specifications
2.4
LIS331DL
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 7.
Absolute maximum ratings
Symbol
Vdd
Vdd_IO
Vin
Ratings
Maximum value
Unit
Supply voltage
-0.3 to 6
V
I/O pins Supply voltage
-0.3 to 6
V
-0.3 to Vdd_IO +0.3
V
Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO)
3000 g for 0.5 ms
APOW
Acceleration (any axis, powered, Vdd=2.5 V)
AUNP
Acceleration (any axis, unpowered)
TOP
Operating temperature range
-40 to +85
°C
TSTG
Storage temperature range
-40 to +125
°C
4 (HBM)
kV
1.5 (CDM)
kV
200 (MM)
V
10000 g for 0.1 ms
3000 g for 0.5 ms
ESD
Note:
10000 g for 0.1 ms
Electrostatic discharge protection
Supply voltage on any pin should never exceed 6.0 V
This is a mechanical shock sensitive device, improper handling can cause permanent
damages to the part
This is an ESD sensitive device, improper handling can cause permanent damages to
the part
14/42
LIS331DL
Mechanical and electrical specifications
2.5
Terminology
2.5.1
Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g
acceleration to it. As the sensor can measure DC accelerations this can be done easily by
pointing the axis of interest towards the center of the Earth, noting the output value, rotating
the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing
so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This
value changes very little over temperature and also over time. The Sensitivity Tolerance
describes the range of sensitivities of a large population of sensors.
2.5.2
Zero-g level
Zero-g level Offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in a steady state on a horizontal surface
will measure 0 g in X axis and 0 g in Y axis whereas the Z axis will measure 1 g. The output
is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h,
data expressed as 2’s complement number). A deviation from ideal value in this case is
called Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and
therefore the offset can slightly change after mounting the sensor onto a printed circuit
board or exposing it to extensive mechanical stress. Offset changes little over temperature,
see “Zero-g level change vs. temperature”. The Zero-g level tolerance (TyOff) describes the
Standard Deviation of the range of Zero-g levels of a population of sensors.
2.5.3
Self test
Self Test allows to check the sensor functionality without moving it. The self test function is
off when the self-test bit of CTRL_REG1 (control register 1) is programmed to ‘0‘. When the
self-test bit of ctrl_reg1 is programmed to ‘1‘ an actuation force is applied to the sensor,
simulating a definite input acceleration. In this case the sensor outputs will exhibit a change
in their DC levels which are related to the selected full scale through the device sensitivity.
When Self Test is activated, the device output level is given by the algebraic sum of the
signals produced by the acceleration acting on the sensor and by the electrostatic test-force.
If the output signals change within the amplitude specified inside Table 3, then the sensor is
working properly and the parameters of the interface chip are within the defined
specifications.
2.5.4
Click and double click recognition
The click and double click recognition functions help to create man-machine interface with
little software overload. The device can be configured to output an interrupt signal on
dedicated pin when tapped in any direction.
If the sensor is exposed to a single input stimulus it generates an interrupt request on inertial
interrupt pins (INT1 and/or INT2). A more advanced feature allows to generate an interrupt
request when a “double click” stimulus is applied. A programmable time between the two
events allows a flexible adaption to the application requirements. Mouse-button like
application, like clicks and double clicks, can be implemented.
This function can be fully programmed by the user in terms of expected amplitude and
timing of the stimuli.
15/42
Functionality
3
LIS331DL
Functionality
The LIS331DL is a nano, low-power, digital output 3-axis linear accelerometer packaged in
an LGA package. The complete device includes a sensing element and an IC interface able
to take the information from the sensing element and to provide a signal to the external
world through an I2C/SPI serial interface.
3.1
Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The
technology allows to carry out suspended silicon structures which are attached to the
substrate in a few points called anchors and are free to move in the direction of the sensed
acceleration. To be compatible with the traditional packaging techniques a cap is placed on
top of the sensing element to avoid blocking the moving parts during the moulding phase of
the plastic encapsulation.
When an acceleration is applied to the sensor the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half-bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the capacitor.
At steady state the nominal value of the capacitors are few pF and when an acceleration is
applied the maximum variation of the capacitive load is in the fF range.
3.2
IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which
converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is
finally available to the user by an analog-to-digital converter.
The acceleration data may be accessed through an I2C/SPI interface thus making the
device particularly suitable for direct interfacing with a microcontroller.
The LIS331DL features a Data-Ready signal (RDY) which indicates when a new set of
measured acceleration data is available thus simplifying data synchronization in the digital
system that uses the device.
The LIS331DL may also be configured to generate an inertial Wake-Up and Free-Fall
interrupt signal accordingly to a programmed acceleration event along the enabled axes.
Both Free-Fall and Wake-Up can be available simultaneously on two different pins.
3.3
Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff).
The trimming values are stored inside the device in a non volatile memory. Any time the
device is turned on, the trimming parameters are downloaded into the registers to be used
during the normal operation. This allows to use the device without further calibration.
16/42
LIS331DL
4
Application hints
Application hints
Figure 5.
LIS331DL electrical connection
Vdd
10µF
1
13
Vdd_IO
TOP VIEW
INT 1
100nF
INT 2
CS
SDO/SA0
9
SDA/SDI/SDO
SCL/SPC
5
GND
Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO
The device core is supplied through Vdd line while the I/O pads are supplied through
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be
placed as near as possible to the pin 14 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO
without blocking the communication bus, in this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the I2C/SPI interface.When using the I2C, CS must be tied high.
The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be
completely programmed by the user through the I2C/SPI interface.
4.1
Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is
qualified for soldering heat resistance according to JEDEC J-STD-020C.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendation are available at www.st.com/mems.
17/42
Digital interfaces
5
LIS331DL
Digital interfaces
The registers embedded inside the LIS331DL may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS
line must be tied high (i.e connected to Vdd_IO).
Table 8.
Serial interface pin description
Pin name
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
5.1
Pin description
I2C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
I2C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
I2C less significant bit of the device address (SA0)
I2C serial interface
The LIS331DL I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
Table 9.
Serial interface pin description
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor
embedded inside the LIS331DL. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the
normal mode.
18/42
LIS331DL
5.1.1
Digital interfaces
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LIS331DL is 001110xb. SDO/SA0 pad can be
used to modify less significant bit of the device address. If SDO pad is connected to voltage
supply LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is
‘0’ (address 0011100b). This solution permits to connect and address two different
accelerometers to the same I2C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the LIS331DL behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7
LSb represent the actual register address while the MSB enables address auto increment. If
the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented
to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(Write) the Master will transmit to the slave with direction unchanged. Table 10 explains how
the SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 10.
SAD+Read/Write patterns
Command
SAD[6:1]
SAD[0] = SDO/SA0
R/W
Read
001110
0
1
00111001 (39h)
Write
001110
0
0
00111000 (38h)
Read
001110
1
1
00111011 (3Bh)
Write
001110
1
0
00111010 (3Ah)
Table 11.
Transfer when Master is writing one byte to slave
Master
ST
SAD + W
Slave
Table 12.
Master
Slave
SAD+R/W
SUB
SAK
DATA
SAK
SP
SAK
Transfer when Master is writing multiple bytes to slave
ST
SAD + W
SUB
SAK
DATA
SAK
DATA
SAK
SP
SAK
19/42
Digital interfaces
LIS331DL
Table 13.
Master
Transfer when Master is receiving (reading) one byte of data from slave
ST
SAD + W
Slave
Table 14.
Master
SUB
SAK
SR
SAD + R
SAK
NMAK
SAK
SP
DATA
Transfer when Master is receiving (reading) multiple bytes of data from slave
ST SAD+W
Slave
SUB
SAK
SR SAD+R
SAK
MAK
SAK
DATA
MAK
DATA
NMAK
SP
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master Acknowledge and NMAK is No
Master Acknowledge.
5.2
SPI bus interface
The LIS331DL SPI is a bus slave. The SPI allows to write and read the registers of the
device.
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
Figure 6.
Read & write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the Serial Port Clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
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LIS331DL
Digital interfaces
Both the Read Register and Write Register commands are completed in 16 clock pulses or
in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just
before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address will be auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb
first).
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS
bit is 0 the address used to read/write data remains the same for every block. When MS bit
is 1 the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
5.2.1
SPI read
Figure 7.
SPI read protocol
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-... : data DO(...-8). Further data in multiple byte reading.
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Digital interfaces
LIS331DL
Figure 8.
Multiple bytes SPI read protocol (2 bytes example)
CS
SPC
SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8
5.2.2
SPI write
Figure 9.
SPI write protocol
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is
performed adding blocks of 8 clock pulses at the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
writing.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device
(MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writing.
Figure 10. Multiple bytes SPI write protocol (2 bytes example)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
22/42
LIS331DL
5.2.3
Digital interfaces
SPI read in 3-wires mode
3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in
CTRL_REG2.
Figure 11. SPI read protocol in 3-wires mode
CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI Read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
Multiple read command is also available in 3-wires mode.
23/42
Register mapping
6
LIS331DL
Register mapping
The table given below provides a listing of the 8 bit registers embedded in the device and
the related addresses:
Table 15.
Register address map
Register address
Name
Type
Default
Hex
Reserved (do not modify)
WHO_AM_I
00-0E
r
Reserved (do not modify)
Reserved
000 1111 00111011
10-1F
rw
20
010 0000 00000111
CTRL_REG2
rw
21
010 0001 00000000
CTRL_REG3
rw
22
010 0010 00000000
HP_FILTER_RESET
r
23
010 0011
dummy
24-26
r
27
010 0111 00000000
--
r
28
010 1000
OUT_X
r
29
010 1001
--
r
2A
010 1010
OUT_Y
r
2B
010 1011
--
r
2C
010 1100
OUT_Z
r
2D
010 1101
Not Used
output
Not Used
output
Not Used
output
2E-2F
Reserved
FF_WU_CFG_1
rw
30
011 0000 00000000
FF_WU_SRC_1(ack1)
r
31
011 0001 00000000
FF_WU_THS_1
rw
32
011 0010 00000000
FF_WU_DURATION_1
rw
33
011 0011 00000000
FF_WU_CFG_2
rw
34
011 0100 00000000
FF_WU_SRC_2 (ack2)
r
35
011 0101 00000000
FF_WU_THS_2
rw
36
011 0110 00000000
FF_WU_DURATION_2
rw
37
011 0111 00000000
CLICK_CFG
rw
38
011 1000 00000000
CLICK_SRC (ack)
r
39
011 1001 00000000
-CLICK_THSY_X
3A
rw
3B
Dummy register
Reserved
STATUS_REG
Reserved (do not modify)
Dummy register
Reserved
CTRL_REG1
Reserved (do not modify)
24/42
0F
Comment
Binary
Not Used
011 1011 00000000
LIS331DL
Register mapping
Table 15.
Register address map (continued)
Register address
Name
Type
Default
Hex
Comment
Binary
CLICK_THSZ
rw
3C
011 1100 00000000
CLICK_TimeLimit
rw
3D
011 1101 00000000
CLICK_Latency
rw
3E
011 1110 00000000
CLICK_Window
rw
3F
011 1111 00000000
Registers marked as “Reserved” must not be changed. The writing to those registers may
cause permanent damages to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered-up.
25/42
Register description
7
LIS331DL
Register description
The device contains a set of registers which are used to control its behavior and to retrieve
acceleration data. The registers address, made of 7 bits, is used to identify them and to
write the data through serial interface.
7.1
WHO_AM_I (0Fh)
Table 16.
0
WHO_AM_I register
0
1
1
1
0
1
1
Yen
Xen
Device identification register.
This register contains the device identifier that for LIS331DL is set to 3Bh.
7.2
CTRL_REG1 (20h)
Table 17.
DR
Table 18.
CTRL_REG1 register
PD
FS
STP
STM
Zen
CTRL_REG1 description
DR
Data rate selection. Default value: 0
(0: 100 Hz output data rate; 1: 400 Hz output data rate)
PD
Power Down Control. Default value: 0
(0: power down mode; 1: active mode)
FS
Full Scale selection. Default value: 0
(refer to Table 3 for typical full scale values)
STP, STM
Self Test Enable. Default value: 0
(0: normal mode; 1: self test P, M enabled)
Zen
Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)
Yen
Y axis enable. Default value: 1
(0: Y axis disabled; 1: Y axis enabled)
Xen
X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)
DR bit allows to select the data rate at which acceleration samples are produced. The
default value is 0 which corresponds to a data-rate of 100 Hz. By changing the content of
DR to “1” the selected data-rate will be set equal to 400 Hz.
PD bit allows to turn the device out of power-down mode. The device is in power-down
mode when PD= ‘0’ (default value after boot). The device is in normal mode when PD is set
to ‘1’.
STP, STM bits are used to activate the self test function. When the bit is set to one, an
output change will occur to the device outputs (refer to Table 3 and 4 for specifications) thus
allowing to check the functionality of the whole measurement chain.
26/42
LIS331DL
Register description
Zen bit enables the generation of Data Ready signal for Z-axis measurement channel when
set to 1. The default value is 1.
Yen bit enables the generation of Data Ready signal for Y-axis measurement channel when
set to 1. The default value is 1.
Xen bit enables the generation of Data Ready signal for X-axis measurement channel when
set to 1. The default value is 1.
7.3
CTRL_REG2 (21h)
Table 19.
SIM
CTRL_REG2 register
BOOT
0(1)
FDS
HP
FF_WU2
HP
FF_WU1
HPcoeff2
HPcoeff1
1. Bit to be kept to “0” for correct device functionality
Table 20.
CTRL_REG2 description
SIM
SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
BOOT
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
FDS
Filtered Data Selection. Default value: 0
(0: internal filter bypassed; 1: data from internal filter sent to output register)
HP
FF_WU2
High Pass filter enabled for Free-Fall/WakeUp # 2. Default value: 0
(0: filter bypassed; 1: filter enabled)
HP
FF_WU1
High Pass filter enabled for Free-Fall/Wake-Up #1. Default value: 0
(0: filter bypassed; 1: filter enabled)
HPcoeff2
HPcoeff1
High pass filter cut-off frequency configuration. Default value: 00
(See Table 21)
SIM bit selects the SPI Serial Interface Mode. When SIM is ‘0’ (default value) the 4-wire
interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire
interface mode output data are sent to SDA_SDI pad.
BOOT bit is used to refresh the content of internal registers stored in the flash memory
block. At the device power up the content of the flash memory block is transferred to the
internal registers related to trimming functions to permit a good behavior of the device itself.
If for any reason the content of trimming registers was changed it is sufficient to use this bit
to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied
inside corresponding internal registers and it is used to calibrate the device. These values
are factory trimmed and they are different for every accelerometer. They permit a good
behavior of the device and normally they have not to be changed. At the end of the boot
process the BOOT bit is set again to ‘0’.
FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the
sensor
HPcoeff[2:1]. These bits are used to configure high-pass filter cut-off frequency ft.
27/42
Register description
LIS331DL
Table 21.
High pass filter cut-off frequency configuration
ft (Hz)
ft (Hz)
(ODR=100 Hz)
(ODR=400 Hz)
00
2
8
01
1
4
10
0.5
2
11
0.25
1
HPcoeff2,1
7.4
CTRL_REG3 [interrupt CTRL register] (22h)
Table 22.
IHL
PP_OD
Table 23.
I2_CFG2
I2_CFG1
I2_CFG0
I1_CFG2
I1_CFG1
I1_CFG0
CTRL_REG3 description
IHL
Interrupt active high, low. Default value 0.
(0: active high; 1: active low)
PP_OD
Push-pull/Open Drain selection on interrupt pad. Default value 0.
(0: push-pull; 1: open drain)
I2_CFG2
I2_CFG1
I2_CFG0
Data signal on INT2 pad control bits. Default value 000.
(see table below)
I1_CFG2
I1_CFG1
I1_CFG0
Data signal on INT1 pad control bits. Default value 000.
(see table below)
Table 24.
7.5
CTRL_REG3 register
Data Signal on INT1(2) pad control bits
I1(2)_CFG2
I1(2)_CFG1
I1(2)_CFG0
INT 1(2) Pad
0
0
0
GND
0
0
1
FF_WU_1
0
1
0
FF_WU_2
0
1
1
FF_WU_1 OR FF_WU_2
1
0
0
Data ready
1
1
1
Click interrupt
HP_FILTER_RESET (23h)
Dummy register. Reading at this address zeroes instantaneously the content of the internal
high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0 g.
This allows to overcome the settling time of the high pass filter.
28/42
LIS331DL
7.6
Register description
STATUS_REG (27h)
Table 25.
ZYXOR
Table 26.
7.7
STATUS_REG register
ZOR
YOR
XOR
ZYXDA
ZDA
YDA
XDA
STATUS_REG description
ZYXOR
X, Y, Z axis Data Overrun. Default value: 0
(0: no overrun has occurred;
1: new data has overwritten the previous one before it was read)
ZOR
Z axis Data Overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the Z-axis has overwritten the previous one)
YOR
Y axis Data Overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the Y-axis has overwritten the previous one)
XOR
X axis Data Overrun. Default value: 0
(0: no overrun has occurred;
1: a new data for the X-axis has overwritten the previous one)
ZYXDA
X, Y and Z axis new Data Available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available)
ZDA
Z axis new Data Available. Default value: 0
(0: a new data for the Z-axis is not yet available;
1: a new data for the Z-axis is available)
YDA
Y axis new Data Available. Default value: 0
(0: a new data for the Y-axis is not yet available;
1: a new data for the Y-axis is available)
XDA
X axis new Data Available. Default value: 0
(0: a new data for the X-axis is not yet available;
1: a new data for the X-axis is available)
OUT_X (29h)
Table 27.
XD7
OUT_X register
XD6
XD5
XD4
XD3
XD2
XD1
XD0
YD2
YD1
YD0
X axis output data expressed as 2’s complement number.
7.8
OUT_Y (2Bh)
Table 28.
YD7
OUT_Y register
YD6
YD5
YD4
YD3
Y axis output data expressed as 2’s complement number.
29/42
Register description
7.9
LIS331DL
OUT_Z (2Dh)
Table 29.
ZD7
OUT_Z register
ZD6
ZD5
ZD4
ZD3
ZD2
ZD1
ZD0
YLIE
XHIE
XLIE
Z axis output data expressed as 2’s complement number.
7.10
FF_WU_CFG_1 (30h)
Table 30.
AOI
Table 31.
30/42
FF_WU_CFG_1 register
LIR
ZHIE
ZLIE
YHIE
FF_WU_CFG_1 description
AOI
And/Or combination of Interrupt events. Default value: 0
(0: OR combination of interrupt events; 1: AND combination of interrupt events)
LIR
Latch Interrupt request into FF_WU_SRC_1 reg with the FF_WU_SRC_1 reg cleared
by reading FF_WU_SRC_1 reg. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
ZHIE
Enable interrupt generation on Z High event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
ZLIE
Enable interrupt generation on Z Low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
YHIE
Enable interrupt generation on Y High event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
YLIE
Enable interrupt generation on Y Low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
XHIE
Enable interrupt generation on X High event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
XLIE
Enable interrupt generation on X Low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
LIS331DL
7.11
Register description
FF_WU_SRC_1 (31h)
Table 32.
FF_WU_SRC_1 register
--
IA
Table 33.
ZH
ZL
YH
YL
XH
XL
FF_WU_SRC_1 description
IA
Interrupt Active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
Z High. Default value: 0
(0: no interrupt, 1: Z High event has occurred)
ZL
Z Low. Default value: 0
(0: no interrupt; 1: Z Low event has occurred)
YH
Y High. Default value: 0
(0: no interrupt, 1: Y High event has occurred)
YL
Y Low. Default value: 0
(0: no interrupt, 1: Y Low event has occurred)
XH
X High. Default value: 0
(0: no interrupt, 1: X High event has occurred)
XL
X Low. Default value: 0
(0: no interrupt, 1: X Low event has occurred)
Free-fall and wake-up source register. Read only register.
Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and
allows the refreshment of data in the FF_WU_SRC_1 register if the latched option was
chosen.
7.12
FF_WU_THS_1 (32h)
Table 34.
FF_WU_THS_1 register
DCRM
Table 35.
THS6
THS5
THS4
THS3
THS2
THS1
THS0
FF_WU_THS_1 description
DCRM
THS6, THS0
Resetting mode selection. Default value: 0
(0: counter reset; 1: counter decremented)
Free-fall / wake-up Threshold: default value: 000 0000
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If
DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration
counter is decremented.
31/42
Register description
7.13
LIS331DL
FF_WU_DURATION_1 (33h)
Table 36.
D7
Table 37.
D7-D0
FF_WU_DURATION_1 register
D6
D5
D4
D3
D2
D1
D0
FF_WU_DURATION_1 description
Duration value. Default value: 0000 0000
Duration register for Free-Fall/Wake-Up interrupt 1. Duration step and maximum value
depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400 Hz, else step
10 msec, from 0 to 2.55 sec when ODR=100 Hz. The counter used to implement duration
function is blocked when LIR=1 in configuration register and the interrupt event is verified
7.14
FF_WU_CFG_2 (34h)
Table 38.
AOI
Table 39.
32/42
FF_WU_CFG_2 register
LIR
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
FF_WU_CFG_2 description
AOI
And/Or combination of Interrupt events. Default value: 0
(0: OR combination of interrupt events; 1: AND combination of interrupt events)
LIR
Latch Interrupt request into FF_WU_SRC_2 reg with the FF_WU_SRC_2 reg cleared
by reading FF_WU_SRC_2 reg. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
ZHIE
Enable interrupt generation on Z High event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
ZLIE
Enable interrupt generation on Z Low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
YHIE
Enable interrupt generation on Y High event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
YLIE
Enable interrupt generation on Y Low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
XHIE
Enable interrupt generation on X High event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
XLIE
Enable interrupt generation on X Low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
LIS331DL
7.15
Register description
FF_WU_SRC_2 (35h)
Table 40.
--
Table 41.
FF_WU_SRC_2 register
IA
ZH
ZL
YH
YL
XH
XL
FF_WU_SRC_2 description
IA
Interrupt Active. Default value: 0
(0: no interrupt has been generated;
1: one or more interrupt events have been generated)
ZH
Z High. Default value: 0
(0: no interrupt; 1: Z High event has occurred)
ZL
Z Low. Default value: 0
(0: no interrupt; 1: Z Low event has occurred)
YH
Y High. Default value: 0
(0: no interrupt; 1: Y High event has occurred)
YL
Y Low. Default value: 0
(0: no interrupt; 1: Y Low event has occurred)
XH
X High. Default value: 0
(0: no interrupt; 1: X High event has occurred)
XL
X Low. Default value: 0
(0: no interrupt; 1: X Low event has occurred)
Free-fall and wake-up source register. Read only register.
Reading at this address clears FF_WU_SRC_2 register and the FF_WU_2 interrupt and
allows the refreshment of data in the FF_WU_SRC_2 register if the latched option was
chosen.
7.16
FF_WU_THS_2 (36h)
Table 42.
DCRM
Table 43.
FF_WU_THS_2 register
THS6
THS5
THS4
THS3
THS2
THS1
THS0
FF_WU_THS_2 description
DCRM
Resetting mode selection. Default value: 0
(0: counter reset; 1: counter decremented)
THS6, THS0
Free-fall / wake-up Threshold. Default value: 000 0000
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If
DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration
counter is decremented.
33/42
Register description
7.17
LIS331DL
FF_WU_DURATION_2 (37h)
Table 44.
D7
Table 45.
D7-D0
FF_WU_DURATION_2 register
D6
D5
D4
D3
D2
D1
D0
FF_WU_DURATION_2 description
Duration value. Default value: 0000 0000
Duration register for Free-Fall/Wake-Up interrupt 2. Duration step and maximum value
depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400 Hz, else step
10 msec, from 0 to 2.55 sec when ODR=100 Hz. The counter used to implement duration
function is blocked when LIR=1 in configuration register and the interrupt event is verified.
7.18
CLICK_CFG (38h)
Table 46.
-
Table 47.
CLICK_CFG register
LIR
Double_Z
Single_Z
Double_Y
Single_Y
Double_X
Single_X
CLICK_CFG description
LIR
Latch Interrupt request into CLICK_SRC reg with the CLICK_SRC reg
refreshed by reading CLICK_SRC reg.
Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
Double_Z
Enable interrupt generation on double click event on Z axis.
Default value: 0
(0: disable interrupt request; 1: enable interrupt request)
Single_Z
Enable interrupt generation on single click event on Z axis.
Default value: 0
(0: disable interrupt request; 1: enable interrupt request)
Double_Y
Enable interrupt generation on double click event on Y axis.
Default value: 0
(0: disable interrupt request; 1: enable interrupt request)
Single_Y
Enable interrupt generation on single click event on Y axis.
Default value: 0
(0: disable interrupt request; 1: enable interrupt request)
Double_X
Enable interrupt generation on double click event on X axis.
Default value: 0
(0: disable interrupt request; 1: enable interrupt request)
Single_X
Enable interrupt generation on single click event on X axis.
Default value: 0
(0: disable interrupt request; 1: enable interrupt request)
Table 48 shows all the possible configurations for Click and Double Click recognition.
34/42
LIS331DL
Register description
Table 48.
7.19
Double_Z / Y / X
Single_Z / Y / X
Click output
0
0
0
0
1
Single
1
0
Double
1
1
Single OR Double
CLICK_SRC (39h)
Table 49.
--
Table 50.
7.20
Click interrupt configurations
CLICK_SRC register
IA
Double_Z
Single_Z
Double_Y
Single_Y
Double_X
Single_X
THSx1
THSx0
CLICK_SRC description
IA
Interrupt Active. Default value: 0
(0: no interrupt has been generated;
1: one or more interrupt events have been generated)
Double_Z
Double click on Z axis event. Default value: 0
(0: no interrupt; 1: Double Z event has occurred)
Single_Z
Single click on Z axis event. Default value: 0
(0: no interrupt; 1: Single Z event has occurred)
Double_Y
Double click on Y axis event. Default value: 0
(0: no interrupt; 1: Double Y event has occurred)
Single_Y
Single click on Y axis event.Default value: 0
(0: no interrupt; 1: Single Y event has occurred)
Double_X
Double click on X axis event. Default value: 0
(0: no interrupt; 1: Double X event has occurred)
Single_X
Single click on X axis event. Default value: 0
(0: no interrupt; 1: Single X event has occurred)
CLICK_THSY_X (3Bh)
Table 51.
THSy3
Table 52.
CLICK_THSY_X register
THSy2
THSy1
THSy0
THSx3
THSx2
CLICK_THSY_X description
THSy3, THSy0 Click Threshold on Y axis. Default value: 0000
THSx3, THSx0 Click Threshold on X axis. Default value: 0000
From 0.5 g (0001) to 7.5 g (1111) with step of 0.5 g.
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Register description
7.21
LIS331DL
CLICK_THSZ (3Ch)
Table 53.
--
Table 54.
CLICK_THSZ register
--
--
--
THSz3
THSz2
THSz1
THSz0
Dur3
Dur2
Dur1
Dur0
Lat3
Lat2
Lat1
Lat0
Win3
Win2
Win1
Win0
CLICK_THSZ description
THSz3, THSz0 Click Threshold on Z axis. Default value: 0000
From 0.5 g (0001) to 7.5 g (1111) with step of 0.5 g.
7.22
CLICK_TimeLimit (3Dh)
Table 55.
Dur7
CLICK_TimeLimit register
Dur6
Dur5
Dur4
From 0 to 127.5 msec with step of 0.5 msec,
7.23
CLICK_Latency (3Eh)
Table 56.
Lat7
CLICK_Latency
Lat6
Lat5
Lat4
From 0 to 255 msec with step of 1 msec.
7.24
CLICK_Window (3Fh)
Table 57.
Win7
CLICK_Window register
Win6
Win5
Win4
From 0 to 255 msec with step of 1 msec.
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LIS331DL
Typical performance characteristics
8
Typical performance characteristics
8.1
Mechanical characteristics at 25 °C
Figure 13. X axis Sensitivity at 2.5 V
25
25
20
20
Percent of parts [%]
Percent of parts [%]
Figure 12. X axis Zero-g level at 2.5 V
15
10
5
0
−150
−100
−50
0
50
Zero−g Level Offset [mg]
100
0
16
150
20
20
18
18
16
16
14
14
12
10
8
4
2
2
100
0
16
150
Figure 16. Z axis Zero-g level at 2.5 V
19.5
20
16.5
17
17.5
18
18.5
Sensitivity [mg/digits]
19
19.5
20
19.5
20
Figure 17. Z axis Sensitivity at 2.5 V
25
20
20
Percent of parts [%]
25
15
10
5
0
−150
19
8
6
−50
0
50
Zero−g Level Offset [mg]
17.5
18
18.5
Sensitivity [mg/digits]
10
4
−100
17
12
6
0
−150
16.5
Figure 15. Y axis Sensitivity at 2.5 V
Percent of parts [%]
Percent of parts [%]
10
5
Figure 14. Y axis Zero-g level at 2.5 V
Percent of parts [%]
15
15
10
5
−100
−50
0
50
Zero−g Level Offset [mg]
100
150
0
16
16.5
17
17.5
18
18.5
Sensitivity [mg/digits]
19
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Typical performance characteristics
8.2
LIS331DL
Mechanical characteristics derived from measurement in the
-40 °C to +85 °C temperature range
Figure 19. X axis Sensitivity change
vs. temperature at 2.5 V
30
30
25
25
20
20
Percent of parts [%]
Percent of parts [%]
Figure 18. X axis Zero-g level change
vs. temperature at 2.5 V
15
15
10
10
5
5
0
−4
−3
−2
−1
0
1
2
3
0
4
−0.1
−0.05
0−g level drift [mg/oC]
35
35
30
30
25
25
20
15
5
5
−1
0
1
2
3
0
4
−0.1
−0.05
0−g level drift [mg/oC]
25
25
20
20
Percent of parts [%]
Percent of parts [%]
30
15
10
5
5
−1
0
1
o
0−g level drift [mg/ C]
38/42
0.1
0.15
15
10
−2
0.05
Figure 23. Z axis Sensitivity change
vs. temperature at 2.5 V
30
−3
0
Sensitivity drift [%/oC]
Figure 22. Z axis Zero-g level change
vs. temperature at 2.5 V
0
−4
0.15
15
10
−2
0.1
20
10
−3
0.05
Figure 21. Y axis Sensitivity change
vs. temperature at 2.5 V
Percent of parts [%]
Percent of parts [%]
Figure 20. Y axis Zero-g level change
vs. temperature at 2.5 V
0
−4
0
Sensitivity drift [%/oC]
2
3
4
0
−0.1
−0.05
0
0.05
o
Sensitivity drift [%/ C]
0.1
0.15
LIS331DL
8.3
Typical performance characteristics
Electrical characteristics at 25 °C
Figure 24. Current consumption
in normal mode at 2.5 V
20
18
16
Percent of parts [%]
14
12
10
8
6
4
2
0
200
220
240
260
280
300
320
340
Current consumption [uA]
360
380
400
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Package information
9
LIS331DL
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK® is an ST trademark.
ECOPACK® specifications are available at: www.st.com.
Figure 25. LGA 16: Mechanical data and package dimensions
Dimensions
Ref.
mm
Min.
inch
Typ. Max.
A1
Min.
Typ.
1.000
A2
0.785
A3
Max.
0.0394
0.0309
0.200
0.0079
D1
2.850
3.000
3.150 0.1122 0.1181 0.1240
E1
2.850
3.000
3.150 0.1122 0.1181 0.1240
L1
1.000
1.060
L2
2.000
2.060
N1
0.500
N2
M
1.000
0.040
0.100
0.0394 0.0417
0.0787 0.0811
0.0197
0.0394
0.160 0.0016 0.0039 0.0063
P1
0.875
0.0344
P2
1.275
0.0502
T1
0.290
T2
0.190
Outline and
mechanical data
0.350
0.410 0.0114 0.0138 0.0161
0.250
0.310 0.0075 0.0098 0.0122
d
0.150
0.0059
k
0.050
0.0020
LGA16 (3x3x1.0mm)
Land Grid Array Package
7983231
40/42
LIS331DL
10
Revision history
Revision history
Table 58.
Document revision history
Date
Revision
Changes
28-Sep-2007
1
Initial release
21-Jan-2008
2
Updated package specification Figure 25: LGA 16: Mechanical data
and package dimensions on page 40.
Minor text changes to improve readability.
16-Apr-2008
3
Updated paragraph 2.1: Mechanical characteristics and added
section 8: Typical performance characteristics.
Updated POA
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LIS331DL
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