A1 PROs IMP802MEPA μp power supplly superviissor wiitth battttery backup swiittch Datasheet

IMP690A , 692A , 802L/M, 805L
POWER MANAGEMENT
µP Power Supply Supervisor
with Battery Backup Switch
The IMP690A/IMP692A/IMP802L/IMP802M/IMP805L simplify power
supply monitoring and control in microprocessor systems. Each circuit
implements four functions: Reset control, watchdog monitoring, batterybackup switching and power-failure monitoring. In addition to
microprocessor reset under powerup and power-down conditions, these
devices provide battery-backup switching to maintain control in powerloss and brown-out situations. Additional monitoring capabilities
can provide an early warning of unregulated power-supply loss before
the voltage regulator drops out. The important features of these four
functions are:
a) 1.6 second watchdog timer to keep microprocessor responsive
b)
4.40V or 4.65V VCC threshold for microprocessor reset at power-up
and power-down
c)
SPDT (single-pole, double-throw) PMOS switch connects backup
power to RAM if VCC fails
Key Features
◆ Design improvement over Maxim
MAX690A/692A/802L/802M/805L
— 70% lower current than Maxim:
100µA maximum
— RESET Operation to 1.1V
◆ Two precision supply-voltage monitor options
— 4.65V (IMP690A/802L/805L)
— 4.40V (IMP692A/802M)
◆ Battery-backup power switch on-chip
◆ Watchdog timer: 1.6 second timeout
◆ Power failure/low battery detection
◆ Short-circuit protection and thermal limiting
◆ Small 8-pin SO package
◆ No external components
◆ Specified over full temperature range
d) 1.25V threshold detector for power loss or general purpose voltage
monitoring
While these features are pin–compatible with the industry standard
power–supply supervisors offered by Maxim, the IMP devices are superior replacements and can reduce power requirements by 70 percent
when compared to Maxim MAX690/MAX692A/MAX802L/MAX802M/
MAX805L devices. Short-circuit and thermal protection have also
been added.
The IMP690A/IMP802L/IMP805L generate a reset pulse when the
supply voltage drops below 4.65V, and the IMP692A/IMP802M
generate a reset below 4.40V. The IMP802L/IMP802M have power–fail
accuracy to ±2%. The IMP805L is the same as the IMP690A except that
RESET is provided instead of

RESET.
Applications
◆ Embedded control systems
◆ Battery–operated systems
◆ Intelligent instruments
◆ Wireless communication systems
◆ PDAs and handheld equipment
◆ µP/µC power supply monitoring
Block Diagrams
8
1
Battery-Switchover
Circuit
2
VCC
Reset
Generator
7
+
VOUT
Unregulated DC
RESET
(RESET)
R1
Watchdog
Timer
R2
+
+
6
WDI
+
+
RESET
4
3.6V
Lithium
Battery
PFO
NMI
VBATT
WDI
VOUT
I/O LINE
GND
GND
CMOS
VCC RAM
GND
5
+
PFI
+
–
RESET
PFI
IMP690A
1.25V
+
0.8V
VCC
VCC
0.1µF
+
1.25V
3.5V
Regulated +5V
BUS
VBATT
Typical Application
PFO
IMP690A, IMP692A, IMP802L, IMP802M,
IMP805L
( ) IMP805L
IMP, Inc.
3
690A_01.eps
GND
690A_03.eps
San Jose, CA
408-432-9100/www.impweb.com
IMP690A , 692A , 802L, 802M, 805L
Pin Configuration
Plastic/CerDip/SO
VOUT
1
VCC
2
GND
3
PFI
4
IMP690A
IMP692A
IMP802L
IMP802M
IMP805L
( ) IMP805L
8
VBATT
7
RESET (RESET)
6
WDI
5
PFO
690A_02.eps
Ordering Information
Part Number
IMP690A
Reset Threshold (V)
Temperature Range
Pins-Package
IMP690ACPA
4.5 to 4.75
0°C to +70°C
8-Plastic DIP
IMP690ACSA
4.5 to 4.75
0°C to +70°C
8-SO
IMP690AC/D
4.5 to 4.75
IMP690AEPA
25°C
DICE
– 40°C to +85°C
8-Plastic DIP
IMP690AESA
4.5 to 4.75
– 40°C to +85°C
8-SO
IMP690AMJA
4.5 to 4.75
Contact Factory
8-CerDIP
IMP692ACPA
4.25 to 4.50
0°C to +70°C
8-Plastic DIP
IMP692ACSA
4.25 to 4.50
0°C to +70°C
8-SO
IMP692AC/D
4.25 to 4.50
25°C
DICE
IMP692AEPA
4.25 to 4.50
– 40°C to +85°C
8-Plastic DIP
IMP692AESA
4.25 to 4.50
– 40°C to +85°C
8-SO
IMP692AMJA
4.25 to 4.50
Contact Factory
8-CerDIP
IMP802LCPA
4.5 to 4.75
0°C to +70°C
8-Plastic DIP
IMP802LCSA
4.5 to 4.75
0°C to +70°C
8-SO
IMP802LEPA
4.5 to 4.75
– 40°C to +85°C
8-Plastic DIP
IMP802LESA
4.5 to 4.75
– 40°C to +85°C
8-SO
IMP802MCPA
4.25 to 4.50
0°C to +70°C
8-Plastic DIP
IMP802MCSA
4.25 to 4.50
0°C to +70°C
8-SO
IMP802MEPA
4.25 to 4.50
– 40°C to +85°C
8-Plastic DIP
IMP802MESA
4.25 to 4.50
– 40°C to +85°C
8-SO
IMP805LCPA
4.5 to 4.75
0°C to +70°C
8-Plastic DIP
IMP805LCSA
4.5 to 4.75
0°C to +70°C
8-SO
IMP805LC/D
4.5 to 4.75
25°C
DICE
IMP805LEPA
4.5 to 4.75
–40°C to +85°C
8-Plastic DIP
IMP805LESA
4.5 to 4.75
–40°C to +85°C
8-SO
IMP805LMJA
4.5 to 4.75
Contact Factory
8-CerDIP
IMP692A
IMP802L
IMP802M
IMP805L
2
IMP690A , 692A , 802L, 802M, 805L
Pin Description
Pin Number
IMP690A/IMP692A
IMP802L/IMP802M
IMP805L
Name
1
1
VOUT
Voltage supply for RAM. When VCC is above the reset threshold, VOUT
connects to VCC through a P-channel MOS device. If VCC falls below the
reset threshold, this output will be connected to the backup supply at
VBATT (or VCC, whichever is higher) through the MOS switch to provide
continuous power to the CMOS RAM.
2
2
VCC
+5V power supply input
3
3
GND
Ground
4
4
PFI
5
5
PFO

6
6
WDI
Watchdog input. The WDI input monitors microprocessor activity. An
internal timer is reset with each transition of the WDI input. If WDI is held
HIGH or LOW for longer than the watchdog timeout period, typically 1.6
seconds, RESET (or
RESET) is asserted for the reset pulse width time,
tRS, of 140ms, minimum.
7
––––

R
 ESET
Active-LOW reset output. When triggered by VCC falling below the reset
threshold or by watchdog timer timeout, RESET (or
RESET) pulses low
for the reset pulse width, t RS, typically 200ms. It will remain low if VCC is
below the reset threshold (4.65V in the IMP690A/IMP802L and 4.4V in
the IMP692A/IMP802L) and remains low for 200ms after VCC rise above
the reset threshold.
––––
7
RESET
Active-HIGH reset output. The inverse of
RESET.
8
8
VBATT
Function
Power failure monitor input. PFI is connected to the internal power fail
comparator which is referenced to 1.25V. The power fail output (PFO)
is active LOW but remains HIGH if PFI is above 1.25V. If this feature is
unused, the PFI pin should be connected to GND or VOUT.
Power-fail output.PFO
 is active LOW whenever the PFI pin is less than
1.25V.
Auxiliary power or backup-battery input. VBATT should be connected to
GND if the function is not used. This input has about 40mV of hysteresis
to prevent rapid toggling between VCC and VBATT.
Absolute Maximum Ratings
Pin Terminal Voltage with Respect to Ground
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 6.0V
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 6.0V
All Other Inputs* . . . . . . . . . . . . . . . . . . . –0.3V to (VCC + 0.3V)
Input Current at VCC . . . . . . . . . . . . . . . . . . 200mA
Input Current at VBATT . . . . . . . . . . . . . . . . . 50mA
Input Current at GND . . . . . . . . . . . . . . . . . 20mA
Output Current:
VOUT . . . . . . . . . . . . . . . Short circuit protected
All Other Inputs . . . . . . . . . . . . . . . . . . . 20mA
Rate of Rise: VBATT and VCC . . . . . . . . . . 100V/µs
Continuous Power Dissipation
Plastic DIP (derate 9mW/°C above 70°C) . . . 800mW
SO (derate 5.9mW/°C above 70°C) . . . . . . . . 500mW
CerDIP (derate 8mW/°C above 70°C) . . . . . . 650mW
Operating Temperature Range (C Devices) . . . . 0°C to 70°C
Operating Temperature Range (E Devices) . . . . –40°C to 85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . –65°C to 160°C
Lead Temperature Soldering, (10 sec) . . . . . . . . 300°C
* The input voltage limits on PFI and WDI may be exceeded if the
current is limited to less than 10mA
These are stress ratings only and functional operation is not implied.
Exposure to absolute maximum ratings for prolonged time periods may
affect device reliability.
3
IMP690A , 692A , 802L, 802M, 805L
Electrical Characteristics
Unless otherwise noted VCC = 4.75V to 5.5V for the IMP690A/IMP802L/IMP805L and VCC = 4.5V to 5.5V for the IMP692A/IMP802M;
VBATT = 2.8V; and TA = TMIN to TMAX.
Parameter
Symbol
VCC, VBATT Voltage Range
(Note 1)
Supply Current Excluding IOUT
IS
ISUPPLY in Battery-Backup Mode
(Excluding IOUT)
VBATT Standby Current
(Note 2)
VOUT Output
VOUT in Battery-Backup Mode
Battery Switch Threshold,
VCC to VBATT
Battery Switchover Hysteresis
Reset Threshold
Reset Threshold Hysteresis
Reset Pulse Width
Reset Output Voltage
Watchdog Timeout
WDI Pulse Width
WDI Input Current
WDI Input Threshold
(Note 3)
PFI Input Threshold
PFI Input Current
PFO Output Voltage
VRT
Conditions
IMP69_AC, IMP802_C
IMP805LC
IMP69_AE, IMP80_ _E
IMP69_AC, IMP802_C
IMP69_AE, IMP802_E, IMP805LE
VCC = 0V, VBATT = 2.8V
TA = 25°C
TA = TMIN to TMAX
5.5V > VCC > VBATT – 0.2V
TA = 25°C
TA = TMIN to TMAX
IOUT = 5mA
IOUT = 50mA
IOUT = 250µA, VCC < VBATT – 0.2V
Power-up
VCC < VRT
Power-down
IMP690A/802L/805L
IMP692A, IMP802M
IMP802L, TA = 25°C, VCC falling
IMP802M, TA = 25°C, VCC falling
tRS
ISOURCE = 800µA
ISINK = 3.2mA
IMP69_AC, IMP802_C, VCC = 1.0V, ISINK = 50µA
IMP69_AE, IMP802_E, VCC = 1.2V, ISINK = 100µA
IMP805LC, ISOURCE = 4µA, VCC = 1.1V
IMP805LE, ISOURCE = 4µA, VCC = 1.2V
IMP805L, ISOURCE = 800µA
IMP805L, ISINK = 3.2mA
tWD
tWP
VIL= 0.4V, VIH = 0.8VCC
WDI = VCC
WDI = 0V
VCC = 5V, Logic LOW
VCC = 5V, Logic HIGH
IMP69_A, IMP805L, VCC = 5V
IMP802_C/E, VCC = 5V
ISOURCE = 800µA
ISINK = 3.2mA
Min
Typ
1.1
1.1
1.1
35
35
– 0.1
–1.0
VCC – 0.025 VCC – 0.010
VCC – 0.25 VCC – 0.10
VBATT – 0.1 VBATT – 0.001
20
–20
40
4.50
4.65
4.25
4.40
4.55
4.30
40
140
200
VCC – 1.5
Max Units
5.5
5.5
5.5
100
100
1.0
5.0
0.02
0.02
V
µA
µA
µA
V
V
mV
4.75
4.50
4.70
4.45
280
mV
V
mV
ms
V
0.4
0.3
0.3
0.8
0.9
VCC – 1.5
1.00
50
–150
3.5
1.20
1.225
– 25
VCC – 1.5
1.60
50
–50
1.25
1.250
0.01
0.4
2.25
150
sec
ns
µA
0.8
V
1.30
1.275
25
V
nA
V
0.4
Notes: 1. If VCC or VBATT is 0V, the other must be greater than 2.0V.
2. Battery charging-current is “–”. Battery discharge-current is “+”.
3. WDI is guaranteed to be in an intermediate level state if WDI is floating and VCC is within the operating voltage range. WDI input
impedance is 50kΩ. WDI is biased to 0.3VCC.
4
IMP690A , 692A , 802L, 802M, 805L
Application Information
Reset Output
Microprocessor Interface.
It is important to initialize a microprocessor to a known state in
response to specific events that could create code execution errors
and “lock-up”. The reset output of these supervisory circuits send
a reset pulse to the microprocessor in response to power-up,
power-down/power-loss or a watchdog time-out. The reset pulse
width, t RS, is typically around 200ms and is LOW for the
IMP690A, IMP692A, IMP802 and HIGH for the IMP805L.
The IMP690 has logic-LOW RESET output while the IMP805 has
an inverted logic-HIGH RESET output. Microprocessors with bidirectional reset pins (69HC11 for example) can pose a problem
when the supervisory circuit and the microprocessor output pins
attempt to go to opposite logic states. The problem can be
resolved by placing a 4.7kΩ resistor between the RESET output
and the microprocessor reset pin. This is shown in Figure 3. Since
the series resistor limits drive capabilities, the reset signal to other
devices should be buffered.
Power-up reset occurs when a rising VCC reaches the reset threshold, VRT, forcing a reset condition in which the reset output is
asserted in the appropriate logic state for the duration of t RS.
Figure 2 shows the reset pin timing.
Power-loss or “brown-out” reset occurs when VCC dips below the
reset threshold resulting in a reset assertion for the duration of tRS.
The reset signal remains asserted as long as VCC is between VRT
and 1.1V, the lowest VCC for which these devices can provide a
guaranteed logic-low output. To ensure logic inputs connected to
the IMP690A/692A/802 RESET pin are in a known state when
VCC is under 1.1V, a 100kΩ pull-down resistor at RESET is needed:
the logic-high IMP805L will need a pull-up resistor to VCC.
A Watchdog time-out reset occurs when a logic “1” or logic “0” is
continuously applied to the WDI pin for more than 1.6 seconds.
After the duration of the reset interval, the watchdog timer starts
a new 1.6 second timing interval; the microprocessor must service
the watchdog input by changing states or by floating the WDI pin
before this interval is finished. If the WDI pin is held either HIGH
or LOW, a reset pulse will be triggered every 1.8 seconds (the 1.6
second timing interval plus the reset pulse width t RS).
+5V
VCC
+0V
+5V
VOUT
3.0V
+0V
tRS
+5V
RESET
+0V
+5V
(RESET)
3.0V
+0V
+5V
PFO
+0V
VBATT = PFI = 3.0V
IOUT = 0mA
( ) IMP805L
690A_04.eps
Figure 2. Timing Diagram
VBATT
8
1
Battery-Switchover
Circuit
2
VCC
Reset
Generator
7
+
VOUT
RESET
(RESET)
Buffered RESET to Other System Components
+
1.25V
3.5V
Watchdog
Timer
+
+
6
VCC
WDI
+
+
1.25V
4
+
PFI
4.7k
5
+
0.8V
PFO
( ) IMP805L
GND
RESET
RESET
IMP690A
IMP690A, IMP692A, IMP802L, IMP802M,
IMP805L
3
VCC
GND
GND
690A_03.eps
690A_05.eps
Figure 1. Block Diagram
Figure 3. Interfacing with bi-directional microprocessor
reset inputs
5
IMP690A , 692A , 802L, 802M, 805L
Application Information
Watchdog Input
As discussed in the Reset section, the Watchdog Input is used to
monitor microprocessor activity. It can be used to insure that the
microprocessor is in a continually responsive state by requiring
that the WDI pin be toggled every second. If the WDI pin is not
toggled within the 1.6 second window (minimum t WD + t RS),
a reset pulse will be asserted to return the microprocessor to the
initial start-up state. Pulses as short as 50ns can be applied to the
WDI pin. If this feature is not used, the WDI pin should be opencircuited or the logic placed into a high-impedance state to allow
the pin to float.
Backup-Battery Switchover
A power loss can be made less severe if the system RAM contents
are preserved. This is achieved in the IMP690/692/802/805 by
switching from the failed VCC to an alternate power source connected at VBATT when VCC is less than the reset threshold voltage
(VCC < VRT), and VCC is less than VBATT. The VOUT pin is normally
connected to VCC through a 2Ω PMOS switch but a brown-out or
loss of VCC will cause a switchover to VBATT by means of a 20Ω
PMOS switch. Although both conditions (VCC < VRT and VCC <
VBATT) must occur for the switchover to VBATT to occur, VOUT will
be switched back to VCC when VCC exceeds VRT irrespective of the
voltage at VBATT. It should be noted that an internal device diode
(D1 in Figure 4) will be forward biased if VBATT exceeds VCC by
more than a diode drop when VCC is switched to VOUT. Because of
this it is recommended that VBATT be no greater than VRT +0.6V.
VCC
VBATT
SW1
SW2
D1 D2
IMP690A IMP802L
IMP692A IMP802M
D3
SW3
IMP805L
Connection
VOUT
Connected to VBATT through internal PMOS switch
VBATT
Connected to VOUT
PFI
Disabled

PFO

RESET

WDI
Logic-LOW
Logic LOW (except on IMP805 where it is HIGH)
Watchdog timer disabled
During the backup power mode, the internal circuitry of the
supervisory circuit draws power from the battery supply. While
VCC is still alive, the comparator circuits remain alive and the current drawn by the device is typically 35µA. When VCC drops more
than 1.1V below VBATT, the internal switchover comparator, the
PFI comparator and WDI comparator will shut off, reducing the
quiescent current drawn by the IC to less than 1µA.
Backup Power Sources - Batteries
Battery voltage selection is important to insure that the battery
does not discharge through the parasitic device diode D1 (see
Figure 4) when VCC is less than VBATT and VCC > VRT.
Table 2. Maximum Battery Voltages
Part No.
MAXIMUM Battery Voltage
IMP690A
4.80
IMP802L
4.80
IMP805L
4.80
IMP692A
4.55
IMP802M
4.55
Battery Replacement while Powered
SW1/SW2 SW3/SW4
Open
Closed
Open
Closed
Closed
Open
IMP690A /IMP802L / IMP805L Reset Threshold = 4.65V
IMP692A /IMP802M Reset Threshold = 4.4V
690A_06.eps
Figure 4. Internal device configuration of battery
switch-over function
6
Pin
Although most batteries that meet the requirements of Table 2 are
acceptable, lithium batteries are very effective backup source due
to their high-energy density and very low self-discharge rates.
SW4
VOUT
CONDITION
VCC > Reset Threshold
VCC < Reset Threshold and
VCC > VBATT
VCC < Reset Threshold and
VCC < VBATT
Table 1. Pin Connections in Battery Backup Mode
Batteries can be replaced even when the device is in a powered
state as long as VCC remains above the reset threshold voltage VRT.
In the IMP devices, a floating VBATT pin will not cause a powersupply switchover as can occur in some other supervisory
circuits. If VBATT is not used, the pin should be grounded.
IMP690A , 692A , 802L, 802M, 805L
Application Information
Backup Power Sources - SuperCapTM
Operation Without a Backup Power Source
Capacitor storage, with very high values of capacitance, can be
used as a back-up power source instead of batteries. SuperCapTM
are capacitors with capacities in the fractional farad range. A 0.1
farad SuperCapTM would provide a useful backup power source.
Like the battery supply, it is important that the capacitor voltage
remain below the maximum voltages shown in Table 2. Although
the circuit of Figure 5 shows the most simple way to connect the
SuperCapTM, this circuit cannot insure that an overvoltage condition will not occur since the capacitor will ultimately charge up to
VCC. To insure that an overvoltage condition does not occur,
the circuit of Figure 6 is preferred. In this circuit configuration, the
diode-resistor pair clamps the capacitor voltage at one diodedrop below VCC. VCC itself should be regulated within ±5% of
5V for the IMP692A/802M or within ±10% of 5V for the
IMP690A/802L/805L to insure that the storage capacitor does not
achieve an overvoltage state.
When operating without a back-up power source, the VBATT pin
should be connected to GND and VOUT should be connected to
VCC, since power source switchover will not occur. Connecting
VOUT to VCC eliminates the voltage drop due to the ON-resistance
of the PMOS switch.
Note: SuperCapTM is a trademark of Baknor Industries
+5V
VCC
VOUT
VBATT
To Static RAM
Power-Fail Comparator
The Power Fail feature is an independent voltage monitoring
function that can be used for any number of monitoring activities.
The PFI function can provide an early sensing of power supply
failure by sensing the voltage of the unregulated DC ahead of
the regulated supply sensing seen by the backup-battery
switchover circuitry.
The PFI pin is compared to a 1.25V internal reference. If the voltage at the PFI pin is less than this reference voltage, the
PFO pin
goes low. By sensing the voltage of the raw DC power supply, the
microprocessor system can prepare for imminent power-loss,
especially if the battery backup supply is not enabled. The input
voltage at the PFI pin results from a simple resistor voltage
divider as shown in Figure 7.
+5V
To µP
RESET
(RESET)
VCC
+
R1
0.1F
GND
( ) IMP805L
IMP690A
IMP692A
PFI IMP802L PFO
IMP802M
IMP805L
R2
690A_07.eps
GND
Figure 5. Capacitor as a backup power source
+5V
+5V
VCC
VBATT
+
100k
0.1F
VOUT
RESET
To Static RAM
PFO
A
B
0V
To µP
IMP692A
IMP802M
A
5R 2
< 1.25V
R1 + R 2
B
5R 2
> 1.25V
R1 + R 2
690A_09.eps
GND
( ) IMP805L
Figure 7. Simple Voltage divider sets PFI trip point
690A_08.eps
Figure 6. Capacitor as back-up Power Source - Voltage
clamped to 0.5V below VCC
7
IMP690A , 692A , 802L, 802M, 805L
Application Information
Power Fail Hysteresis
Monitoring Capabilities of the Power-Fail Input
A noise margin can be added to the simple monitoring circuit of
Figure 7 by adding positive feedback from the
PFO pin. The circuit of Figure 8 adds this positive “latching” effect by means of an
additional resistor R3 connected between
PFO and PFI which
helps in pulling PFI in the direction of
PFO and eliminating an
indecision at the trip point. Resistor R3 is normally about 10 times
higher in resistance than R2 to keep the hysteresis band reasonable and should be larger than 10kΩ to avoid excessive loading on
the
PFO pin. The calculations for the correct values of resistors to
set the hysteresis thresholds are given in Figure 8. A capacitor can
be added to offer additional noise rejection by low-pass filtering.
Although designed for power supply failure monitoring, the PFI
pin can be used for monitoring any voltage condition that can be
scaled by means of a resistive divider. An example is the negative
power supply monitor configured in Figure 9. In this case a good
negative supply will hold the PFI pin below 1.25V and the
PFO
pin will be at a logic “0”. As the negative voltage declines,
the voltage at the PFI pin will rise until it exceeds 1.25V and
the
PFO pin will go to a logic “1”.
+5V
VCC
VIN
R1
+5V
VCC
IMP690A
IMP692A
IMP802L
PFI
IMP802M
IMP805L
R1
R3
R2
C1*
IMP690A
IMP692A
IMP802L
PFO
PFI
IMP802M
IMP805L
R2
GND
V–
PFO
V– = VTRIP
GND
+5V
To µP
*Optional
0V
+5V
PFO
0V
VL
0V
V TRIP =
V IH =
1.25
VTRIP
VIN
VTRIP
V–
5 − 1.25 1.25 − V TRIP
=
R1
R2
VH
 R2 
R +R 
 2
2
0V
690A_11.eps
Figure 9. Using PFI to monitor negative supply voltage
1.25
 R2 R3 
R +R R 
 1
2
3
V L− 1.25 5 − 1.25 1.25
+
=
R1
R3
R2
690A_10.eps
Figure 8. Hysteresis added to PFI pin
8
PFO
IMP690A , 692A , 802L, 802M, 805L
Package Dimensions
Plastic DIP (8-Pin)
Inches
D1
Millimeters
Max
Min
Max
Plastic DIP (8-Pin)*
Min
E
D
E1
A A2
L A1
0°–15°
e
C
b2
eA
eB
b
Plastic DIP (8-Pin)a.eps
CerDIP (8-Pin)
D1
A
–––––
0.210
––––
5.33
A1
0.015
–––––
0.38
–––––
A2
0.115
0.195
2.92
4.95
b
0.014
0.022
0.36
0.56
b2
0.045
0.070
1.14
1.78
b3
0.030
0.045
0.80
1.14
D
0.355
0.400
9.02
10.16
D1
0.005
–––––
0.13
–––––
E
0.300
0.325
7.62
8.26
E1
0.240
0.280
6.10
e
0.100
–––––
eA
0.300
–––––
eB
–––––
0.430
eC
–––––
0.060
L
0.115
0.150
7.11
2.54
7.62
–––––
10.92
2.92
3.81
CerDIP (8-Pin)
D
A
–––––
0.200
––––
5.08
E
A1
0.015
0.070
0.38
1.78
E1
b
0.014
0.023
0.36
0.58
b2
0.038
0.065
0.97
1.65
C
0.008
0.015
0.20
0.38
D
–––––
0.405
–––––
10.29
D1
0.005
–––––
0.13
–––––
E
0.290
0.320
7.37
8.13
E1
0.220
0.310
5.59
A
L A1
0°–15°
e
C
b2
b
Ceramic DIP (8-Pin)a.eps
e
L
SO (8-Pin)
0.125
7.87
2.54
0.200
3.18
5.08
SO (8-Pin)**
0°– 8°
L
E
0.100
A
0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
e
H
C
0.050
0.25
1.27
E
0.150
0.157
3.80
4.00
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
D
0.189
0.197
4.80
5.00
* JEDEC Drawing MS-001BA
** JEDEC Drawing MS-012AA
D
A
e
B
A1
SO (8-Pin).eps
9
IMP690A , 692A , 802L, 802M, 805L
IMP, Inc.
Corporate Headquarters
2830 N. First Street
San Jose, CA 95134-2071
Tel: 408-432-9100
Tel: 800-438-3722
Fax: 408-434-0335
Fax-on-Demand: 1-800-249-1614 (USA)
Fax-on-Demand: 1-303-575-6156 (International)
e-mail: [email protected]
http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc.
All other company and product names are trademarks of their respective owners.
10
© 1998 IMP, Inc.
Printed in USA
Preliminary
Part No.: IMP 690A
Document Number: IMP690A-2-9/98
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