HV209 12-Channel High Voltage Analog Switch Features General Description ❏ HVCMOS technology for high performance ❏ Operating voltage of up to 200V ❏ Output On-resistance typically 22Ω ❏ Integrated bleed resistors on the outputs ❏ Very low quiescent power dissipation -10µA ❏ Low parasitic capacitances ❏ -58dB typical output off isolation at 5MHz ❏ 5.0V to 12V CMOS logic circuitry ❏ Excellent noise immunity ❏ Flexible high voltage supplies The Supertex HV209 is a 200V low charge injection 12channel high voltage analog switch configured as 6 SPDT analog switch intended for medical ultrasound applications. Bleed resistors are integrated on the output switches to eliminate charge built up on the piezo electric transducers. The bleed resistors are at a nominal value of 35K? ? Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The outputs are configured as single pole double throw analog switches. Data is shifted into a 6-bit shift register using an external clock. The LE latches the shift register data into the individual switch latches. A logic high connects a switch common YX to SWX. A logic low connects YX to SWX. A logic hi in CL resets all switches to SWX simultaneously. Block Diagram VPP VNN SW0 D LE CL High Voltage Level Translator Y0 SW0 SW1 D LE CL High Voltage Level Translator Y1 SW1 SW2 VDD D LE CL CLK DIN 6 BIT SHIFT REGISTER High Voltage Level Translator Y2 SW2 SW3 DOUT D LE CL GND High Voltage Level Translator Y3 SW3 SW4 D LE CL High Voltage Level Translator Y4 SW4 SW5 D LE CL CL LE High Voltage Level Translator Y5 SW5 RGND1 / RGND2 Ordering Information VPP – VNN Package Option 48-pin LQFP/TQFP (1.4mm) 200V HV209FG HV209FG-G -G indicates that the package is RoHS compliant (’Green’) Absolute Maximum Ratings VDD Logic power supply voltage -0.5V to +15V VPP - VNN Supply voltage +220V VPP Positive high voltage supply -0.5V to +200V VNN Negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to VDD +0.3V VSIG Analog Signal Range VNN to V PP Peak analog signal current/channel Storage temperature Power dissipation 3.0A -65 C to +150OC O 1.0W All voltages are referenced to ground. Absolute maximum ratings are those values which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. 2 HV209 Electrical Characteristics DC Characteristics (over recommended operating conditions unless otherwise noted) Characteristics Small Signal Switch (ON) Resistance Sym 0°C min max RONS Small Signal Switch (ON) Resistance Matching ∆RONS Large Signal Switch (ON) Resistance RONL Output Switch Shunt Resistance RINT +25°C typ max 30 26 38 48 ISIG = 5mA 25 22 27 32 ISIG = 200mA VNN = -160V 25 22 27 30 18 18 24 27 ISIG = 200mA VNN = -100V 23 20 25 30 ISIG = 5mA 22 16 25 27 ISIG = 200mA VNN = -10V 20 5.0 20 20 min +70°C min max 15 20 35 Units ohms % ohms 50 Test Conditions ISIG = 5mA VPP = 40V, VPP = 100V, VPP = 190V, ISW = 5mA, VPP = 100V, VNN = -100V VSIG = VPP - 10V, ISIG = 1A KΩ Output switch to RGND IRINT = 0.5 mA DC Offset Switch Off 50 50 50 mV No Load, RGND = 0V DC Offset Switch On 50 50 50 mV No Load, RGND = 0V Pos. HV Supply Current IPPQ 10 50 µA ALL SWs OFF Neg. HV Supply Current INNQ -10 -50 µA ALL SWs OFF Pos. HV Supply Current IPPQ 10 50 µA ALL SWs ON ISW = 5mA Neg. HV Supply Current INNQ -10 -50 µA ALL SWs ON ISW = 5mA 3.0 2.0 A VSIG duty cycle ≤ 0.1% Switch Output Peak Current Output Switch Frequency IPP Supply Current INN Supply Current 3.0 fSW 2.0 50 IPP INN KHz Duty Cycle = 50% 6.5 7.0 8.0 VPP = 40V, VNN = -160V 4.0 5.0 5.5 4.0 5.0 5.5 VPP = 190V, VNN = -10V 6.5 7.0 8.0 VPP = 40V, VNN = -160V 4.0 5.0 5.5 4.0 5.0 5.5 mA mA VPP = 100V, VNN = -100V 50KHz Output Switching Frequency with no load VPP = 100V, VNN = -100V VPP = 190V, VNN = -10V Logic Supply Average Current IDD 4.0 4.0 4.0 mA Logic Supply Quiescent Current IDDQ 10 10 10 µA Data Out Source Current ISOR 0.45 0.45 0.70 0.40 mA VOUT = VDD - 0.7V Data Out Sink Current ISINK 0.45 0.45 0.70 0.40 mA VOUT = 0.7V Logic Input Capacitance CIN 10 10 3 10 pF fCLK = 5MHz, VDD = 5.0V HV209 Electrical Characteristics AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted) Characteristics Sym 0°C min +25°C max min typ +70°C max min max Units Set Up Time Before LE Rises tSD 150 150 150 ns Time Width of LE tWLE 150 150 150 ns Clock Delay Time to Data Out tDO Time Width of CL tWCL 150 150 Set Up Time Data to Clock tSU 15 15 Hold Time Data from Clock th 35 35 150 150 8.0 150 Test Conditions ns 150 ns 20 ns 35 ns Clock Freq fCLK 5.0 5.0 5.0 MHz 50% duty cycle fDATA = fCLK/2 Turn On Time tON 5.0 5.0 5.0 µs VSIG = VPP -10V, RL = 10KΩ Turn Off Time tOFF 5.0 5.0 5.0 µs VSIG = VPP -10V, RL = 10KΩ 20 20 20 20 20 20 20 20 20 Maximum VSIG Slew Rate Off Isolation Switch Crosstalk Output Switch Isolation Diode Current dv/dt KO KCR -30 -30 -58 -58 -60 -60 IID -33 -70 300 VPP = 40V, VNN = -160V V/ns VPP = 100V, VNN = -100V VPP = 190V, VNN = -10V -30 dB f = 5MHz, 1KΩ//15pF load -58 dB f = 5MHz, 50Ω load -60 dB f = 5MHz, 50Ω load 300 mA 300ns pulse width, 2.0% duty cycle 300 Off Capacitance SW to GND CSG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, 1MHz On Capacitance SW to GND CSG(ON) 25 50 25 38 50 25 50 pF 0V, 1MHz Positive Output Voltage Spike +VSPK 150 150 150 mV RLOAD = 50Ω Negative Output Voltage Spike -VSPK 150 150 150 mV RLOAD = 50Ω 4 HV209 Operating Conditions* Symbol Parameter VPP supply1 Positive high voltage Negative high voltage VNN Value +40V to VNN+ 200V supply1 -10V to -160V voltage1 VDD Logic power supply VIH High-level input voltage 0.8 VDD to VDD VIL Low-level input voltage 0V to 0.2VDD VSIG Analog signal voltage TA +4.5V to +13.2V peak-to-peak2 VNN +10V to VPP -10V Operating free air-temperature 0°C to 70°C Notes: 1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2 VSIG must be within VPP and VNN voltage range or floating during power up/down transition. Truth Table Data Inputs Switch States LE CL L L L SW0 H L L SW0 L L L SW1 H L L SW1 L L L SW2 H L L SW2 L L SW3 SW3 DO D1 D2 D3 D4 D5 L H Y0 Y1 Y2 Y3 Y4 L L L L L SW4 H L L SW4 L L L H L L X X X X X X H L X X X X X X X H 5 Y5 SW5 SW5 HOLDS PREVIOUS STATE SW0 SW1 SW2 SW3 SW4 SW5 HV209 Test Circuits VPP –10V RL VIN = 10 VP–P @5MHz 10KΩ VOUT VOUT VOUT RL VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND KO = 20Log TON /TOFF Test Circuit DC Offset ON/OFF VOUT VIN OFF Isolation ∆VOUT VIN = 10 VP–P @5MHz VSIG 5V VOUT IID 50Ω 50Ω VPP VPP VDD VNN VNN GND 5V VSIG VPP VPP VDD VNN VNN GND KCR = 20Log Isolation Diode Current VOUT –VSPK 50Ω RL VPP VPP VDD VNN VNN GND VOUT VIN Crosstalk +VSPK 1KΩ 1000pF NC VNN 5V Output Voltage Spike 6 5V VPP VPP VDD VNN VNN GND Q = 1000pF x ∆VOUT Charge Injection 5V HV209 Logic Timing Waveforms DN DN+1 DATA IN 50% LE 50% DN-1 50% 50% t WLE t SD 50% CLOCK t SU 50% th t DO DATA OUT 50% t OFF OFF V OUT (TYP) ON CLR t ON 90% 10% 50% 50% t WCL 7 HV209 Block Diagram VPP VNN SW0 D LE CL High Voltage Level Translator Y0 SW0 SW1 D LE CL High Voltage Level Translator Y1 SW1 SW2 VDD D LE CL CLK DIN High Voltage Level Translator 6 BIT SHIFT REGISTER Y2 SW2 SW3 DOUT D LE CL GND High Voltage Level Translator Y3 SW3 SW4 D LE CL High Voltage Level Translator Y4 SW4 SW5 D LE CL High Voltage Level Translator Y5 SW5 RGND1 / RGND2 CL LE 8 HV209 Pin Configuration HV209 48-Lead LQFP/ TQFP (1.4mm) Pin Function Pin Function 1 N/C 25 SW5 2 SW0 26 Y5 3 Y0 27 SW5 4 SW0 28 N/C 5 N/C 29 SW3 6 SW2 30 Y3 7 Y2 31 SW3 8 SW2 32 N/C 9 N/C 33 SW1 10 SW4 34 Y1 11 Y4 35 SW1 12 SW4 36 N/C 13 N/C 37 RGND1 14 N/C 38 N/C 15 N/C 39 DOUT 16 VNN 40 VDD 17 N/C 41 DIN 18 N/C 42 CLR 19 N/C 43 LE 20 N/C 44 CLK 21 VPP 45 GND 22 N/C 46 N/C 23 N/C 47 N/C 24 N/C 48 RGND2 48-Lead LQFP/ TQFP (1.4mm) 9.00 ± 0.20 7.00 ± 0.20 0.22 ± 0.05 9.00 ± 0.20 7.00 ± 0.20 1.75 nom 48 1.75 nom 1 0.50 BSC Top View 1.60 max 0.09 - 0.20 1.40 ± 0.05 0.05 - 0.15 0O - 7O 0.45 - 0.75 Side View Linear dimensions in millimeters. Angular dimensions in degrees Pin 1 identifier located within the area indicated Corner shape may differ from . drawing. A062906 (4 places)