Holt HI-1568PCIT 5v monolithic dual transceiver Datasheet

HI-1567, HI-1568
MIL-STD-1553 / 1760
5V Monolithic Dual Transceivers
May 2003
DESCRIPTION
PIN CONFIGURATIONS
To minimize the package size for this function, the
transmitter outputs are internally connected to the receiver
inputs, so that only two pins are required for connection to
each coupling transformer. For designs requiring
independent access to transmitter and receiver 1553
signals, please refer to the HI-1569 data sheet.
FEATURES
! Compliant to MIL-STD-1553A & B,
MIL-STD-1760, ARINC 708A
! CMOS technology for low standby power
! Smallest footprint available in 44-pin plastic
chip-scale package with integral heatsink
! Less than 1.0W maximum power dissipation
! Radiation tolerant
! Also available in DIP and small outline
(ESOIC) package options
1568PCI
1568PCT
33 32 31 TXINHA
30 RXA
29 RXA
28 27 26 TXB
25 TXB
24 TXINHB
23 -
44 Pin Plastic 7mm x 7mm
Chip-scale package
VDDA 1
BUSA 2
BUSA 3
RXENA 4
GNDA 5
VDDB 6
BUSB 7
BUSB 8
RXENB 9
GNDB 10
1567PSI
1567PST
1567PSM
1568PSI
1568PST
1568PSM
20
19
18
17
16
15
14
13
12
11
TXA
TXA
TXINHA
RXA
RXA
TXB
TXB
TXINHB
RXB
RXB
20 Pin Plastic ESOIC - WB package
VDDA 1
20 TXA
BUSA 2
19 TXA
BUSA 3
RXENA 4
1567CDI
1567CDT
1567CDM
VDDB 6
BUSB 7
18 TXINHA
17 RXA
16 RXA
GNDA 5
BUSB 8
! Military processing options
! Industry standard pin configurations
(DS1567 Rev. I)
1567PCI
1567PCT
12
13
14
15
16
17
18
19
20
21
22
The receiver section of the each channel converts the 1553
bus bi-phase data to complementary CMOS / TTL data
suitable for inputting to a Manchester decoder. Each
receiver has a separate enable input which can be used to
force the output of the receiver to a logic 0 (HI-1567) or
logic 1 (HI-1568).
- 1
RXENA 2
GNDA 3
GNDA 4
GNDA 5
VDDB 6
VDDB 7
BUSB 8
BUSB 9
BUSB 10
BUSB 11
RXENB
GNDB
GNDB
GNDB
RXB
RXB
-
The transmitter section of each channel takes
complementary CMOS / TTL digital input data and converts
it to bi-phase Manchester encoded 1553 signals suitable
for driving the bus isolation transformer. Separate
transmitter inhibit control signals are provided for each
transmitter.
44 43 BUSA
42 BUSA
41 BUSA
40 BUSA
39 VDDA
38 VDDA
37 TXA
36 TXA
35 34 -
The HI-1567 and HI-1568 are low power CMOS dual
transceivers designed to meet the requirements of
MIL-STD-1553 /1760 specifications.
1568CDI
1568CDT
1568CDM
15 TXB
14 TXB
13 TXINHB
RXENB 9
12 RXB
GNDB 10
11 RXB
20 Pin Ceramic DIP package
HOLT INTEGRATED CIRCUITS
www.holtic.com
05/03
HI-1567, HI-1568
PIN DESCRIPTIONS
PIN
(DIP/ESOIC)
1
SYMBOL
FUNCTION
DESCRIPTION
VDDA
power supply
+5 volt power for channel A
2
BUSA
analog output
MIL-STD-1533 bus driver A, positive signal
3
BUSA
analog output
MIL-STD-1553 bus driver A, negative signal
4
RXENA
digital input
5
GNDA
power supply
Ground for channel A
6
VDDB
power supply
+5 volt power for channel B
7
BUSB
analog output
MIL-STD-1533 bus driver B, positive signal
8
BUSB
analog output
MIL-STD-1553 bus driver B, negative signal
Receiver A enable. If low, forces RXA and RXA low (HI-1567) or High (HI-1568)
9
RXENB
digital input
10
GNDB
power supply
Ground for channel B
11
RXB
digital output
Receiver B output, inverted
12
RXB
digital output
Receiver B output, non-inverted
13
TXINHB
digital input
Receiver B enable. If low, forces RXB and RXB low (HI-1567) or High (HI-1568)
Transmit inhibit, channel B. If high BUSB, BUSB disabled
14
TXB
digital input
Transmitter B digital data input, non-inverted
15
TXB
digital input
Transmitter B digital data input, inverted
16
RXA
digital output
Receiver A output, inverted
17
RXA
digital output
Receiver A output, non-inverted
18
TXINHA
digital input
Transmit inhibit, channel A. If high BUSA, BUSA disabled
19
TXA
digital input
Transmitter A digital data input, non-inverted
20
TXA
digital input
Transmitter A digital data input, inverted
FUNCTIONAL DESCRIPTION
The HI-1567 family of data bus transceivers contain differential voltage source drivers and differential receivers.
They are intended for applications using a MIL-STD-1553
A/B data bus. The device produces a trapezoidal output
waveform during transmission.
TRANSMITTER
Data input to the device’s transmitter section is from the
complementary CMOS /TTL inputs TXA/B and TXA/B.
The transmitter accepts Manchester II bi-phase data and
converts it to differential voltages on BUSA/B and BUSA/B.
The transceiver outputs are either direct or transformer
coupled to the MIL-STD-1553 data bus. Both coupling
methods produce a nominal voltage on the bus of 7.5 volts
peak to peak.
The transmitter is automatically inhibited and placed in the
high impedance state when both TXA/B and TXA/B are either at a logic “1” or logic “0” simultaneously. A logic “1” applied to the TXINHA/B input will force the transmitter to the
high impedance state, regardless of the state of TXA/B and
TXA/B.
RECEIVER
The receiver accepts bi-phase differential data from the
MIL-STD-1553 bus through the same direct or transformer
coupled interface as the transmitter. The receiver’s differential input stage drives a filter and threshold comparator
that produces CMOS/TTL data at the RXA/B and RXA/B
output pins.
Each set of receiver outputs can be independently forced
to a logic "0" (HI-1567) or logic “1” (HI-1568) by setting
RXENA or RXENB low.
MIL-STD-1553 BUS INTERFACE
A direct coupled interface (see Figure 2) uses a 1:2.5 ratio
isolation transformer and two 55 ohm isolation resistors
between the transformer and the bus.
In a transformer coupled interface (see Figure 3), the
transceiver is connected to a 1:1.79 isolation transformer
which in turn is connected to a 1:1.4 coupling transformer.
The transformer coupled method also requires two
coupling resistors equal to 75% of the bus characteristic
impedence (Zo) between the coupling transformer and the
bus.
HOLT INTEGRATED CIRCUITS
2
HI-1567, HI-1568
Data Bus
Each Channel
TRANSMITTER
Isolation
Transformer
Coupler
Network
BUSA/B
TXA/B
Transmit
Logic
Direct or
Transformer
Slope
Control
TXA/B
BUSA/B
TXINHA/B
RECEIVER
RXA/B
Input
Filter
Receive
Logic
RXA/B
Comparator
RXENA/B
Figure 1. Block Diagram
TRANSMIT WAVEFORM - EXAMPLE PATTERN
TXA/B
TXA/B
BUSA/B - BUSA/B
RECEIVE WAVEFORMS - EXAMPLE PATTERN
Vin
(Line to Line)
RXA/B
RXA/B
HOLT INTEGRATED CIRCUITS
3
HI-1567, HI-1568
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD)
Logic input voltage range
Supply Voltage
-0.3 V to +7 V
VDD....................................... 5V... ±5%
-0.3 V dc to +5.5 V
Receiver differential voltage
10 Vp-p
Temperature Range
Driver peak output current
+1.0 A
Power dissipation at 25°C
ceramic DIL, derate
1.0 W
7mW/°C
Solder Temperature
Industrial Screening.........-40°C to +85°C
Hi-Temp Screening........-55°C to +125°C
Military Screening..........-55°C to +125°C
NOTE:
Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to the
device. These are stress ratings only. Operation
at the limits is not recommended.
275°C for 10 sec.
Junction Temperature
175°C
Storage Temperature
-65°C to +150°C
DC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
4.75
5
5.25
V
Operating Voltage
VDD
Total Supply Current
ICC1
Not Transmitting
14
22
mA
ICC2
Transmit one channel @
50% duty cycle
200
340
mA
ICC3
Transmit one channel @
100% duty cycle
400
550
mA
0.11
W
0.95
W
Power Dissipation
PD1
Not Transmitting
PD2
Transmit one channel @
100% duty cycle
0.70
Min. Input Voltage
(HI)
VIH
Digital inputs
Max. Input Voltage
(LO)
VIL
Digital inputs
Min. Input Current
(HI)
IIH
VIH = 4.9V, Digital inputs
Max. Input Current
(LO)
IIL
VIL = 0.1V, Digital inputs
-20
µA
Min. Output Voltage
(HI)
VOH
IOUT = -0.4mA, Digital outputs
2.7
V
(LO)
VIH
IOUT = 4.0mA, Digital outputs
Max. Output Voltage
RECEIVER
2.0
1.4
1.4
V
0.8
V
20
µA
0.4
V
(Measured at Point “AD“ in Figure 2 unless otherwise specified)
Input resistance
RIN
Differential
Input capacitance
CIN
Differential
Common mode rejection ratio
CMRR
Input Level
VIN
Input common mode voltage
Threshold Voltage - Direct-coupled
Detect
VTHD
VTHND
Threshold Voltage - Transformer-coupled Detect
VTHD
No Detect
VTHND
Kohm
5
40
Differential
pF
dB
9
Vp-p
-5.0
5.0
V-pk
1 Mhz Sine Wave
(Measured at Point “AD“ in Figure 2)
1.15
20.0
Vp-p
0.28
Vp-p
1 MHz Sine Wave
(Measured at Point “AT“ in Figure 3)
0.86
14.0
Vp-p
0.20
Vp-p
VICM
No Detect
20
HOLT INTEGRATED CIRCUITS
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HI-1567, HI-1568
DC ELECTRICAL CHARACTERISTICS (cont.)
VDD = 5.0V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
TRANSMITTER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
7.0
9.0
Vp-p
20.0
27.0
Vp-p
10.0
mVp-p
-90
90
mV
-250
250
mV
(Measured at Point “AD” in Figure 2 unless otherwise specified)
Output Voltage
Direct coupled
VOUT
Transformer coupled
VOUT
Output Noise
35 ohm load
(Measured at Point “AD“ in Figure 2)
70 ohm load
(Measured at Point “AT“ in Figure 3)
VON
Output Dynamic Offset Voltage
Direct coupled
VDYN
Transformer coupled
VDYN
Differential, inhibited
35 ohm load
(Measured at Point “AD“ in Figure 2)
70 ohm load
(Measured at Point “AT“ in Figure 3)
Output resistance
ROUT
Differential, not transmitting
Output Capacitance
COUT
1 MHz sine wave
10
Kohm
15
pF
AC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, GND = 0V, TA =Operating Temperature Range (unless otherwise specified).
PARAMETER
RECEIVER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
450
ns
40
ns
150
ns
(Measured at Point “AD” in Figure 2)
Receiver Delay
tDR
Receiver Enable Delay
From input zero crossing to RXA/B or RXA/B
From RXENA/B rising or falling edge to
tREN
RXA/B or RXA/B
TRANSMITTER
(Measured at Point “AD” in Figure 2)
Driver Delay
tDT
TXA/B, TXA/B to BUSA/B, BUSA/B
Rise time
tr
35 ohm load
100
300
ns
Fall Time
tf
35 ohm load
100
300
ns
tDI-H
Inhibited output
100
ns
tDI-L
Active output
150
ns
Inhibit Delay
TRANSMITTER
1:2.5
55 W
BUSA/B
TXA/B
35 W
TXA/B
BUSA/B
TXINHA/B
55 W
Isolation
Transformer
Point “AD“
55 W
RECEIVER
2.5:1
RXA/B
Point “AD“
35 W
55 W
RXA/B
Isolation
Transformer
RXENA/B
Figure 2. Direct Coupled Test Circuits
HOLT INTEGRATED CIRCUITS
5
HI-1567, HI-1568
TRANSMITTER
Point
“AT”
1:1.79
52.5 W
(.75 Zo)
1:1.4
BUSA/B
TXA/B
35 W (.5 Zo)
TXA/B
BUSA/B
TXINHA/B
52.5 W
(.75 Zo)
Isolation
Transformer
1.4:1
52.5 W
(.75 Zo)
Coupling
Transformer
Point
“AT” 1.79:1
RECEIVER
RXA/B
35 W (.5 Zo)
52.5 W
(.75 Zo)
RXA/B
Coupling
Transformer
Isolation
Transformer
RXENA/B
Figure 3. Transformer Coupled Test Circuits
HEAT SINK - ESOIC PACKAGE
Both the HI-1567PSI/T and HI-1568PSI/T use a 20-pin
thermally enhanced SOIC package. The package
includes a metal heat sink located on the bottom surface
of the device. This heat sink should be soldered down to
the printed circuit board for optimum thermal dissipation.
The heat sink is electrically connected to the VDD supply
of the chip and therefore must be isolated from all other
signals.
THERMAL CHARACTERISTICS
PART NUMBER
PACKAGE STYLE
HI-1567PSI / T / M
20-pin Thermally
enhanced plastic
SOIC (ESOIC)
HI-1568PSI / T / M
HI-1567CDI / T / M
HI-1568CDI / T / M
HI-1567PCI / T
HI-1568PCI / T
JUNCTION TEMPERATURE
CONDITION
ØJA
Heat sink
unsoldered
54°C/W
62°C
122°C
162°C
Heat sink
soldered
47°C/W
57°C
117°C
157°C
20-pin Ceramic
side-brazed DIP
Socketed
62°C/W
69°C
129°C
169°C
44-pin Plastic chipscale package
Heat sink
unsoldered
49°C/W
59°C
119°C
159°C
TA=25°C
TA=85°C TA=125°C
Data taken at VDD=5.0V, continuous transmission at 1Mbit/s, single transmitter enabled.
RADIATION TOLERANCE
APPLICATIONS NOTE
The HI-1567 has been characterized for total dose
radiation performance in accordance with MIL-STD-883
method 1019. The part meets all data sheet parameters
after exposure to 25 KRad(Si).
Holt Applications Note AN-500 provides circuit design
notes regarding the use of Holt's family of MIL-STD-1553
transceivers. Layout considerations, as well as
recommended interface and protection components are
included.
HOLT INTEGRATED CIRCUITS
6
HI-1567, HI-1568
ORDERING INFORMATION
PART
NUMBER
IDLE
STATE
PACKAGE
DESCRIPTION
TEMPERATURE
RANGE
PROCESS
FLOW
BURN
IN
LEAD
FINISH
HI-1567PSI
0
20 PIN PLASTIC ESOIC - WB
-40°C TO +85°C
I
NO
SOLDER
HI-1567PST
0
20 PIN PLASTIC ESOIC - WB
-55°C TO +125°C
T
NO
SOLDER
HI-1567PSM
0
20 PIN PLASTIC ESOIC - WB
-55°C TO +125°C
M
YES
SOLDER
HI-1567CDI
0
20 PIN CERAMIC SIDE BRAZED DIP
-40°C TO +85°C
I
NO
GOLD
HI-1567CDT
0
20 PIN CERAMIC SIDE BRAZED DIP
-55°C TO +125°C
T
NO
GOLD
HI-1567CDM
0
20 PIN CERAMIC SIDE BRAZED DIP
-55°C TO +125°C
M
YES
SOLDER
HI-1567PCI
0
44 PIN CHIP SCALE PACKAGE
-40°C TO +85°C
I
NO
SOLDER
HI-1567PCT
0
44 PIN CHIP SCALE PACKAGE
-55°C TO +125°C
T
NO
SOLDER
HI-1568PSI
1
20 PIN PLASTIC ESOIC - WB
-40°C TO +85°C
I
NO
SOLDER
HI-1568PST
1
20 PIN PLASTIC ESOIC - WB
-55°C TO +125°C
T
NO
SOLDER
HI-1568PSM
1
20 PIN PLASTIC ESOIC - WB
-55°C TO +125°C
M
YES
SOLDER
HI-1568CDI
1
20 PIN CERAMIC SIDE BRAZED DIP
-40°C TO +85°C
I
NO
GOLD
HI-1568CDT
1
20 PIN CERAMIC SIDE BRAZED DIP
-55°C TO +125°C
T
NO
GOLD
HI-1568CDM
1
20 PIN CERAMIC SIDE BRAZED DIP
-55°C TO +125°C
M
YES
SOLDER
HI-1568PCI
1
44 PIN CHIP SCALE PACKAGE
-40°C TO +85°C
I
NO
SOLDER
HI-1568PCT
1
44 PIN CHIP SCALE PACKAGE
-55°C TO +125°C
T
NO
SOLDER
Legend: ESOIC - Thermally Enhanced Small Outline Package (SOIC w/built-in heat sink)
WB
- Wide Body
RECOMMENDED TRANSFORMERS
The HI-1567 and HI-1568 transceivers have been
characterized for compliance with the electrical
requirements of MIL-STD-1553 when used with the
following transformers. Holt recommends the Premier
Magnetics parts as offering the best combination of
electrical performance, low cost and small footprint.
MANUFACTURER
Technotrol
Premier Magnetics
Technotrol
Premier Magnetics
PART NUMBER
APPLICATION
TURNS RATIO(S)
DIMENSIONS
TL1553-45
Isolation
Dual tapped 1:1.79, 1:2.5
.630 x 630 x .155 inches
PM-DB2725EX
Isolation
Dual tapped 1:1.79, 1:2.5
.500 x .500 x .375 inches
TQ1553-2
Stub coupling
1:1.4
.625 x .625 x .250 inches
PM-DB2702
Stub coupling
1:1.4
.625 x .500 x .250 inches
HOLT INTEGRATED CIRCUITS
7
PACKAGE DIMENSIONS
inches (millimeters)
20-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB
(Wide Body, Thermally Enhanced)
.0105 ± .0015
(.2667 ± .0381)
.5035 ± .0075
(12.789 ± .191)
.4065 ± .0125
(10.325 ± .318)
Top View
Package Type: 24HEW
Heat sink stud on
bottom of package.
.300
TYP.
(7.620)
Bottom
View
.215
TYP.
(5.461)
.296 ± .003
(7.518 ± .076)
.025
Min..
(.635)
SEE DETAIL A
.018
TYP.
(.457)
.025
Min..
(.635)
.090 ± .010
(2.286 ± .254)
0° to 8°
.050
TYP
(1.27)
.033 ± .017
(.838 ± .432)
.0075 ± .0035
(.191 ± .889)
DETAIL A
20-PIN CERAMIC SIDE-BRAZED DIP
PACKAGE TYPE: 20C
1.000 ± .010
(25.400 ± .254)
.310 ± .010
(7.874 ± .254)
.050 TYP.
(1.270 TYP.)
.200 MAX.
(5.080 MAX.)
.125 MIN.
(3.175 MIN.)
.300 ± .010
(7.620 ± .254)
.085 ± .009
(2.159 ± .229)
.017 ± .002
(.432 ± .051)
.100 ± .005
(2.540 ± .127)
HOLT INTEGRATED CIRCUITS
8
.010 + .002/- .001
(.254 + .051/- .025)
PACKAGE DIMENSIONS
millimeters
44-PIN PLASTIC CHIP-SCALE PACKAGE
Heat sink stud on
bottom of package.
7.00 ± .10
5.65 ± .15
0.50
7.00 ± .10
5.65 ± .15
0.25 typ
0.40 ± .05
0.90 ± .10
0.2 typ
HOLT INTEGRATED CIRCUITS
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