NB7L86M 2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination The NB7L86M is a multi−function differential Logic Gate, which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaComm family of high performance Silicon Germanium products. The NB7L86M is an ultra−low jitter multi−logic gate with a maximum data rate of 12 Gb/s and input clock frequency of 8 GHz suitable for Data Communication Systems, Telecom Systems, Fiber Channel, and GigE applications. Differential inputs incorporate internal 50 W termination resistors and accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVCMOS, LVTTL, CML, or LVDS. The differential 16 mA CML output provides matching internal 50 W termination, and 400 mV output swing when externally terminated 50 W to VCC. The device is housed in a low profile 3x3 mm 16−pin QFN package. Application notes, models, and support documentation are available on www.onsemi.com. http://onsemi.com MARKING DIAGRAM* 16 1 QFN−16 MN SUFFIX CASE 485G A L Y W G Features • • • • • • • • • • • • Maximum Input Clock Frequency up to 8 GHz Maximum Input Data Rate up to 12 Gb/s Typical < 0.5 ps of RMS Clock Jitter = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. < 10 ps of Data Dependent Jitter ORDERING INFORMATION 30 ps Typical Rise and Fall Times 90 ps Typical Propagation Delay 2 ps Typical Within Device Skew Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V CML Output Level (400 mV Peak−to−Peak Output) Differential Output 50 W Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP and SG Devices Pb−Free Packages are Available VTD0 D0 NB7L 86M ALYWG G See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. 50 W D0 VTD0 VTD1 Q 50 W Q 50 W D1 D1 VTD1 50 W 50 W 50 W SEL VTSEL SEL Figure 1. Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 3 1 Publication Order Number: NB7L86M/D NB7L86M D0 VTD0 Exposed Pad (EP) VTD0 D0 16 VCC 1 SEL 2 15 14 13 12 VEE 11 Q NB7L86M SEL 3 10 Q VTSEL 4 9 VCC 5 6 7 8 D1 VTD1 VTD1 D1 Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1, 9 VCC Power Supply 2 SEL LVPECL, CML, LVCMOS, LVTTL, LVDS Input Inverted differential select logic input. 3 SEL LVPECL, CML, LVCMOS, LVTTL, LVDS Input Non−inverted differential select logic Input. 4 VTSEL − Common internal 50 W termination pin for SEL/SEL. See Table 6. (Note 1) 5 VTD1 − Internal 50 W termination pin for D1. See Table 6. (Note 1) 6 D1 LVPECL, CML, LVCMOS, LVTTL, LVDS Input Non−inverted differential clock/data input D1. (Note 1) 7 D1 LVPECL, CML, LVCMOS, LVTTL, LVDS Input Inverted differential clock/data input D1. (Note 1) 8 VTD1 − 10 Q CML Output Non−inverted output with internal 50 W source termination resistor. (Note 2) 11 Q CML Output Inverted output with internal 50 W source termination resistor. (Note 2) 12 VEE Power Supply 13 VTD0 − 14 D0 LVPECL, CML, LVCMOS, LVTTL, LVDS Input Non−inverted differential clock/data input D0. (Note 1) 15 D0 LVPECL, CML, LVCMOS, LVTTL, LVDS Input Non−inverted differential clock/data input D0. (Note 1) 16 VTD0 − Internal 50 W termination pin for D0. (Note 1) − EP − Exposed Pad. Thermal pad on the package bottom must be attached to a heatsinking conduit to improve heat transfer. It is recommended to connect the EP to the lower potential (VEE). Positive supply voltage. All VCC pins must be externally connected to power supply to guarantee proper operation. Internal 50 W termination pin for D1. See Table 6. (Note 1) Negative supply voltage. All VEE pins must be externally connected to power supply to guarantee proper operation. Internal 50 W termination pin for D0. (Note 1) 1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage or left open, and if no signal is applied on Dx, Dx, SEL and SEL then the device will be susceptible to self−oscillation. 2. CML output require 50 W receiver termination resistor to VCC for proper operation. http://onsemi.com 2 NB7L86M 50 W VTD0 VT or VBB Table 2. AND/NAND TRUTH TABLE (Note 3) ∝ b ∝ AND b D0 D1 SEL Q 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 D0 D0 VCC 50 W VTD0 Q 50 W VTD1 Q RD D1 3. D0, D1, SEL are complementary of D0, D1, SEL unless specified otherwise. D1 VTD1 50 W 50 W 50 W VEE VCC VTSEL b SEL SEL Figure 3. Configuration for AND/NAND Function VTD0 50 W D0 Table 3. OR/NOR TRUTH TABLE (Note 4) D0 VTD0 VTD1 50 W Q 50 W Q b or b D0 D1 SEL Q 0 1 0 0 0 1 1 1 VCC D1 1 1 0 1 VT or VBB D1 1 1 1 1 VTD1 50 W 50 W 4. D0, D1, SEL are complementary of D0, D1, SEL unless specified otherwise. 50 W VTSEL b SEL SEL Figure 4. Configuration for OR/NOR Function VTD0 50 W D0 Table 4. XOR/XNOR TRUTH TABLE (Note 5) D0 VTD0 VTD1 VTD1 50 W Q 50 W Q 50 W b XOR b D0 D1 SEL Q 0 1 0 0 D1 0 1 1 1 D1 1 0 0 1 1 0 1 0 50 W 50 W 5. D0, D1, SEL are complementary of D0, D1, SEL unless specified otherwise. VTSEL SEL b SEL Figure 5. Configuration for XOR/XNOR Function http://onsemi.com 3 NB7L86M VTD0 50 W D0 D0 Table 5. 2:1 MUX TRUTH TABLE (Note 6) VTD0 VTD1 50 W Q SEL 50 W Q 1 D1 0 D0 D1 6. D0, D1, SEL are complementary of D0, D1, SEL unless specified otherwise. D1 VTD1 Q 50 W 50 W SEL 50 W VTSEL SEL Figure 6. Configuration for 2:1 MUX Function Table 6. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 7) QFN−16 Flammability Rating Oxygen Index: 28 to 34 > 1500 V > 50 V > 500 V Pb Pkg Pb−Free Pkg Level 1 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 400 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 7. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 7. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units 3.6 V 3.6 V 2.8 |VCC − VEE| V V VCC Positive Power Supply VEE = 0 V VI Input Voltage VEE = 0 V VINPP Differential Input Voltage |D − D| VCC − VEE ≥ VCC − VEE < IIN Input Current Through RT (50 W Resistor) Continuous Surge 25 50 mA mA Iout Output Current Continuous Surge 25 50 mA mA TA Operating Temperature Range QFN−16 −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 8) 0 lfpm 500 lfpm QFN−16 QFN−16 42 36 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 8) QFN−16 3 to 4 °C/W Tsol Wave Solder 265 265 °C VEE ≤ VI ≤ VCC 2.8 V 2.8 V Pb Pb−Free Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 8. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 4 NB7L86M Table 8. DC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C) Characteristic Symbol Min Typ Max Unit 38 50 mA ICC Power Supply Current (Inputs and Outputs Open) VOH Output HIGH Voltage (Notes 9 and 10) VCC − 60 VCC − 30 VCC mV VOL Output LOW Voltage (Notes 9 and 10) VCC − 460 VCC − 400 VCC − 310 mV 1125 VCC − 75 mV Differential Input Driven Single−Ended (see Figures 16 & 18) Vth Input Threshold Reference Voltage Range (Note 11) VIH Single−ended Input HIGH Voltage (Note 12) Vth + 75 VCC mV VIL Single−ended Input LOW Voltage (Note 12) VEE VCC − 150 mV Differential Inputs Driven Differentially (see Figures 17 & 19) VIHD Differential Input HIGH Voltage 1200 VCC mV VILD Differential Input LOW Voltage VEE VCC − 75 mV VCMR Input Common Mode Range (Differential Configuration) 1163 VCC – 38 mV VID Differential Input Voltage (VIHD − VILD) 75 2500 mV IIH Input HIGH Current D0/D0/D1/D1 SEL/SEL 0 0 50 20 150 150 mA IIL Input LOW Current D0/D0/D1/D1 SEL/SEL −50 −50 50 20 100 100 mA RTIN Internal Input Termination Resistor 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 W RTemp Coef Internal I/O Termination Resistor Temperature Coefficient 6.38 mW/°C NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. CML outputs require 50 W receiver termination resistors to VCC for proper operation. 10. Input and output parameters vary 1:1 with VCC. 11. Vth is applied to the complementary input when operating in single−ended mode. 12. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC. http://onsemi.com 5 NB7L86M Table 9. AC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V; Note 13) Symbol Characteristic Min Typ Min Typ Min Typ VOUTPP Output Voltage Amplitude (@VINPPmin) fin ≤ 4 GHz (See Figure 7) fin ≤ 8 GHz 240 125 350 230 240 125 350 230 240 125 350 230 mV fdata Maximum Operating Data Rate 10.7 12 10.7 12 10.7 12 Gb/s tPLH, tPHL Propagation Delay to Output Differential @ 1 GHz (See Figure 7) 70 110 90 135 120 180 70 110 90 135 120 180 70 110 90 135 120 180 ps tSKEW Duty Cycle Skew (Note 14) Device−to−Device Skew (Note 15) 2.0 5.0 10 20 2.0 5.0 10 20 2.0 5.0 10 20 ps tJITTER RMS Random Clock Jitter (Note 16) 0.2 0.2 2.0 4.0 0.5 0.5 8.0 10 0.2 0.2 2.0 4.0 0.5 0.5 8.0 10 0.2 0.2 2.0 4.0 0.5 0.5 8.0 10 ps 400 2500 400 2500 400 2500 mV 35 60 35 60 35 60 ps −40_C Dx/Dx to Q/Q SEL/SEL to Q/Q Peak/Peak Data Dependent Jitter (Note 17) VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 18) tr tf Output Rise/Fall Times @ 1 GHz (20% − 80%) fin = 4 GHz fin =8 GHz fdata = 5 Gb/s fdata =10 Gb/s 75 Q, Q 25_C Max 75 Unit 85_C Max 75 Max NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. Measured by forcing VINPP (TYP) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% − 80%). 14. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @1 GHz. 15. Device to device skew is measured between outputs under identical transition @ 1 GHz. 16. Additive RMS jitter with 50% duty cycle clock signal. 17. Additive peak−to−peak data dependent jitter with input NRZ data (PRBS 2^23−1). 18. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUDE (mV) 500 VCC − VEE = 3.3 V 400 VCC − VEE = 2.5 V 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 INPUT FREQUENCY (GHz) Figure 7. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 6 Voltage (45 mV/div) Voltage (45 mV/div) NB7L86M DDJ = 1.2 ps* DDJ = 1.2 ps* Time (72 ps/div) Time (72 ps/div) Figure 8. Typical Output Waveform at 2.488 Gb/s with PRBS 2^23−1 (Vinpp = 75 mV) Figure 9. Typical Output Waveform at 2.488 Gb/s with PRBS 2^23−1 (Vinpp = 400 mV) Voltage (45 mV/div) Voltage (45 mV/div) *Input signal DDJ = 10 ps DDJ = 2 ps** DDJ = 2 ps** Time (20 ps/div) Time (20 ps/div) Figure 10. Typical Output Waveform at 10 Gb/s with PRBS 2^23−1 (Vinpp = 75 mV) Figure 11. Typical Output Waveform at 10 Gb/s with PRBS 2^23−1 (Vinpp = 400 mV) Voltage (45 mV/div) Voltage (45 mV/div) **Input signal DDJ = 12 ps DDJ = 4 ps*** DDJ = 4 ps*** Time (16 ps/div) Time (16 ps/div) Figure 12. Typical Output Waveform at 12 Gb/s with PRBS 2^23−1 (Vinpp = 75 mV) Figure 13. Typical Output Waveform at 12 Gb/s with PRBS 2^23−1 (Vinpp = 400 mV) ***Input signal DDJ = 14 ps http://onsemi.com 7 NB7L86M D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 14. AC Reference Measurement VCC 50 W 50 W Q D Z = 50 W Driver Device Receiver Device Q D Z = 50 W Figure 15. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 − Termination of ECL Logic Devices) D D D D Vth Vth Figure 16. Differential Input Driven Single−Ended VCC Vthmax Vth VCC VIHmax VILmax D Vthmin GND Figure 17. Differential Inputs Driven Differentially VIHDmax VCMmax VIH Vth VIL VCMR D D VIHmin VILmin VCMmax GND Figure 18. Vth Diagram VILDmax VID = VIHD − VILD VIHDtyp VILDtyp VIHDmin VILDmin Figure 19. VCMR Diagram http://onsemi.com 8 NB7L86M VCC 50 W 50 W Q Q 16 mA VEE Figure 20. CML Output Structure Table 10. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTD0, VTD0, VTD1, VTD1, VTSEL to VCC LVDS Connect VTD0, VTD0 together for D0 input. Connect VTD1, VTD1 together for D0 input. Leave VTSEL open for SEL input. AC−COUPLED Bias VTD0, VTD0, VTSEL and VTD1, VTD1 Inputs within (VCMR) Common Mode Range RSECL, LVPECL Standard ECL Termination Techniques. See AND8020/D. LVTTL, LVCMOS An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. http://onsemi.com 9 NB7L86M Examples interfaces are illustrated below in a 50 W environment (Z = 50 W). Application Information All inputs can accept PECL, CML, and LVDS signal levels. The input voltage can range from VCC to 1.2 V. VCC 50 W VCC 50 W Q D Z NB7L86M VCC VTD Z Q VCC D 50 W NB7L86M 50 W VTD VEE VEE Figure 21. CML to CML Interface VCC VCC 50 W PECL Driver VCC VBIAS 50 W RT Recommended RT Values 3.3 V 150 W VEE 2.5 V 80 W VTD D RT VBias 50 W NB7L86M Z RT 5.0 V 290 W D Z 50 W VTD VEE VEE Figure 22. PECL to CML Receiver Interface VCC VCC D Z VTD LVDS Driver 50 W NB7L86M Z D 50 W VTD VEE VEE Figure 23. LVDS to CML Receiver Interface http://onsemi.com 10 NB7L86M ORDERING INFORMATION Package Shipping † QFN−16 123 Units/Rail NB7L86MMNG QFN−16 (Pb−Free) 123 Units/Rail NB7L86MMNR2 QFN−16 3000 Tape & Reel QFN−16 (Pb−Free) 3000 Tape & Reel Device NB7L86MMN NB7L86MMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 11 NB7L86M PACKAGE DIMENSIONS 16 PIN QFN MN SUFFIX CASE 485G−01 ISSUE B ÇÇÇ ÇÇÇ ÇÇÇ D PIN 1 LOCATION 0.15 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG A B E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW SEATING PLANE A1 C D2 16X L 5 NOTE 5 16X e 0.575 0.022 4 9 1 12 E2 K 16 16X SOLDERING FOOTPRINT* 3.25 0.128 0.30 0.012 EXPOSED PAD 1.50 0.059 3.25 0.128 e 13 b 0.10 C A B 0.05 C EXPOSED PAD 8 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 −−− 0.30 0.50 BOTTOM VIEW 0.50 0.02 NOTE 3 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 12 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NB7L86M/D