MOTOROLA MPC962308DT-5HR2 3.3 v zero delay buffer Datasheet

Freescale Semiconductor, Inc.
MOTOROLA
Order number: MPC962308
Rev 3, 08/2004
SEMICONDUCTOR TECHNICAL DATA
3.3 V Zero Delay Buffer
The MPC962308 is a 3.3 V Zero Delay Buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom and other
high-performance applications. The MPC962308 uses an internal PLL and an
external feedback path to lock its low-skew clock output phase to the reference
clock phase, providing virtually zero propagation delay. The input-to-output
skew is guaranteed to be less than 250 ps and output-to-output skew is
guaranteed to be less than 200 ps.
MPC962308
Features
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1:8 outputs LVCMOS zero-delay buffer
Zero input-output propagation delay, adjustable by the capacitive load on
FBK input
Multiple Configurations, see Table 2. Available MPC962308
Configurations
Multiple low-skew outputs
200 ps max output-output skew
700 ps max device-device skew
Two banks of four outputs, output tristate control by two select inputs
Supports a clock I/O frequency range of 10 MHz to 133 MHz
Low jitter, 200 ps max cycle-cycle (-1, -1H, -4, -5H)
±250 ps static phase offset (SPO)
16-pin SOIC package or 16-pin TSSOP package
Single 3.3 V supply
Ambient temperature range: –40°C to +85°C
Compatible with the CY2308 and CY23S08
Spread spectrum compatible
D SUFFIX
16-LEAD SOIC PACKAGE
CASE 751B-05
DT SUFFIX
16-LEAD TSSOP PACKAGE
CASE 948F-01
Functional Description
The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in Table 1. Select
Input Decoding. Bank B can be tristated if all of the outputs are not required. The select inputs also allow the input clock to be directly
applied to the output for chip and system testing purposes. The MPC962308 PLL enters a power down state when there are no rising
edges on the REF input. During this state, all of the outputs are in tristate and there is less than 50 µA of current draw. The PLL shuts
down in two additional cases explained in Table 1. Select Input Decoding.
Multiple MPC962308 devices can accept and distribute the same input clock throughout the system. In this situation, the difference
between the output skews of two devices will be less than 700 ps.
The MPC962308 is available in five different configurations as shown in Table 2. Available MPC962308 Configurations. In the
MPC962308-1, the reference frequency is reproduced by the PLL and provided at the outputs. A high drive version of this configuration, the MPC962308-1H, is available to provide faster rise and fall times of the device.
The MPC962308-2 provides 2X and 1X the reference frequency at the output banks. In addition, the MPC962308-3 provides 4X
and 2X the reference frequency at the output banks. The output banks driving the feedback will determine the different configurations
of the above devices. The MPC962308-4 provides outputs 2X the reference frequency.The MPC962308-5H is a high drive version
with outputs of REF/2.
The MPC962308 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS
signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines on the
incident edge. Depending on the configuration, the device is offered in a 16-lead SOIC or 16-lead TSSOP package.
© Motorola, Inc. 2004
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MPC962308
Block Diagram
/2
REF
Pin Configuration
MUX
/2
CLKA1
CLKA2
Extra Divider (-3, -4)
Extra Divider (-5H)
S2
S1
SOIC/TSSOP
Top View
FBK
PLL
CLKA3
CLKA4
Select Input
Decoding
/2
CLKB1
CLKB2
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
CLKB3
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Extra Divider (-2, -3)
CLKB4
Table 1. Select Input Decoding
S2
S1
CLOCK A1—A4
CLOCK B1—B4
Output Source
PLL Shutdown
0
0
Three-State
Three-State
PLL
Y
0
1
Driven
Three-State
PLL
N
1
0
Driven1
Driven1
Reference
Y
1
1
Driven
Driven
PLL
N
1. Outputs inverted on MPC962308-2 in bypass mode, S2=1 and S1=0.
Table 2. Available MPC962308 Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
MPC962308-1
Bank A or Bank B
Reference
Reference
MPC962308-1H
Bank A or Bank B
Reference
Reference
MPC962308-2
Bank A
Reference
Reference/2
MPC962308-2
Bank B
2 X Reference
Reference
MPC962308-3
Bank A
2 X Reference
Reference or Reference[1]
MPC962308-3
Bank B
4 X Reference
2 X Reference
MPC962308-4
Bank A or Bank B
2 X Reference
2 X Reference
MPC962308-5H
Bank A or Bank B
Reference /2
Reference /2
1. Output phase is indeterminate (0° or 180° from input clock). If phase integrity is required, use the MPC962308-2.
TIMING SOLUTIONS
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Table 3. Pin Description
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Pin
Signal
Description
1
REF
Input reference frequency, 5 V tolerant input
2
CLKA12
Clock output, Bank A
3
CLKA22
Clock output, Bank A
4
VDD
3.3 V supply
5
GND
1
Ground
6
2
CLKB1
Clock output, Bank B
7
CLKB22
Clock output, Bank B
8
S23
Select input, bit 2
9
S13
Select input, bit 1
10
CLKB32
Clock output, Bank B
11
CLKB42
Clock output, Bank B
12
GND
Ground
13
VDD
3.3 V supply
14
CLKA32
Clock output, Bank A
15
CLKA42
Clock output, Bank A
16
FBK
PLL feedback input
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
Table 4. Maximum Ratings
Characteristics
Value
Unit
–0.5 to +3.9
V
–0.5 to VDD+0.5
V
DC Input Voltage REF
–0.5 to 5.5
V
Storage Temperature
–65 to +150
°C
150
°C
>2000
V
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
Junction
Static Discharge Voltage (per MIL-STD-883, Method 3015)
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Table 5. Operating Conditions for MPC962308-X Industrial Temperature Devices
Parameter
Min
Max
Unit
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
–40
85
°C
CL
Load Capacitance, below 100 MHz
30
pF
Load Capacitance, from 100 MHz to 133 MHz
15
pF
7
pF
Max
Unit
0.8
V
VDD
CIN
Description
Input
Capacitance1
1. Applies to both REF clock and FBK.
Freescale Semiconductor, Inc...
Table 6. Electrical Characteristics for MPC962308-X Industrial Temperature Devices1
Parameter
Description
Test Conditions
Min
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
50.0
µA
IIH
Input HIGH Current
VIN = VDD
100.0
µA
VOL
Output LOW Voltage2
IOL = 8 mA (-1, -2, -3, -4)
IOL = 12 mA (-1H, -5H)
0.4
V
VOH
Output HIGH Voltage2
IOH = -8 mA (-1, -2, -3, -4)
IOH = -12 mA (-1H, -5H)
Power Down Supply Current
REF = 0 MHz
25.0
µA
Supply Current
Unloaded outputs, 100 MHz,
Select inputs at VDD or GND
45.0
mA
70(-1H, -5H)
mA
Unloaded outputs, 66-MHz REF
(-1, -2, -3, -4)
35.0
mA
Unloaded outputs, 35-MHz REF
(-1, -2, -3, -4)
20.0
mA
IDD (PD mode)
IDD
2.0
V
2.4
V
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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Table 7. Switching Characteristics for MPC962308-X Industrial Temperature Devices1
Parameter
Max
Unit
t1
Output Frequency
30-pF load, All devices
10
100
MHz
t1
Output Frequency2
20-pF load, -1H, -5H devices
10
133.3
MHz
t1
Output Frequency2
15-pF load, -1, -2, -3, -4 devices
10
133.3
MHz
Duty Cycle2 = t2 ÷ t1
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4 V, FOUT =66.66 MHz
40.0
60.0
%
Duty Cycle2 = t2 ÷ t1
(-1, -2, -3, -4, -1H, -5H)
Measured at 1.4 V, FOUT <50.0 MHz
45.0
55.0
%
Rise Time2
(-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V,
2.50
ns
Rise Time2
(-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V,
1.50
ns
Rise Time2
(-1H, -5H)
Measured between 0.8 V and 2.0 V,
1.50
ns
Fall Time2
(-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V,
2.50
ns
Fall Time2
(-1, -2, -3, -4)
Measured between 0.8 V and 2.0 V,
1.50
ns
Fall Time2
(-1H, -5H)
Measured between 0.8 V and 2.0 V,
1.25
ns
Output-to-Output Skew on
All outputs equally loaded
200
ps
Output-to-Output Skew
(-1H, -5H)
All outputs equally loaded
200
ps
Output Bank A to Output
Bank B Skew (-1, -4, -5H)
All outputs equally loaded
200
ps
Output Bank A to Output
Bank B Skew (-2, -3)
All outputs equally loaded
400
ps
t6
Delay, REF Rising Edge to
Measured at VDD/2
0
±250
ps
t7
Device-to-Device Skew2
Measured at VDD/2 on the FBK pins of devices
0
700
ps
Freescale Semiconductor, Inc...
t3
t4
Name
t8
Min
Typ
30-pF load
15-pF load
30-pF load
15-pF load
30-pF load
30-pF load
15-pF load
30-pF load
same Bank (-1, -2, -3, -4)2
t5
Test Conditions
FBK Rising Edge2
2
Output Slew Rate
Measured between 0.8 V and 2.0 V on -1H,
1
V/ns
-5H device using Test Circuit # 2
tJ
Cycle-to-Cycle Jitter
Measured at 66.67 MHz, loaded outputs,
(-1, -1H, -4, -5H)2
15-pF load
Measured at 66.67 MHz, loaded outputs,
200
ps
200
ps
100
ps
400
ps
400
ps
1.0
ms
30-pF load
Measured at 133.3 MHz, loaded outputs,
15 pF load
tJ
Cycle-to-Cycle Jitter
Measured at 66.67 MHz, loaded outputs
(-2, -3)2
30-pF load
Measured at 66.67 MHz, loaded outputs
15-pF load
tLOCK
PLL Lock Time2
Stable power supply, valid clocks presented
on REF and FBK pins
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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MPC962308
APPLICATIONS INFORMATION
VCC
1.4 V
GND
VCC
VCC ÷ 2
CCLK
GND
VCC
VCC
VCC ÷ 2
1.4 V
GND
FB_IN
GND
t5
t6
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
Freescale Semiconductor, Inc...
Figure 1. Output-to-Output Skew tSK(O)
VCC
1.4 V
GND
Figure 2. Static Phase Offset Test Reference
VCC
VCC ÷ 2
DEVICE 1
GND
t2
t1
VCC
VCC ÷ 2
DEVICE 2
DC = t2/t1 x 100%
GND
t7
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Figure 4. Device-to-Device Skew
Figure 3. Output Duty Cycle (DC)
VCC = 3.3 V
2.0
tN
tN+1
0.8
tJ = |tN–tN+1|
t4
t3
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
Figure 5. Cycle-to-Cycle Jitter
TIMING SOLUTIONS
Figure 6. Output Transition Time Test Reference
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MPC962308
Test Circuit #1
Test Circuit #2
VDD
0.1 µF
VDD
OUTPUTS
0.1 µF
CLKOUT
1 KΩ
OUTPUTS
1 KΩ
CLOAD
VDD
GND
0.1 µF
GND
0.1 µF
Freescale Semiconductor, Inc...
Test Circuit for all parameters except t8
VDD
GND
CLKOUT
10 pF
GND
Test Circuit for t8, Output slew rate on -1H, -5 device
Ordering Information (Available)
Ordering Code
Package Name
Package Type
MPC962308D-1
D16
16-pin 150-mil SOIC
MPC962308D-1R2
D16
16-pin 150-mil SOIC — Tape and Reel
MPC962308D-1H
D16
16-pin 150-mil SOIC
MPC962308D-1HR2
D16
16-pin 150-mil SOIC — Tape and Reel
MPC962308DT-1H
DT16
16-pin 150-mil TSSOP
MPC962308DT-1HR2
DT16
16-pin 150-mil TSSOP — Tape and Reel
MPC962308D-2
D16
16-pin 150-mil SOIC
MPC962308D-2R2
D16
16-pin 150-mil SOIC — Tape and Reel
Ordering Information (Planned)
Ordering Code
Package Name
Package Type
MPC962308D-3
D16
16-pin 150-mil SOIC
MPC962308D-3R2
D16
16-pin 150-mil SOIC — Tape and Reel
MPC962308D-4
D16
16-pin 150-mil SOIC
MPC962308D-4R2
D16
16-pin 150-mil SOIC — Tape and Reel
MPC962308D-5H
D16
16-pin 150-mil SOIC
MPC962308D-5HR2
D16
16-pin 150-mil SOIC — Tape and Reel
MPC962308DT-5H
DT16
16-pin 150-mil TSSOP
MPC962308DT-5HR2
DT16
16-pin 150-mil TSSOP — Tape and Reel
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PACKAGE DIMENSIONS
D SUFFIX
16 LEAD SOIC PACKAGE
CASE 751B-05
ISSUE K
0.25
8X
PIN'S
NUMBER
M
B
A
6.2
5.8
1
1.75
1.35
0.25
0.10
16
0.49
0.35
0.25
T A B
1.27
4
A
8
10.0
9.8
A
9
T
4.0
3.8
SEATING
PLANE
16X
B
0.1 T
5
0.50
0.25
6
M
14X
PIN 1 INDEX
Freescale Semiconductor, Inc...
16X
X45˚
0.25
0.19
1.25
0.40
SECTION A-A
TIMING SOLUTIONS
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
3. DATUMS A AND B TO BE DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
NOT EXCEED 0.15MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE
INTER-LEAD FLASH OR PROTRUSIONS.
INTER-LEAD FLASH AND PROTRUSIONS
SHALL NOT EXCEED 0.25MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL NOT CAUSE
THE LEAD WIDTH TO EXCEED 0.62MM.
7˚
0˚
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PACKAGE DIMENSIONS
DT SUFFIX
16 LEAD TSSOP PACKAGE
CASE 948F-01
ISSUE O
K
16X
REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
K
K1
Freescale Semiconductor, Inc...
2X
L/2
16
9
J1
B
-U-
L
SECTION N-N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
-V-
M
N
F
DETAIL E
-W-
C
0.10 (0.004)
-T-
SEATING
PLANE
MOTOROLA
H
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0˚
8˚
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0˚
8˚
G
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NOTES
TIMING SOLUTIONS
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NOTES
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