SUTEX HV7224X 40-channel symmetric row driver Datasheet

HV7224
40-Channel Symmetric Row Driver
Ordering Information
Device
80-Lead
Ceramic Gullwing
HV7224
HV7224DG
Package Options
64-Lead 3-Sided
Die in waffle pack
Plastic Gullwing
HV7224PG
80-Lead
Ceramic Gullwing
(MIL-STD-883 Processed*)
HV7224X
RBHV7224DG
* For Hi-Rel process flows, refer to page 5-3 of the Databook.
Features
❏ Processed with
General Description
HVCMOS®
technology
The HV72 is a low-voltage serial to high-voltage parallel converters with push-pull outputs. It is especially suitable for use as a
symmetric row driver in AC thin-film electroluminescent (ACTFEL)
displays.
❏ Symmetric row drive (reduces latent imaging
in ACTFEL displays)
❏ Output voltage up to 240V
When the data reset pin (DRIO) is at logic high, it will reset all the
outputs of the internal shift register to zero. At the same time, the
output of the shift register will start shifting a logic high from the
least significant bit to the most significant bit. The DRIO can be
triggered at any time. The DIR and SHIFT pins control the
direction of data shift through the device. When DIR is at logic
high, DRIOA is the input and DRIOB is the output. When DIR is
grounded, DRIOB is the input and the DRIOA is the output. See the
Output Sequence Operation Table for output sequence. The
POL and OE pins perform the polarity select and output enable
function respectively. Data is loaded on the low to high transition
of the clock. A logic high will cause the output to swing to VPP if
POL is high, or to GND if POL is low. All outputs will be in HighZ state if OE is at logic high. Data output buffers are provided for
cascading devices.
❏ Low-power level shifting
❏ Source/Sink current 70mA (min.)
❏ Shift Register Speed 3MHz
❏ Pin-programmable shift direction (DIR, SHIFT)
❏ Hi-Rel processing available
Absolute Maximum Ratings
Supply voltage, VDD1
-0.5V to +7V
Supply voltage, VPP
Logic input levels
-0.5V to +260V
-0.5V to VDD +0.5V
Continuous total power dissipation 2 Plastic
Ceramic
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
1200mW
1900mW
Plastic
-40°C to +85°C
Ceramic -55°C to +125°C
-65°C to +150°C
260°C
Notes:
1. All voltages are referenced to GND.
2. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 19mW/°C for ceramic.
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products,
1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV7224
Electrical Characteristics
(over recommended operating conditions of VDD = 5V, VPP = 240V, and TA = 25°C unless noted)
DC Characteristics
Symbol
Parameter
Min
Max
Units
Conditions
IDD
VDD supply current
10
mA
fCLK = 3MHz
IPP
High voltage supply current
2.0
4.0
mA
mA
Outputs low or High-Z
One Output High1
IDDQ
Quiescent VDD supply current
100
µA
All VIN = GND or VDD
VOH
High-level output
VOL
Low-level output
HVOUT
190
V
IO= -70mA
Data out
4.5
V
IO= -100µA
HVOUT
50
V
IO= 70mA
Data out
0.5
V
IO= 100µA
IIH
High-level logic input current
1.0
µA
VIH = VDD
IIL
Low-level logic input current
-1.0
µA
VIL = 0V
ISAT
Saturation current HVOUT
P-Ch
-80
mA
N-Ch
75
mA
Note:
1. Only one output can be turned on at a time.
AC Characteristics
Symbol
Parameter
fCLK
Clock frequency
tW (H/L)
Pulse width - clock high or low
150
ns
tSUD
Data set-up time before clock rises
50
ns
tHD
Data hold time after clock rises
50
ns
tSUC
HVOUT delay from clock rises (Hi-Z to H or L)
1.0
µs
CL = 330pF // RL = 10kΩ
tSUE
HVOUT delay from Output Enable falls
600
ns
CL = 330pF // RL = 10kΩ
tHC
HVOUT delay from clock rises (H or L to Hi-Z)
2.0
µs
CL = 330pF // RL = 10kΩ
tHE
Min
Max
Units
3.0
MHz
Conditions
HVOUT delay from Output Enable rises
600
ns
CL = 330pF // RL = 10kΩ
tDHL
*
Delay time clock to data output falls
250
ns
CL = 15pF
tDLH
*
Delay time clock to data output rises
250
ns
CL = 15pF
tONF
HVOUT fall time
2.0
µs
CL = 330pF // RL = 10kΩ
tONR
HVOUT rise time
2.0
µs
CL = 330pF // RL = 10kΩ
tPOW
POL pulse width
3.0
µs
tOEW
Output Enable pulse width
3.0
µs
Slew rate, VPP or GND
45
V/µs
One active output driving
4.7nF load
* The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is
equal to tWH. Therefore the delay is measured from the trailing edge of the clock.
2
HV7224
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Units
4.5
5.5
V
0
240
V
VDD
Logic supply voltage
VPP
High voltage
supply†
VIH
High-level input voltage
0.7 VDD
VDD
V
VIL
Low-level input voltage
0
0.2VDD
V
fCLK
Clock frequency
3
MHz
±70
mA
IO
High voltage output current
TA
Operating free-air temperature
IOD
Plastic
-40
+85
°C
Ceramic
-55
+125
°C
±300
mA
Allowable pulse current through output diode
Notes:
† Output will not switch at V
PP = 0V.
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply VPP.
5. The VPP should not drop below VDD or float during operation.
Power-down sequence should be the reverse of the above.
Input and Output Equivalent Circuits
VDD
VDD
VPP
Data Out
Input
GND
(Power)
GND
(Logic)
GND
(Logic)
Logic Inputs
HVOUT
Logic Data Output
3
High Voltage Outputs
HV7224
Switching Waveforms
l/fCLK
t WL
t WH
VIH
50%
CLK
50%
VIL
t SUD
Data Reset Input
(DRIOA/DRIOB)
50%
50%
50%
t HD
Data
Valid
50%
VIH
Data
Valid
VIL
t DLH
t DHL
VOH
Data Reset Output
(DRIOA/DRIOB)
50%
50%
VOL
t SUC
HVOUT
(POL = H)
t ONR
t HC
VOH
90%
90%
10%
High Impedance
High Impedance
90%
HVOUT
(POL = L)
10%
t SUC
POL
10%
t ONF
t HC
t POW
50%
VOL
VIH
50%
VIL
t OEW
VIH
OE
50%
50%
t SUE
t HE
t ONR
VOH
90%
90%
HVOUT
VIL
10%
High Impedance
High Impedance
90%
HVOUT
10%
t SUE
10%
t HE
t ONF
4
VOL
HV7224
Functional Block Diagram
V PP
OE
Polarity
V DD
P
LT
HVOUT1
D IOA
N
SHIFT
LT
CLK
HVOUT 2
S/R
DIR
LT
HVOUT 40
D IOB
GND
LT = Level Translator
Function Table
Inputs
I/O Relations
CLK
DIR
O/P HIGH
X
X
O/P OFF
X
O/P LOW
O/P OFF
S/R Data
POL
OE
HV Outputs
H
H
L
H
X
L
X
L
HIGH-Z
X
X
H
L
L
L
X
X
X
X
H
All O/P HIGH-Z
Notes:
H = logic high level, L = logic low level, X = irrelevant
Data input (DRIO) loaded on the low-to-high transistion of the clock.
Only one active output can be set at a time.
Output Sequence Operation Table
DIR
Shift
Data Reset In Data Reset Out
HVOUT# Sequence
L
L
DRIOB
DRIOA1
40 → 1
A
H
L
DRIOA
DRIOB2
1 → 40
A
L
H
DRIOB
DRIOA1
20 → 1 → 40 → 21
B
H
H
DRIOA
DRIOB2
21 → 40 → 1 → 20
B
* Reference to package outline or chip layout drawing.
1.DRIOA is DRIOBdelayed by 40 clock pulses.
2. DRIOB is DRIOA delayed by 40 clock pulses.
5
Direction*
Option (See pin-out on P. 12-158)
HV7224
Pin Configurations
HV72
Option A:
Pin Function
1
HVOUT1/40
2
HVOUT 2/39
3
HVOUT 3/38
4
HVOUT 4/37
5
HVOUT 5/36
6
HVOUT 6/35
7
HVOUT 7/34
8
HVOUT 8/33
9
HVOUT 9/32
10
HVOUT 10/31
11
HVOUT 11/30
12
HVOUT 12/29
13
HVOUT 13/28
14
HVOUT 14/27
15
HVOUT 15/26
16
HVOUT 16/25
17
HVOUT 17/24
18
HVOUT 18/23
19
HVOUT 19/22
20
HVOUT 20/21
21
VPP
22
N/C
23
GND (Power)
24
GND (Logic)
25
DIR
26
VDD
27
CLK
28
N/C
29
SHIFT
30
N/C
31
DRIOA
32
N/C
Pin
33
34
Function
N/C
DRIOB
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
OE
NC
POL
N/C
VDD
N/C
GND (Logic)
GND (Power)
N/C
VPP
HVOUT 21/20
HVOUT 22/19
HVOUT 23/18
HVOUT 24/17
HVOUT 25/16
HVOUT 26/15
HVOUT 27/14
HVOUT 28/13
HVOUT 29/12
HVOUT 30/11
HVOUT 31/10
HVOUT 32/9
HVOUT 33/8
HVOUT 34/7
HVOUT 35/6
HVOUT 36/5
HVOUT 37/4
HVOUT 38/3
HVOUT 39/2
HVOUT 40/1
HV72
Option B:
Pin Function
1
HVOUT 20/21
2
HVOUT 19/22
3
HVOUT 18/23
4
HVOUT 17/24
5
HVOUT 16/25
6
HVOUT 15/26
7
HVOUT 14/27
8
HVOUT 13/28
9
HVOUT 12/29
10
HVOUT 11/30
11
HVOUT 10/31
12
HVOUT 9/32
13
HVOUT 8/33
14
HVOUT 7/34
15
HVOUT 6/35
16
HVOUT 5/36
17
HVOUT 4/37
18
HVOUT 3/38
19
HVOUT 2/39
20
HVOUT 1/40
21
VPP
22
N/C
23
GND (Power)
24
GND (Logic)
25
DIR
26
VDD
27
CLK
28
N/C
29
SHIFT
30
N/C
31
DRIOA
32
N/C
Note:
Pin designation for DIR H/L, SHIFT = L.
Example: For DIR = H, pin 1 is HVOUT1.
For DIR = L, pin 1 is HVOUT40.
Pins 65–80 are NC (ceramic only).
Pin
33
34
Function
N/C
DRIOB
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
OE
N/C
POL
N/C
VDD
N/C
GND (Logic)
GND (Power)
N/C
VPP
HVOUT 40/1
HVOUT 39/2
HVOUT 38/3
HVOUT 37/4
HVOUT 36/5
HVOUT 35/6
HVOUT 34/7
HVOUT 33/8
HVOUT 32/9
HVOUT 31/10
HVOUT 30/11
HVOUT 29/12
HVOUT 28/13
HVOUT 27/14
HVOUT 26/15
HVOUT 25/16
HVOUT 24/17
HVOUT 23/18
HVOUT 22/19
HVOUT 21/20
Note:
Pin designation for DIR L/H, SHIFT = H.
Example: For DIR = L, pin 1 is HVOUT20.
For DIR = H, pin 1 is HVOUT21.
Pins 65–80 are NC (ceramic only).
6
HV7224
Package Outline
1
64
41
64
Index
40
65
Index
24
24
1
40
25
25
80
41
top view
top view
3-sided Plastic 64-pin Gullwing Package
80-pin Ceramic Gullwing Package
02/06//02
©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
7
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TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com