Renesas HD6432695 16-bit single-chip microcomputer Datasheet

REJ09B0234-0500
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2633 Group, H8S/2633 F-ZTAT,
H8S/2633R F-ZTAT, H8S/2695
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2600 Series
H8S/2633
H8S/2632
H8S/2631
H8S/2633R
H8S/2695
Rev. 5.00
Revision Date: Mar 28, 2005
HD6432633
HD64F2633
HD6432632
HD6432631
HD64F2633R
HD6432695
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 5.00 Mar 28, 2005 page ii of lxii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 5.00 Mar 28, 2005 page iii of lxii
Rev. 5.00 Mar 28, 2005 page iv of lxii
Preface
These LSIs are high-performance microcomputers with a 32-bit H8S/2600 CPU core and a variety
of built-in peripheral functions necessary for a system configuration.
The built-in peripheral devices include a 16-bit timer pulse unit (TPU), a programmable pulse
generator (PPG)*1, a watchdog timer (WDT), 8-bit timers, a 14-bit PWM timer (PWM)*1, serial
communication interfaces (SCI, IrDA*1), an A/D converter, a D/A converter*1, and I/O ports. An
I2C bus interface (IIC)*1 can also be incorporated as an option. An on-chip DMA controller
(DMAC)*1 and data transfer controller (DTC)*1 perform high-speed data transfer without using
the CPU, enabling use of these LSIs as embedded microcomputers in various advanced control
systems. Two types of internal ROM-flash memory (F-ZTAT™*2) and mask ROM-are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
Notes: 1. This function is not available in the H8S/2695.
2. F-ZTAT is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using the H8S/2633 Group,
H8S/2633R, or H8S/2695 in the design of application systems. Readers are
expected to understand the fundamentals of electrical circuits, logic circuits, and
microcomputers.
Objective:
This manual was written to provide users with an explanation of the hardware
functions and electrical characteristics of the H8S/2633 Group, H8S/2633R, and
H8S/2695. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual
for a detailed description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual is broadly divided into parts covering
the CPU, system control functions, peripheral functions, and electrical characteristics.
• In order to understand the details of the CPU's functions
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual.
Example: Bit order: The MSB is on the left and the LSB is on the right.
Related Manuals:
The latest versions of all related manuals are available from our website.
Please ensure that you have the latest versions of all documents you require.
http://www.renesas.com/eng/
Rev. 5.00 Mar 28, 2005 page v of lxii
H8S/2633 Group manuals:
Document Title
Document No.
H8S/2633 Group Hardware Manual
This manual
H8S/2600 Series, H8S/2000 Series Programming Manual
REJ09B0139
Users manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage
Editor User's Manual
REJ10B0058
H8S, H8/300 Series Simulator/Debugger (for Windows) User's Manual
ADE-702-037
High-performance Embedded Workshop User's Manual
ADE-702-201
Application Notes:
Document Title
Document No.
H8S Family Technical Q & A
REJ05B0397
Rev. 5.00 Mar 28, 2005 page vi of lxii
Comparison of H8S/2633, H8S/2632, H8S/2631,
H8S/2633F-ZTAT, H8S/2633RF-ZTAT, and H8S/2695
Product Specifications
A comparative listing of the specifications of the H8S/2633, H8S/2632, H8S/2631, H8S/2633FZTAT, H8S/2633RF-ZTAT, and H8S/2695 is provided below.
Comparison of H8S/2633, H8S/2632, H8S/2631, H8S/2633F-ZTAT, H8S/2633RF-ZTAT, and
H8S/2695 Product Specifications
H8S/2633 Group
H8S/2633R Group
H8S/2633F-ZTAT
H8S/2633
H8S/2632
Model
HD64F2633F25
HD64F2633TE25
HD64F2633F16
HD64F2633TE16
HD6432633F25
HD6432633TE25
HD6432633F16
HD6432633TE16
HD6432632F25
HD6432632TE25
HD6432632F16
HD6432632TE16
HD6432631F25 HD64F2633RF28 HD6432695F28
HD6432631TE25 HD64F2633RTE28
HD6432631F16
HD6432631TE16
RAM
16 kbytes
16 kbytes
12 kbytes
8 kbytes
16 kbytes
8 kbytes
ROM
256-kbyte flash
memory
256-kbyte mask
ROM
192-kbyte mask
ROM
128-kbyte mask
ROM
256-kbyte flash
memory
192-kbyte mask
ROM
On-chip
ROM
(256 kbytes)
On-chip
ROM
(192 kbytes)
On-chip
ROM
(128 kbytes)
On-chip
ROM
(256 kbytes)
On-chip
ROM
(192 kbytes)
On-chip
RAM
(16k-64)bytes
On-chip
RAM
(12k-64)bytes
On-chip
RAM
(8k-64)bytes
On-chip
RAM
(16k-64)bytes
On-chip
RAM
(8k-64)bytes
On-chip
RAM
(64 bytes)
On-chip
RAM
(64 bytes)
On-chip
RAM
(64 bytes)
On-chip
RAM
(64 bytes)
On-chip
RAM
(64 bytes)
ROM,
RAM
memory
map
H'000000
H'01FFFF
H8S/2631
H8S/2633RF-ZTAT
H8S/2695
H'02FFFF
H'03FFFF
H'FFB000
H'FFC000
H'FFD000
H'FFEFBF
H'FFFFC0
H'FFFFFF
Input clock 2 to 25 MHz* (2 to 16 MHz for 16 MHz operation version)
frequency
range
Operating 25 MHz operation version: 2 to 25 MHz
frequency 16 MHz operation version: 2 to 16 MHz
range
2 to 28 MHz*
Rev. 5.00 Mar 28, 2005 page vii of lxii
H8S/2633 Group
H8S/2633F-ZTAT
H8S/2633
H8S/2632
H8S/2633R Group
H8S/2631
Operating 25 MHz operation version
voltage
PVCC = 4.5 V to 5.5 V, VCC = PLLVCC = 3.0 V to 3.6 V, AVCC = 4.5 V to 5.5
V, Vref = 4.5 V to AVCC
range
16 MHz operation version (low-voltage version)
PVCC = 3.0 V to 5.5 V, VCC = PLLVCC = 3.0 V to 3.6 V
[When using A/D or D/A]
AVCC = 3.6 V to 5.5 V, Vref = 3.6 V to AVCC
[When not using A/D or D/A]
AVCC = 3.3 V to 5.5 V, Vref = 3.3 V to AVCC
Power
supply
pins
2 power supply configurations, PVCC (5 V power supply) and
VCC (3 V power supply), PLLVCC is 3 V power supply
H8S/2633RF-ZTAT
H8S/2695
PVCC = 4.5 V to 5.5 V
(Single power supply version lacking VCC
and PLLVCC pins)
AVCC = 4.5 V to 5.5 V
Vref = 4.5 V to AVCC
• PVCC (5 V power supply) single power
supply configuration
• Do not connect the VCL pin to the
power supply. Instead, connect it to a
ground via a 0.1 µF power supply
stabilizer capacitor (which should be
mounted close to the pin).
• Do not connect the VCC power supply
to the VCL pin.
• Note that the VCL pin is located in the
same position as the VCC pin on the
older H8S/2633 Group and
H8S/2633F.
External
capacitor
0.1 µF
VCL (pin 11: FP128B)
(pin 7: TFP120)
VSS (pin 9: FP128B)
(pin 5: TFP120)
• There is no PLLVCC power supply pin.
EXTAL
VIH: VCC × 0.8 V to VCC + 0.3 V
input level V : –0.3 V to V × 0.2 V
IL
CC
(VCC = 3.0 V to 3.6 V)
Interrupt
sources
External interrupts: NMLIRQ7 to IRQ0
Internal interrupts: 72 sources
VIH: PVCC × 0.8 V to PVCC + 0.3 V
VIL: –0.3 V to PVCC × 0.2 V
(PVCC = 4.5 V to 5.5 V)
External interrupts:
NMLIRQ7 to IRQ0
Internal interrupts:
49 sources
32 kHz
oscillator
Yes (subactive mode, subsleep mode, and watch mode supported)
Rev. 5.00 Mar 28, 2005 page viii of lxii
No (subactive
mode, subsleep
mode, and watch
mode not
supported)
H8S/2633 Group
H8S/2633F-ZTAT
Method of
fixing OSC
pin when
32 kHz
oscillator
not used
H8S/2633
H8S/2632
H8S/2633R Group
H8S/2631
VCC power supply
H8S/2633RF-ZTAT
OSC1
OSC1
OSC2
OSC2
GND
Open
Open
Properties Output of pins 34 and 35 is normally NMOS push-pull output, but is NMOS open-drain output
of multiwhen the IIC bus drive function is selected.
use pins
(pins 34
and 35)
RecomSee section 23A, Clock Oscillator (H8S/2633, H8S/2632, H8S/2631,
mended H8S/2633F).
external
PLL circuit
H8S/2695
No 32 kHz
oscillator.
The HD6432695 is
the HD6432633.
The pins
corresponding to
OSC1 and OSC2 in
the HD64F2633 are
NC pins in the
HD6432695.
No IIC function.
Pins 34 and 35
output is CMOS
output.
See section 23B, Clock Oscillator
(H8S/2633R, H8S/2695).
PC break
controller
(PBC)
Yes
No
DRAM
interface
Yes
No
DMA
controller
(DMAC)
Yes
No
Data
transfer
controller
(DTC)
Yes
No
I/O ports
Functions of H8S/2633, H8S/2632, H8S/2631, H8S/2633F, and H8S/2633R are identical.
See section 10A, I/O Ports, for details.
Some functions of
the H8S/2633
Group have been
eliminated. See
section 10B, I/O
Ports, for details.
Programmable
pulse
generator
(PPG)
Yes
No
8-bit timer
(TMR)
Yes
No
14-bit
PWM
timer
Yes
No
WDTI
Yes
No
IrDA
Yes
No
Rev. 5.00 Mar 28, 2005 page ix of lxii
H8S/2633 Group
H8S/2633F-ZTAT
I2C bus
interface
(IIC)
H8S/2633
H8S/2632
Yes [option]
D/A
converter
Yes
H8S/2633R Group
H8S/2631
H8S/2633RF-ZTAT
H8S/2695
Yes
No
No
Note: * The input clock frequency range is 2 to 25 MHz (2 to 16 MHz on 16 MHz operation version: H8S/2633 Group only).
For 25 MHz < φ ≤ 28 MHz operation on the H8S/2633R and H8S/2695, make sure to use a PLL with a multiplying
factor set to ×2 or ×4 (φ = operating frequency).
Rev. 5.00 Mar 28, 2005 page x of lxii
Notes on H8S/2695
1. Notes on P35 Pin Functions (SCK1, SCK4) in H8S/2695
The following restrictions apply to the functions of P35 (SCK1, SCK4) in the H8S/2695. The
functions indicated by *2 below cannot be used in the H8S/2695, and these combinations must not
be set.
(1) P35 Pin Functions in H8S/2633 Group and H8S/2633R
ICE
0
CKE1(SCI1)
CKE1(SCI4)
0
0
C/A(SCI1)
C/A(SCI4)
0
0
CKE0(SCI1)
CKE0(SCI4)
P35DDR
Pin function
1
0
0
0, 1, 1
1, 0, 1
0, 1, 1
1, 0, 1
0
0
1
1

0
0


0
0
0
1




P35
input pin
P35
output pin*1
SCK1/SCK4
output pin*1
SCK1/SCK4
output pin*1
SCK1/SCK4
input pin
SCL0
input/output pin
IRQ5 input
(2) P35 Pin Functions in H8S/2695
CKE1(SCI1)
CKE1(SCI4)
C/A(SCI1)
C/A(SCI4)
Pin function
0
0
0
1
P35
input pin
P35
output pin
2
1*
2
0*
1
1
1
1



0, 1, 1
1, 0, 1








0*


SCK1/SCK4
input pin
0
0
CKE0(SCI1)
CKE0(SCI4)
P35DDR
2
0*
2
1*
0
0
SCK1/SCK4 SCK1/SCK4
output pin
output pin
3
IRQ5 input
Notes: 1. The output type is normally NMOS push-pull output, but NMOS open-drain output when P35ODR = 1.
2. These combinations must not be set.
3. If SCK1 and SCK4 are used as input (clock input) pins on the H8S/2695, P35DDR must be cleared
to 0.
2. Notes on H8S/2695 Development (Using H8S/2633 Emulator Chip)
The H8S/2695 is not equipped with an I2C bus function and output from pins 34 and 35 is CMOS
output (unless P34ODR or P35ODR is set to 1, respectively). These pins are used for NMOS
push-pull output on the H8S/2633 emulator chip, so the output characteristics of these pins are
different than is the case with the H8S/2695. If it is necessary to use pins 34 and 35 for CMOS
output, use an appropriate resistance to pull up pins 34 and 35 of the H8S/2633 emulator chip.
Rev. 5.00 Mar 28, 2005 page xi of lxii
Manual Reference Pages
H8S/2633 Group
H8S/2633F-ZTAT
H8S/2633
RAM
See section 21, RAM
ROM
See section 22, ROM
H8S/2632
H8S/2633R Group
H8S/2631
H8S/2633RF-ZTAT
H8S/2695
Interrupt Controller See section 5, Interrupt Controller
(INT)
PC Break Controller See section 6, PC Break Controller (PBC)
(PBC)
—
DRAM Interface
See section 7, Bus Controller
—
DMA Controller
(DMAC)
See section 8, DMA Controller (DMAC)
—
Data Transfer
Controller (DTC)
See section 9, Data Transfer Controller (DTC)
—
I/O Ports
See section 10A, I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
16-Bit Timer Pulse
Unit (TPU)
See section 11, 16-Bit Timer Pulse Unit (TPU)
Programmable
Pulse Generator
(PPG)
See section 12, Programmable Pulse Generator (PPG)
See section 10B, I/O
Ports (H8S/2695)
—
8-Bit Timers (TMR) See section 13, 8-Bit Timers (TMR)
—
14-Bit PWM D/A
See section 14, 14-Bit PWM D/A
—
WDT0
See section 15, Watchdog Timer
WDT1
See section 15, Watchdog Timer
Serial
Communication
Interface (SCI)
See section 16, Serial Communication Interface (SCI, IrDA)
IrDA
See section 16, Serial Communication Interface (SCI, IrDA)
Smart Card
Interface
See section 17, Smart Card Interface
I2C Bus Interface
(IIC)
See section 18, I2C Bus Interface (IIC)
A/D Converter
See section 19, A/D Converter
—
—
—
D/A Converter
See section 20, D/A Converter
32 kHz oscillator
See section 23A, Clock Pulse Generator (H8S/2633,
H8S/2632, H8S/2631, H8S/2633F)
See section 23B,
Clock Pulse
Generator
(H8S/2633R,
H8S/2695)
Clock Pulse
Generator
See section 23A, Clock Pulse Generator (H8S/2633,
H8S/2632, H8S/2631, H8S/2633F)
See section 23B, Clock Pulse Generator
(H8S/2633R, H8S/2695)
EXTAL input level
See section 25, Electrical Characteristics (H8S/2633,
H8S/2632, H8S/2631, H8S/2633F)
See section 26,
Electrical
Characteristics
(H8S/2633R)
Rev. 5.00 Mar 28, 2005 page xii of lxii
—
—
See section 27,
Electrical
Characteristics
(H8S/2695)
H8S/2633 Group
H8S/2633F-ZTAT
H8S/2633
H8S/2632
H8S/2633R Group
H8S/2631
Recommended
See section 23A, Clock Pulse Generator (H8S/2633,
external PLL circuit H8S/2632, H8S/2631, H8S/2633F)
Interrupt processing See section 5, Interrupt Controller
vector table
See table 5.4 (a)
H8S/2633RF-ZTAT
H8S/2695
See section 23B, Clock Pulse Generator
(H8S/2633R, H8S/2695)
See section 5,
Interrupt Controller
See table 5.4 (b)
Rev. 5.00 Mar 28, 2005 page xiii of lxii
Rev. 5.00 Mar 28, 2005 page xiv of lxii
Main Revisions in This Edition
Item
Page
Revision (See Manual for Details)
1.1 Overview
1
Description amended
(Before) (SCI, IrDA)*2 → (After) (SCI, IrDA*2)
Table 1.1
Overview
2
Note *1 added
1
1
Possible to connect* PC break controller*
3
Note *1 added
Programmable pulse generator (PPG)*1
8
Figure amended
14-bit PWM timer
D/A converter
A/D converter
Port 9
PPG
P47 /AN7/ DA1
P46 /AN6/ DA0
P45 /AN5
P44 /AN4
P43 /AN3
P42 /AN2
P41 /AN1
P40 /AN0
P33/TxD1/SCL1
P32/SCK0/SDA1/IRQ4
P31/RxD0/IrRxD
P30/TxD0/IrTxD
P97/AN15/DA3
P96/AN14/DA2
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
TPU
14-bit PWM timer
D/A converter
A/D converter
Port 9
PPG
Port 1
Port 4
P33/TxD1/SCL1
P32/SCK0/SDA1/IRQ4
P31/RxD0/IrRxD
P30/TxD0/IrTxD
P97/AN15/DA3
P96/AN14/DA2
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
P47 / AN7/ DA1
P46 / AN6/ DA0
P45 / AN5
P44 / AN4
P43 / AN3
P42 / AN2
P41 / AN1
P40 / AN0
P77/TxD3
P76/RxD3
P75/TMO3/SCK3
P74/TMO2/MRES
P73/TMO1/TEND1/CS7
P72/TMO0/TEND0/CS6
P71/TMR23/TMC23/DREQ1/CS5
P70/TMR01/TMC01/DREQ0/CS4
Port
Figure amended
Vref
AVCC
AVSS
9
Vref
AVCC
AVSS
Port 4
P17 / PO15/ TIOCB2 /PWM3/ TCLKD
P16 / PO14/ TIOCA2/PWM2/IRQ1
P15 / PO13/ TIOCB1 /TCLKC
P14 / PO12/ TIOCA1/IRQ0
P13 / PO11/ TIOCD0 / TCLKB/A23
P12 / PO10/ TIOCC0 / TCLKA/A22
P11 / PO9/ TIOCB0 /DACK1/A21
P10 / PO8/ TIOCA0 /DACK0/A20
Port 1
Port 7
Figure 1.1 (b)
H8S/2633R
Internal Block
Diagram
TPU
Port 7
P77/TxD3
P76/RxD3
P75/TMO3/SCK3
P74/TMO2/MRES
P73/TMO1/TEND1/CS7
P72/TMO0/TEND0/CS6
P71/TMR23/TMC23/DREQ1/CS5
P70/TMR01/TMC01/DREQ0/CS4
Figure 1.1 (a)
H8S/2633,
H8S/2633F,
H8S/2632,
H8S/2631 Internal
Block Diagram
Port
Specification of Power-down mode amended
• Subclock operation*1 (subactive mode, subsleep mode, watch
mode)
P17 / PO15/ TIOCB2 /PWM3/ TCLKD
P16 / PO14/ TIOCA2/PWM2/IRQ1
P15 / PO13/ TIOCB1 / TCLKC
P14 / PO12/ TIOCA1/IRQ0
P13 / PO11/ TIOCD0 / TCLKB/A23
P12 / PO10/ TIOCC0 / TCLKA/A22
P11 / PO9/ TIOCB0 /DACK1/A21
P10 / PO8/ TIOCA0 /DACK0/A20
1.3.2 Internal
Block Diagram
5
Rev. 5.00 Mar 28, 2005 page xv of lxii
Item
Page
Revision (See Manual for Details)
1.3.1 Pin
Arrangement
11
Figures amended
112 pin (Before) P72/TMO0/TEND0/CS6/SYNCI → (After)
P72/TMO0/TEND0/CS6
Figure 1.2 (a)
H8S/2633,
H8S/2633F,
H8S/2632,
H8S/2631 Pin
Arrangement (TFP120: Top View)
12
Figure 1.2 (b)
H8S/2633R Pin
Arrangement (TFP120: Top View)
Figure 1.3 (a)
H8S/2633,
H8S/2633F,
H8S/2632,
H8S/2631 Pin
Arrangement
(FP-128B: Top
View)
13
Figure 1.3 (b)
H8S/2633R Pin
Arrangement
(TFP-128B: Top
View)
14
1.3.2 Pin
Functions in Each
Operating Mode
16
Table 1.2 (a) Pin
Functions in Each
Operating Mode
(H8S/2633,
H8S/2633F,
H8S/2632,
H8S/2631)
Figures amended
122 pin (Before) P72/TMO0/TEND0/CS6/SYNCI → (After)
P72/TMO0/TEND0/CS6
Table amended
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
11
15
VSS
VSS
VSS
VSS
12
16
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/TIOCA3
13
17
PVCC1
PVCC1
PVCC1
PVCC1
14
18
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/TIOCB3
15
19
PB2/A10/TIOCC3
PB2/A10/TIOCC3
PB2/A10/TIOCC3
PB2/TIOCC3
16
20
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/TIOCD3
17
21
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/TIOCA4
18
22
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/TIOCB4
19
23
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/TIOCA5
20
24
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/TIOCB5
21
25
PA0/A16
PA0/A16
PA0/A16
PA0
22
26
PA1/A17/TxD2
PA1/A17/TxD2
PA1/A17/TxD2
PA1/TxD2
23
27
PA2/A18/RxD2
PA2/A18/RxD2
PA2/A18/RxD2
PA2/RxD2
24
28
PA3/A19/SCK2
PA3/A19/SCK2
PA3/A19/SCK2
PA3/SCK2
Rev. 5.00 Mar 28, 2005 page xvi of lxii
Item
Page
Revision (See Manual for Details)
1.3.2 Pin
Functions in Each
Operating Mode
17
Table amended, note *1 added
NC*1
Pin No.
Table 1.2 (a) Pin
Functions in Each
Operating Mode
(H8S/2633,
H8S/2633F,
H8S/2632,
H8S/2631)
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
33
39
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
34
40
PE0/D0
PE0/D0
PE0/D0
PE0
35
41
PE1/D1
PE1/D1
PE1/D1
PE1
36
42
PE2/D2
PE2/D2
PE2/D2
PE2
37
43
PE3/D3
PE3/D3
PE3/D3
PE3
38
44
PE4/D4
PE4/D4
PE4/D4
PE4
39
45
PE5/D5
PE5/D5
PE5/D5
PE5
40
46
PE6/D6
PE6/D6
PE6/D6
PE6
41
47
PE7/D7
PE7/D7
PE7/D7
PE7
42
48
VSS
VSS
VSS
VSS
18
NC*1 FWE*2
19
NC*1
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
20
86
94
87
95
PF3/
88
96
PF2/
Mode 5
Mode 6
Mode 7
PF4
/
/
/
/
PF3/
PF2/
/
/
/
/
PF3/
PF2/
/
/
/
PF3/
/
PF2
/
NC*1
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
111
121
P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/
/
/
/
112
122
P72/TMO0/
/
P72/TMO0/
/
P72/TMO0/
/
P72/TMO0/
113
123
P73/TMO1/
/
P73/TMO1/
/
P73/TMO1/
/
P73/TMO1/
Rev. 5.00 Mar 28, 2005 page xvii of lxii
Item
Page
Revision (See Manual for Details)
1.3.2 Pin
Functions in Each
Operating Mode
21
Table amended, note *1 added
Pin No.
Table 1.2 (b) Pin
Functions in Each
Operating Mode
(H8S/2633R)
22
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
11
15
VSS
VSS
VSS
VSS
12
16
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/TIOCA3
13
17
PVCC1
PVCC1
PVCC1
PVCC1
14
18
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/TIOCB3
15
19
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/TIOCD3
17
21
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/TIOCA4
18
22
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/TIOCB4
19
23
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/TIOCA5
20
24
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/TIOCB5
21
25
PA0/A16
PA0/A16
PA0/A16
PA0
22
26
PA1/A17/TxD2
PA1/A17/TxD2
PA1/A17/TxD2
PA1/TxD2
23
27
PA2/A18/RxD2
PA2/A18/RxD2
PA2/A18/RxD2
PA2/RxD2
24
28
PA3/A19/SCK2
PA3/A19/SCK2
PA3/A19/SCK2
PA3/SCK2
25
29
VSS
VSS
VSS
VSS
NC*1
Pin No.
23
24
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
33
39
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
34
40
PE0/D0
PE0/D0
PE0/D0
PE0
35
41
PE1/D1
PE1/D1
PE1/D1
PE1
36
42
PE2/D2
PE2/D2
PE2/D2
PE2
37
43
PE3/D3
PE3/D3
PE3/D3
PE3
38
44
PE4/D4
PE4/D4
PE4/D4
PE4
39
45
PE5/D5
PE5/D5
PE5/D5
PE5
40
46
PE6/D6
PE6/D6
PE6/D6
PE6
41
47
PE7/D7
PE7/D7
PE7/D7
PE7
42
48
VSS
VSS
VSS
VSS
NC*1
NC*1
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
25
Mode 5
Mode 6
Mode 7
86
94
87
95
PF3/
88
96
PF2/
111
121
P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/
/
/
/
112
122
P72/TMO0/
NC*1
Rev. 5.00 Mar 28, 2005 page xviii of lxii
PF4
/
/
/
/
PF3/
PF2/
/
/
/
/
P72/TMO0/
/
PF3/
PF2/
/
/
/
/
P72/TMO0/
PF3/
/
PF2
/
/
P72/TMO0/
Item
Page
Revision (See Manual for Details)
1.3.2 Pin
Functions in Each
Operating Mode
26
Table amended, note *1 added
Pin No.
Table 1.2 (c) Pin
Functions in Each
Operating Mode
(H8S/2695)
27
Pin Name
FP-128B
Mode 4
Mode 5
Mode 6
Mode 7
15
VSS
VSS
VSS
VSS
16
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/TIOCA3
17
PVCC1
PVCC1
PVCC1
PVCC1
18
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/TIOCB3
19
PB2/A10/TIOCC3
PB2/A10/TIOCC3
PB2/A10/TIOCC3
PB2/TIOCC3
20
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/TIOCD3
21
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/TIOCA4
22
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/TIOCB4
23
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/TIOCA5
24
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/TIOCB5
25
PA0/A16
PA0/A16
PA0/A16
PA0
26
PA1/A17/TxD2
PA1/A17/TxD2
PA1/A17/TxD2
PA1/TxD2
27
PA2/A18/RxD2
PA2/A18/RxD2
PA2/A18/RxD2
PA2/RxD2
28
PA3/A19/SCK2
PA3/A19/SCK2
PA3/A19/SCK2
PA3/SCK2
29
VSS
VSS
VSS
VSS
FP-128B
Mode 4
Mode 5
39
P17/TIOCB2/TCLKD P17/TIOCB2/TCLKD P17/TIOCB2/TCLKD P17/TIOCB2/TCLKD
40
PE0/D0
PE0/D0
PE0/D0
PE0
41
PE1/D1
PE1/D1
PE1/D1
PE1
42
PE2/D2
PE2/D2
PE2/D2
PE2
43
PE3/D3
PE3/D3
PE3/D3
PE3
44
PE4/D4
PE4/D4
PE4/D4
PE4
45
PE5/D5
PE5/D5
PE5/D5
PE5
46
PE6/D6
PE6/D6
PE6/D6
PE6
47
PE7/D7
PE7/D7
PE7/D7
PE7
48
VSS
VSS
VSS
VSS
NC*1
Pin No.
Pin Name
Mode 6
Mode 7
Rev. 5.00 Mar 28, 2005 page xix of lxii
Item
Page
Revision (See Manual for Details)
1.3.2 Pin
Functions in Each
Operating Mode
28
Table amended, note *1 added
Pin No.
Table 1.2 (c) Pin
Functions in Each
Operating Mode
(H8S/2695)
Pin Name
FP-128B
Mode 4
Mode 5
Mode 6
65
P35/SCK1/SCK4/
P35/SCK1/SCK4/
P35/SCK1/SCK4/
P35/SCK1/SCK4/
66
P36/RxD4
P36/RxD4
P36/RxD4
P36/RxD4
67
NC*
1
NC*
1
NC*
1
NC*
1
68
NC*
1
NC*
1
NC*
1
NC*
1
69
P37/TxD4
P37/TxD4
P37/TxD4
P37/TxD4
70
PG0/
PG0/
PG0/
PG0/
71
PG1/
72
PG2/
PG2/
PG2/
PG2
73
PG3/
PG3/
PG3/
PG3
74
PG4/
PG4/
PG4/
PG4
76
NC*
NC*
NC*
NC*
77
PLLCAP
PLLCAP
PLLCAP
PLLCAP
78
PLLVSS
PLLVSS
PLLVSS
PLLVSS
NMI
NMI
NMI
NMI
/
PG1/
/
PG1/
Mode 7
/
PG1/
75
1
1
1
1
79
80
81
29
82
NC*
NC*
83
XTAL
XTAL
XTAL
XTAL
84
NC*
NC*
NC*
NC*
85
EXTAL
86
VSS
VSS
VSS
VSS
87
NC*
1
NC*
1
NC*
1
NC*
1
88
NC*
1
NC*
1
NC*
1
NC*
1
89
PVCC1
PVCC1
FP-128B
Mode 4
Mode 5
95
PF3/
/
96
PF2/
/
2
1
NC*
2
1
EXTAL
1
EXTAL
2
1
EXTAL
PVCC1
PVCC1
NC*1
Pin No.
30
NC*
2
Pin Name
/
Mode 6
PF3/
/
PF2/
/
/
Mode 7
PF3/
/
PF2/
/
/
PF3/
/
PF2
NC*1
Notes: 1. NC pins should be connected to VSS or left open.
2. In the flash memory version this is the FWE pin. In the mask
ROM version this pin should be connected to VSS or left open.
Rev. 5.00 Mar 28, 2005 page xx of lxii
Item
Page
Revision (See Manual for Details)
1.3.3 Pin
Functions
35
Table amended
Table 1.3 (a) Pin
Functions
(H8S/2633,
H8S/2633F,
H8S/2632,
H8S/2631)
Table 1.3 (b) Pin
Functions
(H8S/2633R)
2.6.1 Overview
41
66
Table 2.1
Instruction
Classification
2.6.2 Instructions
and Addressing
Modes
Table 2.2
Combinations of
Instructions and
Addressing Modes
Type
Symbol
I/O
Name and Function
Serial
communication
interface (SCI)/
Smart Card
interface
TxD4, TxD3,
TxD2, TxD1,
TxD0
Output
Transmit data (channel 0 to 4): Data output pins.
RxD4, RxD3, Input
RxD2, RxD1,
RxD0
Receive data (channel 0 to 4): Data input pins.
SCK4, SCK3, I/O
SCK2, SCK1,
SCK0
Serial clock (channel 0 to 4): Clock I/O pins.
SCK0 output type is NMOS push-pull.
Table amended
Type
Symbol
I/O
Name and Function
Serial
communication
interface (SCI)/
Smart Card
interface
TxD4, TxD3,
TxD2, TxD1,
TxD0
Output
Transmit data (channel 0 to 4): Data output pins.
RxD4, RxD3, Input
RxD2, RxD1,
RxD0
Receive data (channel 0 to 4): Data input pins.
SCK4, SCK3, I/O
SCK2, SCK1,
SCK0
Serial clock (channel 0 to 4): Clock I/O pins.
SCK0 output type is NMOS push-pull.
IrDA-equipped
SCI 1 channel
(SCI0)
IrTxD
IrRxD
Output/
Input
IrDA transmission data/receive data: Input/output pins
for the data encoded for the IrDA.
I2C bus interface
(IIC) (optional)
SCL0
SCL1
I/O
2
I C clock input (channel 1, 0):
I2C clock input/output pins.
These functions have a bus driving function.
SCL0's output format is an NMOS open drain.
SDA0
SDA1
I/O
I2C data input/output (channel 1, 0):
I2C clock input/output pins.
These functions have a bus driving function.
SCL0's output format is an NMOS open drain.
Note *5 added
STM*5 • LDM*5
Note: 5. Only register ER0 to ER6 should be used when using the
STM/LDM instruction.
67, 68
Note *3 added
STM*3 LDM*3
Note: 3. Only register ER0 to ER6 should be used when using the
STM/LDM instruction.
Rev. 5.00 Mar 28, 2005 page xxi of lxii
Item
Page
Revision (See Manual for Details)
2.6.3 Table of
Instructions
Classified by
Function
70
Note *2 added
STM*2 • LDM*2
71
TAS*3
Table 2.3
Instructions
Classified by
Function
77
Note: 2. Only register ER0 to ER6 should be used when using the
STM/LDM instruction.
2.8.1 Overview
86
00 00
3. When using the TAS instruction, ...
Figure 2.14
Processing States
Note * amended
Note: * The power-down state also includes a medium- speed
mode, module stop mode, subactive mode, subsleep mode, and
watch mode. (In the H8S/2695, the subactive mode, subsleep
mode, and watch mode are not available.)
Figure 2.15 State
Transitons
87
2.10.2 STM/LDM
Instruction
95
2.10.2 added
2.10.3 Bit
Manipulation
Instructions
95
2.10.3 added
3.4 Pin Functions
in Each Operating
Mode
105
Table amended
Note: 3. Apart from these states, there are also the watch mode,
subactive mode, and subsleep mode. (In the H8S/2695, the watch
mode, subactive mode, and subsleep mode are not available.)
See section ...
Port
Port 1
M
P10
P11 to P13
Table 3.3 Pin
Functions in Each
Mode
3.5 Address Map
in Each Operating
Mode
Note *3 amended
Port A
PA4 to PA0
Port B
107 to
110
ode 4
P/A*
Mode 5
P/A*
Mode 6
P*/A
P*/A
P/A*
P*/A
P/A*
P/A*
P/A*
P*/A
P*/A
P*/A
Mode 7
P
P
P
P
Figures amended
(Before) External area → (After) External address space
Figure 3.1 Memory
Map in Each
Operating Mode in
the H8S/2633,
H8S/2633R to
Figure 3.4 Memory
Map in Each
Operating Mode in
the H8S/2695
Rev. 5.00 Mar 28, 2005 page xxii of lxii
Item
Page
5.2.2 Interrupt
127
Priority Registers A
t L, O (IPRA to
IPRL, IPRO)
Revision (See Manual for Details)
Note * added
DMAC* Refresh timer*
Table 5.3
Correspondence
between Interrupt
Sources and IPR
Settings
133
5.3.3 Interrupt
Exception Handling
Vector Table
Table title amended
Table 5.4 (a)
Interrupt Sources,
Vector Addresses,
and Interrupt
Priorities (H8S/2633,
H8S/2633F,
H8S/2632,
H8S/2631,
H8S/2633R)
5.5.5 IRQ Interrupt 154
5.5.5 added
5.5.6 NMI Interrupt 154
Usage Notes
5.5.6 added
7.1.1 Features
Note * added
172
• Other features
 Refresh counter* (refresh timer) can be used as an interval
timer
 ...
7.2.4 Bus Control 183
Register H (BCRH)
Note * added to bit table
DRAM space* Contiguous DRAM space*
Note: * This function is not available in the H8S/2695. Only 0 may
be written to RMTS2, RMTS1, or RMTS0.
7.2.5 Bus Control
Register L (BCRL)
184
Note * amended
Note: * This function is not available in the H8S/2695. In writing to
OES, DDS, RCTS, the initial value should be written to these bits.
Rev. 5.00 Mar 28, 2005 page xxiii of lxii
Item
Page
Revision (See Manual for Details)
10A.1 Overview
373
SYNCI deleted from table
Table 10A.1 Port
Functions
Port Description
Port 7 • 8-bit I/O
port
Pins
Mode 4
P77/TxD3
P76/RxD3
P75/TMO3/SCK3
P74/TMO2/
P73/TMO1/
/
P72/TMO0/
/
Mode 5
P71/TMRI23/TMCI23/
/
P70/TMRI01/TMCI01/
/
10A.2.1 Overview
377
Mode 6
8-bit I/O port also functioning as 8-bit timer I/O
pins (TMRI01, TMCI01, TMRI23, TMCI23,
TMO0, TMO1, TMO2, TMO3), DMAC I/O pins
,
,
,
), bus
(
control output pins (
to
), SCI I/O pins
(SCK3, RxD3, TxD3), and the manual reset
input pin (
)
Mode 7
8-bit I/O port
also functioning as 8-bit
timer I/O pins
(TMRI01,
TMCI01,
TMRI23,
TMCI23,
TMO0, TMO1,
TMO2, TMO3),
DMAC I/O pins
(
,
,
,
), SCI
I/O pins
(SCK3, RxD3,
TxD3), and the
manual reset
input pin
(
)
Description amended
... Port 1 pins also function as PPG output pins, ... (PWM2 and
PWM3), external interrupt input pins (IRQ0, IRQ1), and address
bus output pins (A23 to A20). ...
10A.2.2 Register
Configuration
378
Port 1 Data Direction Register (P1DDR)
Description amended
Because PPG, TPU, DMAC, and PWM are initialized at a manual
reset, pin states are determined by P1DDR and P1DR.
10A.3.2 Register
Configuration
393
Port 3 Data Direction Register (P3DDR)
Description amended
... in hardware standby mode. The previous state is maintained by
a manual reset and in software standby mode. In manual reset
SCI and IIC are initialized, so the pin state is determined by the
specification of P3DDR and P3DR.
10A.3.3 Pin
Functions
394
Description amended
The port 3 pins double as SCI I/O input pins (TxD0, RxD0, SCK0,
IrTxD, IrRxD, TxD1, RxD1, SCK1, TxD4, RxD4, SCK4), external
interrupt input pins (IRQ4, IRQ5), and IIC I/O pins (SCL0, SDA0,
SCL1, SDA1). The functions ...
Rev. 5.00 Mar 28, 2005 page xxiv of lxii
Item
Page
Revision (See Manual for Details)
10A.3.3 Pin
Functions
395
Table amended
Pin
Table 10A.5 Port 3
Pin Functions
Selection Method and Pin Functions
Switches as follows according to combinations of ICCR0 ICE bit of IIC0, SMR C/
P35/SCK1/
SCK4/SCL0/ bit of SCI1 or SCI4, SCR CKE0 and CKE1 bits, and the P35DDR bit.
When used as a SCL0 I/O pin, always be sure to clear the following bits to 0: SMR
C/ bits of SCI1 or SCI4, and SCR CKE0 and CKE1 bits. Do not set SCK1 and
SCK4 to simultaneous output.
The SCL0 output format is NMOS open drain output, enabling direct bus driving.
ICE
0
1
CKE1 (SCI1)
CKE1 (SCI4)
0
0
C/ (SCI1)
C/ (SCI4)
0
0
CKE0 (SCI1)
CKE0 (SCI4)
0
0
P35DDR
Pin function
0
P35
input pin
1
0, 1, 1
1, 0, 1
0
0
1
1
—
0
0
2
0, 1, 1 *
2
1, 0, 1 *
—
—
0
0
—
—
—
P35
SCK1/SCK4 SCK1/SCK4 SCK1/SCK4
1
1
1
output pin* output pin* output pin*
input pin
—
SCL0
I/O pin
input
Notes: 1. Output type is NMOS push-pull. When P35ODR = 1, it becomes NMOS open
drain output.
2. SCK1 and SCK4 must not be output simultaneously.
10A.5.1 Overview
400
Description amended
... The port 7 is a multipurpose port for the 8-bit timer I/O pins
(TMRI01, TMCI01, TMRI23, TMCI23, TMO0, TMO1, TMO2, and
TMO3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1),
bus control output pins (CS4 to CS7), SCI I/O pins (SCK3, RxD3,
and TxD3), and manual reset input pins (MRES). ...
Figure 10A.4 Port
7 Pin Functions
Figure amended
Port 7
10A.5.3 Pin
Functions
403
Port 7 pins
Pin functions in modes 4 to 6
P77 / TxD3
P77 (I/O) / TxD3 (output)
P76 / RxD3
P76 (I/O) / RxD3 (input)
P75 / TMO3 / SCK3
P75 (I/O) / TMO3 (output) / SCK3 (I/O)
P74 / TMO2 / MRES
P74 (I/O) / TMO2 (output) / MRES (input)
P73 / TMO1 / TEND1 / CS7
P73 (input) / TMO1 (output) / TEND1 (output) / CS7 (output)
P72 / TMO0 / TEND0 / CS6
P72 (input) / TMO0 (output) / TEND0 (output) / CS6 (output)
P71 / TMRI23 / TMCI23 / DREQ1 / CS5
P71 (input) / TMRI23 (input) / TMCI23 (input) / DREQ1 (input) / CS5 (output)
P70 / TMRI01 / TMCI01 / DREQ0 / CS4
P70 (input) / TMRI01 (input) / TMCI01 (input) / DREQ0 (input) / CS4 (output)
Description amended
The port 7 are mulipurpose pins which function as 8-bit timer I/O
pins, (TMRI01, TMCI01, TMRI23, TMCI23, TMO0, TMO1, TMO2,
and TMO3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and
TEND1), bus control output pins (CS4 to CS7), SCI I/O pins
(SCK3, RxD3, and TxD3), and manual reset input pins (MRES). ...
Rev. 5.00 Mar 28, 2005 page xxv of lxii
Item
Page
Revision (See Manual for Details)
10A.5.3 Pin
Functions
404
SYNCI deleted from table
Table 10A.8 Port 7
Pin Functions
Pin
Selection Method and Pin Functions
P72/TMO0/
/
Switches as follows according to combinations of operating mode and DMATCR
TEE0 bit of DMAC, OS3 to OS0 bits of 8-bit timer TCSR0, and the P72DDR bit.
Modes 4 to 6
Operating
Mode
TEE0
0
OS3 to OS0
P72DDR
Pin function
10A.7.2 Register
Configuration
409
All 0
0
P72
input
pin
1
0
Any is 1
—
—
—
0
output
P72
input
pin
1
output
pin
M ode 7
TMO0
output
All 0
1
Any is 1
—
1
—
—
P72
output
pin
TMO0
output
output
Port A Data Direction Register (PADDR)
Description amended
•Modes 4 to 6
… irrespective of the value of bits PA3DDR to PA0DDR. When
pins are not used as address outputs, …
410
Port A Data Register (PADR)
Description amended
PADR is an 8-bit readable/writable register that stores output data
for port A pins (PA3 to PA0). …
Port A Register (PORTA)
Description amended
… Writing of output data for the port A pins (PA3 to PA0) must
always be performed on PADA. …
411
Port A Open Drain Control Register (PAODR)
Description amended
PAODR is an 8-bit readable/writable register that controls whether
PMOS is on or off for each port A pin (PA3 to PA0). …
Rev. 5.00 Mar 28, 2005 page xxvi of lxii
Item
Page
Revision (See Manual for Details)
10A.9.1 Overview
420
Figure amended
Figure 10A.12 Port
C Pin Functions
Port C
10A.13.2 Register
Configuration
444
Port C pins
Pin functions in modes 4 and 5
PC7/A7/PWM1
A7 (output)
PC6/A6/PWM0
A6 (output)
PC5/A5
A5 (output)
PC4/A4
A4 (output)
PC3/A3
A3 (output)
PC2/A2
A2 (output)
PC1/A1
A1 (output)
PC0/A0
A0 (output)
Pin functions in mode 6
Pin functions in mode 7
When PCDDR = 1
When PCDDR = 0
PC7 (I/O) / PWM1 (output)
A7 (output)
PC7 (input) / PWM1 (output)
PC6 (I/O) / PWM0 (output)
A6 (output)
PC6 (input) / PWM0 (output)
PC5 (I/O)
A5 (output)
PC5 (input)
PC4 (I/O)
A4 (output)
PC4 (input)
PC3 (I/O)
A3 (output)
PC3 (input)
PC2 (I/O)
A2 (output)
PC2 (input)
PC1 (I/O)
A1 (output)
PC1 (input)
PC0 (I/O)
A0 (output)
PC0 (input)
Port A Data Direction Register (PADDR)
Description amended
... In modes 4 and 5, the PGDDR bits are initialized to H'10 ...
10B.3.3 Pin
Functions
472
10B.4.1 Overview
475
Description amended
The port 3 pins double as SCI I/O input pins (TxD0, RxD0, SCK0,
TxD1, RxD1, SCK1, TxD4, RxD4, SCK4), external interrupt input
pins (IRQ4, IRQ5). The functions ...
Description amended
... Port 4 pins also function as A/D converter analog input pins
(AN0 to AN7). ...
10B.5.3 Pin
Functions
Table 10B.8 Port 7
Pin Functions
481
Table amended
Pin
Selection Method and Pin Functions
P72/
Switches as follows according to combinations of operating mode and the P72DDR
bit.
P72DDR
Pin function
Mode 7
Modes 4 to 6
Operating
Mode
0
P72 input
pin
1
output
pin
0
1
P72 input
pin
P72 output
pin
Rev. 5.00 Mar 28, 2005 page xxvii of lxii
Item
Page
Revision (See Manual for Details)
10B.7.2 Register
Configuration
486
Port A Data Register (PADR)
Description amended
PADR is an 8-bit readable/writable register that stores output data
for port A pins (PA3 to PA0). …
Port A Register (PORTA)
Description amended
… Writing of output data for the port A pins (PA3 to PA0) must
always be performed on PADA. …
487
Port A Open Drain Control Register (PAODR)
Description amended
00 00 00
PAODR is an 8-bit readable/writable register that controls whether
PMOS is on or off for each port A pin (PA3 to PA0). …
10B.9.1 Overview
496
Figure amended
Figure 10B.12 Port
C Pin Functions
Port C
10B.13.2 Register
Configuration
519
Port C pins
Pin functions in modes 4 and 5
PC7/A7
A7 (output)
PC6/A6
A6 (output)
PC5/A5
A5 (output)
PC4/A4
A4 (output)
PC3/A3
A3 (output)
PC2/A2
A2 (output)
PC1/A1
A1 (output)
PC0/A0
A0 (output)
Pin functions in mode 6
Pin functions in mode 7
When PCDDR = 1
When PCDDR = 0
PC7 (I/O)
A7 (output)
PC7 (input)
PC6 (I/O)
A6 (output)
PC6 (input)
PC5 (I/O)
A5 (output)
PC5 (input)
PC4 (I/O)
A4 (output)
PC4 (input)
PC3 (I/O)
A3 (output)
PC3 (input)
PC2 (I/O)
A2 (output)
PC2 (input)
PC1 (I/O)
A1 (output)
PC1 (input)
PC0 (I/O)
A0 (output)
PC0 (input)
Port G Data Direction Register (PGDDR)
Description amended
... In modes 4 and 5, the PGDDR bits are initialized to H'10 ...
Rev. 5.00 Mar 28, 2005 page xxviii of lxii
Item
Page
Revision (See Manual for Details)
11.2.1 Timer
Control Register
(TCR)
534
Bits 4 and 3Clock Edge 1 and 0 (CKEG1, CKEG0)
11.7 Usage Notes
615
Note of bit table amended
Note: Internal clock edge selection is valid when the input clock is
φ/4 or slower. This setting is ignored if the input clock is φ/1, or
when overflow/underflow of another channel is selected. (The
clock is counted at the falling edge when φ/1 is selected.)
Figure 11.57
Contention
between TCNT
Write and Overflow
15.1.2 Block
Diagram
Figure amended
TCNT
H'FFFF
M
Prohibited
TCFV flag
684
Note *2 added
Overflow
Figure 15.1 (a)
Block Diagram of
WDT0
WOVI 0
(interrupt request
signal)
WDTOVF
Internal reset signal*1
φ/2*2
φ/64*2
φ/128*2
φ/512*2
φ/2048*2
φ/8192*2
φ/32768*2
φ/131072*2
Interrupt
control
Clock
Reset
control
Clock
select
Internal clock
sources
Notes: 1. The type of internal reset signal depends on a register
setting.
2. The φ in the subactive and subsleep mode is φSUB.
15.2.2 Timer
Control/Status
Register (TCSR)
691
WDT0 Input Clock Select
Note *2 added
Clock*2 Overflow Period*1
Notes: 1. An overflow period is the time interval ...
2. The φ in the subactive and subsleep mode is φSUB.
16.3.2 Operation
in Asynchronous
Mode
Figure 16.7
Sample Serial
Reception Data
Format
746
Note * added
DMAC* DTC*
Note: * The DMAC and DTC are not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page xxix of lxii
Item
Page
Revision (See Manual for Details)
16.5 Usage Notes
776
Operation in Case of Mode Transmission
• Transmission
Note * added
Operation should be also stopped ... before making a transition
from transmission by DTC* transfer to module stop mode,
software standby mode, watch mode*, subactive mode*, or
subsleep mode* transition. To perform transmission with the DTC*
after the relevant mode is cleared, setting TE and TIE to 1 will set
the TXI flag and start DTC* transimmsion.
Note: * The DTC is not available in the H8S/2695.
779
Figure 16.28
Sample Flowchart
for Mode Transition
during Reception
17.3.6 Data
Transfer
Operations
803
Note * added
[2] Includes module stop mode, watch mode*, subactive mode*,
and subsleep mode*.
Note: * In the H8S/2695, the watch mode, subactive mode, and
subsleep mode are not available.
Serial Data Transmission (Except Block Transfer Mode)
Note * added
DMAC* DTC*
Note: * The DMAC and DTC are not available in the H8S/2695.
807
Serial Data Reception (Except Block Transfer Mode)
Note * added
DMAC* DTC*
Note: * The DMAC and DTC are not available in the H8S/2695.
18.2.2 Slave
Address Register
(SAR)
825
Description amended
Bit 0  Format Select (FS): Used together with the FSX bit in
SARX to select the communication format.
826
Bit table amended
SAR
Bit 0
SARX
Bit 0
FS
FSX
Operating Mode
0
0
I C bus format
2
•
1
1
0
1
•
SAR slave address recognized
•
SARX slave address ignored
2
I C bus format
•
SAR slave address ignored
•
SARX slave address recognized
Synchronous serial format
•
Rev. 5.00 Mar 28, 2005 page xxx of lxii
SAR and SARX slave addresses recognized
2
I C bus format
SAR and SARX slave addresses ignored
(Initial value)
Item
Page
Revision (See Manual for Details)
18.2.3 Second
Slave Address
Register (SARX)
826
Bit 0  Format Select X (FSX):
18.2.5 I2C Bus
Control Register
(ICCR)
832
18.2.6 I2C Bus
Status Register
(ICSR)
842
Description amended
Used together with the FS bit in SAR to select the communication
format.
Bit 4  Transmit/Receive Select (TRS)
No.4 description deleted from clearing conditions
Description amended
Bit 0  Acknowledge Bit (ACKB)
... the value set by internal software is read. In addition, writing to
this bit overwrites the setting for acknowledge data sent when
receiving data, regardless of the TRS value. In this case the value
loaded from the receive device is maintained unchanged, so
caution is necessary when using instructions that manipulate the
bits in this register.
18.3.2 Initial Setting 848
Figure 18.6
Flowchart for IIC
Initialization
(Example)
Figure amended
Start initialization
Set MSTP4 = 0 (IIC0)
MSTP3 = 0 (IIC1)
(MSTPCRL)
Clear module stop.
Set IICE = 1 (STCR)
Enable CPU access by IIC control register and data register.
Set DDCSWR
18.3.4 Master
Receive Operation
853
Clear IIC internal latch
Figure amended
Master receive mode
Figure 18.10
Flowchart for Master
Receive Mode
(Receiving Multiple
Bytes) (WAIT = 1)
(Example)
Set TRS = 0 (ICCR)
Set ACKB = 0 (ICSR)
[1] Set to receive mode.
Set WAIT = 1 (ICMR)
855
Description amended
[1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to
receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data
setting). Then set the WAIT bit in ICMR to 1.
Rev. 5.00 Mar 28, 2005 page xxxi of lxii
Item
Page
18.3.11 Initialization 869
of Internal State
Revision (See Manual for Details)
Description amended
To prevent problems ... the IC state.
1. Execute initialization of the internal state according to the setting
of bits CLR3 to CLR0.
2. Clear of bits BC2 to BC0.
3. Execute a stop condition issuance instruction ...
4. R-execute initialization of internal state according to the setting
of bits CLR3 to CLR0.
5. Initialize (reset) the IIC registers.
18.4 Usage Notes
871
Table 18.7
Permissible SCL
Rise Time (tSr)
Values
Table amended
Time Indication
2
I C Bus
Specification φ =
(Max.)
5 MHz
tcyc
IICX Indication
0
7.5tcyc
φ=
8 MHz
φ=
φ=
φ=
φ=
φ=
10 MHz 16 MHz 20 MHz 25 MHz 28 MHz
Standard
mode
1000 ns
1000 ns 937 ns
750 ns
468 ns
375 ns
—
—
High-speed
mode
300 ns
300 ns
300 ns
300 ns
300 ns
—
—
300 ns
Note: When 7.5 tcyc is selected as the transfer rate, the actual
transfer rate may be extended if φ exceeds 20 MHz.
878, 879
Notes on Arbitration Lost in Master Mode
Description added
19.2.2 A/D
Control/Status
Register (ADCSR)
886
Description and note * amende
Bit 7  A/D End Flag (ADF)
[Clearing conditions]
... • When the DMAC* or DTC* is activated by an ADI interrupt
and ADDR is read
Note: * The DMAC and DTC functions are not available in the
H8S/2695.
20.1.4 Register
Configuration
907
Address of MSTPCRA amended
(Before) H'FDF8 → (After) H'FDE8
Table 20.2 D/A
Converter Registers
22.1 Overview
917
Description amended
The H8S/2633 Group and H8S/2633R have 256-kbytes of on-chip
flash memory, or 256 kbytes of on-chip mask ROM, the H8S/2632,
H8S/2695 have 192 kbytes of mask ROM, and H8S/2631 has 128
kbytes of mask ROM. The ROM is ...
Rev. 5.00 Mar 28, 2005 page xxxii of lxii
Item
Page
Revision (See Manual for Details)
22.11.1 Socket
Adapter and
Memory Map
961
Description replaced
Table 22.14
Socket Adapter
Models
Table 22.14 added

Figure of Socket Adapter Pin Correspondence Diagram deleted
22.14 Note on
980
Switching from FZTAT Version to
mask ROM Version
Table amended
Table 22.27
Registers Present
in F-ZTAT Version
but Absent in mask
ROM Version
23A.2.2 LowPower Control
Register
(LPWRCR)
984
23B.2.2 LowPower Control
Register
(LPWRCR)
997
24.1 Overview
1006
Table 24.1 LSI
Internal States in
Each Operating
Mode
Register
Abbreviation
Address
Flash memory control register 1
FLMCR1
H'FFA8
Flash memory control register 2
FLMCR2
H'FFA9
Erase block register 1
EBR1
H'FFAA
Erase block register 2
EBR2
H'FFAB
Note amended
Bits 1 and 0Frequency Multiplication Factor (STC1, STC0)
Note: A system clock frequency multiplied by the multiplication
factor (STC1 and STC0) should not exceed the maximum
operating frequency defined in section 25, Electrical
Characteristics. Current consumption and noise can be reduced by
using this function’s PLL ×4 setting and lowering the external clock
frequency.
Note amended
Bits 1 and 0Frequency Multiplication Factor (STC1, STC0)
00 00
Note: A system clock frequency multiplied by the multiplication
factor (STC1 and STC0) should not exceed the maximum
operating frequency defined in sections 26 and 27, Electrical
Characteristics. Current consumption and noise can be reduced by
using this function’s PLL ×4 setting and lowering the external clock
frequency. The input clock frequency ...
Note 6 amended
Note: 6. With the exception of ports D and E, an I/O port always
returns a value of 1 when read in the H8S/2633 Group and
H8S/2633R. Use as an output port is possible.
Rev. 5.00 Mar 28, 2005 page xxxiii of lxii
Item
Page
Revision (See Manual for Details)
24.6.3 Setting
Oscillation
Stabilization Time
after Clearing
Software Standby
Mode
1024
Description amended
24.10.3 Usage
Notes
1033
Using a Crystal Oscillator: Set bits STS2 to STS0 so that the
standby time is at least 8 ms (the oscillation stabilization time) (at
least 5 ms for the H8S/2633R or H8S/2695).
(2) Interrupt sources and subactive mode/watch mode transition
Description amended
For on-Chip peripheral modules that stop operating in subactive
mode (DMAC, DTC, TPU, PCB, IIC), a corresponding interrupt
cannot be cleared in subactive mode. ...
24.12 φ Clock
Output Disabling
Function
1034
Description amended, note * added
... in each processing state. Using the on-chip PLL circuit to lower
the oscillator frequency or prohibiting external φ clock output also
have the effect of reducing unwanted electromagnetic
interference*. Therefore, consideration should be given to these
options when deciding on system board settings.
Note: * Electromagnetic interference: EMI (Electro Magnetic
Interference)
25.3.1 Clock Timing 1045
Table amended
Table 25.5 Clock
Timing
25.4 A/D
Conversion
Characteristics
Table 25.11 A/D
Conversion
Characteristics
Condition A
Condition B
16MHz
1071
25MHz
Item
Symbol
Min
Max
Min
Max
Unit
Clock fall time
tCf
—
12
—
5
ns
Test Conditions
Clock oscillator settling
time at reset (crystal)
tOSC1
20
—
10
—
ms
Figure 25.3
Clock oscillator settling
time in software standby
(crystal)
tOSC2
10
—
8
—
ms
Figure 24.3
External clock output
stabilization delay time
tDEXT
2
—
2
—
ms
Figure 25.3
Table condition amended and notes *1, *2 added
Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V,
AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS =
PLLVSS = 0 V, φ = 32.768 kHz, 2 to 16 MHz, ...
Condition B: ... φ = 32.768 kHz, 2 to 25 MHz, ...
Notes: 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are
not used (used as I/O ports).
2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used
(used as I/O ports).
Rev. 5.00 Mar 28, 2005 page xxxiv of lxii
Item
Page
Revision (See Manual for Details)
25.5 D/A
Conversion
Characteristics
1072
Table condition amended and notes *1, *2 added
Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V,
AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS =
PLLVSS = 0 V, φ = 32.768 kHz, 2 to 16 MHz, ...
Table 25.12 D/A
Conversion
Characteristics
Condition B: ... φ = 32.768 kHz, 2 to 25 MHz, ...
Notes: 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are
not used (used as I/O ports).
2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used
(used as I/O ports).
A.1 Instruction List 1137
(1) Data Transfer Instructions
Table A.1
Instruction Set
Note *4 added
LDM*4 STM*4
1156
Notes *4, [10], [11] added
Notes: 4. Only register ER0 to ER6 should be used when using the
STM/LDM instruction.
[10] MAC instruction results are indicated in the flags when the
STMAC instruction is executed.
[11] A maximum of three additional states are required for
execution of one of these instructions within three states after
execution of a MAC instruction. For example, if there is a one-state
instruction (such as NOP) between a MAC instruction and one of
these instructions, that instruction will be two states longer.
A.2 Instruction
Codes
1165
Note *3 added
LDM*3
Table A.2
Instruction Codes
1170
STM*3
1171
Note: 3. Only register ER0 to ER6 should be used when using the
STM/LDM instruction.
1166
Table amended
(Before) MOV.L #xx:32,Rd → (After) MOV.L #xx:32,ERd
A.4 Number of
1184
States Required for
Instruction
1188
Execution
Table A.5 Number 1189
of Cycles in
Instruction
Execution
Note *5 added
5
LDM*
STM*5
Note: 5. Only register ER0 to ER6 should be used when using the
STM/LDM instruction.
Rev. 5.00 Mar 28, 2005 page xxxv of lxii
Item
Page
Revision (See Manual for Details)
A.5 Bus States
during Instruction
Execution
1197
Note *9 added
LDM.L @SP+, (ERn-ERn+1)*9
LDM.L @SP+, (ERn-ERn+2)*9
1202
LDM.L @SP+, (ERn-ERn+3)*9
STM.L (ERn-ERn+1), @-SP*9
STM.L (ERn-ERn+2), @-SP *9
STM.L (ERn-ERn+3), @-SP *9
A.6 Condition
Code Modification
Table A.7
Condition Code
Modification
1203
Note: 9. Only register ER0 to ER6 should be used when using the
STM/LDM instruction.
1206
Note *2 added
LDM*2
1208
STM*2
TAS*2
1209
Notes: 1. This instruction should be used with ...
2. Only register ER0 to ER6 should be used when using the
STM/LDM instruction.
B.1A Addresses
(H8S/2633 Group,
H8S/2633F,
H8S/2633R)
1210
Table amended
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'FDB0
IrCR
IrE
IrCKS2
IrCKS1
IrCKS0
—
—
—
—
SCI0,
IrDA
H'FDB4
SCRX
—
IICX1
IICX0
IICE
FLSHE
—
—
—
IIC
8
H'FDB5
DDCSWR
—
—
—
—
CLR3
CLR2
CLR1
CLR0
IIC
8
H'FDB8
DADRAH0/ DA13/
DACR0
TEST
DA12/
PWME
DA11/
—
DA10/
—
DA9/
OEB
DA8/
OEA
DA7/
OS
DA6/
CKS
PWM0
8
Rev. 5.00 Mar 28, 2005 page xxxvi of lxii
Module
Name
Data Bus
Width
(bits)
Register
Address Name
8
Item
Page
Revision (See Manual for Details)
B.2 Functions
1228
SCRX H'FDB4 IIC
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
—
IICX1
IICX0
IICE
FLSHE
—
—
—
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Flash memory control register enable
0
Excludes addresses H'FFFFA8 to H'FFFFAC as flash control
registers.
(Initial value)
1
Selects addresses H'FFFFA8 to H'FFFFAC as flash control
registers.
I2C master enable
0
1
2
Disables CPU access of I C bus interface data register and control
register.
2
Enables CPU access of I C bus interface data register and control
register.
I2C transfer rate select 1, 0
Selects the transfer rate in master mode in conjunction with CKS2 to CKS0 in ICMR.
See the section on the I2C bus mode register (ICMR) for details.
1246
MDCA H'FDE7 System
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
—
—
—
—
—
MDS2
MDS1
MDS0
1
0
0
0
0
—*
—*
—*
R/W
—
—
—
—
R
R
R
Mode select 2 to 0
* Input level determined by mode pins.
Note: * Determined by pins MD2 to MD0.
MSTPCRA H'FDE8 System
Bit
:
7
6
5
4
3
2
1
0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
R/W
:
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Module stop
0
Module stop mode is cleared.
1
Module stop mode is set.
MSTPCRB H'FDE9 System
Bit
:
7
6
5
4
3
2
1
0
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
Initial value :
R/W
:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Module stop
0
Module stop mode canceled.
1
Module stop mode enabled.
Rev. 5.00 Mar 28, 2005 page xxxvii of lxii
Item
Page
Revision (See Manual for Details)
B.2 Functions
1247
MSTPCRC H'FDEA System
Bit
:
7
6
5
4
3
2
1
0
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value :
R/W
:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Module stop
1249
0
Module stop mode canceled.
1
Module stop mode enabled.
LPWRCR H'FDEC System
Bit
:
7
6
5
4
3
DTON*1 LSON*1 NESEL*1 SUBSTP*1 RFCUT*1
Initial value :
R/W
:
2
1
0
—
STC1
STC0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Frequency multiplier
STC1
0
1
STC0
0
1
0
1
Description
× 1 (initial value)
×2
×4
Do not set.
Note: A system clock frequency multiplied by the multiplication factor
(STC1 and STC0) should not exceed the maximum operating
frequency defined in sections 25, 26, and 27, Electrical
Characteristics.
Current consumption and noise can be reduced by using this
function’s PLL ×4 setting and lowering the external clock frequency.
1279
Description amended
TCNT3Timer Counter 3 H'FE86 TPU3 (Up Counter)
TCNT4Timer Counter 4 H'FE96 TPU4 (Up/Down Counter*)
TCNT5Timer Counter 5 H'FEA6 TPU5 (Up/Down Counter*)
TCNT0Timer Counter 0 H'FF16 TPU0 (Up Counter)
TCNT1Timer Counter 1 H'FF26 TPU1 (Up/Down Counter*)
TCNT2Timer Counter 2 H'FF36 TPU2 (Up/Down Counter*)
1286
Note * added
Refresh timer*
Rev. 5.00 Mar 28, 2005 page xxxviii of lxii
Item
Page
Revision (See Manual for Details)
C.4 Port 7 Block
Diagram
1341
Figure amended
RDR7
8-bit timer
Figure C.4 (b) Port
7 Block Diagram
(Pin P72)
C.12 Port G Block
Diagram
Timer output TMO0
Timer output enable
RPOR7
1366
Figure amended
OE output
OE output enable
Figure C.12 (b)
Port G Block
Diagram (Pin PG1)
Bus controller
Chip select
RDRG
RPORG
IRQ interrupt input
C.16 Port 7 Block
Diagram
1384
Figure title amended

Figure of Port 7 Block Diagram (Pin P72) deleted

Figure of Port 7 Block Diagram (Pin P73) deleted
1395
Figure title amended

Figure of Port C Block Diagram (Pins PC6 and PC7) deleted
Figure C.16 (a)
Port 7 Block
Diagram (Pins P70
to P73)
C.20 Port C Block
Diagram
Figure C.20 Port C
Block Diagram
(Pins PC0 to PC7)
Rev. 5.00 Mar 28, 2005 page xxxix of lxii
Item
Page
Revision (See Manual for Details)
C.24 Port G Block
Diagram
1407
Figure amended
Bus controller
Figure C.24 (b)
Port G Block
Diagram (Pin PG1)
Chip select
RDRG
RPORG
IRQ interrupt input
Appendix G
Package
Dimensions
1420
Figure G.1 replaced
1421
Figure G.2 replaced
Figure G.1
TFP-120 Package
Dimensions
Figure G.2
FP-128B Package
Dimensions
Rev. 5.00 Mar 28, 2005 page xl of lxii
Contents
Section 1 Overview.............................................................................................................
1.1
1.2
1.3
Overview...........................................................................................................................
Internal Block Diagram.....................................................................................................
Pin Description .................................................................................................................
1.3.1 Pin Arrangement..................................................................................................
1.3.2 Pin Functions in Each Operating Mode ...............................................................
1.3.3 Pin Functions .......................................................................................................
1
1
7
11
11
16
31
Section 2 CPU ...................................................................................................................... 49
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Overview...........................................................................................................................
2.1.1 Features................................................................................................................
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................
2.1.3 Differences from H8/300 CPU ............................................................................
2.1.4 Differences from H8/300H CPU .........................................................................
CPU Operating Modes......................................................................................................
Address Space...................................................................................................................
Register Configuration......................................................................................................
2.4.1 Overview..............................................................................................................
2.4.2 General Registers.................................................................................................
2.4.3 Control Registers .................................................................................................
2.4.4 Initial Register Values .........................................................................................
Data Formats.....................................................................................................................
2.5.1 General Register Data Formats............................................................................
2.5.2 Memory Data Formats.........................................................................................
Instruction Set...................................................................................................................
2.6.1 Overview..............................................................................................................
2.6.2 Instructions and Addressing Modes.....................................................................
2.6.3
Table of Instructions Classified by Function ......................................................
2.6.4 Basic Instruction Formats ....................................................................................
Addressing Modes and Effective Address Calculation.....................................................
2.7.1 Addressing Mode.................................................................................................
2.7.2 Effective Address Calculation .............................................................................
Processing States ..............................................................................................................
2.8.1 Overview..............................................................................................................
2.8.2 Reset State ...........................................................................................................
2.8.3 Exception-Handling State ....................................................................................
2.8.4 Program Execution State .....................................................................................
49
49
50
51
52
52
57
58
58
59
60
62
63
63
65
66
66
67
69
77
79
79
82
86
86
87
88
90
Rev. 5.00 Mar 28, 2005 page xli of lxii
2.8.5 Bus-Released State ..............................................................................................
2.8.6 Power-Down State ...............................................................................................
2.9 Basic Timing.....................................................................................................................
2.9.1 Overview..............................................................................................................
2.9.2 On-Chip Memory (ROM, RAM).........................................................................
2.9.3 On-Chip Supporting Module Access Timing ......................................................
2.9.4 External Address Space Access Timing ..............................................................
2.10 Usage Note .......................................................................................................................
2.10.1 TAS Instruction ...................................................................................................
2.10.2 STM/LDM Instruction.........................................................................................
2.10.3 Usage Notes on Bit Manipulation Instructions ....................................................
91
91
92
92
92
93
95
95
95
95
95
Section 3 MCU Operating Modes .................................................................................. 97
3.1
3.2
3.3
3.4
3.5
Overview...........................................................................................................................
3.1.1 Operating Mode Selection ...................................................................................
3.1.2 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
3.2.1 Mode Control Register (MDCR) .........................................................................
3.2.2 System Control Register (SYSCR)......................................................................
3.2.3 Pin Function Control Register (PFCR) ................................................................
Operating Mode Descriptions ...........................................................................................
3.3.1 Mode 4.................................................................................................................
3.3.2 Mode 5.................................................................................................................
3.3.3 Mode 6.................................................................................................................
3.3.4 Mode 7.................................................................................................................
Pin Functions in Each Operating Mode ............................................................................
Address Map in Each Operating Mode.............................................................................
97
97
98
98
98
99
101
104
104
104
104
105
105
106
Section 4 Exception Handling ......................................................................................... 111
4.1
4.2
4.3
Overview...........................................................................................................................
4.1.1 Exception Handling Types and Priority...............................................................
4.1.2 Exception Handling Operation ............................................................................
4.1.3 Exception Vector Table .......................................................................................
Reset .................................................................................................................................
4.2.1 Overview..............................................................................................................
4.2.2 Types of Reset .....................................................................................................
4.2.3 Reset Sequence ....................................................................................................
4.2.4 Interrupts after Reset............................................................................................
4.2.5 State of On-Chip Supporting Modules after Reset Release .................................
Traces................................................................................................................................
Rev. 5.00 Mar 28, 2005 page xlii of lxii
111
111
112
112
114
114
114
115
117
118
118
4.4
4.5
4.6
4.7
Interrupts...........................................................................................................................
Trap Instruction ................................................................................................................
Stack Status after Exception Handling..............................................................................
Notes on Use of the Stack.................................................................................................
119
120
121
122
Section 5 Interrupt Controller .......................................................................................... 123
5.1
5.2
5.3
5.4
5.5
5.6
Overview...........................................................................................................................
5.1.1 Features................................................................................................................
5.1.2 Block Diagram.....................................................................................................
5.1.3 Pin Configuration ................................................................................................
5.1.4 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
5.2.1 System Control Register (SYSCR)......................................................................
5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO).............................
5.2.3 IRQ Enable Register (IER) ..................................................................................
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL).....................................
5.2.5 IRQ Status Register (ISR)....................................................................................
Interrupt Sources...............................................................................................................
5.3.1 External Interrupts ...............................................................................................
5.3.2 Internal Interrupts ................................................................................................
5.3.3 Interrupt Exception Handling Vector Table.........................................................
Interrupt Operation ...........................................................................................................
5.4.1 Interrupt Control Modes and Interrupt Operation................................................
5.4.2 Interrupt Control Mode 0.....................................................................................
5.4.3 Interrupt Control Mode 2.....................................................................................
5.4.4 Interrupt Exception Handling Sequence ..............................................................
5.4.5 Interrupt Response Times ....................................................................................
Usage Notes ......................................................................................................................
5.5.1 Contention between Interrupt Generation and Disabling.....................................
5.5.2 Instructions that Disable Interrupts......................................................................
5.5.3 Times when Interrupts are Disabled ....................................................................
5.5.4 Interrupts during Execution of EEPMOV Instruction .........................................
5.5.5 IRQ Interrupt .......................................................................................................
5.5.6 NMI Interrupt Usage Notes .................................................................................
DTC and DMAC Activation by Interrupt
(DMAC and DTC functions are not available in the H8S/2695)......................................
5.6.1 Overview..............................................................................................................
5.6.2 Block Diagram.....................................................................................................
5.6.3 Operation (DMAC and DTC functions are not available in the H8S/2695) ........
123
123
124
125
125
126
126
127
128
129
130
131
131
132
132
142
142
146
148
150
151
152
152
153
153
154
154
154
155
155
156
157
Rev. 5.00 Mar 28, 2005 page xliii of lxii
Section 6 PC Break Controller (PBC)
(This function is not available in the H8S/2695) .................................... 159
6.1
6.2
6.3
Overview...........................................................................................................................
6.1.1 Features................................................................................................................
6.1.2 Block Diagram.....................................................................................................
6.1.3 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
6.2.1 Break Address Register A (BARA) .....................................................................
6.2.2 Break Address Register B (BARB) .....................................................................
6.2.3 Break Control Register A (BCRA) ......................................................................
6.2.4 Break Control Register B (BCRB) ......................................................................
6.2.5 Module Stop Control Register C (MSTPCRC) ...................................................
Operation ..........................................................................................................................
6.3.1 PC Break Interrupt Due to Instruction Fetch .......................................................
6.3.2 PC Break Interrupt Due to Data Access ..............................................................
6.3.3 Notes on PC Break Interrupt Handling................................................................
6.3.4 Operation in Transitions to Power-Down Modes ................................................
6.3.5 PC Break Operation in Continuous Data Transfer...............................................
6.3.6 When Instruction Execution is Delayed by One State .........................................
6.3.7 Additional Notes..................................................................................................
159
159
160
161
161
161
161
162
164
164
165
165
166
166
167
168
169
170
Section 7 Bus Controller ................................................................................................... 171
7.1
7.2
7.3
Overview...........................................................................................................................
7.1.1 Features................................................................................................................
7.1.2 Block Diagram.....................................................................................................
7.1.3 Pin Configuration ................................................................................................
7.1.4 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
7.2.1 Bus Width Control Register (ABWCR)...............................................................
7.2.2 Access State Control Register (ASTCR) .............................................................
7.2.3 Wait Control Registers H and L (WCRH, WCRL)..............................................
7.2.4 Bus Control Register H (BCRH) .........................................................................
7.2.5 Bus Control Register L (BCRL) ..........................................................................
7.2.6 Pin Function Control Register (PFCR) ................................................................
7.2.7 Memory Control Register (MCR)........................................................................
7.2.8 DRAM Control Register (DRAMCR) .................................................................
7.2.9 Refresh Timer Counter (RTCNT)........................................................................
7.2.10 Refresh Time Constant Register (RTCOR) .........................................................
Overview of Bus Control..................................................................................................
7.3.1 Area Partitioning..................................................................................................
Rev. 5.00 Mar 28, 2005 page xliv of lxii
171
171
173
174
175
176
176
177
178
181
184
186
189
191
193
193
194
194
7.3.2 Bus Specifications ...............................................................................................
7.3.3 Memory Interfaces...............................................................................................
7.3.4 Interface Specifications for Each Area ................................................................
7.3.5 Chip Select Signals ..............................................................................................
7.4 Basic Bus Interface ...........................................................................................................
7.4.1 Overview..............................................................................................................
7.4.2 Data Size and Data Alignment.............................................................................
7.4.3 Valid Strobes .......................................................................................................
7.4.4 Basic Timing........................................................................................................
7.4.5 Wait Control ........................................................................................................
7.5 DRAM Interface (This function is not available in the H8S/2695) ..................................
7.5.1 Overview..............................................................................................................
7.5.2 Setting up DRAM Space......................................................................................
7.5.3 Address Multiplexing ..........................................................................................
7.5.4 Data Bus ..............................................................................................................
7.5.5 DRAM Interface Pins ..........................................................................................
7.5.6 Basic Timing........................................................................................................
7.5.7 Precharge State Control .......................................................................................
7.5.8 Wait Control ........................................................................................................
7.5.9 Byte Access Control ............................................................................................
7.5.10 Burst Operation....................................................................................................
7.5.11 Refresh Control....................................................................................................
7.6 DMAC Single Address Mode and DRAM Interface
(This function is not available in the H8S/2695) ..............................................................
7.6.1 DDS=1 .................................................................................................................
7.6.2 DDS=0 .................................................................................................................
7.7 Burst ROM Interface ........................................................................................................
7.7.1 Overview..............................................................................................................
7.7.2 Basic Timing........................................................................................................
7.7.3 Wait Control ........................................................................................................
7.8 Idle Cycle..........................................................................................................................
7.8.1 Operation .............................................................................................................
7.8.2 Pin States in Idle Cycle........................................................................................
7.9 Write Data Buffer Function ..............................................................................................
7.10 Bus Release.......................................................................................................................
7.10.1 Overview..............................................................................................................
7.10.2 Operation .............................................................................................................
7.10.3 Pin States in External Bus Released State ...........................................................
7.10.4 Transition Timing ................................................................................................
7.10.5 Notes....................................................................................................................
195
196
197
198
199
199
199
201
202
210
212
212
212
213
213
214
214
216
217
219
221
225
229
229
230
231
231
231
233
234
234
238
239
240
240
240
241
242
243
Rev. 5.00 Mar 28, 2005 page xlv of lxii
7.11 Bus Arbitration (DMAC and DTC functions are not available in the H8S/2695) ...........
7.11.1 Overview..............................................................................................................
7.11.2 Operation .............................................................................................................
7.11.3 Bus Transfer Timing............................................................................................
7.12 Resets and the Bus Controller...........................................................................................
244
244
244
245
245
Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695) .................................... 247
8.1
8.2
8.3
8.4
8.5
Overview...........................................................................................................................
8.1.1 Features................................................................................................................
8.1.2 Block Diagram.....................................................................................................
8.1.3 Overview of Functions ........................................................................................
8.1.4 Pin Configuration ................................................................................................
8.1.5 Register Configuration.........................................................................................
Register Descriptions (1) (Short Address Mode)..............................................................
8.2.1 Memory Address Registers (MAR) .....................................................................
8.2.2 I/O Address Register (IOAR) ..............................................................................
8.2.3 Execute Transfer Count Register (ETCR) ...........................................................
8.2.4 DMA Control Register (DMACR) ......................................................................
8.2.5 DMA Band Control Register (DMABCR) ..........................................................
Register Descriptions (2) (Full Address Mode)................................................................
8.3.1 Memory Address Register (MAR).......................................................................
8.3.2 I/O Address Register (IOAR) ..............................................................................
8.3.3 Execute Transfer Count Register (ETCR) ...........................................................
8.3.4 DMA Control Register (DMACR) ......................................................................
8.3.5 DMA Band Control Register (DMABCR) ..........................................................
Register Descriptions (3) ..................................................................................................
8.4.1 DMA Write Enable Register (DMAWER)..........................................................
8.4.2 DMA Terminal Control Register (DMATCR) ....................................................
8.4.3 Module Stop Control Register (MSTPCR)..........................................................
Operation ..........................................................................................................................
8.5.1 Transfer Modes....................................................................................................
8.5.2 Sequential Mode ..................................................................................................
8.5.3 Idle Mode.............................................................................................................
8.5.4 Repeat Mode........................................................................................................
8.5.5 Single Address Mode...........................................................................................
8.5.6 Normal Mode.......................................................................................................
8.5.7 Block Transfer Mode...........................................................................................
8.5.8 DMAC Activation Sources..................................................................................
8.5.9 Basic DMAC Bus Cycles ....................................................................................
Rev. 5.00 Mar 28, 2005 page xlvi of lxii
247
247
248
249
251
252
253
254
255
256
258
262
268
268
268
269
271
275
280
280
283
284
285
285
287
290
293
297
300
303
309
312
8.5.10
8.5.11
8.5.12
8.5.13
8.5.14
8.6
8.7
DMAC Bus Cycles (Dual Address Mode)...........................................................
DMAC Bus Cycles (Single Address Mode) ........................................................
Write Data Buffer Function .................................................................................
DMAC Multi-Channel Operation........................................................................
Relation between External Bus Requests, Refresh Cycles, the DTC,
and the DMAC.....................................................................................................
8.5.15 NMI Interrupts and DMAC .................................................................................
8.5.16 Forced Termination of DMAC Operation ...........................................................
8.5.17 Clearing Full Address Mode................................................................................
Interrupts...........................................................................................................................
Usage Notes ......................................................................................................................
313
321
327
328
329
330
331
332
333
334
Section 9 Data Transfer Controller (DTC)
(This function is not available in the H8S/2695) .................................... 339
9.1
9.2
9.3
Overview...........................................................................................................................
9.1.1 Features................................................................................................................
9.1.2 Block Diagram.....................................................................................................
9.1.3 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
9.2.1 DTC Mode Register A (MRA) ............................................................................
9.2.2 DTC Mode Register B (MRB).............................................................................
9.2.3 DTC Source Address Register (SAR)..................................................................
9.2.4 DTC Destination Address Register (DAR)..........................................................
9.2.5 DTC Transfer Count Register A (CRA) ..............................................................
9.2.6 DTC Transfer Count Register B (CRB)...............................................................
9.2.7 DTC Enable Registers (DTCER).........................................................................
9.2.8 DTC Vector Register (DTVECR)........................................................................
9.2.9 Module Stop Control Register A (MSTPCRA) ...................................................
Operation ..........................................................................................................................
9.3.1 Overview..............................................................................................................
9.3.2 Activation Sources...............................................................................................
9.3.3 DTC Vector Table ...............................................................................................
9.3.4 Location of Register Information in Address Space ............................................
9.3.5 Normal Mode.......................................................................................................
9.3.6 Repeat Mode........................................................................................................
9.3.7 Block Transfer Mode...........................................................................................
9.3.8 Chain Transfer .....................................................................................................
9.3.9 Operation Timing.................................................................................................
9.3.10 Number of DTC Execution States .......................................................................
9.3.11 Procedures for Using DTC ..................................................................................
339
339
340
341
342
342
343
344
345
345
346
346
347
348
349
349
351
353
357
358
359
360
362
363
364
366
Rev. 5.00 Mar 28, 2005 page xlvii of lxii
9.4
9.5
9.3.12 Examples of Use of the DTC............................................................................... 367
Interrupts........................................................................................................................... 370
Usage Notes ...................................................................................................................... 370
Section 10A I/O Ports
(H8S/2633, H8S/2632, H8S/2631, H8S/2633R) ............................... 371
10A.1
10A.2
10A.3
10A.4
10A.5
10A.6
10A.7
10A.8
10A.9
Overview.......................................................................................................................
Port 1 .............................................................................................................................
10A.2.1 Overview ......................................................................................................
10A.2.2 Register Configuration .................................................................................
10A.2.3 Pin Functions ................................................................................................
Port 3 .............................................................................................................................
10A.3.1 Overview ......................................................................................................
10A.3.2 Register Configuration .................................................................................
10A.3.3 Pin Functions ................................................................................................
Port 4 .............................................................................................................................
10A.4.1 Overview ......................................................................................................
10A.4.2 Register Configuration .................................................................................
10A.4.3 Pin Functions ................................................................................................
Port 7 .............................................................................................................................
10A.5.1 Overview ......................................................................................................
10A.5.2 Register Configuration .................................................................................
10A.5.3 Pin Functions ................................................................................................
Port 9 .............................................................................................................................
10A.6.1 Overview ......................................................................................................
10A.6.2 Register Configuration .................................................................................
10A.6.3 Pin Functions ................................................................................................
Port A ............................................................................................................................
10A.7.1 Overview ......................................................................................................
10A.7.2 Register Configuration .................................................................................
10A.7.3 Pin Functions ................................................................................................
10A.7.4 MOS Input Pull-Up Function .......................................................................
Port B ............................................................................................................................
10A.8.1 Overview ......................................................................................................
10A.8.2 Register Configuration .................................................................................
10A.8.3 Pin Functions ................................................................................................
10A.8.4 MOS Input Pull-Up Function .......................................................................
Port C ............................................................................................................................
10A.9.1 Overview ......................................................................................................
10A.9.2 Register Configuration .................................................................................
Rev. 5.00 Mar 28, 2005 page xlviii of lxii
371
377
377
378
379
392
392
392
394
398
398
399
399
400
400
401
403
406
406
407
407
408
408
409
412
413
414
414
415
418
419
420
420
421
10A.10
10A.11
10A.12
10A.13
10A.9.3 Pin Functions for Each Mode .......................................................................
10A.9.4 MOS Input Pull-Up Function .......................................................................
Port D ............................................................................................................................
10A.10.1 Overview ......................................................................................................
10A.10.2 Register Configuration .................................................................................
10A.10.3 Pin Functions ................................................................................................
10A.10.4 MOS Input Pull-Up Function .......................................................................
Port E.............................................................................................................................
10A.11.1 Overview ......................................................................................................
10A.11.2 Register Configuration .................................................................................
10A.11.3 Pin Functions ................................................................................................
10A.11.4 MOS Input Pull-Up Function .......................................................................
Port F.............................................................................................................................
10A.12.1 Overview ......................................................................................................
10A.12.2 Register Configuration .................................................................................
10A.12.3 Pin Functions ................................................................................................
Port G ............................................................................................................................
10A.13.1 Overview ......................................................................................................
10A.13.2 Register Configuration .................................................................................
10A.13.3 Pin Functions ................................................................................................
424
426
427
427
428
430
431
432
432
433
435
436
437
437
438
440
443
443
444
446
Section 10B I/O Ports (H8S/2695) ................................................................................. 449
10B.1
10B.2
10B.3
10B.4
10B.5
10B.6
Overview.......................................................................................................................
Port 1 .............................................................................................................................
10B.2.1 Overview ......................................................................................................
10B.2.2 Register Configuration .................................................................................
10B.2.3 Pin Functions ................................................................................................
Port 3 .............................................................................................................................
10B.3.1 Overview ......................................................................................................
10B.3.2 Register Configuration .................................................................................
10B.3.3 Pin Functions ................................................................................................
Port 4 .............................................................................................................................
10B.4.1 Overview ......................................................................................................
10B.4.2 Register Configuration .................................................................................
10B.4.3 Pin Functions ................................................................................................
Port 7 .............................................................................................................................
10B.5.1 Overview ......................................................................................................
10B.5.2 Register Configuration .................................................................................
10B.5.3 Pin Functions ................................................................................................
Port 9 .............................................................................................................................
449
454
454
455
457
469
469
469
472
475
475
476
476
477
477
478
479
482
Rev. 5.00 Mar 28, 2005 page xlix of lxii
10B.7
10B.8
10B.9
10B.10
10B.11
10B.12
10B.13
10B.6.1 Overview ......................................................................................................
10B.6.2 Register Configuration .................................................................................
10B.6.3 Pin Functions ................................................................................................
Port A ............................................................................................................................
10B.7.1 Overview ......................................................................................................
10B.7.2 Register Configuration .................................................................................
10B.7.3 Pin Functions ................................................................................................
10B.7.4 MOS Input Pull-Up Function .......................................................................
Port B ............................................................................................................................
10B.8.1 Overview ......................................................................................................
10B.8.2 Register Configuration .................................................................................
10B.8.3 Pin Functions ................................................................................................
10B.8.4 MOS Input Pull-Up Function .......................................................................
Port C ............................................................................................................................
10B.9.1 Overview ......................................................................................................
10B.9.2 Register Configuration .................................................................................
10B.9.3 Pin Functions for Each Mode .......................................................................
10B.9.4 MOS Input Pull-Up Function .......................................................................
Port D ............................................................................................................................
10B.10.1 Overview ......................................................................................................
10B.10.2 Register Configuration .................................................................................
10B.10.3 Pin Functions ................................................................................................
10B.10.4 MOS Input Pull-Up Function .......................................................................
Port E.............................................................................................................................
10B.11.1 Overview ......................................................................................................
10B.11.2 Register Configuration .................................................................................
10B.11.3 Pin Functions ................................................................................................
10B.11.4 MOS Input Pull-Up Function .......................................................................
Port F.............................................................................................................................
10B.12.1 Overview ......................................................................................................
10B.12.2 Register Configuration .................................................................................
10B.12.3 Pin Functions ................................................................................................
Port G ............................................................................................................................
10B.13.1 Overview ......................................................................................................
10B.13.2 Register Configuration .................................................................................
10B.13.3 Pin Functions ................................................................................................
482
483
483
484
484
485
488
489
490
490
491
494
495
496
496
497
500
502
503
503
504
506
507
508
508
509
511
512
513
513
514
516
518
518
519
521
Section 11 16-Bit Timer Pulse Unit (TPU).................................................................. 523
11.1 Overview........................................................................................................................... 523
11.1.1 Features................................................................................................................ 523
Rev. 5.00 Mar 28, 2005 page l of lxii
11.2
11.3
11.4
11.5
11.6
11.7
11.1.2 Block Diagram.....................................................................................................
11.1.3 Pin Configuration ................................................................................................
11.1.4 Register Configuration.........................................................................................
Register Descriptions........................................................................................................
11.2.1 Timer Control Register (TCR).............................................................................
11.2.2 Timer Mode Register (TMDR)............................................................................
11.2.3 Timer I/O Control Register (TIOR).....................................................................
11.2.4 Timer Interrupt Enable Register (TIER)..............................................................
11.2.5 Timer Status Register (TSR)................................................................................
11.2.6 Timer Counter (TCNT)........................................................................................
11.2.7 Timer General Register (TGR) ............................................................................
11.2.8 Timer Start Register (TSTR) ...............................................................................
11.2.9 Timer Synchro Register (TSYR) .........................................................................
11.2.10 Module Stop Control Register A (MSTPCRA) ...................................................
Interface to Bus Master.....................................................................................................
11.3.1 16-Bit Registers ...................................................................................................
11.3.2 8-Bit Registers .....................................................................................................
Operation ..........................................................................................................................
11.4.1 Overview..............................................................................................................
11.4.2 Basic Functions....................................................................................................
11.4.3 Synchronous Operation .......................................................................................
11.4.4 Buffer Operation..................................................................................................
11.4.5 Cascaded Operation .............................................................................................
11.4.6 PWM Modes........................................................................................................
11.4.7 Phase Counting Mode..........................................................................................
Interrupts...........................................................................................................................
11.5.1 Interrupt Sources and Priorities ...........................................................................
11.5.2 DTC/DMAC Activation (This function is not available in the H8S/2695) .........
11.5.3 A/D Converter Activation....................................................................................
Operation Timing..............................................................................................................
11.6.1 Input/Output Timing............................................................................................
11.6.2 Interrupt Signal Timing .......................................................................................
Usage Notes ......................................................................................................................
527
528
530
532
532
537
539
552
555
559
560
561
562
563
564
564
564
566
566
567
573
576
580
582
588
595
595
597
597
598
598
602
606
Section 12 Programmable Pulse Generator (PPG)
(This function is not available in the H8S/2695) .................................. 617
12.1 Overview...........................................................................................................................
12.1.1 Features................................................................................................................
12.1.2 Block Diagram.....................................................................................................
12.1.3 Pin Configuration ................................................................................................
617
617
618
619
Rev. 5.00 Mar 28, 2005 page li of lxii
12.1.4 Registers ..............................................................................................................
12.2 Register Descriptions........................................................................................................
12.2.1 Next Data Enable Registers H and L (NDERH, NDERL)...................................
12.2.2 Output Data Registers H and L (PODRH, PODRL)............................................
12.2.3 Next Data Registers H and L (NDRH, NDRL)....................................................
12.2.4 Notes on NDR Access .........................................................................................
12.2.5 PPG Output Control Register (PCR) ...................................................................
12.2.6 PPG Output Mode Register (PMR) .....................................................................
12.2.7 Port 1 Data Direction Register (P1DDR).............................................................
12.2.8 Module Stop Control Register A (MSTPCRA) ...................................................
12.3 Operation ..........................................................................................................................
12.3.1 Overview..............................................................................................................
12.3.2 Output Timing .....................................................................................................
12.3.3 Normal Pulse Output ...........................................................................................
12.3.4 Non-Overlapping Pulse Output ...........................................................................
12.3.5 Inverted Pulse Output ..........................................................................................
12.3.6 Pulse Output Triggered by Input Capture............................................................
12.4 Usage Notes ......................................................................................................................
620
621
621
622
623
623
625
627
630
630
631
631
632
633
635
638
639
639
Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695) .................................. 641
13.1 Overview...........................................................................................................................
13.1.1 Features................................................................................................................
13.1.2 Block Diagram.....................................................................................................
13.1.3 Pin Configuration ................................................................................................
13.1.4 Register Configuration.........................................................................................
13.2 Register Descriptions........................................................................................................
13.2.1 Timer Counters 0 to 3 (TCNT0 to TCNT3).........................................................
13.2.2 Time Constant Registers A0 to A3 (TCORA0 to TCORA3)...............................
13.2.3 Time Constant Registers B0 to B3 (TCORB0 to TCORB3) ...............................
13.2.4 Timer Control Registers 0 to 3 (TCR0 to TCR3) ................................................
13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3) .................................
13.2.6 Module Stop Control Register A (MSTPCRA) ...................................................
13.3 Operation ..........................................................................................................................
13.3.1 TCNT Incrementation Timing .............................................................................
13.3.2 Compare Match Timing.......................................................................................
13.3.3 Timing of External RESET on TCNT .................................................................
13.3.4 Timing of Overflow Flag (OVF) Setting .............................................................
13.3.5 Operation with Cascaded Connection..................................................................
13.4 Interrupts...........................................................................................................................
Rev. 5.00 Mar 28, 2005 page lii of lxii
641
641
642
643
644
645
645
645
646
646
649
652
653
653
654
656
656
657
658
13.4.1 Interrupt Sources and DTC Activation
(The H8S/2695 does not have a DTC function or an 8-bit timer)........................
13.4.2 A/D Converter Activation....................................................................................
13.5 Sample Application...........................................................................................................
13.6 Usage Notes ......................................................................................................................
13.6.1 Contention between TCNT Write and Clear........................................................
13.6.2 Contention between TCNT Write and Increment ................................................
13.6.3 Contention between TCOR Write and Compare Match ......................................
13.6.4 Contention between Compare Matches A and B .................................................
13.6.5 Switching of Internal Clocks and TCNT Operation ...........................................
13.6.6 Interrupts and Module Stop Mode .......................................................................
658
658
659
660
660
661
662
663
663
665
Section 14 14-Bit PWM D/A
(This function is not available in the H8S/2695) .................................. 667
14.1 Overview...........................................................................................................................
14.1.1 Features................................................................................................................
14.1.2 Block Diagram.....................................................................................................
14.1.3 Pin Configuration ................................................................................................
14.1.4 Register Configuration.........................................................................................
14.2 Register Descriptions........................................................................................................
14.2.1 PWM D/A Counter (DACNT).............................................................................
14.2.2 PWM D/A Data Registers A and B (DADRA and DADRB) ..............................
14.2.3 PWM D/A Control Register (DACR)..................................................................
14.2.4 Module Stop Control Register B (MSTPCRB) ...................................................
14.3 Bus Master Interface.........................................................................................................
14.4 Operation ..........................................................................................................................
667
667
668
669
669
670
670
671
672
674
675
679
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695) .............
15.1 Overview...........................................................................................................................
15.1.1 Features................................................................................................................
15.1.2 Block Diagram.....................................................................................................
15.1.3 Pin Configuration ................................................................................................
15.1.4 Register Configuration.........................................................................................
15.2 Register Descriptions........................................................................................................
15.2.1 Timer Counter (TCNT)........................................................................................
15.2.2 Timer Control/Status Register (TCSR)................................................................
15.2.3 Reset Control/Status Register (RSTCSR)............................................................
15.2.4 Pin Function Control Register (PFCR) ................................................................
15.2.5 Notes on Register Access ....................................................................................
15.3 Operation ..........................................................................................................................
683
683
683
684
686
686
687
687
688
693
694
695
697
Rev. 5.00 Mar 28, 2005 page liii of lxii
15.3.1 Watchdog Timer Operation .................................................................................
15.3.2 Interval Timer Operation .....................................................................................
15.3.3 Timing of Setting Overflow Flag (OVF) .............................................................
15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) .........................
15.4 Interrupts...........................................................................................................................
15.5 Usage Notes ......................................................................................................................
15.5.1 Contention between Timer Counter (TCNT) Write and Increment.....................
15.5.2 Changing Value of PSS and CKS2 to CKS0 .......................................................
15.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................
15.5.4 System Reset by
Signal......................................................................
15.5.5 Internal Reset in Watchdog Timer Mode.............................................................
15.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................
WDTOVF
697
699
699
700
701
701
701
702
702
702
702
703
Section 16 Serial Communication Interface (SCI, IrDA)
(The H8S/2695 is not equipped with an IrDA function) .................... 705
16.1 Overview...........................................................................................................................
16.1.1 Features................................................................................................................
16.1.2 Block Diagram.....................................................................................................
16.1.3 Pin Configuration ................................................................................................
16.1.4 Register Configuration.........................................................................................
16.2 Register Descriptions........................................................................................................
16.2.1 Receive Shift Register (RSR) ..............................................................................
16.2.2 Receive Data Register (RDR)..............................................................................
16.2.3 Transmit Shift Register (TSR).............................................................................
16.2.4 Transmit Data Register (TDR) ............................................................................
16.2.5 Serial Mode Register (SMR) ...............................................................................
16.2.6 Serial Control Register (SCR) .............................................................................
16.2.7 Serial Status Register (SSR) ................................................................................
16.2.8 Bit Rate Register (BRR) ......................................................................................
16.2.9 Smart Card Mode Register (SCMR)....................................................................
16.2.10 IrDA Control Register (IrCR)..............................................................................
16.2.11 Module Stop Control Registers B and C (MSTPCRB, MSTPCRC) ...................
16.3 Operation ..........................................................................................................................
16.3.1 Overview..............................................................................................................
16.3.2 Operation in Asynchronous Mode .......................................................................
16.3.3 Multiprocessor Communication Function ...........................................................
16.3.4 Operation in Clocked Synchronous Mode...........................................................
16.3.5 IrDA Operation....................................................................................................
16.4 SCI Interrupts....................................................................................................................
16.5 Usage Notes ......................................................................................................................
Rev. 5.00 Mar 28, 2005 page liv of lxii
705
705
707
708
709
711
711
711
712
712
713
716
720
724
732
734
735
737
737
739
750
758
767
770
772
Section 17 Smart Card Interface .....................................................................................
17.1 Overview...........................................................................................................................
17.1.1 Features................................................................................................................
17.1.2 Block Diagram.....................................................................................................
17.1.3 Pin Configuration ................................................................................................
17.1.4 Register Configuration.........................................................................................
17.2 Register Descriptions........................................................................................................
17.2.1 Smart Card Mode Register (SCMR)....................................................................
17.2.2 Serial Status Register (SSR) ................................................................................
17.2.3 Serial Mode Register (SMR) ...............................................................................
17.2.4 Serial Control Register (SCR) .............................................................................
17.3 Operation ..........................................................................................................................
17.3.1 Overview..............................................................................................................
17.3.2 Pin Connections...................................................................................................
17.3.3 Data Format .........................................................................................................
17.3.4 Register Settings ..................................................................................................
17.3.5 Clock....................................................................................................................
17.3.6 Data Transfer Operations.....................................................................................
17.3.7 Operation in GSM Mode .....................................................................................
17.3.8 Operation in Block Transfer Mode ......................................................................
17.4 Usage Notes ......................................................................................................................
783
783
783
784
785
786
787
787
789
791
793
794
794
795
796
798
800
802
810
811
812
Section 18 I2C Bus Interface [Option]
(This function is not available in the H8S/2695) .................................. 817
18.1 Overview...........................................................................................................................
18.1.1 Features................................................................................................................
18.1.2 Block Diagram.....................................................................................................
18.1.3 Input/Output Pins.................................................................................................
18.1.4 Register Configuration.........................................................................................
18.2 Register Descriptions........................................................................................................
18.2.1 I2C Bus Data Register (ICDR).............................................................................
18.2.2 Slave Address Register (SAR).............................................................................
18.2.3 Second Slave Address Register (SARX) .............................................................
18.2.4 I2C Bus Mode Register (ICMR) ..........................................................................
18.2.5 I2C Bus Control Register (ICCR) ........................................................................
18.2.6 I2C Bus Status Register (ICSR) ...........................................................................
18.2.7 Serial Control Register X (SCRX).......................................................................
18.2.8 DDC Switch Register (DDCSWR)......................................................................
18.2.9 Module Stop Control Register B (MSTPCRB) ...................................................
18.3 Operation ..........................................................................................................................
817
817
818
820
821
822
822
825
826
827
829
838
843
844
845
846
Rev. 5.00 Mar 28, 2005 page lv of lxii
18.3.1 I2C Bus Data Format............................................................................................
18.3.2 Initial Setting .......................................................................................................
18.3.3 Master Transmit Operation..................................................................................
18.3.4 Master Receive Operation ...................................................................................
18.3.5 Slave Receive Operation......................................................................................
18.3.6 Slave Transmit Operation ....................................................................................
18.3.7 IRIC Setting Timing and SCL Control ................................................................
18.3.8 Operation Using the DTC ....................................................................................
18.3.9 Noise Canceler.....................................................................................................
18.3.10 Sample Flowcharts...............................................................................................
18.3.11 Initialization of Internal State ..............................................................................
18.4 Usage Notes ......................................................................................................................
846
848
848
852
858
861
863
864
865
865
868
869
Section 19 A/D Converter................................................................................................. 881
19.1 Overview...........................................................................................................................
19.1.1 Features................................................................................................................
19.1.2 Block Diagram.....................................................................................................
19.1.3 Pin Configuration ................................................................................................
19.1.4 Register Configuration.........................................................................................
19.2 Register Descriptions........................................................................................................
19.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................
19.2.2 A/D Control/Status Register (ADCSR) ...............................................................
19.2.3 A/D Control Register (ADCR) ............................................................................
19.2.4 Module Stop Control Register A (MSTPCRA) ...................................................
19.3 Interface to Bus Master.....................................................................................................
19.4 Operation ..........................................................................................................................
19.4.1 Single Mode (SCAN = 0) ....................................................................................
19.4.2 Scan Mode (SCAN = 1).......................................................................................
19.4.3 Input Sampling and A/D Conversion Time .........................................................
19.4.4 External Trigger Input Timing.............................................................................
19.5 Interrupts...........................................................................................................................
19.6 Usage Notes ......................................................................................................................
881
881
882
883
884
885
885
886
889
890
891
892
892
894
896
897
898
899
Section 20 D/A Converter
(This function is not available in the H8S/2695) .................................. 905
20.1 Overview...........................................................................................................................
20.1.1 Features................................................................................................................
20.1.2 Block Diagram.....................................................................................................
20.1.3 Input and Output Pins ..........................................................................................
20.1.4 Register Configuration.........................................................................................
Rev. 5.00 Mar 28, 2005 page lvi of lxii
905
905
906
907
907
20.2 Register Descriptions........................................................................................................
20.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3).................................................
20.2.2 D/A Control Register 01 and 23 (DACR01 and DACR23) .................................
20.2.3 Module Stop Control Register A and C (MSTPCRA and MSTPCRC)...............
20.3 Operation ..........................................................................................................................
908
908
908
910
912
Section 21 RAM ..................................................................................................................
21.1 Overview...........................................................................................................................
21.1.1 Block Diagram.....................................................................................................
21.1.2 Register Configuration.........................................................................................
21.2 Register Descriptions........................................................................................................
21.2.1 System Control Register (SYSCR)......................................................................
21.3 Operation ..........................................................................................................................
21.4 Usage Notes ......................................................................................................................
913
913
913
914
914
914
915
915
Section 22 ROM ..................................................................................................................
22.1 Overview...........................................................................................................................
22.1.1 Block Diagram.....................................................................................................
22.1.2 Register Configuration.........................................................................................
22.2 Register Descriptions........................................................................................................
22.2.1 Mode Control Register (MDCR) .........................................................................
22.3 Operation ..........................................................................................................................
22.4 Flash Memory Overview ..................................................................................................
22.4.1 Features................................................................................................................
22.4.2 Overview..............................................................................................................
22.4.3 Flash Memory Operating Modes .........................................................................
22.4.4 On-Board Programming Modes...........................................................................
22.4.5 Flash Memory Emulation in RAM ......................................................................
22.4.6 Differences between Boot Mode and User Program Mode .................................
22.4.7 Block Configuration ............................................................................................
22.4.8 Pin Configuration ................................................................................................
22.4.9 Register Configuration.........................................................................................
22.5 Register Descriptions........................................................................................................
22.5.1 Flash Memory Control Register 1 (FLMCR1) ....................................................
22.5.2 Flash Memory Control Register 2 (FLMCR2) ....................................................
22.5.3 Erase Block Register 1 (EBR1) ...........................................................................
22.5.4 Erase Block Register 2 (EBR2) ...........................................................................
22.5.5 RAM Emulation Register (RAMER)...................................................................
22.5.6 Flash Memory Power Control Register (FLPWCR)............................................
22.5.7 Serial Control Register X (SCRX).......................................................................
917
917
917
917
918
918
918
921
921
922
923
924
926
927
928
928
929
930
930
933
934
935
936
938
938
Rev. 5.00 Mar 28, 2005 page lvii of lxii
22.6 On-Board Programming Modes........................................................................................
22.6.1 Boot Mode ...........................................................................................................
22.6.2 User Program Mode.............................................................................................
22.7 Programming/Erasing Flash Memory...............................................................................
22.7.1 Program Mode .....................................................................................................
22.7.2 Program-Verify Mode .........................................................................................
22.7.3 Erase Mode ..........................................................................................................
22.7.4 Erase-Verify Mode ..............................................................................................
22.8 Protection..........................................................................................................................
22.8.1 Hardware Protection ............................................................................................
22.8.2 Software Protection .............................................................................................
22.8.3 Error Protection ...................................................................................................
22.9 Flash Memory Emulation in RAM ...................................................................................
22.10 Interrupt Handling when Programming/Erasing Flash Memory.......................................
22.11 Flash Memory Programmer Mode....................................................................................
22.11.1 Socket Adapter and Memory Map.......................................................................
22.11.2 Programmer Mode Operation ..............................................................................
22.11.3 Memory Read Mode ............................................................................................
22.11.4 Auto-Program Mode............................................................................................
22.11.5 Auto-Erase Mode.................................................................................................
22.11.6 Status Read Mode ................................................................................................
22.11.7 Status Polling .......................................................................................................
22.11.8 Programmer Mode Transition Time ....................................................................
22.11.9 Notes on Memory Programming .........................................................................
22.12 Flash Memory and Power-Down States............................................................................
22.12.1 Note on Power-Down States................................................................................
22.13 Flash Memory Programming and Erasing Precautions.....................................................
22.14 Note on Switching from F-ZTAT Version to Mask ROM Version ..................................
939
940
944
946
947
948
952
952
954
954
955
956
958
960
960
961
962
963
967
969
971
972
972
973
974
974
975
980
Section 23A Clock Pulse Generator
(H8S/2633, H8S/2632, H8S/2631, H8S/2633F) ............................... 981
23A.1
23A.2
23A.3
Overview.......................................................................................................................
23A.1.1 Block Diagram..............................................................................................
23A.1.2 Register Configuration .................................................................................
Register Descriptions ....................................................................................................
23A.2.1 System Clock Control Register (SCKCR)....................................................
23A.2.2 Low-Power Control Register (LPWRCR)....................................................
Oscillator.......................................................................................................................
23A.3.1 Connecting a Crystal Resonator ...................................................................
23A.3.2 External Clock Input.....................................................................................
Rev. 5.00 Mar 28, 2005 page lviii of lxii
981
981
982
982
982
983
984
984
987
23A.4
23A.5
23A.6
23A.7
23A.8
23A.9
PLL Circuit....................................................................................................................
Medium-Speed Clock Divider.......................................................................................
Bus Master Clock Selection Circuit ..............................................................................
Subclock Oscillator .......................................................................................................
Subclock Waveform Shaping Circuit............................................................................
Note on Crystal Resonator ............................................................................................
989
989
990
990
991
991
Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695) .............................. 993
23B.1
23B.2
23B.3
23B.4
23B.5
23B.6
23B.7
23B.8
23B.9
Overview....................................................................................................................... 993
23B.1.1 Block Diagram.............................................................................................. 994
23B.1.2 Register Configuration ................................................................................. 994
Register Descriptions .................................................................................................... 995
23B.2.1 System Clock Control Register (SCKCR).................................................... 995
23B.2.2 Low-Power Control Register (LPWRCR).................................................... 996
Oscillator....................................................................................................................... 997
23B.3.1 Connecting a Crystal Resonator ................................................................... 997
23B.3.2 External Clock Input................................................................................... 1000
PLL Circuit.................................................................................................................. 1002
Medium-Speed Clock Divider..................................................................................... 1002
Bus Master Clock Selection Circuit ............................................................................ 1003
Subclock Oscillator (This function is not available in the H8S/2695) ........................ 1003
Subclock Waveform Shaping Circuit.......................................................................... 1004
Note on Crystal Resonator .......................................................................................... 1004
Section 24 Power-Down Modes....................................................................................
24.1 Overview.........................................................................................................................
24.1.1 Register Configuration.......................................................................................
24.2 Register Descriptions......................................................................................................
24.2.1 Standby Control Register (SBYCR) ..................................................................
24.2.2 System Clock Control Register (SCKCR) .........................................................
24.2.3 Low-Power Control Register (LPWRCR) .........................................................
24.2.4 Timer Control/Status Register (TCSR)..............................................................
24.2.5 Module Stop Control Register (MSTPCR)........................................................
24.3 Medium-Speed Mode .....................................................................................................
24.4 Sleep Mode .....................................................................................................................
24.4.1 Sleep Mode ........................................................................................................
24.4.2 Exiting Sleep Mode ...........................................................................................
24.5 Module Stop Mode .........................................................................................................
24.5.1 Module Stop Mode ............................................................................................
24.5.2 Usage Notes.......................................................................................................
1005
1005
1010
1011
1011
1013
1014
1017
1018
1019
1020
1020
1020
1021
1021
1023
Rev. 5.00 Mar 28, 2005 page lix of lxii
24.6 Software Standby Mode..................................................................................................
24.6.1 Software Standby Mode ....................................................................................
24.6.2 Exiting Software Standby Mode........................................................................
24.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode.
24.6.4 Software Standby Mode Application Example..................................................
24.6.5 Usage Notes.......................................................................................................
24.7 Hardware Standby Mode ................................................................................................
24.7.1 Hardware Standby Mode ...................................................................................
24.7.2 Hardware Standby Mode Timing.......................................................................
24.8 Watch Mode (This function is not available in the H8S/2695).......................................
24.8.1 Watch Mode ......................................................................................................
24.8.2 Exiting Watch Mode..........................................................................................
24.8.3 Notes..................................................................................................................
24.9 Subsleep Mode (This function is not available in the H8S/2695)...................................
24.9.1 Subsleep Mode ..................................................................................................
24.9.2 Exiting Subsleep Mode......................................................................................
24.10 Subactive Mode (This function is not available in the H8S/2695) .................................
24.10.1 Subactive Mode .................................................................................................
24.10.2 Exiting Subactive Mode ....................................................................................
24.10.3 Usage Notes.......................................................................................................
24.11 Direct Transitions (This function is not available in the H8S/2695) ..............................
24.11.1 Overview of Direct Transitions .........................................................................
24.12 φ Clock Output Disabling Function ................................................................................
1023
1023
1024
1024
1025
1026
1027
1027
1027
1028
1028
1029
1030
1031
1031
1031
1032
1032
1032
1033
1033
1033
1034
Section 25 Electrical Characteristics
(H8S/2633, H8S/2632, H8S/2631, H8S/2633F) ................................. 1035
25.1 Absolute Maximum Ratings ...........................................................................................
25.2 DC Characteristics ..........................................................................................................
25.3 AC Characteristics ..........................................................................................................
25.3.1 Clock Timing .....................................................................................................
25.3.2 Control Signal Timing .......................................................................................
25.3.3 Bus Timing ........................................................................................................
25.3.4 DMAC Timing...................................................................................................
25.3.5 Timing of On-Chip Supporting Modules...........................................................
25.4 A/D Conversion Characteristics .....................................................................................
25.5 D/A Conversion Characteristics .....................................................................................
25.6 Flash Memory Characteristics ........................................................................................
25.7 Usage Note .....................................................................................................................
Rev. 5.00 Mar 28, 2005 page lx of lxii
1035
1036
1044
1045
1047
1049
1059
1063
1071
1072
1073
1074
Section 26 Electrical Characteristics (H8S/2633R) ................................................
26.1 Absolute Maximum Ratings ...........................................................................................
26.2 DC Characteristics ..........................................................................................................
26.3 AC Characteristics ..........................................................................................................
26.3.1 Clock Timing .....................................................................................................
26.3.2 Control Signal Timing .......................................................................................
26.3.3 Bus Timing ........................................................................................................
26.3.4 DMAC Timing...................................................................................................
26.3.5 Timing of On-Chip Supporting Modules...........................................................
26.4 A/D Conversion Characteristics .....................................................................................
26.5 D/A Conversion Characteristics .....................................................................................
26.6 Flash Memory Characteristics ........................................................................................
26.7 Usage Note .....................................................................................................................
1075
1075
1076
1081
1082
1084
1086
1096
1100
1107
1108
1109
1110
Section 27 Electrical Characteristics (H8S/2695)....................................................
27.1 Absolute Maximum Ratings ...........................................................................................
27.2 DC Characteristics ..........................................................................................................
27.3 AC Characteristics ..........................................................................................................
27.3.1 Clock Timing .....................................................................................................
27.3.2 Control Signal Timing .......................................................................................
27.3.3 Bus Timing ........................................................................................................
27.3.4 Timing of On-Chip Supporting Modules...........................................................
27.4 A/D Conversion Characteristics .....................................................................................
27.5 Usage Note .....................................................................................................................
1111
1111
1112
1115
1116
1118
1120
1128
1131
1131
Appendix A Instruction Set ............................................................................................ 1133
A.1
A.2
A.3
A.4
A.5
A.6
Instruction List................................................................................................................
Instruction Codes ............................................................................................................
Operation Code Map.......................................................................................................
Number of States Required for Instruction Execution....................................................
Bus States during Instruction Execution.........................................................................
Condition Code Modification .........................................................................................
1133
1157
1172
1176
1190
1204
Appendix B Internal I/O Register ................................................................................. 1210
B.1A Addresses (H8S/2633 Group, H8S/2633F, H8S/2633R) ................................................ 1210
B.1B Addresses (H8S/2695) .................................................................................................... 1220
B.2 Functions ........................................................................................................................ 1227
Appendix C I/O Port Block Diagrams ........................................................................ 1325
C.1
Port 1 Block Diagram ..................................................................................................... 1325
Rev. 5.00 Mar 28, 2005 page lxi of lxii
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10
C.11
C.12
C.13
C.14
C.15
C.16
C.17
C.18
C.19
C.20
C.21
C.22
C.23
C.24
Port 3 Block Diagram .....................................................................................................
Port 4 Block Diagram .....................................................................................................
Port 7 Block Diagram .....................................................................................................
Port 9 Block Diagram .....................................................................................................
Port A Block Diagram ....................................................................................................
Port B Block Diagram.....................................................................................................
Port C Block Diagram.....................................................................................................
Port D Block Diagram ....................................................................................................
Port E Block Diagram.....................................................................................................
Port F Block Diagram .....................................................................................................
Port G Block Diagram ....................................................................................................
Port 1 Block Diagram .....................................................................................................
Port 3 Block Diagram .....................................................................................................
Port 4 Block Diagram .....................................................................................................
Port 7 Block Diagram .....................................................................................................
Port 9 Block Diagram .....................................................................................................
Port A Block Diagram ....................................................................................................
Port B Block Diagram.....................................................................................................
Port C Block Diagram.....................................................................................................
Port D Block Diagram ....................................................................................................
Port E Block Diagram.....................................................................................................
Port F Block Diagram .....................................................................................................
Port G Block Diagram ....................................................................................................
1331
1339
1340
1347
1348
1352
1353
1355
1356
1357
1365
1369
1375
1383
1384
1389
1390
1394
1395
1396
1397
1398
1406
Appendix D Pin States ..................................................................................................... 1410
D.1
Port States in Each Mode................................................................................................ 1410
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode ............................................................................................. 1418
Appendix F Product Code Lineup ................................................................................ 1419
Appendix G Package Dimensions ................................................................................. 1420
Rev. 5.00 Mar 28, 2005 page lxii of lxii
Section 1 Overview
Section 1 Overview
1.1
Overview
The H8S/2633 Group is a series of microcomputers (MCUs: microcomputer units), built around
the H8S/2600 CPU, employing Renesas’ proprietary architecture, and equipped with peripheral
functions on-chip.
The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip peripheral functions required for system configuration include DMA controller
(DMAC)*2, data transfer controller (DTC)*2 bus masters, ROM and RAM memory, a 16-bit
timer-pulse unit (TPU), programmable pulse generator (PPG)*2, 8-bit timer*2, 14-bit PWM timer
(PWM)*2, watchdog timer (WDT), serial communication interface (SCI, IrDA*2), A/D converter,
D/A converter*2, and I/O ports. It is also possible to incorporate an on-chip PC bus interface
(IIC)*2 as an option.
On-chip ROM is available as 256-kbyte flash memory (F-ZTAT™ version)*1 or as 256-, 128-, or
64-kbyte mask ROM. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and
word data to be accessed in one state. Instruction fetching has been speeded up, and processing
speed increased.
Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or
external expansion mode.
The features of the H8S/2633 Group are shown in table 1.1.
Notes: 1. F-ZTAT™ is a trademark of Renesas Technology Corp.
2. This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 1 of 1422
REJ09B0234-0500
Section 1 Overview
Table 1.1
Overview
Item
Specification
CPU
•
General-register machine
 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
•
High-speed operation suitable for realtime control
 Maximum clock rate: 25 MHz (H8S/2633 Group, H8S/2633F),
28 MHz (H8S/2633R, H8S/2695)
 High-speed arithmetic operations
8/16/32-bit register-register add/subtract
16 × 16-bit register-register multiply
16 × 16 + 42-bit multiply and accumulate
32 ÷ 16-bit register-register divide
•
: 40 ns, 35 ns
: 160 ns, 140 ns
: 160 ns, 140 ns
: 800 ns, 700 ns
Instruction set suitable for high-speed operation
 Sixty-nine basic instructions
 8/16/32-bit move/arithmetic and logic instructions
 Unsigned/signed multiply and divide instructions
 Multiply-and accumulate instruction
 Powerful bit-manipulation instructions
•
Two CPU operating modes
 Normal mode: 64-kbyte address space
(cannot be used in the H8S/2633 Group)
 Advanced mode: 16-Mbyte address space
Bus controller
•
Address space divided into 8 areas, with bus specifications settable
independently for each area
•
Choice of 8-bit or 16-bit access space for each area
•
2-state or 3-state access space can be designated for each area
•
Number of program wait states can be set for each area
•
Burst ROM directly connectable
Possible to connect*1 a maximum of 8 MB of DRAM (alternatively, it is
•
also possible to use an interval timer)
• External bus release function
PC break
controller*1
•
Supports debugging functions by means of PC break interrupts
•
Two break channels
Rev. 5.00 Mar 28, 2005 page 2 of 1422
REJ09B0234-0500
Section 1 Overview
Item
Specification
DMA controller
1
(DMAC)*
•
Short address mode and full address mode selectable
•
Short address mode: 4 channels
Full address mode: 2 channels
•
Transfer possible in repeat mode/block transfer mode
•
Activation by internal interrupt possible
•
Can be activated by internal interrupt or software
•
Multiple transfers or multiple types of transfer possible for one activation
source
•
Transfer possible in repeat mode, block transfer mode, etc.
•
Request can be sent to CPU for interrupt that activated DTC
•
6-channel 16-bit timer on-chip
•
Pulse I/O processing capability for up to 16 pins'
•
Automatic 2-phase encoder count capability
•
Maximum 16-bit pulse output possible with TPU as time base
•
Output trigger selectable in 4-bit groups
•
Non-overlap margin can be set
•
Direct output or inverse output setting possible
•
8-bit up counter (external event count possible)
Transfer possible in single address mode
Data transfer
controller (DTC)*1
16-bit timer-pulse
unit (TPU)
Programmable
pulse generator
(PPG)*1
8-bit timer*1
4 channels
•
Time constant register × 2
•
2 channel connection possible
Watchdog timer
2 channels*2
•
Watchdog timer or interval timer selectable
•
Operation using sub-clock supported (WDT1 only)
14-bit PWM timer
(PWM)*1
•
Maximum of 4 outputs
•
Resolution: 1/16384
•
Maximum carrier frequency: 390.6 kHz (operating at 25 MHz),
437.6 kHz (operating at 28 MHz)
•
Asynchronous mode or synchronous mode selectable
•
Multiprocessor communication function
•
Smart card interface function
Serial
communication
interface (SCI)
5 channels
(SCI0 to SCI4)
Rev. 5.00 Mar 28, 2005 page 3 of 1422
REJ09B0234-0500
Section 1 Overview
Item
Specification
IrDA-equipped SCI*1 •
1 channel (SCI0)
•
Supports IrDA standard version 1.0
TxD and RxD encoding/decoding in IrDA format
•
Start/stop synchronization mode or clock synchronization mode selectable
•
Multiprocessor communications function
•
Smart card interface function
•
Resolution: 10 bits
•
Input: 16 channels
•
High-speed conversion: 10.72 µs minimum conversion time
(at 25-MHz operation)
•
Single or scan mode selectable
•
Sample and hold circuit
•
A/D conversion can be activated by external trigger or timer trigger
•
Resolution: 8 bits
•
Output: 4 channels
I/O ports
•
73 I/O pins, 16 input-only pins
Memory
•
PROM or mask ROM
•
High-speed static RAM
A/D converter
D/A converter*1
Interrupt controller
Product Name
ROM
RAM
H8S/2633
256 kbytes
16 kbytes
H8S/2632
192 kbytes
12 kbytes
H8S/2631
128 kbytes
8 kbytes
H8S/2633R
256 kbytes
16 kbytes
H8S/2695
192 kbytes
8 kbytes
•
Nine external interrupt pins (NMI, IRQ0 to IRQ7)
•
72 internal interrupt sources (including options), 49 interrupt sources in
the H8S/2695
•
Eight priority levels settable
Rev. 5.00 Mar 28, 2005 page 4 of 1422
REJ09B0234-0500
Section 1 Overview
Item
Specification
Power-down state
•
Medium-speed mode
•
Sleep mode
•
Module stop mode
•
Software standby mode
•
Hardware standby mode
1
Subclock operation* (subactive mode, subsleep mode, watch mode)
•
Operating modes
Clock pulse
generator
Four MCU operating modes
External Data Bus
CPU
Operating
Mode Mode
Description
On-Chip
ROM
Initial
Value
Maximu
m Value
4
On-chip ROM disabled
expansion mode
Disabled
16 bits
16 bits
5
On-chip ROM disabled
expansion mode
Disabled
8 bits
16 bits
6
On-chip ROM enabled
expansion mode
Enabled
8 bits
16 bits
7
Single-chip mode
Enabled
—
—
Advanced
H8S/2633, H8S/2632, H8S/2631
•
On-chip PLL circuit (×1, ×2, ×4)
•
Input clock frequency: 2 to 25 MHz
H8S/2633R, H8S/2695
Packages
2
I C bus interface
1
(IIC)* 2 channels
(optional)
•
On-chip PLL circuit (×1, ×2, ×4): 2 to 25 MHz
(×2, ×4):
25 to 28 MHz
•
Input clock frequency: 2 to 25 MHz
•
120-pin plastic TQFP (TFP-120)
•
128-pin plastic QFP (FP-128B)
•
Conforms to I2C bus interface type advocated by Philips
•
Single master mode/slave mode
•
Possible to determine arbitration lost conditions
•
Supports two slave addresses
Rev. 5.00 Mar 28, 2005 page 5 of 1422
REJ09B0234-0500
Section 1 Overview
Item
Specification
Product lineup
H8S/2633 Group, H8S/2633F, H8S/2633R, H8S/2695 Operating Frequencies
and Voltages
28-MHz Operation
Version
25-MHz Operation
Version
16-MHz Operation
Version
Input clock
frequency range
2 to 25 MHz
2 to 25 MHz
2 to 16 MHz
Operating
frequency range
2 to 25 MHz
2 to 25 MHz
(For 25 to 28 MHz
operation, make sure to
use a PLL with a
multiplying factor set to
×2 or ×4.)
2 to 16 MHz
Operating voltage
range
PVCC = 4.5 to 5.5 V
(This is a single power
supply and has no Vcc
pin. Refer to sections 26
and 27, for details.)
PVCC = 4.5 to 5.5 V
PVCC = 3.0 to 5.5 V
VCC = 3.0 to 3.6 V
VCC = 3.0 to 3.6 V
AVCC = 4.5 to 5.5 V
[When using A/D or
D/A]*2
AVCC = 3.6 to 5.5 V
Vref = 3.6 V to AVCC
Vref = 4.5 to AVCC
AVCC = 4.5 to 5.5 V
Vref = 4.5 to AVCC
Flash version
Model (ROM/RAM)
Mask version
Model (ROM/RAM)
[When not using A/D or
D/A]*2
AVCC = 3.3 to 5.5 V
Vref = 3.3 V to AVCC
HD64F2633RF28
(256 kbytes/16 kbytes)
HD64F2633F25
(256 kbytes/16 kbytes)
HD64F2633F16
(256 kbytes/16 kbytes)
HD64F2633RTE28
(256 kbytes/16 kbytes)
HD64F2633TE25
(256 kbytes/16 kbytes)
HD64F2633TE16
(256 kbytes/16 kbytes)
HD6432695F28*1
(192 kbytes/8 kbytes)
HD6432633F25
(256 kbytes/16 kbytes)
HD6432633F16
(256 kbytes/16 kbytes)
HD6432633TE25
(256 kbytes/16 kbytes)
HD6432633TE16
(256 kbytes/16 kbytes)
HD6432632F25
(192 kbytes/12 kbytes)
HD6432632F16
(192 kbytes/12 kbytes)
HD6432632TE25
(192 kbytes/12 kbytes)
HD6432632TE16
(192 kbytes/12 kbytes)
HD6432631F25
(128 kbytes/8 kbytes)
HD6432631F16
(128 kbytes/8 kbytes)
HD6432631TE25
(128 kbytes/8 kbytes)
HD6432631TE16
(128 kbytes/8 kbytes)
Notes: 1. The module configuration of the HD6432695 differs from that of the HD6432633,
HD64F2633, and HD64F2633R. (For information on the module configuration refer to
comparison of H8S/2633, H8S/2632, H8S/2631, H8S/2633F-ZTAT, H8S/2633RF-ZTAT,
and H8S/2695 Product Specifications.
2. In the case of the 16-MHz operation version, the operating power supply ranges differ
depending on whether A/D or D/A conversion is used.
Rev. 5.00 Mar 28, 2005 page 6 of 1422
REJ09B0234-0500
Section 1 Overview
Item
Specification
Product lineup
Models and Corresponding Packages
Model Name
Package
HD64F2633F25
FP-128B
HD64F2633F16
HD6432633F25
HD6432633F16
HD6432632F25
HD6432632F16
HD6432631F25
HD6432631F16
HD64F2633RF28
HD6432695F28
HD64F2633TE25
TFP-120
HD64F2633TE16
HD6432633TE25
HD6432633TE16
HD6432632TE25
HD6432632TE16
HD6432631TE25
HD6432631TE16
HD64F2633RTE28
Notes: 1. This function is not available in the H8S/2695.
2. The watchdog timer in the H8S/2695 has one channel only.
1.2
Internal Block Diagram
Figure 1.1 (a) shows an internal block diagram of the H8S/2633, H8S/2633F, H8S/2632, and
H8S/2631. Figure 1.1 (b) shows the internal block diagram of the H8S/2633R. Figure 1.1 (c)
shows the internal block diagram of the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 7 of 1422
REJ09B0234-0500
Port A
Port B
PC7/A7/PWM1
PC6/A6/PWM0
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
8bit timer × 4 channels
SCI × 5 channels
(IrDA × 1channel)
I2C bus interface
(option)
TPU
Port C
WDT × 2 channels
RAM
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3 / A11/TIOCD3
PB2/A10/TIOCC3
PB1/A9/TIOCB3
PB0/A8/TIOCA3
14-bit PWM timer
Port 3
Port F
DMAC
ROM
(Mask ROM,
flash memory*1)
Peripheral address bus
Bus controller
PC break controller
(2 channels)
Peripheral data bus
PE7 / D7
PE6 / D6
PE5 / D5
PE4 / D4
PE3 / D3
PE2 / D2
PE1 / D1
PE0 / D0
Internal data bus
Internal address bus
PD7 / D15
PD6 / D14
PD5 / D13
PD4 / D12
PD3 / D11
PD2 / D10
PD1 / D9
PD0 / D8
DTC
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
D/A converter
A/D converter
Port 9
PPG
Port 4
Vref
AVCC
AVSS
P17 / PO15/ TIOCB2 /PWM3/ TCLKD
P16 / PO14/ TIOCA2/PWM2/IRQ1
P15 / PO13/ TIOCB1 / TCLKC
P14 / PO12/ TIOCA1/IRQ0
P13 / PO11/ TIOCD0 /TCLKB/A23
P12 / PO10/ TIOCC0 /TCLKA/A22
P11 / PO9/ TIOCB0 /DACK1/A21
P10 / PO8/ TIOCA0 /DACK0/A20
Port 1
P37/TxD4
P36/RxD4
P35/SCK1/SCK4/SCL0/IRQ5
P34/RxD1/SDA0
P33/TxD1/SCL1
P32/SCK0/SDA1/IRQ4
P31/RxD0/IrRxD
P30/TxD0/IrTxD
P97/AN15/DA3
P96/AN14/DA2
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
P47 / AN7/DA1
P46 / AN6/DA0
P45 / AN5
P44 / AN4
P43 / AN3
P42 / AN2
P41 / AN1
P40 / AN0
P77/TxD3
P76/RxD3
P75/TMO3/SCK3
P74/TMO2/MRES
P73/TMO1/TEND1/CS7
P72/TMO0/TEND0/CS6
P71/TMR23/TMC23/DREQ1/CS5
P70/TMR01/TMC01/DREQ0/CS4
Port E
H8S/2600 CPU
Port G
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/OE/IRQ7
PG0/CAS/IRQ6
Port D
Interrupt controller
Port 7
PF7/φ
PF6/AS/LCAS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
PF2/LCAS /WAIT/BREQO
PF1/BACK/BUZZ
PF0/BREQ/IRQ2
PLL
MD2
MD1
MD0
OSC2
OSC1
EXTAL
XTAL
PLLVCC
PLLCAP
PLLVSS
STBY
RES
WDTOVF
NMI
FWE*2
Clock pulse
generator
PVCC1
PVCC2
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
Section 1 Overview
Notes: 1. Applies to the H8S/2633 only.
2. The FWE pin is used only in the flash memory version.
Figure 1.1 (a) H8S/2633, H8S/2633F, H8S/2632, H8S/2631 Internal Block Diagram
Rev. 5.00 Mar 28, 2005 page 8 of 1422
REJ09B0234-0500
Port A
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3 / A11/TIOCD3
PB2/A10/TIOCC3
PB1/A9/TIOCB3
PB0/A8/TIOCA3
PC7/A7/PWM1
PC6/A6/PWM0
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
14-bit PWM timer
Port 3
8bit timer × 4 channels
SCI × 5 channels
(IrDA × 1channel)
I2C bus interface
(option)
TPU
Port B
WDT × 2 channels
RAM
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
Port C
Bus controller
ROM
(flash memory)
Peripheral address bus
Port F
DMAC
Peripheral data bus
PE7 / D7
PE6 / D6
PE5 / D5
PE4 / D4
PE3 / D3
PE2 / D2
PE1 / D1
PE0 / D0
Internal data bus
Internal address bus
PD7 / D15
PD6 / D14
PD5 / D13
PD4 / D12
PD3 / D11
PD2 / D10
PD1 / D9
PD0 / D8
DTC
PC break controller
(2 channels)
D/A converter
A/D converter
Port 9
PPG
P37/TxD4
P36/RxD4
P35/SCK1/SCK4/SCL0/IRQ5
P34/RxD1/SDA0
P33/TxD1/SCL1
P32/SCK0/SDA1/IRQ4
P31/RxD0/IrRxD
P30/TxD0/IrTxD
P97/AN15/DA3
P96/AN14/DA2
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
P47 / AN7/ DA1
P46 / AN6/ DA0
P45 / AN5
P44 / AN4
P43 / AN3
P42 / AN2
P41 / AN1
P40 / AN0
Port 4
Vref
AVCC
AVSS
Port 1
P17 / PO15/ TIOCB2 /PWM3/ TCLKD
P16 / PO14/ TIOCA2/PWM2/IRQ1
P15 / PO13/ TIOCB1 / TCLKC
P14 / PO12/ TIOCA1/IRQ0
P13 / PO11/ TIOCD0 / TCLKB/A23
P12 / PO10/ TIOCC0 / TCLKA/A22
P11 / PO9/ TIOCB0 / DACK1/A21
P10 / PO8/ TIOCA0 / DACK0/A20
P77/TxD3
P76/RxD3
P75/TMO3/SCK3
P74/TMO2/MRES
P73/TMO1/TEND1/CS7
P72/TMO0/TEND0/CS6
P71/TMR23/TMC23/DREQ1/CS5
P70/TMR01/TMC01/DREQ0/CS4
Port E
H8S/2600 CPU
Port G
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/OE/IRQ7
PG0/CAS/IRQ6
Port D
Interrupt controller
Port 7
PF7/φ
PF6/AS/LCAS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
PF2/LCAS /WAIT/BREQO
PF1/BACK/BUZZ
PF0/BREQ/IRQ2
PLL
MD2
MD1
MD0
OSC2
OSC1
EXTAL
XTAL
PLLVCC
PLLCAP
PLLVSS
STBY
RES
WDTOVF
NMI
FWE
VCL
Clock pulse
generator
PVCC1
PVCC2
VSS
VSS
VSS
VSS
VSS
VSS
Section 1 Overview
Figure 1.1 (b) H8S/2633R Internal Block Diagram
Rev. 5.00 Mar 28, 2005 page 9 of 1422
REJ09B0234-0500
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
Port A
Port B
PB7 / A 1 5 /TIOCB5
PB6 / A 1 4 /TIOCA5
PB5 / A 1 3 /TIOCB4
PB4 / A 1 2 /TIOCA4
PB3 / A 1 1 /TIOCD3
PB2 / A 1 0 /TIOCC3
PB1 / A 9 /TIOCB3
PB0 / A 8 /TIOCA3
Port C
PC7 / A 7
PC6 / A 6
PC5 / A 5
PC4 / A 4
PC3 / A 3
PC2 / A 2
PC1 / A 1
PC0 / A 0
Peripheral address bus
Peripheral data bus
Port F
ROM
(Mask ROM)
PA3 /A19/SCK2
PA2 /A18/RxD2
PA1 /A17/TxD2
PA0 / A16
WDT × 1 channel
Port G
RAM
Port 3
SCI × 5 channels
TPU
Port 9
A/D converter
Port 4
Vref
AVCC
AVSS
P17/TIOCB2/TCLKD
P16/TIOCA2/IRQ1
P15/TIOCB1/TCLKC
P14/TIOCA1/IRQ0
P13/TIOCD0/TCLKB/A23
P12/TIOCC0/TCLKA/A22
P11/TIOCB0/A21
P10/TIOCA0/A20
Port 1
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
P77 / T x D 3
P76 / R x D 3
P75 /SCK3
P74 /MRES
P73 / CS7
P72 / CS6
P71 / CS5
P70 / CS4
Interrupt controller
Port 7
PG4 / CS0
PG3 / CS1
PG2 / CS2
PG1 / CS3/IRQ7
PG0 /IRQ6
H8S/2600 CPU
Internal address bus
PLL
PLLCAP
PLLVSS
STBY
RES
WDTOVF
NMI
PF7 / φ
PF6 / AS
PF5 / RD
PF4 / HWR
PF3 / LWR/ADTRG/IRQ3
PF2 / WAIT/ BREQO
PF1 / BACK
PF0 / BREQ/IRQ2
Clock pulse
generator
VCL
MD2
MD1
MD0
EXTAL
XTAL
Port E
Internal data bus
Port D
Bus controller
PVCC
PVCC
VSS
VSS
VSS
VSS
VSS
VSS
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Section 1 Overview
Figure 1.1 (c) H8S/2695 Internal Block Diagram
Rev. 5.00 Mar 28, 2005 page 10 of 1422
REJ09B0234-0500
P37 / TxD4
P36 / RxD4
P35 / SCK1/SCK4/IRQ5
P34 / RxD1
P33 / TxD1
P32 / SCK0/IRQ4
P31 / RxD0
P30 / TxD0
P97 / AN15
P96 / AN14
P95 / AN13
P94 / AN12
P93 / AN11
P92 / AN10
P91 / AN9
P90 / AN8
Section 1 Overview
1.3
Pin Description
1.3.1
Pin Arrangement
STBY
NMI
RES
PLLVSS
PLLCAP
PLLVCC
WDTOVF
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/OE/IRQ7
PG0/CAS/IRQ6
P37/TxD4
TOP VIEW
(TFP-120)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
P36/RxD4
P35/SCK1/SCK4/SCL0/IRQ5
P34/RxD1/SDA0
P33/TxD1/SCL1
VSS
P32/SCK0/SDA1/IRQ4
PVCC2
P31/RxD0/IrRxD
P30/TxD0/IrTxD
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PVCC1
PD0/D8
VSS
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
P17/PO15/TIOCB2/PWM3/TCKLD
P16/PO14/TIOCA2/PWM2/IRQ1
P15/PO13/TIOCB1/TCLKC
PC0/A0
PC1/A1
PC2/A2
PC3/A3
VSS
PC4/A4
VCC
PC5/A5
PC6/A6/PWM0
PC7/A7/PWM1
VSS
PB0/A8/TIOCA3
PVCC1
PB1/A9/TIOCB3
PB2/A10/TIOCC3
PB3/A11/TIOCD3
PB4/A12/TIOCA4
PB5/A13/TIOCB4
PB6/A14/TIOCA5
PB7/A15/TIOCB5
PA0/A16
PA1/A17/TxD2
PA2/A18/RxD2
PA3/A19/SCK2
VSS
P10/PO8/TIOCA0/DACK0/A20
P11/PO9/TIOCB0/DACK1/A21
P12/PO10/TIOCC0/TCLKA/A22
P13/PO11/TIOCD0/TCLKB/A23
P14/PO12/TIOCA1/IRQ0
AVCC
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6/DA0
P47/AN7/DA1
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12
P95/AN13
P96/AN14/DA2
P97/AN15/DA3
AVSS
P70/TMRI01/TMCI01/DREQ0/CS4
P71/TMRI23/TMCI23/DREQ1/CS5
P72/TMO0/TEND0/CS6
P73/TMO1/TEND1/CS7
P74/TMO2/MRES
P75/TMO3/SCK3
P76/RxD3
P77/TxD3
MD0
MD1
MD2
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PF0/BREQ/IRQ2
PF1/BACK/BUZZ
PF2/LCAS/WAIT/BREQO
PF3/LWR/ADTRG/IRQ3
PF4/HWR
PF5/RD
PF6/AS/LCAS
VSS
PF7/φ
PVCC1
OSC2
OSC1
VSS
EXTAL
VCC
XTAL
FWE*
Figures 1.2 (a) and 1.3 (a) show the pin arrangement of the H8S/2633, H8S/2633F, H8S/2632, and
H8S/2631. Figures 1.2 (b) and 1.3 (b) show the pin arrangement of the H8S/2633R. Figure 1.3 (c)
shows the pin arrangement of the H8S/2695.
Note: * The FWE pin is used only in the flash memory version.
In the mask ROM version the FWE pin is an NC pin, and should be left open or connected to VSS.
Figure 1.2 (a) H8S/2633, H8S/2633F, H8S/2632, H8S/2631 Pin Arrangement
(TFP-120: Top View)
Rev. 5.00 Mar 28, 2005 page 11 of 1422
REJ09B0234-0500
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
STBY
NMI
RES
PLLVSS
PLLCAP
NC
WDTOVF
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/OE/IRQ7
PG0/CAS/IRQ6
P37/TxD4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TOP VIEW
(TFP-120)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P36/RxD4
P35/SCK1/SCK4/SCL0/IRQ5
P34/RxD1/SDA0
P33/TxD1/SCL1
VSS
P32/SCK0/SDA1/IRQ4
PVCC2
P31/RxD0/IrRxD
P30/TxD0/IrTxD
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PVCC1
PD0/D8
VSS
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
P17/PO15/TIOCB2/PWM3/TCKLD
P16/PO14/TIOCA2/PWM2/IRQ1
P15/PO13/TIOCB1/TCLKC
PC0/A0
PC1/A1
PC2/A2
PC3/A3
VSS
PC4/A4
VCL
PC5/A5
PC6/A6/PWM0
PC7/A7/PWM1
VSS
PB0/A8/TIOCA3
PVCC1
PB1/A9/TIOCB3
PB2/A10/TIOCC3
PB3/A11/TIOCD3
PB4/A12/TIOCA4
PB5/A13/TIOCB4
PB6/A14/TIOCA5
PB7/A15/TIOCB5
PA0/A16
PA1/A17/TxD2
PA2/A18/RxD2
PA3/A19/SCK2
VSS
P10/PO8/TIOCA0/DACK0/A20
P11/PO9/TIOCB0/DACK1/A21
P12/PO10/TIOCC0/TCLKA/A22
P13/PO11/TIOCD0/TCLKB/A23
P14/PO12/TIOCA1/IRQ0
AVCC
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6/DA0
P47/AN7/DA1
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12
P95/AN13
P96/AN14/DA2
P97/AN15/DA3
AVSS
P70/TMRI01/TMCI01/DREQ0/CS4
P71/TMRI23/TMCI23/DREQ1/CS5
P72/TMO0/TEND0/CS6
P73/TMO1/TEND1/CS7
P74/TMO2/MRES
P75/TMO3/SCK3
P76/RxD3
P77/TxD3
MD0
MD1
MD2
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PF0/BREQ/IRQ2
PF1/BACK/BUZZ
PF2/LCAS/WAIT/BREQO
PF3/LWR/ADTRG/IRQ3
PF4/HWR
PF5/RD
PF6/AS/LCAS
VSS
PF7/φ
PVCC1
OSC2
OSC1
VSS
EXTAL
NC
XTAL
FWE*
Section 1 Overview
0.1µF
Note: * The FWE pin is used only in the flash memory version.
In the mask ROM version the FWE pin is an NC pin, and should be left open or connected to VSS.
Figure 1.2 (b) H8S/2633R Pin Arrangement (TFP-120: Top View)
Rev. 5.00 Mar 28, 2005 page 12 of 1422
REJ09B0234-0500
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
TOP VIEW
(FP-128B)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
P34/RxD1/SDA0
P33/TxD1/SCL1
VSS
P32/SCK0/SDA1/IRQ4
PVCC2
P31/RxD0/IrRxD
P30/TxD0/IrTxD
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PVCC1
PD0/D8
VSS
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
P17/PO15/TIOCB2/PWM3/TCLKD
MD1
MD2
NC
NC
PC0/A0
PC1/A1
PC2/A2
PC3/A3
VSS
PC4/A4
VCC
PC5/A5
PC6/A6/PWM0
PC7/A7/PWM1
VSS
PB0/A8/TIOCA3
PVCC1
PB1/A9/TIOCB3
PB2/A10/TIOCC3
PB3/A11/TIOCD3
PB4/A12/TIOCA4
PB5/A13/TIOCB4
PB6/A14/TIOCA5
PB7/A15/TIOCB5
PA0/A16
PA1/A17/TxD2
PA2/A18/RxD2
PA3/A19/SCK2
VSS
P10/PO8/TIOCA0/DACK0/A20
P11/PO9/TIOCB0/DACK1/A21
P12/PO10/TIOCC0/TCLKA/A22
P13/PO11/TIOCD0/TCLKB/A23
P14/PO12/TIOCA1/IRQ0
NC
NC
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2/PWM2/IRQ1
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6/DA0
P47/AN7/DA1
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12
P95/AN13
P96/AN14/DA2
P97/AN15/DA3
AVSS
P70/TMRI01/TMCI01/DREQ0/CS4
P71/TMRI23/TMCI23/DREQ1/CS5
P72/TMO0/TEND0/CS6
P73/TMO1/TEND1/CS7
P74/TMO2/MRES
P75/TMO3/SCK3
P76/RxD3
P77/TxD3
MD0
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Vref
AVCC
NC
NC
PF0/BREQ/IRQ2
PF1/BACK/BUZZ
PF2/LCAS/WAIT/BREQO
PF3/LWR/ADTRG/IRQ3
PF4/HWR
PF5/RD
PF6/AS/LCAS
VSS
PF7/φ
PVCC1
OSC2
OSC1
VSS
EXTAL
VCC
XTAL
FWE*
STBY
NMI
RES
PLLVSS
PLLCAP
PLLVCC
WDTOVF
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/OE/IRQ7
PG0/CAS/IRQ6
P37/TxD4
NC
NC
P36/RxD4
P35/SCK1/SCK4/SCL0/IRQ5
Section 1 Overview
Note: * The FWE pin is used only in the flash memory version.
In the mask ROM version the FWE pin is an NC pin, and should be left open or connected to VSS.
Figure 1.3 (a) H8S/2633, H8S/2633F, H8S/2632, H8S/2631 Pin Arrangement
(FP-128B: Top View)
Rev. 5.00 Mar 28, 2005 page 13 of 1422
REJ09B0234-0500
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
TOP VIEW
(FP-128B)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
P34/RxD1/SDA0
P33/TxD1/SCL1
VSS
P32/SCK0/SDA1/IRQ4
PVCC2
P31/RxD0/IrRxD
P30/TxD0/IrTxD
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PVCC1
PD0/D8
VSS
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
P17/PO15/TIOCB2/PWM3/TCLKD
MD1
MD2
NC
NC
PC0/A0
PC1/A1
PC2/A2
PC3/A3
VSS
PC4/A4
VCL
PC5/A5
PC6/A6/PWM0
PC7/A7/PWM1
VSS
PB0/A8/TIOCA3
PVCC1
PB1/A9/TIOCB3
PB2/A10/TIOCC3
PB3/A11/TIOCD3
PB4/A12/TIOCA4
PB5/A13/TIOCB4
PB6/A14/TIOCA5
PB7/A15/TIOCB5
PA0/A16
PA1/A17/TxD2
PA2/A18/RxD2
PA3/A19/SCK2
VSS
P10/PO8/TIOCA0/DACK0/A20
P11/PO9/TIOCB0/DACK1/A21
P12/PO10/TIOCC0/TCLKA/A22
P13/PO11/TIOCD0/TCLKB/A23
P14/PO12/TIOCA1/IRQ0
NC
NC
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2/PWM2/IRQ1
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6/DA0
P47/AN7/DA1
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12
P95/AN13
P96/AN14/DA2
P97/AN15/DA3
AVSS
P70/TMRI01/TMCI01/DREQ0/CS4
P71/TMRI23/TMCI23/DREQ1/CS5
P72/TMO0/TEND0/CS6
P73/TMO1/TEND1/CS7
P74/TMO2/MRES
P75/TMO3/SCK3
P76/RxD3
P77/TxD3
MD0
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Vref
AVCC
NC
NC
PF0/BREQ/IRQ2
PF1/BACK/BUZZ
PF2/LCAS/WAIT/BREQO
PF3/LWR/ADTRG/IRQ3
PF4/HWR
PF5/RD
PF6/AS/LCAS
VSS
PF7/φ
PVCC1
OSC2
OSC1
VSS
EXTAL
NC
XTAL
FWE*
STBY
NMI
RES
PLLVSS
PLLCAP
NC
WDTOVF
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/OE/IRQ7
PG0/CAS/IRQ6
P37/TxD4
NC
NC
P36/RxD4
P35/SCK1/SCK4/SCL0/IRQ5
Section 1 Overview
0.1µF
Note: * The FWE pin is used only in the flash memory version.
In the mask ROM version the FWE pin is an NC pin, and should be left open or connected to VSS.
Figure 1.3 (b) H8S/2633R Pin Arrangement (FP-128B: Top View)
Rev. 5.00 Mar 28, 2005 page 14 of 1422
REJ09B0234-0500
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
TOP VIEW
(FP-128B)
P34/RxD1
P33/TxD1
VSS
P32/SCK0/IRQ4
PVCC
P31/RxD0
P30/TxD0
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PVCC
PD0/D8
VSS
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
P17/TIOCB2/TCLKD
MD1
MD2
NC
NC
PC0/A0
PC1/A1
PC2/A2
PC3/A3
VSS
PC4/A4
VCL
PC5/A5
PC6/A6
PC7/A7
VSS
PB0/A8/TIOCA3
PVCC
PB1/A9/TIOCB3
PB2/A10/TIOCC3
PB3/A11/TIOCD3
PB4/A12/TIOCA4
PB5/A13/TIOCB4
PB6/A14/TIOCA5
PB7/A15/TIOCB5
PA0/A16
PA1/A17/TxD2
PA2/A18/RxD2
PA3/A19/SCK2
VSS
P10/TIOCA0/A20
P11/TIOCB0/A21
P12/TIOCC0/TCLKA/A22
P13/TIOCD0/TCLKB/A23
P14/TIOCA1/IRQ0
NC
NC
P15/TIOCB1/TCLKC
P16/TIOCA2/IRQ1
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12
P95/AN13
P96/AN14
P97/AN15
AVSS
P70/CS4
P71/CS5
P72/CS6
P73/CS7
P74/MRES
P75/SCK3
P76/RxD3
P77/TxD3
MD0
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Vref
AVCC
NC
NC
PF0/BREQ/IRQ2
PF1/BACK
PF2/WAIT/BREQO
PF3/LWR/ADTRG/IRQ3
PF4/HWR
PF5/RD
PF6/AS
VSS
PF7/φ
PVCC
NC
NC
VSS
EXTAL
NC
XTAL
NC*
STBY
NMI
RES
PLLVSS
PLLCAP
NC
WDTOVF
PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/IRQ7
PG0/IRQ6
P37/TxD4
NC
NC
P36/RxD4
P35/SCK1/SCK4/IRQ5
Section 1 Overview
0.1µF
Note: * In the flash memory version this is the FWE pin.
In the mask ROM version this pin should be left open or connected to VSS.
Figure 1.3 (c) H8S/2695 Pin Arrangement (FP-128B: Top View)
Rev. 5.00 Mar 28, 2005 page 15 of 1422
REJ09B0234-0500
Section 1 Overview
1.3.2
Pin Functions in Each Operating Mode
Table 1.2 (a) shows the pin functions of the H8S/2633, H8S/2633F, H8S/2632, and H8S/2631 in
each of the operating modes. Table 1.2 (b) shows the pin functions of the H8S/2633R in each of
the operating modes. Table 1.2 (c) shows the pin functions of the H8S/2695 in each of the
operating modes.
Table 1.2 (a) Pin Functions in Each Operating Mode (H8S/2633, H8S/2633F, H8S/2632,
H8S/2631)
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
1
5
A0
A0
PC0/A0
PC0
2
6
A1
A1
PC1/A1
PC1
3
7
A2
A2
PC2/A2
PC2
4
8
A3
A3
PC3/A3
PC3
5
9
VSS
VSS
VSS
VSS
6
10
A4
A4
PC4/A4
PC4
7
11
VCC
VCC
VCC
VCC
8
12
A5
A5
PC5/A5
PC5
9
13
A6
A6
PC6/A6/PWM0
PC6/PWM0
10
14
A7
A7
PC7/A7/PWM1
PC7/PWM1
11
15
VSS
VSS
VSS
VSS
12
16
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/TIOCA3
13
17
PVCC1
PVCC1
PVCC1
PVCC1
14
18
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/TIOCB3
15
19
PB2/A10/TIOCC3
PB2/A10/TIOCC3
PB2/A10/TIOCC3
PB2/TIOCC3
16
20
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/TIOCD3
17
21
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/TIOCA4
18
22
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/TIOCB4
19
23
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/TIOCA5
20
24
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/TIOCB5
21
25
PA0/A16
PA0/A16
PA0/A16
PA0
22
26
PA1/A17/TxD2
PA1/A17/TxD2
PA1/A17/TxD2
PA1/TxD2
23
27
PA2/A18/RxD2
PA2/A18/RxD2
PA2/A18/RxD2
PA2/RxD2
24
28
PA3/A19/SCK2
PA3/A19/SCK2
PA3/A19/SCK2
PA3/SCK2
Rev. 5.00 Mar 28, 2005 page 16 of 1422
REJ09B0234-0500
Section 1 Overview
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
25
29
VSS
VSS
VSS
VSS
26
30
P10/PO8/TIOCA0/
DACK0/A20
P10/PO8/TIOCA0/
DACK0/A20
P10/PO8/TIOCA0/
DACK0/A20
P10/PO8/TIOCA0/
27
31
DACK1/A21
P11/PO9/TIOCB0/
P11/PO9/TIOCB0/
DACK1/A21
P11/PO9/TIOCB0/
DACK1/A21
P11/PO9/TIOCB0/
28
32
P12/PO10/TIOCC0/
TCLKA/A22
P12/PO10/TIOCC0/
TCLKA/A22
P12/PO10/TIOCC0/
TCLKA/A22
P12/PO10/TIOCC0/
TCLKA
29
33
P13/PO11/TIOCD0/
TCLKB/A23
P13/PO11/TIOCD0/
TCLKB/A23
P13/PO11/TIOCD0/
TCLKB/A23
P13/PO11/TIOCD0/
TCLKB
30
34
P14/PO12/TIOCA1/
P14/PO12/TIOCA1/
P14/PO12/TIOCA1/
P14/PO12/TIOCA1/
1
NC*
1
NC*
NC*
1
IRQ0
IRQ0
IRQ0
DACK0
DACK1
IRQ0
—
35
1
NC*
—
36
NC*
NC*
NC*
NC*
31
37
P15/PO13/TIOCB1/
TCLKC
P15/PO13/TIOCB1/
TCLKC
P15/PO13/TIOCB1/
TCLKC
P15/PO13/TIOCB1/
TCLKC
32
38
P16/PO14/TIOCA2/
PWM2/IRQ1
P16/PO14/TIOCA2/
PWM2/IRQ1
P16/PO14/TIOCA2/
PWM2/IRQ1
P16/PO14/TIOCA2/
PWM2/IRQ1
33
39
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
34
40
PE0/D0
PE0/D0
PE0/D0
PE0
35
41
PE1/D1
PE1/D1
PE1/D1
PE1
36
42
PE2/D2
PE2/D2
PE2/D2
PE2
37
43
PE3/D3
PE3/D3
PE3/D3
PE3
38
44
PE4/D4
PE4/D4
PE4/D4
PE4
39
45
PE5/D5
PE5/D5
PE5/D5
PE5
40
46
PE6/D6
PE6/D6
PE6/D6
PE6
41
47
PE7/D7
PE7/D7
PE7/D7
PE7
42
48
VSS
VSS
VSS
VSS
43
49
D8
D8
D8
PD0
44
50
PVCC1
PVCC1
PVCC1
PVCC1
45
51
D9
D9
D9
PD1
46
52
D10
D10
D10
PD2
47
53
D11
D11
D11
PD3
48
54
D12
D12
D12
PD4
49
55
D13
D13
D13
PD5
1
1
1
1
Rev. 5.00 Mar 28, 2005 page 17 of 1422
REJ09B0234-0500
Section 1 Overview
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
50
56
D14
D14
D14
PD6
51
57
D15
D15
D15
PD7
52
58
P30/TxD0/IrTxD
P30/TxD0/IrTxD
P30/TxD0/IrTxD
P30/TxD0/IrTxD
53
59
P31/RxD0/IrRxD
P31/RxD0/IrRxD
P31/RxD0/IrRxD
P31/RxD0/IrRxD
54
60
PVCC2
PVCC2
PVCC2
PVCC2
55
61
P32/SCK0/SDA1/
P32/SCK0/SDA1/
P32/SCK0/SDA1/
P32/SCK0/SDA1/
56
62
VSS
VSS
VSS
VSS
57
63
P33/TxD1/SCL1
P33/TxD1/SCL1
P33/TxD1/SCL1
P33/TxD1/SCL1
58
64
P34/RxD1/SDA0
P34/RxD1/SDA0
P34/RxD1/SDA0
P34/RxD1/SDA0
59
65
P35/SCK1/SCK4/
SCL0/IRQ5
P35/SCK1/SCK4/
SCL0/IRQ5
P35/SCK1/SCK4/
SCL0/IRQ5
P35/SCK1/SCK4/
SCL0/IRQ5
60
66
P36/RxD4
P36/RxD4
P36/RxD4
P36/RxD4
IRQ4
*1
IRQ4
*1
NC*
1
1
67
NC
—
68
NC*
NC*
NC*
NC*
61
69
P37/TxD4
P37/TxD4
P37/TxD4
P37/TxD4
62
70
PG0/CAS/IRQ6
PG0/CAS/IRQ6
PG0/CAS/IRQ6
PG0/IRQ6
63
71
PG1/CS3/OE/IRQ7
PG1/CS3/OE/IRQ7
PG1/CS3/OE/IRQ7
PG1/IRQ7
64
72
PG2/CS2
PG2/CS2
PG2/CS2
PG2
65
73
PG3/CS1
PG3/CS1
PG3/CS1
PG3
66
74
PG4/CS0
PG4/CS0
PG4/CS0
PG4
67
75
WDTOVF
WDTOVF
WDTOVF
WDTOVF
68
76
PLLVCC
PLLVCC
PLLVCC
PLLVCC
69
77
PLLCAP
PLLCAP
PLLCAP
PLLCAP
70
78
PLLVSS
PLLVSS
PLLVSS
PLLVSS
71
79
RES
RES
RES
RES
72
80
NMI
NMI
NMI
NMI
73
81
STBY
STBY
STBY
*2
1
*2
NC
IRQ4
—
1
NC
*1
IRQ4
STBY
74
82
FWE
FWE
FWE
FWE*2
75
83
XTAL
XTAL
XTAL
XTAL
76
84
VCC
VCC
VCC
VCC
77
85
EXTAL
EXTAL
EXTAL
EXTAL
Rev. 5.00 Mar 28, 2005 page 18 of 1422
REJ09B0234-0500
*2
1
Section 1 Overview
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
78
86
VSS
VSS
VSS
VSS
79
87
OSC1
OSC1
OSC1
OSC1
80
88
OSC2
OSC2
OSC2
OSC2
81
89
PVCC1
PVCC1
PVCC1
PVCC1
82
90
PF7/φ
PF7/φ
PF7/φ
PF7/φ
83
91
VSS
VSS
VSS
VSS
84
92
85
93
86
94
87
95
88
96
89
97
90
98
AS/LCAS
RD
HWR
PF3/LWR/ADTRG/
IRQ3
PF2/LCAS/WAIT/
BREQO
PF1/BACK/BUZZ
PF0/BREQ/IRQ2
AS/LCAS
RD
HWR
PF3/LWR/ADTRG/
IRQ3
PF2/LCAS/WAIT/
BREQO
PF1/BACK/BUZZ
PF0/BREQ/IRQ2
AS/LCAS
RD
HWR
PF3/LWR/ADTRG/
IRQ3
PF2/LCAS/WAIT/
BREQO
PF1/BACK/BUZZ
PF0/BREQ/IRQ2
—
99
NC*1
NC*1
NC*1
—
100
NC*
NC*
NC*
NC*
91
101
AVCC
AVCC
AVCC
AVCC
92
102
Vref
Vref
Vref
Vref
93
103
P40/AN0
P40/AN0
P40/AN0
P40/AN0
94
104
P41/AN1
P41/AN1
P41/AN1
P41/AN1
95
105
P42/AN2
P42/AN2
P42/AN2
P42/AN2
96
106
P43/AN3
P43/AN3
P43/AN3
P43/AN3
97
107
P44/AN4
P44/AN4
P44/AN4
P44/AN4
98
108
P45/AN5
P45/AN5
P45/AN5
P45/AN5
99
109
P46/AN6/DA0
P46/AN6/DA0
P46/AN6/DA0
P46/AN6/DA0
1
1
1
PF6
PF5
PF4
PF3/ADTRG/IRQ3
PF2
PF1/BUZZ
PF0/IRQ2
NC*1
1
100
110
P47/AN7/DA1
P47/AN7/DA1
P47/AN7/DA1
P47/AN7/DA1
101
111
P90/AN8
P90/AN8
P90/AN8
P90/AN8
102
112
P91/AN9
P91/AN9
P91/AN9
P91/AN9
103
113
P92/AN10
P92/AN10
P92/AN10
P92/AN10
104
114
P93/AN11
P93/AN11
P93/AN11
P93/AN11
105
115
P94/AN12
P94/AN12
P94/AN12
P94/AN12
Rev. 5.00 Mar 28, 2005 page 19 of 1422
REJ09B0234-0500
Section 1 Overview
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
106
116
P95/AN13
P95/AN13
P95/AN13
P95/AN13
107
117
P96/AN14/DA2
P96/AN14/DA2
P96/AN14/DA2
P96/AN14/DA2
108
118
P97/AN15/DA3
P97/AN15/DA3
P97/AN15/DA3
P97/AN15/DA3
109
119
AVSS
AVSS
AVSS
AVSS
110
120
111
121
112
122
113
123
114
124
DREQ1/CS5
DREQ1/CS5
DREQ1/CS5
DREQ1
P72/TMO0/TEND0/ P72/TMO0/TEND0/ P72/TMO0/TEND0/ P72/TMO0/TEND0
CS6
CS6
CS6
P73/TMO1/TEND1/ P73/TMO1/TEND1/ P73/TMO1/TEND1/ P73/TMO1/TEND1
CS7
CS7
CS7
P74/TMO2/MRES
P74/TMO2/MRES
P74/TMO2/MRES
P74/TMO2/MRES
115
125
P75/TMO3/SCK3
P75/TMO3/SCK3
P75/TMO3/SCK3
P75/TMO3/SCK3
116
126
P76/RxD3
P76/RxD3
P76/RxD3
P76/RxD3
P70/TMRI01/TMCI01/ P70/TMRI01/TMCI01/ P70/TMRI01/TMCI01/ P70/TMRI01/TMCI01/
DREQ0/CS4
DREQ0/CS4
DREQ0
DREQ0/CS4
P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/
117
127
P77/TxD3
P77/TxD3
P77/TxD3
P77/TxD3
118
128
MD0
MD0
MD0
MD0
119
1
MD1
MD1
MD1
MD1
120
2
MD2
MD2
MD2
MD2
—
3
1
NC*
1
NC*
1
NC*
NC*
—
4
NC*
1
NC*
1
1
NC*
NC*
1
1
Notes: 1. NC pins should be connected to VSS or left open.
2. FWE is used only in the flash memory version. Leave open or connect VSS in the mask
ROM version.
Rev. 5.00 Mar 28, 2005 page 20 of 1422
REJ09B0234-0500
Section 1 Overview
Table 1.2 (b) Pin Functions in Each Operating Mode (H8S/2633R)
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
1
5
A0
A0
PC0/A0
PC0
2
6
A1
A1
PC1/A1
PC1
3
7
A2
A2
PC2/A2
PC2
4
8
A3
A3
PC3/A3
PC3
5
9
VSS
VSS
VSS
VSS
6
10
A4
A4
PC4/A4
PC4
7
11
VCL
VCL
VCL
VCL
8
12
A5
A5
PC5/A5
PC5
9
13
A6
A6
PC6/A6/PWM0
PC6/PWM0
10
14
A7
A7
PC7/A7/PWM1
PC7/PWM1
11
15
VSS
VSS
VSS
VSS
12
16
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/TIOCA3
13
17
PVCC1
PVCC1
PVCC1
PVCC1
14
18
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/TIOCB3
15
19
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/TIOCD3
17
21
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/TIOCA4
18
22
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/TIOCB4
19
23
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/TIOCA5
20
24
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/TIOCB5
21
25
PA0/A16
PA0/A16
PA0/A16
PA0
22
26
PA1/A17/TxD2
PA1/A17/TxD2
PA1/A17/TxD2
PA1/TxD2
23
27
PA2/A18/RxD2
PA2/A18/RxD2
PA2/A18/RxD2
PA2/RxD2
24
28
PA3/A19/SCK2
PA3/A19/SCK2
PA3/A19/SCK2
PA3/SCK2
25
29
VSS
VSS
VSS
VSS
26
30
P10/PO8/TIOCA0/
DACK0/A20
P10/PO8/TIOCA0/
DACK0/A20
P10/PO8/TIOCA0/
DACK0/A20
P10/PO8/TIOCA0/
27
31
P11/PO9/TIOCB0/
DACK1/A21
P11/PO9/TIOCB0/
DACK1/A21
P11/PO9/TIOCB0/
DACK1/A21
P11/PO9/TIOCB0/
28
32
P12/PO10/TIOCC0/
TCLKA/A22
P12/PO10/TIOCC0/
TCLKA/A22
P12/PO10/TIOCC0/
TCLKA/A22
P12/PO10/TIOCC0/
TCLKA
29
33
P13/PO11/TIOCD0/
TCLKB/A23
P13/PO11/TIOCD0/
TCLKB/A23
P13/PO11/TIOCD0/
TCLKB/A23
P13/PO11/TIOCD0/
TCLKB
DACK0
DACK1
Rev. 5.00 Mar 28, 2005 page 21 of 1422
REJ09B0234-0500
Section 1 Overview
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
30
34
P14/PO12/TIOCA1/
P14/PO12/TIOCA1/
P14/PO12/TIOCA1/
P14/PO12/TIOCA1/
—
35
1
NC*
1
NC*
1
NC*
NC*
—
36
NC*
NC*
NC*
1
NC*
31
37
P15/PO13/TIOCB1/
TCLKC
P15/PO13/TIOCB1/
TCLKC
P15/PO13/TIOCB1/
TCLKC
P15/PO13/TIOCB1/
TCLKC
32
38
P16/PO14/TIOCA2/
PWM2/IRQ1
P16/PO14/TIOCA2/
PWM2/IRQ1
P16/PO14/TIOCA2/
PWM2/IRQ1
P16/PO14/TIOCA2/
PWM2/IRQ1
33
39
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
P17/PO15/TIOCB2/
PWM3/TCLKD
34
40
PE0/D0
PE0/D0
PE0/D0
PE0
35
41
PE1/D1
PE1/D1
PE1/D1
PE1
36
42
PE2/D2
PE2/D2
PE2/D2
PE2
37
43
PE3/D3
PE3/D3
PE3/D3
PE3
38
44
PE4/D4
PE4/D4
PE4/D4
PE4
39
45
PE5/D5
PE5/D5
PE5/D5
PE5
40
46
PE6/D6
PE6/D6
PE6/D6
PE6
41
47
PE7/D7
PE7/D7
PE7/D7
PE7
42
48
VSS
VSS
VSS
VSS
43
49
D8
D8
D8
PD0
IRQ0
1
IRQ0
1
IRQ0
IRQ0
1
1
44
50
PVCC1
PVCC1
PVCC1
PVCC1
45
51
D9
D9
D9
PD1
46
52
D10
D10
D10
PD2
47
53
D11
D11
D11
PD3
48
54
D12
D12
D12
PD4
49
55
D13
D13
D13
PD5
50
56
D14
D14
D14
PD6
51
57
D15
D15
D15
PD7
52
58
P30/TxD0/IrTxD
P30/TxD0/IrTxD
P30/TxD0/IrTxD
P30/TxD0/IrTxD
53
59
P31/RxD0/IrRxD
P31/RxD0/IrRxD
P31/RxD0/IrRxD
P31/RxD0/IrRxD
54
60
PVCC2
PVCC2
PVCC2
PVCC2
55
61
P32/SCK0/SDA1/
P32/SCK0/SDA1/
P32/SCK0/SDA1/
P32/SCK0/SDA1/
56
62
VSS
VSS
VSS
VSS
IRQ4
IRQ4
Rev. 5.00 Mar 28, 2005 page 22 of 1422
REJ09B0234-0500
IRQ4
IRQ4
Section 1 Overview
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
57
63
P33/TxD1/SCL1
P33/TxD1/SCL1
P33/TxD1/SCL1
P33/TxD1/SCL1
58
64
P34/RxD1/SDA0
P34/RxD1/SDA0
P34/RxD1/SDA0
P34/RxD1/SDA0
59
65
P35/SCK1/SCK4/
SCL0/IRQ5
P35/SCK1/SCK4/
SCL0/IRQ5
P35/SCK1/SCK4/
SCL0/IRQ5
P35/SCK1/SCK4/
SCL0/IRQ5
60
66
P36/RxD4
P36/RxD4
P36/RxD4
P36/RxD4
*1
NC*
1
1
67
NC
—
68
NC*
NC*
NC*
NC*
61
69
P37/TxD4
P37/TxD4
P37/TxD4
P37/TxD4
62
70
PG0/CAS/IRQ6
PG0/CAS/IRQ6
PG0/CAS/IRQ6
PG0/IRQ6
63
71
PG1/CS3/OE/IRQ7
PG1/CS3/OE/IRQ7
PG1/CS3/OE/IRQ7
PG1/IRQ7
64
72
PG2/CS2
PG2/CS2
PG2/CS2
PG2
65
73
PG3/CS1
PG3/CS1
PG3/CS1
PG3
66
74
PG4/CS0
PG4/CS0
PG4/CS0
PG4
67
75
WDTOVF
WDTOVF
WDTOVF
WDTOVF
68
76
NC*1
NC*1
NC*1
NC*1
69
77
PLLCAP
PLLCAP
PLLCAP
PLLCAP
70
78
PLLVSS
PLLVSS
PLLVSS
PLLVSS
71
79
RES
RES
RES
RES
72
80
NMI
NMI
NMI
NMI
73
81
STBY
STBY
STBY
STBY
74
82
FWE
FWE
FWE
FWE
75
83
XTAL
XTAL
XTAL
XTAL
76
84
NC*1
NC*1
NC*1
NC*1
77
85
EXTAL
EXTAL
EXTAL
EXTAL
1
NC
*1
—
1
NC
*1
1
78
86
VSS
VSS
VSS
VSS
79
87
OSC1
OSC1
OSC1
OSC1
80
88
OSC2
OSC2
OSC2
OSC2
81
89
PVCC1
PVCC1
PVCC1
PVCC1
82
90
PF7/φ
PF7/φ
PF7/φ
PF7/φ
83
91
84
92
85
93
VSS
VSS
VSS
AS/LCAS
RD
AS/LCAS
RD
AS/LCAS
RD
VSS
PF6
PF5
Rev. 5.00 Mar 28, 2005 page 23 of 1422
REJ09B0234-0500
Section 1 Overview
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
86
94
87
95
88
96
89
97
90
98
HWR
PF3/LWR/ADTRG/
IRQ3
PF2/LCAS/WAIT/
BREQO
PF1/BACK/BUZZ
PF0/BREQ/IRQ2
*1
Mode 5
Mode 6
Mode 7
HWR
HWR
PF4
PF3/LWR/ADTRG/
PF3/LWR/ADTRG/
PF3/ADTRG/IRQ3
IRQ3
PF2/LCAS/WAIT/
BREQO
PF1/BACK/BUZZ
PF0/BREQ/IRQ2
PF1/BUZZ
PF0/IRQ2
*1
NC*
1
1
99
NC
—
100
NC*
NC*
NC*
NC*
91
101
AVCC
AVCC
AVCC
AVCC
92
102
Vref
Vref
Vref
Vref
93
103
P40/AN0
P40/AN0
P40/AN0
P40/AN0
94
104
P41/AN1
P41/AN1
P41/AN1
P41/AN1
95
105
P42/AN2
P42/AN2
P42/AN2
P42/AN2
96
106
P43/AN3
P43/AN3
P43/AN3
P43/AN3
97
107
P44/AN4
P44/AN4
P44/AN4
P44/AN4
1
NC
PF2
—
1
NC
*1
IRQ3
PF2/LCAS/WAIT/
BREQO
PF1/BACK/BUZZ
PF0/BREQ/IRQ2
1
98
108
P45/AN5
P45/AN5
P45/AN5
P45/AN5
99
109
P46/AN6/DA0
P46/AN6/DA0
P46/AN6/DA0
P46/AN6/DA0
100
110
P47/AN7/DA1
P47/AN7/DA1
P47/AN7/DA1
P47/AN7/DA1
101
111
P90/AN8
P90/AN8
P90/AN8
P90/AN8
102
112
P91/AN9
P91/AN9
P91/AN9
P91/AN9
103
113
P92/AN10
P92/AN10
P92/AN10
P92/AN10
104
114
P93/AN11
P93/AN11
P93/AN11
P93/AN11
105
115
P94/AN12
P94/AN12
P94/AN12
P94/AN12
106
116
P95/AN13
P95/AN13
P95/AN13
P95/AN13
107
117
P96/AN14/DA2
P96/AN14/DA2
P96/AN14/DA2
P96/AN14/DA2
108
118
P97/AN15/DA3
P97/AN15/DA3
P97/AN15/DA3
P97/AN15/DA3
109
119
AVSS
AVSS
AVSS
AVSS
110
120
111
121
112
122
P70/TMRI01/TMCI01/ P70/TMRI01/TMCI01/ P70/TMRI01/TMCI01/ P70/TMRI01/TMCI01/
DREQ0/CS4
DREQ0/CS4
DREQ0
DREQ0/CS4
P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/ P71/TMRI23/TMCI23/
DREQ1/CS5
DREQ1/CS5
DREQ1/CS5
DREQ1
P72/TMO0/TEND0/ P72/TMO0/TEND0/ P72/TMO0/TEND0/ P72/TMO0/TEND0
CS6
CS6
CS6
Rev. 5.00 Mar 28, 2005 page 24 of 1422
REJ09B0234-0500
Section 1 Overview
Pin No.
Pin Name
TFP-120 FP-128B Mode 4
Mode 5
Mode 6
Mode 7
113
123
P73/TMO1/TEND1/
P73/TMO1/TEND1/
P73/TMO1/TEND1/
P73/TMO1/TEND1
114
124
P74/TMO2/MRES
P74/TMO2/MRES
P74/TMO2/MRES
P74/TMO2/MRES
CS7
CS7
CS7
115
125
P75/TMO3/SCK3
P75/TMO3/SCK3
P75/TMO3/SCK3
P75/TMO3/SCK3
116
126
P76/RxD3
P76/RxD3
P76/RxD3
P76/RxD3
117
127
P77/TxD3
P77/TxD3
P77/TxD3
P77/TxD3
118
128
MD0
MD0
MD0
MD0
119
1
MD1
MD1
MD1
MD1
120
2
MD2
MD2
MD2
MD2
—
3
NC*
1
NC*
1
NC*
1
NC*
—
4
NC*
1
NC*
1
NC*
1
NC*
1
1
Note: 1. NC pins should be connected to VSS or left open.
Rev. 5.00 Mar 28, 2005 page 25 of 1422
REJ09B0234-0500
Section 1 Overview
Table 1.2 (c) Pin Functions in Each Operating Mode (H8S/2695)
Pin No.
Pin Name
FP-128B
Mode 4
Mode 5
Mode 6
Mode 7
5
A0
A0
PC0/A0
PC0
6
A1
A1
PC1/A1
PC1
7
A2
A2
PC2/A2
PC2
8
A3
A3
PC3/A3
PC3
9
VSS
VSS
VSS
VSS
10
A4
A4
PC4/A4
PC4
11
VCL
VCL
VCL
VCL
12
A5
A5
PC5/A5
PC5
13
A6
A6
PC6/A6
PC6
14
A7
A7
PC7/A7
PC7
15
VSS
VSS
VSS
VSS
16
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/A8/TIOCA3
PB0/TIOCA3
17
PVCC1
PVCC1
PVCC1
PVCC1
18
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/A9/TIOCB3
PB1/TIOCB3
19
PB2/A10/TIOCC3
PB2/A10/TIOCC3
PB2/A10/TIOCC3
PB2/TIOCC3
20
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/A11/TIOCD3
PB3/TIOCD3
21
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/A12/TIOCA4
PB4/TIOCA4
22
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/A13/TIOCB4
PB5/TIOCB4
23
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/A14/TIOCA5
PB6/TIOCA5
24
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/A15/TIOCB5
PB7/TIOCB5
25
PA0/A16
PA0/A16
PA0/A16
PA0
26
PA1/A17/TxD2
PA1/A17/TxD2
PA1/A17/TxD2
PA1/TxD2
27
PA2/A18/RxD2
PA2/A18/RxD2
PA2/A18/RxD2
PA2/RxD2
28
PA3/A19/SCK2
PA3/A19/SCK2
PA3/A19/SCK2
PA3/SCK2
29
VSS
VSS
VSS
VSS
30
P10/TIOCA0/A20
P10/TIOCA0/A20
P10/TIOCA0/A20
P10/TIOCA0
31
P11/TIOCB0/A21
P11/TIOCB0/A21
P11/TIOCB0/A21
P11/TIOCB0
32
P12/TIOCC0/
TCLKA/A22
P12/TIOCC0/
TCLKA/A22
P12/TIOCC0/
TCLKA/A22
P12/TIOCC0/
TCLKA
33
P13/TIOCD0/
TCLKB/A23
P13/TIOCD0/
TCLKB/A23
P13/TIOCD0/
TCLKB/A23
P13/TIOCD0/
TCLKB
Rev. 5.00 Mar 28, 2005 page 26 of 1422
REJ09B0234-0500
Section 1 Overview
Pin No.
FP-128B
Pin Name
Mode 4
Mode 5
Mode 6
Mode 7
34
P14/TIOCA1/IRQ0
P14/TIOCA1/IRQ0
P14/TIOCA1/IRQ0
P14/TIOCA1/IRQ0
35
NC*
36
NC*
37
P15/TIOCB1/TCLKC P15/TIOCB1/TCLKC P15/TIOCB1/TCLKC P15/TIOCB1/TCLKC
38
P16/TIOCA2/IRQ1
39
P17/TIOCB2/TCLKD P17/TIOCB2/TCLKD P17/TIOCB2/TCLKD P17/TIOCB2/TCLKD
40
PE0/D0
PE0/D0
PE0/D0
PE0
41
PE1/D1
PE1/D1
PE1/D1
PE1
42
PE2/D2
PE2/D2
PE2/D2
PE2
43
PE3/D3
PE3/D3
PE3/D3
PE3
44
PE4/D4
PE4/D4
PE4/D4
PE4
45
PE5/D5
PE5/D5
PE5/D5
PE5
46
PE6/D6
PE6/D6
PE6/D6
PE6
47
PE7/D7
PE7/D7
PE7/D7
PE7
48
VSS
VSS
VSS
VSS
49
D8
D8
D8
PD0
1
NC*
1
NC*
1
NC*
1
NC*
P16/TIOCA2/IRQ1
1
NC*
1
NC*
P16/TIOCA2/IRQ1
1
1
P16/TIOCA2/IRQ1
50
PVCC1
PVCC1
PVCC1
PVCC1
51
D9
D9
D9
PD1
52
D10
D10
D10
PD2
53
D11
D11
D11
PD3
54
D12
D12
D12
PD4
55
D13
D13
D13
PD5
56
D14
D14
D14
PD6
57
D15
D15
D15
PD7
58
P30/TxD0
P30/TxD0
P30/TxD0
P30/TxD0
59
P31/RxD0
P31/RxD0
P31/RxD0
P31/RxD0
60
PVCC2
PVCC2
PVCC2
PVCC2
61
P32/SCK0/IRQ4
P32/SCK0/IRQ4
P32/SCK0/IRQ4
P32/SCK0/IRQ4
62
VSS
VSS
VSS
VSS
63
P33/TxD1
P33/TxD1
P33/TxD1
P33/TxD1
64
P34/RxD1
P34/RxD1
P34/RxD1
P34/RxD1
Rev. 5.00 Mar 28, 2005 page 27 of 1422
REJ09B0234-0500
Section 1 Overview
Pin No.
Pin Name
FP-128B
Mode 4
Mode 5
Mode 6
Mode 7
65
P35/SCK1/SCK4/
P35/SCK1/SCK4/
P35/SCK1/SCK4/
P35/SCK1/SCK4/
66
P36/RxD4
P36/RxD4
P36/RxD4
P36/RxD4
67
1
NC*
1
NC*
1
NC*
NC*
68
NC
*1
*1
*1
NC*
69
P37/TxD4
P37/TxD4
P37/TxD4
P37/TxD4
70
PG0/IRQ6
PG0/IRQ6
PG0/IRQ6
PG0/IRQ6
71
PG1/CS3/IRQ7
PG1/CS3/IRQ7
PG1/CS3/IRQ7
PG1/IRQ7
72
PG2/CS2
PG2/CS2
PG2/CS2
PG2
73
PG3/CS1
PG3/CS1
PG3/CS1
PG3
74
PG4/CS0
PG4/CS0
PG4/CS0
PG4
75
WDTOVF
WDTOVF
WDTOVF
WDTOVF
76
1
NC*
1
NC*
1
NC*
NC*
IRQ5
IRQ5
NC
IRQ5
NC
IRQ5
1
1
1
77
PLLCAP
PLLCAP
PLLCAP
PLLCAP
78
PLLVSS
PLLVSS
PLLVSS
PLLVSS
79
RES
RES
RES
RES
80
NMI
NMI
NMI
NMI
81
STBY
STBY
STBY
STBY
82
NC*2
NC*2
NC*2
NC*2
83
XTAL
84
NC*
NC*
NC*
NC*
85
EXTAL
EXTAL
EXTAL
EXTAL
86
VSS
VSS
VSS
VSS
87
NC*1
NC*1
NC*1
NC*1
88
NC*1
NC*1
NC*1
NC*1
89
PVCC1
PVCC1
PVCC1
PVCC1
90
PF7/φ
PF7/φ
PF7/φ
PF7/φ
91
VSS
VSS
VSS
VSS
AS
RD
HWR
AS
RD
HWR
AS
RD
HWR
92
93
94
1
XTAL
1
Rev. 5.00 Mar 28, 2005 page 28 of 1422
REJ09B0234-0500
XTAL
1
XTAL
1
PF6
PF5
PF4
Section 1 Overview
Pin No.
Pin Name
FP-128B
Mode 4
Mode 5
Mode 6
Mode 7
95
PF3/LWR/ADTRG/
PF3/LWR/ADTRG/
PF3/LWR/ADTRG/
PF3/ADTRG/IRQ3
96
97
98
IRQ3
PF2/WAIT/BREQO
PF1/BACK
PF0/BREQ/IRQ2
*1
IRQ3
PF2/WAIT/BREQO
PF1/BACK
PF0/BREQ/IRQ2
PF1
PF0/IRQ2
*1
NC*
1
1
NC
100
NC*
NC*
NC*
NC*
101
AVCC
AVCC
AVCC
AVCC
102
Vref
Vref
Vref
Vref
103
P40/AN0
P40/AN0
P40/AN0
P40/AN0
104
P41/AN1
P41/AN1
P41/AN1
P41/AN1
105
P42/AN2
P42/AN2
P42/AN2
P42/AN2
106
P43/AN3
P43/AN3
P43/AN3
P43/AN3
107
P44/AN4
P44/AN4
P44/AN4
P44/AN4
108
P45/AN5
P45/AN5
P45/AN5
P45/AN5
109
P46/AN6
P46/AN6
P46/AN6
P46/AN6
110
P47/AN7
P47/AN7
P47/AN7
P47/AN7
111
P90/AN8
P90/AN8
P90/AN8
P90/AN8
112
P91/AN9
P91/AN9
P91/AN9
P91/AN9
113
P92/AN10
P92/AN10
P92/AN10
P92/AN10
114
P93/AN11
P93/AN11
P93/AN11
P93/AN11
115
P94/AN12
P94/AN12
P94/AN12
P94/AN12
116
P95/AN13
P95/AN13
P95/AN13
P95/AN13
117
P96/AN14
P96/AN14
P96/AN14
P96/AN14
1
NC
PF2
99
1
NC
*1
IRQ3
PF2/WAIT/BREQO
PF1/BACK
PF0/BREQ/IRQ2
1
118
P97/AN15
P97/AN15
P97/AN15
P97/AN15
119
AVSS
AVSS
AVSS
AVSS
120
P70/CS4
P70/CS4
P70/CS4
P70
121
P71/CS5
P71/CS5
P71/CS5
P71
122
P72/CS6
P72/CS6
P72/CS6
P72
123
P73/CS7
P73/CS7
P73/CS7
P73
124
P74/MRES
P74/MRES
P74/MRES
P74/MRES
125
P75/SCK3
P75/SCK3
P75/SCK3
P75/SCK3
Rev. 5.00 Mar 28, 2005 page 29 of 1422
REJ09B0234-0500
Section 1 Overview
Pin No.
Pin Name
FP-128B
Mode 4
126
P76/RxD3
P76/RxD3
P76/RxD3
P76/RxD3
127
P77/TxD3
P77/TxD3
P77/TxD3
P77/TxD3
128
MD0
MD0
MD0
MD0
1
MD1
MD1
MD1
MD1
2
MD2
MD2
MD2
MD2
3
1
NC*
1
NC*
1
NC*
NC*
4
NC*
1
NC*
1
Mode 5
1
NC*
Mode 6
NC*
Mode 7
1
1
Notes: 1. NC pins should be connected to VSS or left open.
2. In the flash memory version this is the FWE pin. In the mask ROM version this pin
should be connected to VSS or left open.
Rev. 5.00 Mar 28, 2005 page 30 of 1422
REJ09B0234-0500
Section 1 Overview
1.3.3
Pin Functions
Table 1.3 (a) outlines the pin functions of the H8S/2633, H8S/2633F, H8S/2632, and H8S/2631.
Table 1.3 (b) outlines the pin functions of the H8S/2633R. Table 1.3 (c) outlines the pin functions
of the H8S/2695.
Table 1.3 (a) Pin Functions (H8S/2633, H8S/2633F, H8S/2632, H8S/2631)
Type
Symbol
I/O
Name and Function
Power
VCC
Input
Power supply: For connection to the power supply.
All VCC pins should be connected to the system power
supply.
PVCC1,
PVCC2
Input
Port power supply pin. Connect all pins to the same
power supply.
VSS
Input
Ground: For connection to ground
(0 V). All VSS pins should be connected to the system
power supply (0 V).
PLLVCC
Input
PLL power supply: Power supply for on-chip PLL
oscillator.
PLLVSS
Input
PLL ground: Ground for on-chip PLL oscillator.
PLLCAP
Input
PLL capacitance: External capacitance pin for on-chip
PLL oscillator.
XTAL
Input
Connects to a crystal oscillator.
See section 23A, Clock Pulse Generator (H8S/2633,
H8S/2632, H8S/2631, H8S/2633F), for typical
connection diagrams for a crystal oscillator and
external clock input.
EXTAL
Input
Connects to a crystal oscillator.
The EXTAL pin can also input an external clock.
See section 23A, Clock Pulse Generator (H8S/2633,
H8S/2632, H8S/2631, H8S/2633F), for typical
connection diagrams for a crystal oscillator and
external clock input.
OSC1
Input
Subclock: Connects to a 32.768 kHz crystal oscillator.
See section 23A, Clock Pulse Generator (H8S/2633,
H8S/2632, H8S/2631, H8S/2633F), for examples of
connections to a crystal oscillator.
OSC2
Input
Subclock: Connects to a 32.768 kHz crystal oscillator.
See section 23A, Clock Pulse Generator (H8S/2633,
H8S/2632, H8S/2631, H8S/2633F), for examples of
connections to a crystal oscillator.
Clock
Rev. 5.00 Mar 28, 2005 page 31 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
Clock
φ
Output
System clock: Supplies the system clock to an external
device.
Operating mode
control
MD2 to MD0
Input
Mode pins: These pins set the operating mode.
The relation between the settings of pins MD2 to MD0
and the operating mode is shown below. These pins
should not be changed while the H8S/2633 Group is
operating.
MD2
MD1
MD0
Operating Mode
0
0
0
—
1
—
0
—
1
—
0
Mode 4
1
Mode 5
0
Mode 6
1
Mode 7
1
1
0
1
System control
RES
Input
Reset input: When this pin is driven low, the chip is
reset.
MRES
Input
Manual reset: When this pin is driven low, a
transmission is made to manual reset mode.
STBY
Input
Standby: When this pin is driven low, a transition is
made to hardware standby mode.
BREQ
Input
Bus request: Used by an external bus master to issue
a bus request to the H8S/2633 Group.
BREQO
Output
Bus request output: The external bus request signal
used when an internal bus master accesses external
space in the external bus-released state.
BACK
Output
Bus request acknowledge: Indicates that the bus has
been released to an external bus master.
FWE
Input
Flash write enable: Pin for flash memory use (in
planning stage).
Rev. 5.00 Mar 28, 2005 page 32 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
Interrupts
NMI
Input
Nonmaskable interrupt: Requests a nonmaskable
interrupt. When this pin is not used, it should be fixed
high.
IRQ7 to IRQ0
Input
Interrupt request 7 to 0: These pins request a
maskable interrupt.
Address bus
A23 to A0
Output
Address bus: These pins output an address.
Data bus
D15 to D0
I/O
Data bus: These pins constitute a bidirectional data
bus.
Output
Chip select: Selection signal for areas 0 to 7.
Output
Address strobe: When this pin is low, it indicates that
address output on the address bus is enabled.
RD
Output
Read: When this pin is low, it indicates that the
external address space can be read.
HWR
Output
High write/write enable/upper write enable:
A strobe signal that writes to external space and
indicates that the upper half (D15 to D8) of the data
bus is enabled.
The 2CAS type DRAM write enable signal.
The 2WE type DRAM upper write enable signal.
LWR
Output
Low write/lower column address strobe/lower write
enable:
A strobe signal that writes to external space and
indicates that the lower half (D7 to D0) of the data bus
is enabled.
The 2CAS type (LCASS = 1) DRAM lower column
address strobe signal.
The 2WE type DRAM lower write enable signal.
CAS
Output
Upper column address strobe/column address strobe:
The 2CAS type DRAM upper column address strobe
signal.
LCAS
Output
Lower column address strobe:
The 2CAS type DRAM lower column address strobe
signal.
OE
Output
Output enable:
Output enable signal for DRAM space read access.
WAIT
Input
Wait: Requests insertion of a wait state in the bus
cycle when accessing external 3-state address space.
Bus control
CS7 to CS0
AS
Rev. 5.00 Mar 28, 2005 page 33 of 1422
REJ09B0234-0500
Section 1 Overview
Type
DMA controller
(DMAC)
16-bit timerpulse unit (TPU)
Symbol
I/O
Name and Function
Input
DMA request 1,0:
Requests DMAC activation.
Output
DMA transfer completed 1,0:
Indicates DMAC data transfer end.
Output
DMA transfer acknowledge 1,0:
DMAC single address transfer acknowledge pin.
TCLKD to
TCLKA
Input
Clock input D to A: These pins input an external clock.
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0
I/O
Input capture/ output compare match A0 to D0:
The TGR0A to TGR0D input capture input or output
compare output, or PWM output pins.
TIOCA1,
TIOCB1
I/O
Input capture/ output compare match A1 and B1:
The TGR1A and TGR1B input capture input or output
compare output, or PWM output pins.
TIOCA2,
TIOCB2
I/O
Input capture/ output compare match A2 and B2:
The TGR2A and TGR2B input capture input or output
compare output, or PWM output pins.
TIOCA3,
TIOCB3,
TIOCC3,
TIOCD3
I/O
Input capture/ output compare match A3 to D3:
The TGR3A to TGR3D input capture input or output
compare output, or PWM output pins.
TIOCA4,
TIOCB4
I/O
Input capture/output compare match A4 and B4:
The TGR4A and TGR4B input capture input or output
compare output, or PWM output pins.
TIOCA5,
TIOCB5
I/O
Input capture/output compare match A5 and B5:
The TGR5A and TGR5B input capture input or output
compare output, or PWM output pins.
DREQ1,
DREQ0
TEND1,
TEND0
DACK1,
DACK0
Programmable
pulse generator
(PPG)
PO15 to PO8 Output
8-bit timer
TMO0 to
TMO3
Output
Compare match output: The compare match output
pins.
TMCI01,
TMCI23
Input
Counter external clock input: Input pins for the external
clock input to the counter.
TMRI01,
TMRI23
Input
Counter external reset input: The counter reset input
pins.
Rev. 5.00 Mar 28, 2005 page 34 of 1422
REJ09B0234-0500
Pulse output 15 to 8: Pulse output pins.
Section 1 Overview
Type
Symbol
I/O
Name and Function
Output
PWMX timer output: PWM D/A pulse output pins.
WDTOVF
Output
Watchdog timer overflows: The counter overflows
signal output pin in watchdog timer mode.
BUZZ
Output
BUZZ output: Output pins for the pulse divided by the
watchdog timer.
TxD4, TxD3,
TxD2, TxD1,
TxD0
Output
Transmit data (channel 0 to 4): Data output pins.
14-bit PWM timer PWM0 to
(PWMX)
PWM3
Watchdog
timer (WDT)
Serial
communication
interface (SCI)/
Smart Card
interface
RxD4, RxD3, Input
RxD2, RxD1,
RxD0
Receive data (channel 0 to 4): Data input pins.
SCK4, SCK3, I/O
SCK2, SCK1,
SCK0
Serial clock (channel 0 to 4): Clock I/O pins.
SCK0 output type is NMOS push-pull.
IrTxD
IrRxD
Output/
Input
IrDA transmission data/receive data: Input/output pins
for the data encoded for the IrDA.
I2C bus interface SCL0
(IIC) (optional)
SCL1
I/O
I2C clock input (channel 1, 0):
2
I C clock input/output pins.
These functions have a bus driving function.
SCL0's output format is an NMOS open drain.
SDA0
SDA1
I/O
I2C data input/output (channel 1, 0):
2
I C clock input/output pins.
These functions have a bus driving function.
SCL0's output format is an NMOS open drain.
IrDA-equipped
SCI 1 channel
(SCI0)
A/D converter
AN15 to AN0 Input
Analog 15 to 0: Analog input pins.
ADTRG
Input
A/D conversion external trigger input: Pin for input of
an external trigger to start A/D conversion.
D/A converter
DA3 to DA0
Output
Analog output: Analog output pins for D/A converter.
A/D converter,
D/A converter
AVCC
Input
A/D converter and D/A converter power supply pin.
When the A/D converter and D/A converter are not
used, this pin should be connected to the system
power supply (+5 V).
AVSS
Input
Analog circuit ground and reference voltage
A/D converter and D/A converter ground and reference
voltage.
Connect to system power supply (0 V).
Rev. 5.00 Mar 28, 2005 page 35 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
A/D converter,
D/A converter
Vref
Input
A/D converter and D/A converter reference voltage
input pin.
When the A/D converter and D/A converter are not
used, this pin should be connected to the system
power supply (+5 V).
I/O ports
P17 to P10
I/O
Port 1: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port 1 data
direction register (P1DDR).
P37 to P30
I/O
Port 3: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port 3 data
direction register (P3DDR).
P47 to P40
Input
Port 4: An 8-bit input port.
P77 to P70
I/O
Port 7: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port 7 data
direction register (P7DDR).
P97 to P90
Input
Port 9: An 8-bit input port.
PA3 to PA0
I/O
Port A: A 4-bit I/O port. Input or output can be
designated for each bit by means of the port A data
direction register (PADDR).
PB7 to PB0
I/O
Port B: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port B data
direction register (PBDDR).
PC7 to PC0
I/O
Port C: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port C data
direction register (PCDDR).
PD7 to PD0
I/O
Port D: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port D data
direction register (PDDDR).
PE7 to PE0
I/O
Port E: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port E data
direction register (PEDDR).
PF7 to PF0
I/O
Port F: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port F data
direction register (PFDDR).
PG4 to PG0
I/O
Port G: An 5-bit I/O port. Input or output can be
designated for each bit by means of the port G data
direction register (PGDDR).
Rev. 5.00 Mar 28, 2005 page 36 of 1422
REJ09B0234-0500
Section 1 Overview
Table 1.3 (b) Pin Functions (H8S/2633R)
Type
Symbol
I/O
Name and Function
Power
VCL
Output
On-chip power supply stabilizer pin: The VCL pin need
not be connected to the power supply. Connect this pin
to VSS via a 0.1 µF capacitor (placed close to the
pins).
PVCC1,
PVCC2
Input
Port power supply pin. Connect all pins to the same
power supply.
VSS
Input
Ground: For connection to ground
(0 V). All VSS pins should be connected to the system
power supply (0 V).
PLLVSS
Input
PLL ground: Ground for on-chip PLL oscillator.
PLLCAP
Input
PLL capacitance: External capacitance pin for on-chip
PLL oscillator.
XTAL
Input
Connects to a crystal oscillator.
See section 23B, Clock Pulse Generator (H8S/2633R,
H8S/2695), for typical connection diagrams for a
crystal oscillator and external clock input.
EXTAL
Input
Connects to a crystal oscillator.
The EXTAL pin can also input an external clock.
See section 23B, Clock Pulse Generator (H8S/2633R,
H8S/2695), for typical connection diagrams for a
crystal oscillator and external clock input.
OSC1
Input
Subclock: Connects to a 32.768 kHz crystal oscillator.
See section 23B, Clock Pulse Generator (H8S/2633R,
H8S/2695), for examples of connections to a crystal
oscillator.
OSC2
Input
Subclock: Connects to a 32.768 kHz crystal oscillator.
See section 23B, Clock Pulse Generator (H8S/2633R,
H8S/2695), for examples of connections to a crystal
oscillator.
φ
Output
System clock: Supplies the system clock to an external
device.
Clock
Rev. 5.00 Mar 28, 2005 page 37 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
Operating mode
control
MD2 to MD0
Input
Mode pins: These pins set the operating mode.
The relation between the settings of pins MD2 to MD0
and the operating mode is shown below. These pins
should not be changed while the H8S/2633 Group is
operating.
MD2
MD1
MD0
Operating Mode
0
0
0
—
1
—
0
—
1
—
0
Mode 4
1
Mode 5
0
Mode 6
1
Mode 7
1
1
0
1
System control
Interrupts
Address bus
RES
Input
Reset input: When this pin is driven low, the chip is
reset.
MRES
Input
Manual reset: When this pin is driven low, a
transmission is made to manual reset mode.
STBY
Input
Standby: When this pin is driven low, a transition is
made to hardware standby mode.
BREQ
Input
Bus request: Used by an external bus master to issue
a bus request to the H8S/2633 Group.
BREQO
Output
Bus request output: The external bus request signal
used when an internal bus master accesses external
space in the external bus-released state.
BACK
Output
Bus request acknowledge: Indicates that the bus has
been released to an external bus master.
FWE
Input
Flash write enable: Pin for flash memory use (in
planning stage).
NMI
Input
Nonmaskable interrupt: Requests a nonmaskable
interrupt. When this pin is not used, it should be fixed
high.
IRQ7 to IRQ0
Input
Interrupt request 7 to 0: These pins request a
maskable interrupt.
A23 to A0
Output
Address bus: These pins output an address.
Rev. 5.00 Mar 28, 2005 page 38 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
Data bus
D15 to D0
I/O
Data bus: These pins constitute a bidirectional data
bus.
Output
Chip select: Selection signal for areas 0 to 7.
Output
Address strobe: When this pin is low, it indicates that
address output on the address bus is enabled.
RD
Output
Read: When this pin is low, it indicates that the
external address space can be read.
HWR
Output
High write/write enable/upper write enable:
A strobe signal that writes to external space and
indicates that the upper half (D15 to D8) of the data
bus is enabled.
The 2CAS type DRAM write enable signal.
The 2WE type DRAM upper write enable signal.
LWR
Output
Low write/lower column address strobe/lower write
enable:
A strobe signal that writes to external space and
indicates that the lower half (D7 to D0) of the data bus
is enabled.
The 2CAS type (LCASS = 1) DRAM lower column
address strobe signal.
The 2WE type DRAM lower write enable signal.
CAS
Output
Upper column address strobe/column address strobe:
The 2CAS type DRAM upper column address strobe
signal.
LCAS
Output
Lower column address strobe:
The 2CAS type DRAM lower column address strobe
signal.
OE
Output
Output enable:
Output enable signal for DRAM space read access.
WAIT
Input
Wait: Requests insertion of a wait state in the bus
cycle when accessing external 3-state address space.
Input
DMA request 1,0:
Requests DMAC activation.
Output
DMA transfer completed 1,0:
Indicates DMAC data transfer end.
Output
DMA transfer acknowledge 1,0:
DMAC single address transfer acknowledge pin.
Bus control
DMA controller
(DMAC)
CS7 to CS0
AS
DREQ1,
DREQ0
TEND1,
TEND0
DACK1,
DACK0
Rev. 5.00 Mar 28, 2005 page 39 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
16-bit timerpulse unit (TPU)
TCLKD to
TCLKA
Input
Clock input D to A: These pins input an external clock.
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0
I/O
Input capture/ output compare match A0 to D0:
The TGR0A to TGR0D input capture input or output
compare output, or PWM output pins.
TIOCA1,
TIOCB1
I/O
Input capture/ output compare match A1 and B1:
The TGR1A and TGR1B input capture input or output
compare output, or PWM output pins.
TIOCA2,
TIOCB2
I/O
Input capture/ output compare match A2 and B2:
The TGR2A and TGR2B input capture input or output
compare output, or PWM output pins.
TIOCA3,
TIOCB3,
TIOCC3,
TIOCD3
I/O
Input capture/ output compare match A3 to D3:
The TGR3A to TGR3D input capture input or output
compare output, or PWM output pins.
TIOCA4,
TIOCB4
I/O
Input capture/output compare match A4 and B4:
The TGR4A and TGR4B input capture input or output
compare output, or PWM output pins.
TIOCA5,
TIOCB5
I/O
Input capture/output compare match A5 and B5:
The TGR5A and TGR5B input capture input or output
compare output, or PWM output pins.
Programmable
pulse generator
(PPG)
PO15 to PO8 Output
Pulse output 15 to 8: Pulse output pins.
8-bit timer
TMO0 to
TMO3
Output
Compare match output: The compare match output
pins.
TMCI01,
TMCI23
Input
Counter external clock input: Input pins for the external
clock input to the counter.
TMRI01,
TMRI23
Input
Counter external reset input: The counter reset input
pins.
Output
PWMX timer output: PWM D/A pulse output pins.
WDTOVF
Output
Watchdog timer overflows: The counter overflows
signal output pin in watchdog timer mode.
BUZZ
Output
BUZZ output: Output pins for the pulse divided by the
watchdog timer.
14-bit PWM timer PWM0 to
(PWMX)
PWM3
Watchdog
timer (WDT)
Rev. 5.00 Mar 28, 2005 page 40 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
Serial
communication
interface (SCI)/
Smart Card
interface
TxD4, TxD3,
TxD2, TxD1,
TxD0
Output
Transmit data (channel 0 to 4): Data output pins.
RxD4, RxD3, Input
RxD2, RxD1,
RxD0
Receive data (channel 0 to 4): Data input pins.
SCK4, SCK3, I/O
SCK2, SCK1,
SCK0
Serial clock (channel 0 to 4): Clock I/O pins.
SCK0 output type is NMOS push-pull.
IrTxD
IrRxD
Output/
Input
IrDA transmission data/receive data: Input/output pins
for the data encoded for the IrDA.
I2C bus interface SCL0
(IIC) (optional)
SCL1
I/O
I2C clock input (channel 1, 0):
2
I C clock input/output pins.
These functions have a bus driving function.
SCL0's output format is an NMOS open drain.
SDA0
SDA1
I/O
I2C data input/output (channel 1, 0):
I2C clock input/output pins.
These functions have a bus driving function.
SCL0's output format is an NMOS open drain.
IrDA-equipped
SCI 1 channel
(SCI0)
A/D converter
AN15 to AN0 Input
ADTRG
Input
Analog 15 to 0: Analog input pins.
A/D conversion external trigger input: Pin for input of
an external trigger to start A/D conversion.
D/A converter
DA3 to DA0
Output
Analog output: Analog output pins for D/A converter.
A/D converter,
D/A converter
AVCC
Input
A/D converter and D/A converter power supply pin.
When the A/D converter and D/A converter are not
used, this pin should be connected to the system
power supply (+5 V).
AVSS
Input
Analog circuit ground and reference voltage
A/D converter and D/A converter ground and reference
voltage.
Connect to system power supply (0 V).
Vref
Input
A/D converter and D/A converter reference voltage
input pin.
When the A/D converter and D/A converter are not
used, this pin should be connected to the system
power supply (+5 V).
Rev. 5.00 Mar 28, 2005 page 41 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
I/O ports
P17 to P10
I/O
Port 1: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port 1 data
direction register (P1DDR).
P37 to P30
I/O
Port 3: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port 3 data
direction register (P3DDR).
P47 to P40
Input
Port 4: An 8-bit input port.
P77 to P70
I/O
Port 7: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port 7 data
direction register (P7DDR).
P97 to P90
Input
Port 9: An 8-bit input port.
PA3 to PA0
I/O
Port A: A 4-bit I/O port. Input or output can be
designated for each bit by means of the port A data
direction register (PADDR).
PB7 to PB0
I/O
Port B: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port B data
direction register (PBDDR).
PC7 to PC0
I/O
Port C: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port C data
direction register (PCDDR).
PD7 to PD0
I/O
Port D: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port D data
direction register (PDDDR).
PE7 to PE0
I/O
Port E: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port E data
direction register (PEDDR).
PF7 to PF0
I/O
Port F: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port F data
direction register (PFDDR).
PG4 to PG0
I/O
Port G: An 5-bit I/O port. Input or output can be
designated for each bit by means of the port G data
direction register (PGDDR).
Rev. 5.00 Mar 28, 2005 page 42 of 1422
REJ09B0234-0500
Section 1 Overview
Table 1.3 (c) Pin Functions (H8S/2695)
Type
Symbol
I/O
Name and Function
Power
VCL
Output
On-chip power supply stabilizer pin: The VCL pin need
not be connected to the power supply. Connect this pin
to VSS via a 0.1 µF capacitor (placed close to the
pins).
PVCC
Input
Port power supply pin. Connect all pins to the same
power supply.
VSS
Input
Ground: For connection to ground
(0 V). All VSS pins should be connected to the system
power supply (0 V).
PLLVSS
Input
PLL ground: Ground for on-chip PLL oscillator.
PLLCAP
Input
PLL capacitance: External capacitance pin for on-chip
PLL oscillator.
XTAL
Input
Connects to a crystal oscillator.
See section 23B, Clock Pulse Generator (H8S/2633R,
H8S/2695), for typical connection diagrams for a
crystal oscillator and external clock input.
EXTAL
Input
Connects to a crystal oscillator.
The EXTAL pin can also input an external clock.
See section 23B, Clock Pulse Generator (H8S/2633R,
H8S/2695), for typical connection diagrams for a
crystal oscillator and external clock input.
φ
Output
System clock: Supplies the system clock to an external
device.
MD2 to MD0
Input
Mode pins: These pins set the operating mode.
The relation between the settings of pins MD2 to MD0
and the operating mode is shown below. These pins
should not be changed while the H8S/2633 Group is
operating.
Clock
Operating mode
control
MD2
MD1
MD0
Operating Mode
0
0
0
—
1
—
1
0
—
1
—
1
0
1
0
Mode 4
1
Mode 5
0
Mode 6
1
Mode 7
Rev. 5.00 Mar 28, 2005 page 43 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
System control
RES
Input
Reset input: When this pin is driven low, the chip is
reset.
MRES
Input
Manual reset: When this pin is driven low, a
transmission is made to manual reset mode.
STBY
Input
Standby: When this pin is driven low, a transition is
made to hardware standby mode.
BREQ
Input
Bus request: Used by an external bus master to issue
a bus request to the H8S/2633 Group.
BREQO
Output
Bus request output: The external bus request signal
used when an internal bus master accesses external
space in the external bus-released state.
BACK
Output
Bus request acknowledge: Indicates that the bus has
been released to an external bus master.
NMI
Input
Nonmaskable interrupt: Requests a nonmaskable
interrupt. When this pin is not used, it should be fixed
high.
IRQ7 to IRQ0
Input
Interrupt request 7 to 0: These pins request a
maskable interrupt.
Address bus
A23 to A0
Output
Address bus: These pins output an address.
Data bus
D15 to D0
I/O
Data bus: These pins constitute a bidirectional data
bus.
Output
Chip select: Selection signal for areas 0 to 7.
Output
Address strobe: When this pin is low, it indicates that
address output on the address bus is enabled.
RD
Output
Read: When this pin is low, it indicates that the
external address space can be read.
HWR
Output
High write/write enable/upper write enable:
A strobe signal that writes to external space and
indicates that the upper half (D15 to D8) of the data
bus is enabled.
The 2CAS type DRAM write enable signal.
The 2WE type DRAM upper write enable signal.
Interrupts
Bus control
CS7 to CS0
AS
Rev. 5.00 Mar 28, 2005 page 44 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
Bus control
LWR
Output
Low write/lower column address strobe/lower write
enable:
A strobe signal that writes to external space and
indicates that the lower half (D7 to D0) of the data bus
is enabled.
The 2CAS type (LCASS = 1) DRAM lower column
address strobe signal.
The 2WE type DRAM lower write enable signal.
WAIT
Input
Wait: Requests insertion of a wait state in the bus
cycle when accessing external 3-state address space.
TCLKD to
TCLKA
Input
Clock input D to A: These pins input an external clock.
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0
I/O
Input capture/ output compare match A0 to D0:
The TGR0A to TGR0D input capture input or output
compare output, or PWM output pins.
TIOCA1,
TIOCB1
I/O
Input capture/ output compare match A1 and B1:
The TGR1A and TGR1B input capture input or output
compare output, or PWM output pins.
TIOCA2,
TIOCB2
I/O
Input capture/ output compare match A2 and B2:
The TGR2A and TGR2B input capture input or output
compare output, or PWM output pins.
TIOCA3,
TIOCB3,
TIOCC3,
TIOCD3
I/O
Input capture/ output compare match A3 to D3:
The TGR3A to TGR3D input capture input or output
compare output, or PWM output pins.
TIOCA4,
TIOCB4
I/O
Input capture/output compare match A4 and B4:
The TGR4A and TGR4B input capture input or output
compare output, or PWM output pins.
TIOCA5,
TIOCB5
I/O
Input capture/output compare match A5 and B5:
The TGR5A and TGR5B input capture input or output
compare output, or PWM output pins.
Output
Watchdog timer overflows: The counter overflows
signal output pin in watchdog timer mode.
16-bit timerpulse unit (TPU)
Watchdog
timer (WDT)
WDTOVF
Rev. 5.00 Mar 28, 2005 page 45 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
Serial
communication
interface (SCI)/
Smart Card
interface
TxD4, TxD3,
TxD2, TxD1,
TxD0
Output
Transmit data (channel 0, 1, 2): Data output pins.
A/D converter
RxD4, RxD3, Input
RxD2, RxD1,
RxD0
Receive data (channel 0, 1, 2): Data input pins.
SCK4, SCK3, I/O
SCK2, SCK1,
SCK0
Serial clock (channel 0, 1, 2): Clock I/O pins.
SCK0 output type is NMOS push-pull.
AN15 to AN0 Input
Analog 15 to 0: Analog input pins.
ADTRG
Input
A/D conversion external trigger input: Pin for input of
an external trigger to start A/D conversion.
AVCC
Input
A/D converter power supply pin.
When the A/D converter are not used, this pin should
be connected to the system power supply (+5 V).
AVSS
Input
Analog circuit ground and reference voltage
A/D converter ground and reference voltage.
Connect to system power supply (0 V).
Vref
Input
A/D converter reference voltage input pin.
When the A/D converter are not used, this pin should
be connected to the system power supply (+5 V).
I/O ports
P17 to P10
I/O
Port 1: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port 1 data
direction register (P1DDR).
P37 to P30
I/O
Port 3: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port 3 data
direction register (P3DDR).
P47 to P40
Input
Port 4: An 8-bit input port.
P77 to P70
I/O
Port 7: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port 7 data
direction register (P7DDR).
P97 to P90
Input
Port 9: An 8-bit input port.
PA3 to PA0
I/O
Port A: A 4-bit I/O port. Input or output can be
designated for each bit by means of the port A data
direction register (PADDR).
PB7 to PB0
I/O
Port B: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port B data
direction register (PBDDR).
Rev. 5.00 Mar 28, 2005 page 46 of 1422
REJ09B0234-0500
Section 1 Overview
Type
Symbol
I/O
Name and Function
I/O ports
PC7 to PC0
I/O
Port C: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port C data
direction register (PCDDR).
PD7 to PD0
I/O
Port D: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port D data
direction register (PDDDR).
PE7 to PE0
I/O
Port E: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port E data
direction register (PEDDR).
PF7 to PF0
I/O
Port F: An 8-bit I/O port. Input or output can be
designated for each bit by means of the port F data
direction register (PFDDR).
PG4 to PG0
I/O
Port G: An 5-bit I/O port. Input or output can be
designated for each bit by means of the port G data
direction register (PGDDR).
Rev. 5.00 Mar 28, 2005 page 47 of 1422
REJ09B0234-0500
Section 1 Overview
Rev. 5.00 Mar 28, 2005 page 48 of 1422
REJ09B0234-0500
Section 2 CPU
Section 2 CPU
2.1
Overview
The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is
ideal for realtime control.
2.1.1
Features
The H8S/2600 CPU has the following features.
• Upward-compatible with H8/300 and H8/300H CPUs
 Can execute H8/300 and H8/300H object programs
• General-register architecture
 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit
registers)
• Sixty-nine basic instructions
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
 Multiply-and-accumulate instruction
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]
• 16-Mbyte address space
 Program: 16 Mbytes
 Data:
16 Mbytes (4 Gbytes architecturally)
Rev. 5.00 Mar 28, 2005 page 49 of 1422
REJ09B0234-0500
Section 2 CPU
• High-speed operation
 All frequently-used instructions execute in one or two states
 Maximum clock rate: 25 MHz (H8S/2633, H8S/2633F, H8S/2632, H8S/2631),
28 MHz (H8S/2633R, H8S/2695)
 8/16/32-bit register-register add/subtract: 40 ns (25 MHz), 35 ns (28 MHz)
 8 × 8-bit register-register multiply:
120 ns (25 MHz), 105 ns (28 MHz)
 16 ÷ 8-bit register-register divide:
480 ns (25 MHz), 420 ns (28 MHz)
 16 × 16-bit register-register multiply:
160 ns (25 MHz), 140 ns (28 MHz)
 32 ÷ 16-bit register-register divide:
800 ns (25 MHz), 700 ns (28 MHz)
• Two CPU operating modes
 Normal mode*
 Advanced mode
Note: * Not available in the H8S/2633 Group.
• Power-down state
 Transition to power-down state by SLEEP instruction
 CPU clock speed selection
2.1.2
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions is different in each
CPU.
Execution States
Instruction
Mnemonic
H8S/2600
H8S/2000
MULXU
MULXU.B Rs, Rd
3
12
MULXS
MULXU.W Rs, ERd
4
20
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
Rev. 5.00 Mar 28, 2005 page 50 of 1422
REJ09B0234-0500
Section 2 CPU
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
2.1.3
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.
• More general registers and control registers
 Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been
added.
• Expanded address space
 Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.
 Advanced mode supports a maximum 16-Mbyte address space.
Note: * Not available in the H8S/2633 Group.
• Enhanced addressing
 The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 Signed multiply and divide instructions have been added.
 A multiply-and-accumulate instruction has been added.
 Two-bit shift instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.
• Higher speed
 Basic instructions execute twice as fast.
Rev. 5.00 Mar 28, 2005 page 51 of 1422
REJ09B0234-0500
Section 2 CPU
2.1.4
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.
• Additional control register
 One 8-bit and two 32-bit control registers have been added
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced
 A multiply-and-accumulate instruction has been added
 Two-bit shift instructions have been added
 Instructions for saving and restoring multiple registers have been added
 A test and set instruction has been added
• Higher speed
 Basic instructions execute twice as fast
2.2
CPU Operating Modes
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode* supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for
program and data areas combined). The mode is selected by the mode pins of the microcontroller.
Note: * Not available in the H8S/2633 Group.
Normal mode*
Maximum 64 kbytes, program
and data areas combined
CPU operating modes
Advanced mode
Maximum 16-Mbytes for
program and data areas
combined
Note: * Not available in the H8S/2633 Group.
Figure 2.1 CPU Operating Modes
Rev. 5.00 Mar 28, 2005 page 52 of 1422
REJ09B0234-0500
Section 2 CPU
(1) Normal Mode (Not Available in the H8S/2633 Group)
The exception vector table and stack have the same structure as in the H8/300 CPU.
Address Space: A maximum address space of 64 kbytes can be accessed.
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as
the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain
any value, even when the corresponding general register (Rn) is used as an address register. If the
general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn)
or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding
extended register (En) will be affected.
Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of
effective addresses (EA) are valid.
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area
starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16
bits (figure 2.2). The exception vector table differs depending on the microcontroller. For details
of the exception vector table, see section 4, Exception Handling.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Power-on reset exception vector
Manual reset exception vector
(Reserved for system use)
Exception
vector table
Exception vector 1
Exception vector 2
Figure 2.2 Exception Vector Table (Normal Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16Rev. 5.00 Mar 28, 2005 page 53 of 1422
REJ09B0234-0500
Section 2 CPU
bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note
that this area is also used for the exception vector table.
Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call,
and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto
the stack in exception handling, they are stored as shown in figure 2.3. When EXR is invalid, it is
not pushed onto the stack. For details, see section 4, Exception Handling.
SP
PC
(16 bits)
EXR*1
Reserved*1*3
CCR
CCR*3
SP
*2
(SP
)
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
Figure 2.3 Stack Structure in Normal Mode
(2) Advanced Mode
Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally
a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4
Gbytes for program and data areas combined).
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as
the upper 16-bit segments of 32-bit registers or address registers.
Instruction Set: All instructions and addressing modes can be used.
Rev. 5.00 Mar 28, 2005 page 54 of 1422
REJ09B0234-0500
Section 2 CPU
Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top
area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32
bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4).
For details of the exception vector table, see section 4, Exception Handling.
H'00000000
Reserved
Power-on reset exception vector
H'00000003
H'00000004
Reserved
Manual reset exception vector
H'00000007
H'00000008
Exception vector table
H'0000000B
(Reserved for system use)
H'0000000C
H'00000010
Reserved
Exception vector 1
Figure 2.4 Exception Vector Table (Advanced Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing
a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as
H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the
first part of this range is also the exception vector table.
Rev. 5.00 Mar 28, 2005 page 55 of 1422
REJ09B0234-0500
Section 2 CPU
Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a
subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR)
are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. When
EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
EXR*1
Reserved*1*3
CCR
SP
SP
Reserved
PC
(24 bits)
(a) Subroutine Branch
*2
(SP
)
PC
(24 bits)
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
Figure 2.5 Stack Structure in Advanced Mode
Rev. 5.00 Mar 28, 2005 page 56 of 1422
REJ09B0234-0500
Section 2 CPU
2.3
Address Space
Figure 2.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode.
H'0000
H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot be
used by the
H8S/2633
Group
H'FFFFFFFF
(b) Advanced Mode
(a) Normal Mode*
Note: * Not available in the H8S/2633 Group.
Figure 2.6 Memory Map
Rev. 5.00 Mar 28, 2005 page 57 of 1422
REJ09B0234-0500
Section 2 CPU
2.4
Register Configuration
2.4.1
Overview
The CPU has the internal registers shown in figure 2.7. There are two types of registers: general
registers and control registers.
General Registers (Rn) and Extended Registers (En)
15
07
07
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
EXR T — — — — I2 I1 I0
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
41
63
Sign extension
MAC
32
MACH
MACL
31
Legend:
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
0
Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit*
H:
U:
N:
Z:
V:
C:
MAC:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Multiply-accumulate register
Note: * Cannot be used as an interrupt mask bit in the H8S/2633 Group.
Figure 2.7 CPU Registers
Rev. 5.00 Mar 28, 2005 page 58 of 1422
REJ09B0234-0500
Section 2 CPU
2.4.2
General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and
can be used as both address registers and data registers. When a general register is used as a data
register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used
as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
RH registers
(R0H to R7H)
ER registers
(ER0 to ER7)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.8 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the
stack.
Rev. 5.00 Mar 28, 2005 page 59 of 1422
REJ09B0234-0500
Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.9 Stack
2.4.3
Control Registers
The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),
8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC).
(1) Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)
(2) Extended Control Register (EXR)
This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0).
Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed
in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is
executed.
Bits 6 to 3—Reserved: They are always read as 1.
Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to
7). For details, refer to section 5, Interrupt Controller.
Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. All interrupts, including NMI, are disabled for three states after one of these
instructions is executed, except for STC.
Rev. 5.00 Mar 28, 2005 page 60 of 1422
REJ09B0234-0500
Section 2 CPU
(3) Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted
regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details, refer to section 5, Interrupt Controller.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction
on the flag bits, refer to Appendix A.1, Instruction List.
Rev. 5.00 Mar 28, 2005 page 61 of 1422
REJ09B0234-0500
Section 2 CPU
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
(4) Multiply-Accumulate Register (MAC)
This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are
a sign extension.
2.4.4
Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
Rev. 5.00 Mar 28, 2005 page 62 of 1422
REJ09B0234-0500
Section 2 CPU
2.5
Data Formats
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.
Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte
operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit
BCD data.
2.5.1
General Register Data Formats
Figure 2.10 shows the data formats in general registers.
Data Type
Register Number
Data Format
1-bit data
RnH
7
0
7 6 5 4 3 2 1 0
Don’t care
Don’t care
7
0
7 6 5 4 3 2 1 0
1-bit data
4-bit BCD data
RnL
RnH
4 3
7
Upper
4-bit BCD data
0
Lower
Don’t care
RnL
Byte data
RnH
4 3
7
Upper
Don’t care
7
0
Lower
0
Don’t care
MSB
Byte data
LSB
RnL
7
0
Don’t care
MSB
LSB
Figure 2.10 General Register Data Formats
Rev. 5.00 Mar 28, 2005 page 63 of 1422
REJ09B0234-0500
Section 2 CPU
Data Type
Register Number
Word data
Rn
Word data
En
Data Format
15
0
MSB
15
LSB
0
MSB
LSB
Longword data
ERn
31
16 15
MSB
En
0
Rn
Legend:
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
Figure 2.10 General Register Data Formats (cont)
Rev. 5.00 Mar 28, 2005 page 64 of 1422
REJ09B0234-0500
LSB
Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data
in memory, but word or longword data must begin at an even address. If an attempt is made to
access word or longword data at an odd address, no address error occurs but the least significant
bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to
instruction fetches.
Data Type
Data Format
Address
7
1-bit data
Address L
Byte data
Address L MSB
Word data
7
0
6
5
4
2
1
0
LSB
Address 2M MSB
Address 2M + 1
Longword data
3
LSB
Address 2N MSB
Address 2N + 1
Address 2N + 2
Address 2N + 3
LSB
Figure 2.11 Memory Data Formats
When ER7 is used as an address register to access the stack, the operand size should be word size
or longword size.
Rev. 5.00 Mar 28, 2005 page 65 of 1422
REJ09B0234-0500
Section 2 CPU
2.6
Instruction Set
2.6.1
Overview
The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Size
Types
Data transfer
MOV
POP*1, PUSH*1
BWL
5
LDM*5, STM*5
MOVFPE*3, MOVTPE*3
L
ADD, SUB, CMP, NEG
BWL
ADDX, SUBX, DAA, DAS
B
INC, DEC
BWL
Arithmetic
operations
WL
B
23
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
BW
EXTU, EXTS
TAS*4
WL
B
MAC, LDMAC, STMAC, CLRMAC
—
Logic operations
AND, OR, XOR, NOT
BWL
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL
8
Bit manipulation
B
14
Branch
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
Bcc*2, JMP, BSR, JSR, RTS
—
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
9
Block data transfer EEPMOV
—
1
Legend:
B: Byte
W: Word
L: Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Not available in the H8S/2633 Group.
4. When using the TAS instruction, use register ER0, ER1, ER4, or ER5.
5. Only register ER0 to ER6 should be used when using the STM/LDM instruction.
Rev. 5.00 Mar 28, 2005 page 66 of 1422
REJ09B0234-0500
Arithmetic
operations
—
L
BWL
B
—
ADDX, SUBX
ADDS, SUBS
BWL
BWL
—
—
—
—
TAS*2
MAC
CLRMAC
LDMAC,
STMAC
—
—
NEG
BW
—
EXTU, EXTS
BW
—
MULXU,
DIVXU
MULXS,
DIVXS
L
—
—
—
WL
B
—
—
INC, DEC
DAA, DAS
B
BWL
BWL
WL
—
ADD, CMP
MOVEPE*1,
MOVTPE*1
—
BWL
Rn
SUB
—
—
LDM*3, STM*3
BWL
—
#xx
MOV
BWL
@ERn
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
@(d:16,ERn)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
@(d:32,ERn)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
@–ERn/@ERn+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
@aa:8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
@aa:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
@aa:24
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
@aa:32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@(d:8,PC)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@(d:16,PC)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@@aa:8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
L
WL
Table 2.2
POP, PUSH
Instruction
2.6.2
Data
transfer
Function
Addressing Modes
Section 2 CPU
Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU
can use.
Combinations of Instructions and Addressing Modes
Rev. 5.00 Mar 28, 2005 page 67 of 1422
REJ09B0234-0500
Rev. 5.00 Mar 28, 2005 page 68 of 1422
REJ09B0234-0500
—
—
NOP
Block data transfer
—
@ERn
—
—
—
W
W
—
—
—
—
—
—
B
—
—
—
@(d:16,ERn)
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
@(d:32,ERn)
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
@–ERn/@ERn+
Notes: 1. Not available in the H8S/2633 Group.
2. When using the TAS instruction, use register ER0, ER1, ER4, or ER5.
3. Only register ER0 to ER6 should be used when using the STM/LDM instruction.
Legend:
B: Byte
W: Word
L: Longword
—
—
B
ANDC,
ORC, XORC
B
B
B
—
LDC
—
—
—
—
RTE
SLEEP
—
—
—
—
RTS
TRAPA
STC
System
control
—
—
JMP, JSR
—
—
Bcc, BSR
B
—
Bit manipulation
Branch
BWL
BWL
—
NOT
BWL
—
BWL
#xx
AND, OR,
XOR
Instruction
Rn
Shift
Logic
operations
Function
Addressing Modes
@aa:8
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
@aa:16
—
—
—
W
W
—
—
—
—
—
—
B
—
—
—
@aa:24
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@aa:32
—
—
—
W
W
—
—
—
—
—
—
B
—
—
—
@(d:8,PC)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@(d:16,PC)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@@aa:8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
—
—
—
—
—
—
—
—
—
Section 2 CPU
Section 2 CPU
2.6.3
Table of Instructions Classified by Function
Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3
is defined below.
Operation Notation
Rs
General register (destination)*
General register (source)*
Rn
General register*
Rd
ERn
General register (32-bit register)
MAC
Multiply-accumulate register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move
¬
NOT (logical complement)
:8/:16/:24/:32
8-, 16-, 24-, or 32-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Rev. 5.00 Mar 28, 2005 page 69 of 1422
REJ09B0234-0500
Section 2 CPU
Table 2.3
Instructions Classified by Function
Type
Instruction
Size*1
Function
Data transfer
MOV
B/W/L
(EAs) → Rd, Rs → (Ead)
Moves data between two general registers or between a
general register and memory, or moves immediate data
to a general register.
MOVFPE
B
Cannot be used in the H8S/2633 Group.
MOVTPE
B
Cannot be used in the H8S/2633 Group.
POP
W/L
@SP+ → Rn
Pops a register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L
@SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a register onto the stack. PUSH.W Rn is
identical to MOV.W Rn, @–SP. PUSH.L ERn is identical
to MOV.L ERn, @–SP.
LDM*2
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM*2
L
Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general
registers, or on immediate data and data in a general
register. (Immediate byte data cannot be subtracted
from byte data in a general register. Use the SUBX or
ADD instruction.)
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on
byte data in two general registers, or on immediate data
and data in a general register.
INC
DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2.
(Byte operands can be incremented or decremented by
1 only.)
ADDS
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a
32-bit register.
DAA
DAS
B
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a
general register by referring to the CCR to produce 4-bit
BCD data.
Arithmetic
operations
Rev. 5.00 Mar 28, 2005 page 70 of 1422
REJ09B0234-0500
Section 2 CPU
Type
Instruction
Size*1
Function
Arithmetic
operations
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder.
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the result.
NEG
B/W/L
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of
data in a general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
TAS*3
B
@ERd – 0, 1 → (<bit 7> of @Erd)
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
Rev. 5.00 Mar 28, 2005 page 71 of 1422
REJ09B0234-0500
Section 2 CPU
Type
Instruction
Size*1
Function
Arithmetic
operations
MAC
—
(EAs) × (EAd) + MAC → MAC
Performs signed multiplication on memory contents and
adds the result to the multiply-accumulate register. The
following operations can be performed:
16 bits × 16 bits + 32 bits → 32 bits, saturating
16 bits × 16 bits + 42 bits → 42 bits, non-saturating
CLRMAC
—
0 → MAC
Clears the multiply-accumulate register to zero.
LDMAC
STMAC
L
Rs → MAC, MAC → Rd
Transfers data between a general register and a
multiply-accumulate register.
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register
and another general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate data.
NOT
B/W/L
¬ (Rd) → (Rd)
Takes the one's complement of general register
contents.
SHAL
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.
SHLL
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.
ROTL
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
ROTXL
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.
Logic
operations
Shift
operations
Rev. 5.00 Mar 28, 2005 page 72 of 1422
REJ09B0234-0500
Section 2 CPU
Type
Instruction
Size*1
Function
Bitmanipulation
instructions
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory
operand to 1. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory
operand to 0. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory
operand. The bit number is specified by 3-bit immediate
data or the lower three bits of a general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory
operand and sets or clears the Z flag accordingly. The
bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
BIAND
B
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in
a general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
BIOR
B
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
Rev. 5.00 Mar 28, 2005 page 73 of 1422
REJ09B0234-0500
Section 2 CPU
Type
Instruction
Size*1
Function
Bitmanipulation
instructions
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a
general register or memory operand and stores the
result in the carry flag.
BIXOR
B
C ⊕ ¬ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with the inverse of a
specified bit in a general register or memory operand
and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory
operand to the carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general
register or memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a
general register or memory operand.
BIST
B
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a
specified bit in a general register or memory operand.
The bit number is specified by 3-bit immediate data.
Rev. 5.00 Mar 28, 2005 page 74 of 1422
REJ09B0234-0500
Section 2 CPU
Type
Instruction
Size*1
Function
Branch
instructions
Bcc
—
Branches to a specified address if a specified condition
is true. The branching conditions are listed below.
Mnemonic
Description
Condition
BRA(BT)
Always (true)
Always
BRN(BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC(BHS)
Carry clear
(high or same)
C=0
BCS(BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z∨(N ⊕ V) = 0
BLE
Less or equal
Z∨(N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address.
BSR
—
Branches to a subroutine at a specified address.
JSR
—
Branches to a subroutine at a specified address.
RTS
—
Returns from a subroutine.
Rev. 5.00 Mar 28, 2005 page 75 of 1422
REJ09B0234-0500
Section 2 CPU
Type
Size*1
Function
—
Starts trap-instruction exception handling.
—
Returns from an exception-handling routine.
SLEEP
—
Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves the source operand contents or immediate data
to CCR or EXR. Although CCR and EXR are 8-bit
registers, word-size transfers are performed between
them and memory. The upper 8 bits are valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or
memory. Although CCR and EXR are 8-bit registers,
word-size transfers are performed between them and
memory. The upper 8 bits are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with
immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate
data.
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with
immediate data.
NOP
—
PC + 2 → PC
Only increments the program counter.
Instruction
System control TRAPA
instructions
RTE
Rev. 5.00 Mar 28, 2005 page 76 of 1422
REJ09B0234-0500
Section 2 CPU
Type
Instruction
Size*1
Function
Block data
transfer
instruction
EEPMOV.B
—
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W
—
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block according to parameters set in
general registers R4L or R4, ER5, and ER6.
R4L or R4: size of block (bytes)
ER5: starting source address
ER6: starting destination address
Execution of the next instruction begins as soon as the
transfer is completed.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0 to ER6 should be used when using the STM/LDM instruction.
3. When using the TAS instruction, use register ER0, ER1, ER4, or ER5.
2.6.4
Basic Instruction Formats
The H8S/2633 Group instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).
(1) Operation Field: Indicates the function of the instruction, the addressing mode, and the
operation to be carried out on the operand. The operation field always includes the first 4 bits of
the instruction. Some instructions have two operation fields.
(2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data
registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register
field.
(3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement.
Rev. 5.00 Mar 28, 2005 page 77 of 1422
REJ09B0234-0500
Section 2 CPU
(4) Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2.12 shows examples of instruction formats.
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16, etc.
Figure 2.12 Instruction Formats (Examples)
Rev. 5.00 Mar 28, 2005 page 78 of 1422
REJ09B0234-0500
Section 2 CPU
2.7
Addressing Modes and Effective Address Calculation
2.7.1
Addressing Mode
The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of
these addressing modes. Arithmetic and logic instructions can use the register direct and
immediate modes. Data transfer instructions can use all addressing modes except program-counter
relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.4
Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
(1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit
general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit
registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified
as 32-bit registers.
(2) Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn) which contains the address of the operand on memory. If the address is a program
instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit
displacement contained in the instruction is added to an address register (ERn) specified by the
register field of the instruction, and the sum gives the address of a memory operand. A 16-bit
displacement is sign-extended when added.
Rev. 5.00 Mar 28, 2005 page 79 of 1422
REJ09B0234-0500
Section 2 CPU
(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn:
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address
register contents and the sum is stored in the address register. The value added is 1 for byte
access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or
longword transfer instruction, the register value should be even.
• Register indirect with pre-decrement—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the result becomes the address of a memory operand. The result is
also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer
instruction, or 4 for longword transfer instruction. For word or longword transfer instruction,
the register value should be even.
(5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the
absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits
long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.5 indicates the accessible absolute address ranges.
Table 2.5
Absolute Address Access Ranges
Normal Mode*
Advanced Mode
8 bits (@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
Absolute Address
Data address
32 bits (@aa:32)
Program instruction
address
24 bits (@aa:24)
Note: * Not available in the H8S/2633 Group.
Rev. 5.00 Mar 28, 2005 page 80 of 1422
REJ09B0234-0500
H'000000 to H'FFFFFF
Section 2 CPU
(6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
(7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and
added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch
address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the
displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.
(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The upper bits of the absolute address are all assumed to be 0,
so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in
advanced mode). In normal mode* the memory operand is a word operand and the branch address
is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of
which is assumed to be all 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
Note: * Not available in the H8S/2633 Group.
Rev. 5.00 Mar 28, 2005 page 81 of 1422
REJ09B0234-0500
Section 2 CPU
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(b) Advanced Mode
Note: * Not available in the H8S/2633 Group.
Figure 2.13 Branch Address Specification in Memory Indirect Mode
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
2.7.2
Effective Address Calculation
Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal
mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Note: * Not available in the H8S/2633 Group.
Rev. 5.00 Mar 28, 2005 page 82 of 1422
REJ09B0234-0500
4
3
rm
rn
r
r
disp
r
op
r
• Register indirect with pre-decrement @–ERn
op
Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
op
Register indirect with displacement
@(d:16, ERn) or @(d:32, ERn)
op
Register indirect (@ERn)
op
Register direct (Rn)
Addressing Mode and Instruction Format
disp
1
2
4
0
1, 2, or 4
General register contents
Byte
Word
Longword
0
0
0
0
1, 2, or 4
General register contents
Sign extension
General register contents
General register contents
Operand Size Value added
31
31
31
31
31
Effective Address Calculation
24 23
24 23
24 23
24 23
Don’t care
31
Don’t care
31
Don’t care
31
Don’t care
31
Operand is general register contents.
Effective Address (EA)
0
0
0
0
Table 2.6
2
1
No.
Section 2 CPU
Effective Address Calculation
Rev. 5.00 Mar 28, 2005 page 83 of 1422
REJ09B0234-0500
Rev. 5.00 Mar 28, 2005 page 84 of 1422
REJ09B0234-0500
6
op
op
abs
abs
abs
op
IMM
Immediate #xx:8/#xx:16/#xx:32
@aa:32
op
@aa:24
@aa:16
op
abs
Absolute address
5
@aa:8
Addressing Mode and Instruction Format
No.
Effective Address Calculation
24 23
24 23
24 23
24 23
87
16 15
Sign extension
H'FFFF
Operand is immediate data.
Don’t care
31
Don’t care
31
Don’t care
31
Don’t care
31
Effective Address (EA)
0
0
0
0
Section 2 CPU
abs
op
abs
• Advanced mode
op
• Normal mode*
Memory indirect @@aa:8
op
@(d:8, PC)/@(d:16, PC)
Program-counter relative
disp
Addressing Mode and Instruction Format
Note: * Not available in the H8S/2633 Group.
8
7
No.
31
31
31
87
abs
87
abs
Memory contents
15
Memory contents
H'000000
H'000000
disp
PC contents
Sign
extension
23
23
Effective Address Calculation
0
0
0
0
0
0
24 23
24 23
24 23
Don’t care
31
Don’t care
31
Don’t care
31
H'00
16 15
Effective Address (EA)
0
0
0
Section 2 CPU
Rev. 5.00 Mar 28, 2005 page 85 of 1422
REJ09B0234-0500
Section 2 CPU
2.8
Processing States
2.8.1
Overview
The CPU has five main processing states: the reset state, exception handling state, program
execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the
processing states. Figure 2.15 indicates the state transitions.
Reset state
The CPU and all on-chip supporting modules have been
initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal
processing flow in response to a reset, interrupt, or trap
instruction.
Processing
states
Program execution
state
The CPU executes program instructions in sequence.
Bus-released state
The external bus has been released in response to a bus
request signal from a bus master other than the CPU.
Sleep mode
Power-down state
CPU operation is stopped
to conserve power.*
Software standby
mode
Hardware standby
mode
Note: * The power-down state also includes a medium-speed mode, module stop mode,
subactive mode, subsleep mode, and watch mode. (In the H8S/2695, the subactive mode,
subsleep mode, and watch mode are not available.)
Figure 2.14 Processing States
Rev. 5.00 Mar 28, 2005 page 86 of 1422
REJ09B0234-0500
Section 2 CPU
End of bus request
Bus request
Program execution state
SLEEP
instruction
with
SSBY = 0
ion
ha
nd
lin
g
s
bu
t
of est
es
d
En requ requ
s
Bu
Sleep mode
SLEEP
instruction
with
SSBY = 1
e
pt r
rru
Inte
st
que
En
d
o
ha f ex
nd ce
lin pti
g on
Re
qu
es
tf
or
ex
ce
pt
Bus-released state
Exception handling state
External interrupt request
Software standby mode
RES= High
MRES= High
STBY= High, RES= Low
Manual reset state*1
Power-on reset state*1
Reset state*1
Hardware standby mode*2
Power-down state*3
Notes: 1. From any state except hardware standby mode, a transition to the power-on reset state occurs whenever RES
goes low. From any state except hardware standby mode and power-on reset mode, a transition to the manual
reset state occurs whenever MRES goes low. A transition can also be made to the reset state when the
watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
3. Apart from these states, there are also the watch mode, subactive mode, and subsleep mode. (In the H8S/2695,
the watch mode, subactive mode, and subsleep mode are not available.) See section 24, Power-Down States.
Figure 2.15 State Transitions
2.8.2
Reset State
The CPU enters the reset state when the RES pin goes low, or when the MRES pin goes low while
manual resets are enabled by the MRESE bit. In the reset state, currently executing processing is
halted and all interrupts are disabled.
For details of MRESE bit setting, see section 3.2.2, System Control Register (SYSCR).
Reset exception handling starts when the RES or MRES pin* changes from low to high.
The reset state can also be entered in the event of watchdog timer overflow. For details see section
15, Watchdog Timer.
Note: * MRES pin in the case of a manual reset.
Rev. 5.00 Mar 28, 2005 page 87 of 1422
REJ09B0234-0500
Section 2 CPU
2.8.3
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
(1) Types of Exception Handling and Their Priority
Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7
indicates the types of exception handling and their priority. Trap instruction exception handling is
always accepted, in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2.7
Exception Handling Types and Priority
Priority
Type of Exception
Detection Timing
Start of Exception Handling
High
Reset
Synchronized with clock
Exception handling starts
immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.
Trace
End of instruction
execution or end of
exception-handling
sequence*1
When the trace (T) bit is set to
1, the trace starts at the end of
the current instruction or current
exception-handling sequence
Interrupt
End of instruction
execution or end of
exception-handling
sequence*2
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence
Trap instruction
When TRAPA instruction
is executed
Exception handling starts when
a trap (TRAPA) instruction is
executed*3
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not
executed at the end of the RTE instruction.
2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
3. Trap instruction exception handling is always accepted, in the program execution state.
Rev. 5.00 Mar 28, 2005 page 88 of 1422
REJ09B0234-0500
Section 2 CPU
(2) Reset Exception Handling
After the RES pin has gone low and the reset state has been entered, when RES pin goes high
again, reset exception handling starts. After the reset state has been entered by driving the MRES
pin low while manual resets are enabled by the MRESE bit, reset exception handling starts when
MRES pin is driven high again. The CPU enters the power-on reset state when the RES pin is low,
and enters the manual reset state when the MRES pin is low. When reset exception handling starts
the CPU fetches a start address (vector) from the exception vector table and starts program
execution from that address. All interrupts, including NMI, are disabled during reset exception
handling and after it ends.
(3) Traces
Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR
is set to 1. When trace mode is established, trace exception handling starts at the end of each
instruction.
At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode
is cleared. Interrupt masks are not affected.
The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to
return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction.
Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit.
(4) Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer
(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU
alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start
address (vector) from the exception vector table and program execution starts from that start
address.
Figure 2.16 shows the stack after exception handling ends.
Rev. 5.00 Mar 28, 2005 page 89 of 1422
REJ09B0234-0500
Section 2 CPU
Normal mode*2
EXR
Reserved*1
SP
SP
CCR
CCR*1
CCR
CCR*1
PC
(16 bits)
PC
(16 bits)
(a) Interrupt control mode 0
(b) Interrupt control mode 2
Advanced mode
SP
SP
EXR
Reserved*1
CCR
CCR
PC
(24 bits)
PC
(24 bits)
(c) Interrupt control mode 0
(d) Interrupt control mode 2
Notes: 1. Ignored when returning.
2. Not available in the H8S/2633 Group.
Figure 2.16 Stack Structure after Exception Handling (Examples)
2.8.4
Program Execution State
In this state the CPU executes program instructions in sequence.
Rev. 5.00 Mar 28, 2005 page 90 of 1422
REJ09B0234-0500
Section 2 CPU
2.8.5
Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts operations.
Bus masters other than the CPU are DMA controller (DMAC)* and data transfer controller
(DTC)*.
For further details, refer to section 7, Bus Controller.
Note: * DMAC and DTC functions are not available in the H8S/2695.
2.8.6
Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,
software standby mode, hardware standby mode, subsleep mode*1, and watch mode*1. There are
also three other power-down modes: medium-speed mode, module stop mode, and subactive
mode*1. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock.
Module stop mode permits halting of the operation of individual modules, other than the CPU.
Subactive mode*1, subsleep mode*1, and watch mode*1 are power-down states using subclock
input. For details, refer to section 24, Power-Down Modes.
(1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while
the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep
mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of
CPU registers are retained.
(2) Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is set
to 0, and the PSS bit in TCSR (WDT1)*2 is set to 0. In software standby mode, the CPU and
clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of
CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states.
(3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY
pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop.
The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip
RAM contents are retained.
Notes: 1. This function is not available in the H8S/2695.
2. WDT1 is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 91 of 1422
REJ09B0234-0500
Section 2 CPU
2.9
Basic Timing
2.9.1
Overview
The H8S/2600 CPU is driven by a system clock, denoted by the symbol φ. The period from one
rising edge of φ to the next is referred to as a "state." The memory cycle or bus cycle consists of
one, two, or three states. Different methods are used to access on-chip memory, on-chip
supporting modules, and the external address space.
2.9.2
On-Chip Memory (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows
the pin states.
Bus cycle
T1
φ
Internal address bus
Read
access
Address
Internal read signal
Internal data bus
Read data
Internal write signal
Write
access
Internal data bus
Write data
Figure 2.17 On-Chip Memory Access Cycle
Rev. 5.00 Mar 28, 2005 page 92 of 1422
REJ09B0234-0500
Section 2 CPU
Bus cycle
T1
φ
Address bus
Unchanged
AS
High
RD
High
HWR, LWR
High
Data bus
High-impedance state
Figure 2.18 Pin States during On-Chip Memory Access
2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the
access timing for the on-chip supporting modules. Figure 2.20 shows the pin states.
Rev. 5.00 Mar 28, 2005 page 93 of 1422
REJ09B0234-0500
Section 2 CPU
Bus cycle
T1
T2
φ
Internal address bus
Address
Internal read signal
Read
access
Read data
Internal data bus
Internal write signal
Write
access
Internal data bus
Write data
Figure 2.19 On-Chip Supporting Module Access Cycle
Bus cycle
T1
T2
φ
Address bus
Unchanged
AS
High
RD
High
HWR, LWR
High
Data bus
High-impedance state
Figure 2.20 Pin States during On-Chip Supporting Module Access
Rev. 5.00 Mar 28, 2005 page 94 of 1422
REJ09B0234-0500
Section 2 CPU
2.9.4
External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 7, Bus Controller.
2.10
Usage Note
2.10.1
TAS Instruction
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. If the TAS
instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or
ER5 is used.
2.10.2
STM/LDM Instruction
With the STM or LDM instruction, the ER7 register is used as the stack pointer, and thus cannot
be used as a register that allows save (STM) or restore (LDM) operation.
With a single STM or LDM instruction, two to four registers can be saved or restored. The
available registers are as follows:
For two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5
For three registers: ER0 to ER2, or ER4 to ER6
For four registers: ER0 to ER3
For the Renesas H8S or H8/300 Series C/C++ Compiler, the STM/LDM instruction including ER7
is not created.
2.10.3
Usage Notes on Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate
the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore,
special care is necessary to use these instructions for the registers and the ports that include writeonly bit.
The BCLR instruction can be used to clear to 0 the flags in the internal I/O registers. In this time,
if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the
flag beforehand.
Rev. 5.00 Mar 28, 2005 page 95 of 1422
REJ09B0234-0500
Section 2 CPU
Rev. 5.00 Mar 28, 2005 page 96 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Overview
3.1.1
Operating Mode Selection
The H8S/2633 Group has four operating modes (modes 4 to 7). These modes enable selection of
the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by
setting the mode pins (MD2 to MD0).
Table 3.1 lists the MCU operating modes.
Table 3.1
MCU Operating Mode Selection
External Data Bus
MCU
CPU
Operating
Operating
Mode
MD2 MD1 MD0 Mode
Description
0*
1*
0
1
7
—
—
—
—
0
1
1
0
5
6
0
Max.
Width
1
2*
3*
4
0
On-Chip Initial
ROM
Width
0
1
1
Advanced On-chip ROM disabled, Disabled 16 bits
expanded mode
8 bits
0
On-chip ROM enabled, Enabled 8 bits
expanded mode
1
Single-chip mode
16 bits
16 bits
16 bits
—
Note: * Not available in the H8S/2633 Group.
The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2633 Group actually
accesses a maximum of 16 Mbytes.
Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral
devices.
The external expansion modes allow switching between 8-bit and 16-bit bus modes. After
program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on
the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8bit access is selected for all areas, 8-bit bus mode is set.
Rev. 5.00 Mar 28, 2005 page 97 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
Note that the functions of each pin depend on the operating mode.
The H8S/2633 Group can be used only in modes 4 to 7. This means that the mode pins must be set
to select one of these modes. Do not change the inputs at the mode pins during operation.
3.1.2
Register Configuration
The H8S/2633 Group has a mode control register (MDCR) that indicates the inputs at the mode
pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the
H8S/2633 Group. Table 3.2 summarizes these registers.
Table 3.2
MCU Registers
Name
Abbreviation
R/W
Initial Value
Address*
Mode control register
MDCR
R/W
Undetermined
H'FDE7
System control register
SYSCR
R/W
H'01
H'FDE5
Pin function control register
PFCR
R/W
H'0D/H'00
H'FDEB
Note: * Lower 16 bits of the address.
3.2
Register Descriptions
3.2.1
Mode Control Register (MDCR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
—
—
—
—
—
MDS2
MDS1
MDS0
1
0
0
0
0
—*
—*
—*
R/W
—
—
—
—
R
R
R
Note: * Determined by pins MD2 to MD0.
MDCR is an 8-bit register that indicates the current operating mode of the H8S/2633 Group.
Bit 7—Reserved: Only 1 should be written to this bit.
Bits 6 to 3—Reserved: These bits always read as 0 and cannot be modified.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0.
MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input
Rev. 5.00 Mar 28, 2005 page 98 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
levels are latched into these bits when MDCR is read. These latches are cancelled by a power-on
reset, but maintained by a manual reset.
3.2.2
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
MACS
—
INTM1
INTM0
NMIEG
MRESE
—
RAME
0
0
0
0
0
0
0
1
R/W
—
R/W
R/W
R/W
R/W
—
R/W
:
Initial value :
R/W
:
SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation
for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI,
pin input, and enables or disables on-chip RAM.
enables or disables
MRES
SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. MACS, INTM1,
INTM0, NMIEG, and RAME bits are initialized in manual reset mode, but the MRESE bit is not
initialized. SYSCR is not initialized in software standby mode.
Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the
MAC instruction.
Bit 7
MACS
Description
0
Non-saturating calculation for MAC instruction
1
Saturating calculation for MAC instruction
(Initial value)
Bit 6—Reserved: This bit always read as 0 and cannot be modified.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5
Bit 4
INTM1
INTM0
Interrupt
Control Mode
Description
0
0
0
Control of interrupts by I bit
1
—
Setting prohibited
0
2
Control of interrupts by I2 to I0 bits and IPR
1
—
Setting prohibited
1
(Initial value)
Rev. 5.00 Mar 28, 2005 page 99 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
Description
0
An interrupt is requested at the falling edge of NMI input
1
An interrupt is requested at the rising edge of NMI input
(Initial value)
Bit 2—Manual Reset Selection Bit (MRESE): Enables or disables manual reset input. It is
pin to the manual reset input (
).
possible to set the P74/TM02/
MRES
MRES
Table 3.3 shows the relationship between the
MRES pin power-on reset and manual reset.
Bit 2
MRESE
Description
0
Disables manual reset.
Possible to use P74/TM02*/
1
Enables manual reset.
Possible to use P74/TM02*/
MRES pin as P74/TM02* input pin.
(Initial value)
MRES pin as MRES input pin.
Note: * This function is not available in the H8S/2695.
Table 3.3
Relationship Between Power-On Reset and Manual Reset
Pin
RES
MRES
Reset Type
0
*
Power-on reset
1
0
Manual reset
1
1
Operation state
(Initial state)
*: Don’t care
Bit 1—Reserved: This bit always read as 0 and cannot be modified.
Rev. 5.00 Mar 28, 2005 page 100 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
(Initial value)
Note: When the DTC* is used, the RAME bit must be set to 1.
* The DTC function is not available in the H8S/2695.
3.2.3
Bit
Pin Function Control Register (PFCR)
7
6
5
4
3
2
1
0
CSS07
CSS36
BUZZE
LCASS
AE3
AE2
AE1
AE0
0
0
0
0
1/0
1/0
0
1/0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
Initial value :
R/W
:
PFCR is an 8-bit readable-writable register that carries out CS selection control for PG4 and PG1
pins, LCAS selection control for PF2 and PF6 pins, and address output control during extension
modes with ROM.
PFCR is initialized by H'0D/H'00 by a power-on reset or a hardware standby mode. The
immediately previous state is maintained in manual reset or software standby mode.
Bit 7—CS0/CS7 Select (CSS07): Selects the CS output content for PG4 pin. In modes 4 to 6, the
selected CS is output by setting the corresponding DDR to 1.
Bit 7
CSS07
Description
0
Select
1
Select
CS0
CS7
(Initial value)
Rev. 5.00 Mar 28, 2005 page 101 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
Bit 6—CS3/CS6 Select (CSS36): Selects the CS output content for PG1 pin. In modes 4 to 6, the
selected CS is output by setting the corresponding DDR to 1.
Bit 6
CSS36
Description
0
Select
1
CS3
Select CS6
(Initial value)
Bit 5—BUZZ Output Enable (BUZZE)*: Disables/enables BUZZ output of PF1 pin. Input
clock of WDT1 selected by PSS, CKS2 to CKS0 bits is output as a BUZZ signal.
Bit 5
BUZZE
Description
0
Functions as PF1 input pin
1
Functions as BUZZ output pin
(Initial value)
Note: * This function is not available in the H8S/2695. This bit should not be set to 1.
Bit 4—LCAS Output Pin Selection Bit (LCASS)*: Selects the LCAS signal output pin.
Bit 4
LCASS
Description
0
Outputs LCAS signal from PF2
1
Outputs LCAS signal from PF6
(Initial value)
Note: * This function is not available in the H8S/2695. This bit should not be set to 1.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling
of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is
enabled for address output, the address is output regardless of the corresponding DDR setting.
When a pin is disabled for address output, it becomes an output port when the corresponding DDR
bit is set to 1.
Rev. 5.00 Mar 28, 2005 page 102 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
Bit 3
Bit 2
Bit 1
Bit 0
AE3
AE2
AE1
AE0
Description
0
0
0
0
A8–A23 address output disabled
1
A8 address output enabled; A9–A23 address output disabled
0
A8, A9 address output enabled; A10–A23 address output
disabled
1
A8–A10 address output enabled; A11–A23 address output
disabled
0
A8–A11 address output enabled; A12–A23 address output
disabled
1
A8–A12 address output enabled; A13–A23 address output
disabled
0
A8–A13 address output enabled; A14–A23 address output
disabled
1
A8–A14 address output enabled; A15–A23 address output
disabled
0
A8–A15 address output enabled; A16–A23 address output
disabled
1
A8–A16 address output enabled; A17–A23 address output
disabled
0
A8–A17 address output enabled; A18–A23 address output
disabled
1
A8–A18 address output enabled; A19–A23 address output
disabled
0
A8–A19 address output enabled; A20–A23 address output
disabled
1
A8–A20 address output enabled; A21–A23 address output
disabled
(Initial value*)
0
A8–A21 address output enabled; A22, A23 address output
disabled
1
A8–A23 address output enabled
1
1
0
1
1
0
0
1
1
0
1
(Initial value*)
Note: * In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.
In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to
1.
Rev. 5.00 Mar 28, 2005 page 103 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
3.3
Operating Mode Descriptions
3.3.1
Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of
port F carries bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3.3.2
Mode 5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of
port F carries bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and
port E becomes a data bus.
3.3.3
Mode 6
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
Ports 1, A, B, and C, function as input port pins immediately after a reset. Address output can be
performed by setting the corresponding DDR (data direction register) bits to 1.
Port D function as a data bus, and part of port F carries data bus signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and
port E becomes a data bus.
Rev. 5.00 Mar 28, 2005 page 104 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
3.3.4
Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
but external addresses cannot be accessed.
All I/O ports are available for use as input-output ports.
3.4
Pin Functions in Each Operating Mode
The pin functions of ports A to G vary depending on the operating mode. Table 3.4 shows their
functions in each operating mode.
Table 3.4
Pin Functions in Each Mode
Port
Port 1
P10
P11 to P13
Port A
PA4 to PA0
Port B
Mode 4
Mode 5
Mode 6
Mode 7
P/A*
P*/A
P/A*
P*/A
P*/A
P*/A
P
P/A*
P/A*
P/A*
P/A*
P*/A
P*/A
P
P
P
P
P
Port C
A
A
P*/A
Port D
D
Port E
D
P*/D
PF7
P/D*
P/C*
D
P*/D
P/C*
P/C*
PF6 to PF4
C
PF3
P/C*
P*/C
C
P*/C
C
P*/C
P*/C
P*/C
P*/C
P
P*/C
P
Port F
PF2 to PF0
Port G
PG4
PG3 to PG0
C
P*/C
C
P*/C
P
P*/C
P
Legend:
P: I/O port
A: Address bus output
D: Data bus I/O
C: Control signals, clock I/O
*: After reset
Rev. 5.00 Mar 28, 2005 page 105 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
3.5
Address Map in Each Operating Mode
An address map of the H8S/2633, H8S/2633R are shown in figure 3.1, and an address map of the
H8S/2632 in figure 3.2, and an address map of the H8S/2631 in figure 3.3, and an address map of
the H8S/2695 in figure 3.4.
The address space is 16 Mbytes in modes 4 to 7 (advanced modes).
The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus
Controller.
Rev. 5.00 Mar 28, 2005 page 106 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
H'000000
Mode 6
(advanced expanded mode
with on-chip ROM enabled)
H'000000
Mode 7
(advanced single-chip mode)
H'000000
On-chip ROM
External address
space
On-chip ROM
H'03FFFF
H'040000
H'FFB000
External address
space
H'FFB000
On-chip RAM*1
H'FFB000
On-chip RAM*1
On-chip RAM
H'FFEFBF
H'FFEFC0
External address space
H'FFF800
H'FFEFC0
Internal I/O registers*2
H'FFFF40
H'FFFF60
H'FFFFC0
H'FFFFFF
External address space
H'FFF800
External address space
Internal I/O registers
On-chip RAM*1
H'FFF800
Internal I/O registers*2
H'FFFF40
H'FFFF60
H'FFFFC0
H'FFFFFF
Internal I/O registers*2
H'FFFF3F
External address space
Internal I/O registers
On-chip RAM*1
H'FFFF60 Internal I/O registers
H'FFFFC0
H'FFFFFF
On-chip RAM
Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
2. Area H'FFF800 to H'FFFDAB is reserved, and must not be accessed.
Figure 3.1 Memory Map in Each Operating Mode in the H8S/2633, H8S/2633R
Rev. 5.00 Mar 28, 2005 page 107 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
H'000000
Mode 6
(advanced expanded mode
with on-chip ROM enabled)
Mode 7
(advanced single-chip mode)
H'000000
H'000000
On-chip ROM
On-chip ROM
External address
space
H'02FFFF
H'030000
Reserved area
H'FFB000
H'FFC000
Reserved area
H'040000
External address
space
H'FFB000
H'FFC000
Reserved area
On-chip RAM*1
H'FFC000
On-chip RAM
On-chip RAM*1
H'FFEFBF
H'FFEFC0
External address space
H'FFF800
H'FFEFC0
Internal I/O registers*2
H'FFFF40
H'FFFF60
H'FFFFC0
H'FFFFFF
External address space
H'FFF800
External address space
Internal I/O registers
On-chip RAM*1
H'FFF800
Internal I/O registers*2
H'FFFF40
Internal I/O registers*2
H'FFFF3F
External address space
H'FFFF60 Internal I/O registers
H'FFFF60 Internal I/O registers
H'FFFFC0
H'FFFFFF
H'FFFFC0
H'FFFFFF
On-chip RAM*1
On-chip RAM
Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
2. Area H'FFF800 to H'FFFDAB is reserved, and must not be accessed.
Figure 3.2 Memory Map in Each Operating Mode in the H8S/2632
Rev. 5.00 Mar 28, 2005 page 108 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
H'000000
Mode 6
(advanced expanded mode
with on-chip ROM enabled)
Mode 7
(advanced single-chip mode)
H'000000
H'000000
On-chip ROM
On-chip ROM
H'01FFFF
H'020000
External address
space
Reserved area
H'FFB000
H'FFD000
Reserved area
H'040000
External address
space
H'FFB000
H'FFD000
Reserved area
On-chip RAM*1
H'FFD000
On-chip RAM
On-chip RAM*1
H'FFEFBF
H'FFEFC0
External address space
H'FFF800
H'FFEFC0
Internal I/O registers*2
H'FFFF40
H'FFFF60
H'FFFFC0
H'FFFFFF
External address space
H'FFF800
External address space
Internal I/O registers
On-chip RAM*1
H'FFF800
Internal I/O registers*2
H'FFFF40
Internal I/O registers*2
H'FFFF3F
External address space
H'FFFF60 Internal I/O registers
H'FFFF60 Internal I/O registers
H'FFFFC0
H'FFFFFF
H'FFFFC0
H'FFFFFF
On-chip RAM*1
On-chip RAM
Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
2. Area H'FFF800 to H'FFFDAB is reserved, and must not be accessed.
Figure 3.3 Memory Map in Each Operating Mode in the H8S/2631
Rev. 5.00 Mar 28, 2005 page 109 of 1422
REJ09B0234-0500
Section 3 MCU Operating Modes
Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
H'000000
Mode 6
(advanced expanded mode
with on-chip ROM enabled)
Mode 7
(advanced single-chip mode)
H'000000
H'000000
On-chip ROM
On-chip ROM
External address
space
H'02FFFF
H'030000
Reserved area
H'FFB000
H'FFD000
Reserved area
H'040000
External address
space
H'FFB000
H'FFD000
Reserved area
On-chip RAM*1
H'FFD000
On-chip RAM
On-chip RAM*1
H'FFEFBF
H'FFEFC0
External address space
H'FFF800
H'FFEFC0
Internal I/O registers*2
H'FFFF40
H'FFFF60
H'FFFFC0
H'FFFFFF
External address space
H'FFF800
External address space
Internal I/O registers
On-chip RAM*1
H'FFF800
Internal I/O registers*2
H'FFFF40
Internal I/O registers*2
H'FFFF3F
External address space
H'FFFF60 Internal I/O registers
H'FFFF60 Internal I/O registers
H'FFFFC0
H'FFFFFF
H'FFFFC0
H'FFFFFF
On-chip RAM*1
On-chip RAM
Notes: 1. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
2. Area H'FFF800 to H'FFFDAB is reserved, and must not be accessed.
Figure 3.4 Memory Map in Each Operating Mode in the H8S/2695
Rev. 5.00 Mar 28, 2005 page 110 of 1422
REJ09B0234-0500
Section 4 Exception Handling
Section 4 Exception Handling
4.1
Overview
4.1.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, direct transition, trap
instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more
exceptions occur simultaneously, they are accepted and processed in order of priority. Trap
instruction exceptions are accepted at all times, in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4.1
Exception Types and Priority
Priority
Exception Type
High
Reset
Low
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin or MRES pin, or when the watchdog overflows. The
CPU enters the power-on reset state when the RES pin is
low, and the manual reset state when the MRES pin is low
Trace*1
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Direct transition
Starts when a direct transition occurs due to execution of a
SLEEP instruction
Interrupt
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued*2
Trap instruction (TRAPA)*3 Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in program
execution state.
Rev. 5.00 Mar 28, 2005 page 111 of 1422
REJ09B0234-0500
Section 4 Exception Handling
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:
1. The program counter (PC), condition code register (CCR), and extended register (EXR) are
pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
4.1.3
Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vector addresses are
assigned to different exception sources.
Table 4.2 lists the exception sources and their vector addresses.
Power-on reset
Reset
Manual reset
Trace
Exception
sources
External interrupts: NMI, IRQ7 to IRQ0
Interrupts
Internal interrupts: 72 interrupt sources in
on-chip supporting modules
Trap instruction
Figure 4.1 Exception Sources
Rev. 5.00 Mar 28, 2005 page 112 of 1422
REJ09B0234-0500
Section 4 Exception Handling
Table 4.2
Exception Vector Table
Vector Address*1
Exception Source
Vector Number
Advanced Mode
Power-on reset
Manual reset*3
0
H'0000 to H'0003
1
H'0004 to H'0007
Reserved for system use
2
H'0008 to H'000B
3
H'000C to H'000F
4
H'0010 to H'0013
Trace
5
H'0014 to H'0017
Direct transition*3
6
H'0018 to H'001B
7
H'001C to H'001F
8
H'0020 to H'0023
9
H'0024 to H'0027
10
H'0028 to H'002B
11
H'002C to H'002F
12
H'0030 to H'0033
13
H'0034 to H'0037
14
H'0038 to H'003B
15
H'003C to H'003F
IRQ0
16
H'0040 to H'0043
IRQ1
17
H'0044 to H'0047
IRQ2
18
H'0048 to H'004B
IRQ3
19
H'004C to H'004F
IRQ4
20
H'0050 to H'0053
IRQ5
21
H'0054 to H'0057
IRQ6
22
H'0058 to H'005B
IRQ7
23
H'005C to H'005F
24
H'0060 to H'0063
External interrupt
NMI
Trap instruction (4 sources)
Reserved for system use
External interrupt
Internal interrupt*2


127
H'01FC to H'01FF
Notes: 1. Lower 16 bits of the address.
2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling
Vector Table.
3. See section 24.11, Direct Transitions, for details on direct transitions.
This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 113 of 1422
REJ09B0234-0500
Section 4 Exception Handling
4.2
Reset
4.2.1
Overview
A reset has the highest exception handling priority. There are two kinds of reset: a power-on reset
executed via the RES pin, and a manual reset executed via the MRES pin.
When the RES or MRES pin* goes low, currently executing processing is halted and the chip
enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip
supporting modules. Immediately after a reset, interrupt control mode 0 is set.
Reset exception handling starts when the RES or MRES pin* changes from low to high.
The reset state can also be entered in the event of watchdog timer overflow. For details see
section 15, Watchdog Timer.
Note: * MRES pin in the case of a manual reset.
4.2.2
Types of Reset
There are two types of reset: power-on reset and manual reset.
Table 4.3 shows the types of reset. When turning power on, do so as a power-on reset.
Both power-on reset and manual reset initialize the internal state of the CPU. In a power-on reset,
all of the registers of the built-in vicinity modules are initialized, while in a manual reset, the
registers of the built-in vicinity models except for bus controllers and I/O ports are initialized. The
states of the bus controllers and I/O ports are maintained.
During a manual reset built-in vicinity modules are initialized, and ports used as input pins for
built-in vicinity modules switch to the input ports controlled by DDR and DR.
If using manual reset, set the MRESE bit to 1 beforehand, thereby enabling manual resets.
See section 3.2.2, System Control Register (SYSCR) for settings of the MRESE bit.
There are also power-on resets and manual resets as the two types of reset carried out by the
watchdog timer.
Rev. 5.00 Mar 28, 2005 page 114 of 1422
REJ09B0234-0500
Section 4 Exception Handling
Table 4.3
Types of Reset
Conditions for
Transition to Reset
Internal State
Type
MRES
RES
CPU
Built-in vicinity module
Power-on reset
*
Low
Initialization
Initialization
Manual reset
Low
High
Initialization
Initialization except for bus controller
and I/O port
*: Don't Care
4.2.3
Reset Sequence
This LSI enters reset state when the RES pin or MRES pin goes low.
To ensure that this LSI is reset, hold the RES pin or the MRES pin low for at least 20 ms at powerup. To reset during operation, hold the RES pin or the MRES pin low for at least 20 states.
When the RES pin or the MRES pin goes high after being held low for the necessary time, this
LSI starts reset exception handling as follows.
1. The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.2 and 4.3 show examples of the reset sequence.
Rev. 5.00 Mar 28, 2005 page 115 of 1422
REJ09B0234-0500
Section 4 Exception Handling
Vector
fetch
*
Internal
processing
Prefetch of first program
instruction
*
*
φ
RES, MRES
Address bus
(1)
(3)
(5)
RD
High
HWR, LWR
D15 to D0
(2)
(4)
(6)
(1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000*,
(3) = H'000002; when manual reset, (1)= H'000004, (3)= H'000006)
(2) (4) Start address (contents of reset exception handling vector address)
(5)
Start address ((5) = (2) (4))
(6)
First program instruction
Note: * 3 program wait states are inserted.
Figure 4.2 Reset Sequence (Modes 4 and 5)
Rev. 5.00 Mar 28, 2005 page 116 of 1422
REJ09B0234-0500
Section 4 Exception Handling
Prefetch of
Internal first program
processing instruction
Vector
fetch
φ
RES, MRES
Internal
address bus
(3)
(1)
(5)
Internal read
signal
High
Internal write
signal
Internal data
bus
(2)
(4)
(6)
(1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000,
(3) = H'000002)
(2) (4) Start address (contents of reset exception handling vector address)
(5)
Start address ((5) = (2) (4))
(6)
First program instruction
Figure 4.3 Reset Sequence (Modes 6 and 7)
4.2.4
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
Rev. 5.00 Mar 28, 2005 page 117 of 1422
REJ09B0234-0500
Section 4 Exception Handling
4.2.5
State of On-Chip Supporting Modules after Reset Release
After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively,
and all modules except the DMAC* and DTC*, enter module stop mode. Consequently, on-chip
supporting module registers cannot be read or written to. Register reading and writing is enabled
when module stop mode is exited.
Note: * DMAC and DTC functions are not available in the H8S/2695.
4.3
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction.
Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking.
Table 4.4 shows the state of CCR and EXR after execution of trace exception handling.
Interrupts are accepted even within the trace exception handling routine.
The T bit saved on the stack retains its value of 1, and when control is returned from the trace
exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Table 4.4
Status of CCR and EXR after Trace Exception Handling
Interrupt Control Mode
CCR
I
0
2
EXR
UI
I2 to I0
T
Trace exception handling cannot be used.
1
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution
Rev. 5.00 Mar 28, 2005 page 118 of 1422
REJ09B0234-0500
—
—
0
Section 4 Exception Handling
4.4
Interrupts
Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and
72 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources
and the number of interrupts of each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
16-bit timer-pulse unit (TPU), 8-bit timer*, serial communication interface (SCI), data transfer
controller (DTC)*, DMA controller (DMAC)*, PC break controller (PBC)*, A/D converter, and
I2C bus interface (IIC)*. Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The
interrupt controller has two interrupt control modes and can assign interrupts other than NMI to
eight priority/mask levels to enable multiplexed interrupt control.
For details of interrupts, see section 5, Interrupt Controller.
Note: * This function is not available in the H8S/2695.
External
interrupts
Interrupts
Internal
interrupts
Notes:
NMI (1)
IRQ7 to IRQ0 (8)
WDT*1 (2)
Refresh timer*2 *3 (1)
TPU (26)
8-bit timer*3 (12)
SCI (20)
DTC*3 (1)
DMAC*3 (4)
PBC*3 (1)
A/D converter (1)
IIC*3 (4) (Option)
Numbers in parentheses are the numbers of interrupt sources.
1. When the watchdog timer is used as an interval timer, it generates
an interrupt request at each counter overflow.
2. When refresh timer is used as an interval time, an interrupt request
is generated by compare match.
3. This function is not available in the H8S/2695.
Figure 4.4 Interrupt Sources and Number of Interrupts
Rev. 5.00 Mar 28, 2005 page 119 of 1422
REJ09B0234-0500
Section 4 Exception Handling
4.5
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.5
Status of CCR and EXR after Trap Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
I2 to I0
T
0
1
—
—
—
2
1
—
—
0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution
Rev. 5.00 Mar 28, 2005 page 120 of 1422
REJ09B0234-0500
Section 4 Exception Handling
4.6
Stack Status after Exception Handling
Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP
SP
CCR
CCR*
PC
(16 bits)
(a) Interrupt control mode 0
EXR
Reserved*
CCR
CCR*
PC
(16 bits)
(b) Interrupt control mode 2
Note: * Ignored on return.
Figure 4.5 (1) Stack Status after Exception Handling (Normal Modes: Not Available in the
H8S/2633 Group)
SP
SP
CCR
EXR
Reserved*
CCR
PC
(24 bits)
PC
(24 bits)
(a) Interrupt control mode 0
(b) Interrupt control mode 2
Note: * Ignored on return.
Figure 4.5 (2) Stack Status after Exception Handling (Advanced Modes)
Rev. 5.00 Mar 28, 2005 page 121 of 1422
REJ09B0234-0500
Section 4 Exception Handling
4.7
Notes on Use of the Stack
When accessing word data or longword data, the H8S/2633 Group assumes that the lowest address
bit is 0. The stack should always be accessed by word transfer instruction or longword transfer
instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the
following instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what
happens when the SP value is odd.
CCR
SP
R1L
SP
PC
PC
SP
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFF
TRAP instruction executed MOV.B R1L, @–ER7
SP set to H'FFFEFF
Data saved above SP
Contents of CCR lost
Legend:
CCR: Condition code register
PC: Program counter
R1L: General register R1L
SP: Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0,
in advanced mode.
Figure 4.6 Operation when SP Value is Odd
Rev. 5.00 Mar 28, 2005 page 122 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Overview
5.1.1
Features
The H8S/2633 Group controls interrupts by means of an interrupt controller. The interrupt
controller has the following features:
• Two interrupt control modes
 Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in
the system control register (SYSCR)
• Priorities settable with IPR
 An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI
 NMI is assigned the highest priority level of 8, and can be accepted at all times
• Independent vector addresses
 All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine
• Nine external interrupts
 NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
edge can be selected for NMI
 Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7
to IRQ0
• DTC* and DMAC* control
 DTC and DMAC activation is performed by means of interrupts
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 123 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.1.2
Block Diagram
A block diagram of the interrupt controller is shown in Figure 5.1.
CPU
INTM1, INTM0
SYSCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
ISCR
IER
Interrupt
request
Vector
number
Priority
determination
I
Internal interrupt
request
SWDTEND to
TEI4
I2 to I0
IPR
Interrupt controller
Legend:
ISCR:
IER:
ISR:
IPR:
SYSCR:
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register
System control register
Figure 5.1 Block Diagram of Interrupt Controller
Rev. 5.00 Mar 28, 2005 page 124 of 1422
REJ09B0234-0500
CCR
EXR
Section 5 Interrupt Controller
5.1.3
Pin Configuration
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1
Interrupt Controller Pins
Name
Symbol
I/O
Function
Nonmaskable interrupt
NMI
Input
Nonmaskable external interrupt; rising or
falling edge can be selected
External interrupt
requests 7 to 0
IRQ7
5.1.4
to IRQ0 Input
Maskable external interrupts; rising, falling, or
both edges, or level sensing, can be selected
Register Configuration
Table 5.2 summarizes the registers of the interrupt controller.
Table 5.2
Interrupt Controller Registers
Name
Abbreviation
R/W
Initial Value
Address*1
System control register
SYSCR
R/W
H'01
H'FDE5
IRQ sense control register H
ISCRH
R/W
H'00
H'FE12
IRQ sense control register L
ISCRL
R/W
H'00
H'FE13
IRQ enable register
IER
R/W
H'00
H'FE14
IRQ status register
ISR
R/(W)*2
H'00
H'FE15
Interrupt priority register A
IPRA
R/W
H'77
H'FEC0
Interrupt priority register B
IPRB
R/W
H'77
H'FEC1
Interrupt priority register C
IPRC
R/W
H'77
H'FEC2
Interrupt priority register D
IPRD
R/W
H'77
H'FEC3
Interrupt priority register E
IPRE
R/W
H'77
H'FEC4
Interrupt priority register F
IPRF
R/W
H'77
H'FEC5
Interrupt priority register G
IPRG
R/W
H'77
H'FEC6
Interrupt priority register H
IPRH
R/W
H'77
H'FEC7
Interrupt priority register I
IPRI
R/W
H'77
H'FEC8
Interrupt priority register J
IPRJ
R/W
H'77
H'FEC9
Interrupt priority register K
IPRK
R/W
H'77
H'FECA
Interrupt priority register L
IPRL
R/W
H'77
H'FECB
Interrupt priority register O
IPRO
R/W
H'77
H'FECE
Notes: 1. Lower 16 bits of the address.
2. Can only be written with 0 for flag clearing.
Rev. 5.00 Mar 28, 2005 page 125 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.2
Register Descriptions
5.2.1
System Control Register (SYSCR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
MACS
—
INTM1
INTM0
NMIEG
MRESE
—
RAME
0
0
0
0
0
0
0
1
R/W
—
R/W
R/W
R/W
R/W
—
R/W
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI.
Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control
Register (SYSCR).
SYSCR is initialized to H'01 by a power-on reset, manual reset, and in hardware standby mode.
SYSCR is not initialized in software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two
interrupt control modes for the interrupt controller.
Bit 5
Bit 4
INTM1
INTM0
Interrupt
Control Mode
Description
0
0
0
Interrupts are controlled by I bit
1
—
Setting prohibited
0
2
Interrupts are controlled by bits I2 to I0, and IPR
1
—
Setting prohibited
1
(Initial value)
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG
Description
0
Interrupt request generated at falling edge of NMI input
1
Interrupt request generated at rising edge of NMI input
Rev. 5.00 Mar 28, 2005 page 126 of 1422
REJ09B0234-0500
(Initial value)
Section 5 Interrupt Controller
5.2.2
Bit
Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO)
:
7
6
5
4
3
2
1
0
—
IPR6
IPR5
IPR4
—
IPR2
IPR1
IPR0
Initial value :
0
1
1
1
0
1
1
1
R/W
—
R/W
R/W
R/W
—
R/W
R/W
R/W
:
The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5.3.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified.
Table 5.3
Correspondence between Interrupt Sources and IPR Settings
Bits
Register
6 to 4
2 to 0
IPRA
IRQ0
IRQ1
IPRB
IRQ2
IRQ3
IPRC
IRQ6
IRQ7
IRQ4
IRQ5
DTC*
IPRD
IPRE
Watchdog timer 0
PC break*
A/D converter, watchdog timer 1*
IPRF
TPU channel 0
TPU channel 1
IPRG
TPU channel 2
TPU channel 3
IPRH
TPU channel 4
TPU channel 5
IPRI
8-bit timer channel 0*
8-bit timer channel 1*
IPRJ
DMAC*
SCI channel 0
IPRK
SCI channel 1
IPRL
8-bit timer 2, 3*
SCI channel 2
IIC (Option)*
IPRO
SCI channel 3
SCI channel 4
Refresh timer*
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 127 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range
from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding
interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority
level, level 7, by setting H'7.
When interrupt requests are generated, the highest-priority interrupt according to the priority
levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt
mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if
the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to
the CPU.
5.2.3
Bit
IRQ Enable Register (IER)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests
IRQ7 to IRQ0.
IER is initialized to H'00 by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to
IRQ0 are enabled or disabled.
Bit n
IRQnE
Description
0
IRQn interrupts disabled
1
IRQn interrupts enabled
(Initial value)
(n = 7 to 0)
Rev. 5.00 Mar 28, 2005 page 128 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.2.4
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCRH
Bit
15
:
14
13
12
11
10
9
8
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
0
0
0
0
0
0
0
0
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
7
6
5
4
3
2
1
0
Initial value :
R/W
ISCRL
Bit
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or
both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and
B (IRQ0SCA, IRQ0SCB)
Bits 15 to 0
IRQ7SCB to
IRQ0SCB
IRQ7SCA to
IRQ0SCA
0
0
Interrupt request generated at IRQ7 to IRQ0 input low level
(initial value)
1
Interrupt request generated at falling edge of IRQ7 to IRQ0 input
1
Description
0
Interrupt request generated at rising edge of IRQ7 to IRQ0 input
1
Interrupt request generated at both falling and rising edges of
IRQ7 to IRQ0 input
Rev. 5.00 Mar 28, 2005 page 129 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.2.5
Bit
IRQ Status Register (ISR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Note: * Only 0 can be written, to clear the flag.
ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
They are not initialized in software standby mode.
Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to
IRQ0 interrupt requests.
Bit n
IRQnF
Description
0
[Clearing conditions] (Initial value)
• Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
• When interrupt exception handling is executed when low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high
• When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
• When the DTC* is activated by an IRQn interrupt, and the DISEL bit in MRB of the
DTC* is cleared to 0
1
[Setting conditions]
• When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
0)
• When a falling edge occurs in IRQn input when falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input when rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input when both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
(n = 7 to 0)
Note: * The DTC function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 130 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.3
Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (72
sources).
5.3.1
External Interrupts
There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ7 to IRQ0 can
be used to restore the H8S/2633 Group from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.
IRQnE
IRQnSCA, IRQnSCB
IRQnF
Edge/level
detection circuit
IRQn interrupt
S
Q
request
R
IRQn input
Clear signal
Note: n: 7 to 0
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0
Rev. 5.00 Mar 28, 2005 page 131 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Figure 5.3 shows the timing of setting IRQnF.
φ
IRQn
input pin
IRQnF
Figure 5.3 Timing of Setting IRQnF
The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
5.3.2
Internal Interrupts
There are 72*1 sources for internal interrupts from on-chip supporting modules.
• For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular interrupt source, an interrupt request is issued to the interrupt controller.
• The interrupt priority level can be set by means of IPR.
• The DMAC*2 and DTC*2 can be activated by a TPU, 8-bit timer*2, SCI, or other interrupt
request. When the DMAC*2 and DTC*2 are activated by an interrupt, the interrupt control
mode and interrupt mask bits are not affected.
Notes: 1. The H8S/2695 has 54 sources for internal interrupts from on-chip supporting modules.
2. This function is not available in the H8S/2695.
5.3.3
Interrupt Exception Handling Vector Table
Tables 5.4(a) and 5.4(b) show interrupt exception handling sources, vector addresses, and interrupt
priorities. For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of the IPR. The situation when two or more
modules are set to the same priority, and priorities within a module, are fixed as shown in
table 5.4.
Rev. 5.00 Mar 28, 2005 page 132 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Table 5.4 (a) Interrupt Sources, Vector Addresses, and Interrupt Priorities
(H8S/2633, H8S/2633F, H8S/2632, H8S/2631, H8S/2633R)
Interrupt Source
NMI
IRQ0
Origin of
Interrupt
Source
External
pin
Vector
Address*
Vector
Number
Advanced
Mode
7
H'001C
IPR
High
16
H'0040
IPRA6 to 4
IRQ1
17
H'0044
IPRA2 to 0
IRQ2
IRQ3
18
19
H'0048
H'004C
IPRB6 to 4
IRQ4
IRQ5
20
21
H'0050
H'0054
IPRB2 to 0
IRQ6
IRQ7
22
23
H'0058
H'005C
IPRC6 to 4
SWDTEND (software activation
interrupt end)
DTC
24
H'0060
IPRC2 to 0
WOVI0 (interval timer)
Watchdog
timer 0
25
H'0064
IPRD6 to 4
Reserved
—
26
H'0068
IPRD2 to 0
PC break
PC break
27
H'006C
IPRE6 to 4
ADI (A/D conversion end)
A/D
28
H'0070
IPRE2 to 0
WOVI1 (interval timer)
Watchdog
timer 1
29
H'0074
Reserved
—
30
31
H'0078
H'007C
TGI0A (TGR0A input
capture/compare match)
TPU
channel 0
32
H'0080
TGI0B (TGR0B input
capture/compare match)
33
H'0084
TGI0C (TGR0C input
capture/compare match)
34
H'0088
TGI0D (TGR0D input
capture/compare match)
35
H'008C
36
H'0090
37
38
39
H'0094
H'0098
H'009C
TCI0V (overflow 0)
Reserved
—
Priority
IPRF6 to 4
Low
Rev. 5.00 Mar 28, 2005 page 133 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Interrupt Source
Origin of
Interrupt
Source
TGI1A (TGR1A input
capture/compare match)
TPU
channel 1
Vector
Address*
Vector
Number
Advanced
Mode
IPR
Priority
40
H'00A0
IPRF2 to 0
High
TGI1B (TGR1B input
capture/compare match)
41
H'00A4
TCI1V (overflow 1)
42
H'00A8
TCI1U (underflow 1)
43
H'00AC
44
H'00B0
TGI2B (TGR2B input
capture/compare match)
45
H'00B4
TCI2V (overflow 2)
46
H'00B8
47
H'00BC
48
H'00C0
TGI3B (TGR3B input
capture/compare match)
49
H'00C4
TGI3C (TGR3C input
capture/compare match)
50
H'00C8
TGI3D (TGR3D input
capture/compare match)
51
H'00CC
TCI3V (overflow 3)
52
H'00D0
TGI2A (TGR2A input
capture/compare match)
TPU
channel 2
TCI2U (underflow 2)
TGI3A (TGR3A input
capture/compare match)
TPU
channel 3
Reserved
—
53
54
55
H'00D4
H'00D8
H'00DC
TGI4A (TGR4A input
capture/compare match)
TPU
channel 4
56
H'00E0
TGI4B (TGR4B input
capture/compare match)
57
H'00E4
TCI4V (overflow 4)
58
H'00E8
TCI4U (underflow 4)
59
H'00EC
Rev. 5.00 Mar 28, 2005 page 134 of 1422
REJ09B0234-0500
IPRG6 to 4
IPRG2 to 0
IPRH6 to 4
Low
Section 5 Interrupt Controller
Interrupt Source
Origin of
Interrupt
Source
TGI5A (TGR5A input
capture/compare match)
TPU
channel 5
Vector
Address*
Vector
Number
Advanced
Mode
IPR
Priority
60
H'00F0
IPRH2 to 0
High
TGI5B (TGR5B input
capture/compare match)
61
H'00F4
TCI5V (overflow 5)
62
H'00F8
TCI5U (underflow 5)
63
H'00FC
64
H'0100
65
H'0104
66
H'0108
CMIA0 (compare match A0)
CMIB0 (compare match B0)
8-bit timer
channel 0
OVI0 (overflow 0)
Reserved
—
67
H'010C
CMIA1 (compare match A1)
8-bit timer
channel 1
68
H'0110
69
H'0114
70
H'0118
71
72
H'011C
H'0120
DEND0B (channel 0B transfer end)
73
H'0124
DEND1A (channel 1/channel 1A
transfer end)
74
H'0128
DEND1B (channel 1B transfer end)
75
H'012C
CMIB1 (compare match B1)
OVI1 (overflow 1)
Reserved
DED0A (channel 0/channel 0A
transfer end)
—
DMAC
Reserved
—
76
77
78
79
H'0130
H'0134
H'0138
H'013C
ERI0 (receive error 0)
SCI
channel 0
80
H'0140
81
H'0144
TXI0 (transmit data empty 0)
82
H'0148
TEI0 (transmission end 0)
83
H'014C
84
H'0150
85
H'0154
TXI1 (transmit data empty 1)
86
H'0158
TEI1 (transmission end 1)
87
H'015C
RXI0 (reception completed 0)
ERI1 (receive error 1)
RXI1 (reception completed 1)
SCI
channel 1
IPRI6 to 4
IPRI2 to 0
IPRJ6 to 4
IPRJ2 to 0
IPRK6 to 4
Low
Rev. 5.00 Mar 28, 2005 page 135 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Interrupt Source
ERI2 (receive error 2)
RXI2 (reception completed 2)
Origin of
Interrupt
Source
SCI
channel 2
Vector
Address*
Vector
Number
Advanced
Mode
IPR
Priority
88
H'0160
IPRK2 to 0
High
89
H'0164
TXI2 (transmit data empty 2)
90
H'0168
TEI2 (transmission end 2)
91
H'016C
92
H'0170
93
H'0174
94
H'0178
CMIA0 (compare match A2)
CMIB0 (compare match B2)
8 bit timer
channel 2
OVI0 (overflow 2)
Reserved
—
95
H'017C
CMIA1 (compare match A3)
8 bit timer
channel 3
96
H'0180
97
H'0184
98
H'0188
CMIB1 (compare match B3)
OVI1 (overflow 3)
Reserved
—
IICI0 (1 byte
transmission/reception completed)
IIC channel 100
0 (optional)
H'0190
101
H'0194
IIC channel 102
1 (optional)
H'0198
103
H'019C
DDCSW1 (format switch)
IICI1 (1 byte
transmission/reception completed)
Reserved
99
IPRL6 to 4
H'018C
IPRL2 to 0
Reserved
—
104
105
106
107
H'01A0
H'01A4
H'01A8
H'01AC
IPRM6 to 4
Reserved
—
108
109
110
111
H'01B0
H'01B4
H'01B8
H'01BC
IPRM2 to 0
Reserved
—
112
113
114
115
H'01C0
H'01C4
H'01C8
H'01CC
IPRN6 to 4
Reserved
—
116
117
118
119
H'01D0
H'01D4
H'01D8
H'01DC
IPRN2 to 0
Rev. 5.00 Mar 28, 2005 page 136 of 1422
REJ09B0234-0500
Low
Section 5 Interrupt Controller
Origin of
Interrupt
Source
Vector
Address*
Vector
Number
Advanced
Mode
IPR
Priority
120
H'01E0
IPRO6 to 4
High
121
H'01E4
TXI3 (transmission data empty 3)
122
H'01E8
TEI3 (transmission end 3)
123
H'01EC
124
H'01F0
125
H'01F4
TXI4 (transmission data empty 4)
126
H'01F8
TEI4 (transmission end 4)
127
H'01FC
Interrupt Source
ERI3 (reception error 3)
RXI3 (reception completed 3)
ERI4 (reception error 4)
RXI4 (reception completed 4)
SCI
channel 3
SCI
channel 4
IPRO2 to 0
Low
Note: * Lower 16 bits of the start address.
Rev. 5.00 Mar 28, 2005 page 137 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Table 5.4 (b) Interrupt Sources, Vector Addresses, and Interrupt Priorities (H8S/2695)
Interrupt Source
NMI
Origin of
Interrupt
Source
Vector
Number
Advanced
Mode
IPR
7
H'001C
16
H'0040
IPRA6 to 4
IRQ1
17
H'0044
IPRA2 to 0
IRQ2
IRQ3
18
19
H'0048
H'004C
IPRB6 to 4
IRQ4
IRQ5
20
21
H'0050
H'0054
IPRB2 to 0
IRQ6
IRQ7
22
23
H'0058
H'005C
IPRC6 to 4
IRQ0
External
pin
Vector
Address*
High
Reserved
—
24
H'0060
IPRC2 to 0
WOVI0 (interval timer)
Watchdog
timer 0
25
H'0064
IPRD6 to 4
Reserved
—
26
H'0068
IPRD2 to 0
27
H'006C
IPRE6 to 4
IPRE2 to 0
ADI (A/D conversion end)
A/D
28
H'0070
Reserved
—
29
30
31
H'0074
H'0078
H'007C
TGI0A (TGR0A input
capture/compare match)
TPU
channel 0
32
H'0080
TGI0B (TGR0B input
capture/compare match)
33
H'0084
TGI0C (TGR0C input
capture/compare match)
34
H'0088
TGI0D (TGR0D input
capture/compare match)
35
H'008C
TCI0V (overflow 0)
36
H'0090
37
38
39
H'0094
H'0098
H'009C
Reserved
—
Rev. 5.00 Mar 28, 2005 page 138 of 1422
REJ09B0234-0500
Priority
IPRF6 to 4
Low
Section 5 Interrupt Controller
Interrupt Source
Origin of
Interrupt
Source
TGI1A (TGR1A input
capture/compare match)
TPU
channel 1
Vector
Address*
Vector
Number
Advanced
Mode
IPR
Priority
40
H'00A0
IPRF2 to 0
High
TGI1B (TGR1B input
capture/compare match)
41
H'00A4
TCI1V (overflow 1)
42
H'00A8
TCI1U (underflow 1)
43
H'00AC
44
H'00B0
TGI2B (TGR2B input
capture/compare match)
45
H'00B4
TCI2V (overflow 2)
46
H'00B8
47
H'00BC
48
H'00C0
TGI3B (TGR3B input
capture/compare match)
49
H'00C4
TGI3C (TGR3C input
capture/compare match)
50
H'00C8
TGI3D (TGR3D input
capture/compare match)
51
H'00CC
TCI3V (overflow 3)
52
H'00D0
TGI2A (TGR2A input
capture/compare match)
TPU
channel 2
TCI2U (underflow 2)
TGI3A (TGR3A input
capture/compare match)
TPU
channel 3
Reserved
—
53
54
55
H'00D4
H'00D8
H'00DC
TGI4A (TGR4A input
capture/compare match)
TPU
channel 4
56
H'00E0
TGI4B (TGR4B input
capture/compare match)
57
H'00E4
TCI4V (overflow 4)
58
H'00E8
TCI4U (underflow 4)
59
H'00EC
IPRG6 to 4
IPRG2 to 0
IPRH6 to 4
Low
Rev. 5.00 Mar 28, 2005 page 139 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Interrupt Source
Origin of
Interrupt
Source
TGI5A (TGR5A input
capture/compare match)
TPU
channel 5
Vector
Address*
Vector
Number
Advanced
Mode
IPR
Priority
60
H'00F0
IPRH2 to 0
High
TGI5B (TGR5B input
capture/compare match)
61
H'00F4
TCI5V (overflow 5)
62
H'00F8
TCI5U (underflow 5)
63
H'00FC
Reserved
—
64
65
66
67
H'0100
H'0104
H'0108
H'010C
IPRI6 to 4
Reserved
—
68
69
70
71
H'0110
H'0114
H'0118
H'011C
IPRI2 to 0
Reserved
—
72
73
74
75
76
77
78
79
H'0120
H'0124
H'0128
H'012C
H'0130
H'0134
H'0138
H'013C
IPRJ6 to 4
ERI0 (receive error 0)
SCI
channel 0
80
H'0140
IPRJ2 to 0
81
H'0144
TXI0 (transmit data empty 0)
82
H'0148
TEI0 (transmission end 0)
83
H'014C
84
H'0150
85
H'0154
TXI1 (transmit data empty 1)
86
H'0158
TEI1 (transmission end 1)
87
H'015C
88
H'0160
89
H'0164
TXI2 (transmit data empty 2)
90
H'0168
TEI2 (transmission end 2)
91
H'016C
RXI0 (reception completed 0)
ERI1 (receive error 1)
RXI1 (reception completed 1)
ERI2 (receive error 2)
RXI2 (reception completed 2)
SCI
channel 1
SCI
channel 2
Rev. 5.00 Mar 28, 2005 page 140 of 1422
REJ09B0234-0500
IPRK6 to 4
IPRK2 to 0
Low
Section 5 Interrupt Controller
Interrupt Source
Origin of
Interrupt
Source
Reserved
Vector
Address*
Vector
Number
Advanced
Mode
—
92
93
94
95
96
97
98
99
Reserved
—
Reserved
IPR
Priority
H'0170
H'0174
H'0178
H'017C
H'0180
H'0184
H'0188
H'018C
IPRL6 to 4
High
100
101
102
103
H'0190
H'0194
H'0198
H'019C
IPRL2 to 0
—
104
105
106
107
H'01A0
H'01A4
H'01A8
H'01AC
IPRM6 to 4
Reserved
—
108
109
110
111
H'01B0
H'01B4
H'01B8
H'01BC
IPRM2 to 0
Reserved
—
112
113
114
115
H'01C0
H'01C4
H'01C8
H'01CC
IPRN6 to 4
Reserved
—
116
117
118
119
H'01D0
H'01D4
H'01D8
H'01DC
IPRN2 to 0
ERI3 (reception error 3)
SCI
channel 3
120
H'01E0
IPRO6 to 4
121
H'01E4
TXI3 (transmission data empty 3)
122
H'01E8
TEI3 (transmission end 3)
123
H'01EC
124
H'01F0
125
H'01F4
TXI4 (transmission data empty 4)
126
H'01F8
TEI4 (transmission end 4)
127
H'01FC
RXI3 (reception completed 3)
ERI4 (reception error 4)
RXI4 (reception completed 4)
SCI
channel 4
IPRO2 to 0
Low
Note: * Lower 16 bits of the start address.
Rev. 5.00 Mar 28, 2005 page 141 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.4
Interrupt Operation
5.4.1
Interrupt Control Modes and Interrupt Operation
Interrupt operations in the H8S/2633 Group differ depending on the interrupt control mode.
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for
each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt
sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 5.5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated
by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR.
Table 5.5
Interrupt Control Modes
SYSCR
Interrupt
Priority Setting
Control Mode INTM1 INTM0 Registers
Interrupt
Mask Bits Description
0
0
—
2
—
1
0
—
I
Interrupt mask control is
performed by the I bit.
1
—
—
Setting prohibited
0
IPR
I2 to I0
8-level interrupt mask control
is performed by bits I2 to I0.
8 priority levels can be set with
IPR.
1
—
—
Setting prohibited
Rev. 5.00 Mar 28, 2005 page 142 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Figure 5.4 shows a block diagram of the priority decision circuit.
Interrupt
control
mode 0
I
Interrupt
acceptance
control
Default priority
determination
Interrupt source
Vector number
8-level
mask control
IPR
I2 to I0
Interrupt control mode 2
Figure 5.4 Block Diagram of Interrupt Control Operation
Rev. 5.00 Mar 28, 2005 page 143 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
(1) Interrupt Acceptance Control
In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.
Table 5.6 shows the interrupts selected in each interrupt control mode.
Table 5.6
Interrupts Selected in Each Interrupt Control Mode (1)
Interrupt Mask Bits
Interrupt Control Mode
I
Selected Interrupts
0
0
All interrupts
1
NMI interrupts
*
All interrupts
2
Legend:
*: Don’t care
(2) 8-Level Control
In interrupt control mode 2, 8-level mask level determination is performed for the selected
interrupts in interrupt acceptance control according to the interrupt priority level (IPR).
The interrupt source selected is the interrupt with the highest priority level, and whose priority
level set in IPR is higher than the mask level.
Table 5.7
Interrupts Selected in Each Interrupt Control Mode (2)
Interrupt Control Mode
Selected Interrupts
0
All interrupts
2
Highest-priority-level (IPR) interrupt whose priority level is greater
than the mask level (IPR > I2 to I0)
Rev. 5.00 Mar 28, 2005 page 144 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
(3) Default Priority Determination
When an interrupt is selected by 8-level control, its priority is determined and a vector number is
generated.
If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.8 shows operations and control signal functions in each interrupt control mode.
Table 5.8
Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt
Control
Mode
Interrupt
Acceptance
Control
Setting
INTM1
INTM0
I
0
0
0
2
1
0
IM
—*1
X
8-Level Control
X
Default Priority
Determination
T
(Trace)
I2 to I0
IPR
—
—*2
—
IM
PR
T
Legend:
: Interrupt operation control performed
X: No operation (All interrupts enabled)
IM: Used as interrupt mask bit
PR: Sets priority
—: Not used
Notes: 1. Set to 1 when interrupt is accepted.
2. Keep the initial setting.
Rev. 5.00 Mar 28, 2005 page 145 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.4.2
Interrupt Control Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by
means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and
disabled when set to 1.
Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
[2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I
bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending.
[3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
the priority system is accepted, and other interrupt requests are held pending.
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
[5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
[6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Rev. 5.00 Mar 28, 2005 page 146 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Program execution status
No
Interrupt generated?
Yes
Yes
NMI
No
No
I=0
Hold pending
Yes
No
IRQ0
Yes
No
IRQ1
Yes
TEI4
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 0
Rev. 5.00 Mar 28, 2005 page 147 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.4.3
Interrupt Control Mode 2
Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts
by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR.
Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
[2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.4 is selected.
[3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
[5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
[6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Rev. 5.00 Mar 28, 2005 page 148 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Program execution status
Interrupt generated?
No
Yes
Yes
NMI
No
Level 7 interrupt?
No
Yes
Mask level 6
or below?
Yes
No
Level 6 interrupt?
No
Yes
Level 1 interrupt?
No
Mask level 5
or below?
No
Yes
Yes
Mask level 0?
No
Yes
Save PC, CCR, and EXR
Hold pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 2
Rev. 5.00 Mar 28, 2005 page 149 of 1422
REJ09B0234-0500
Rev. 5.00 Mar 28, 2005 page 150 of 1422
REJ09B0234-0500
(1)
(2)
(4)
(3)
Internal
operation
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
(2) (4) Instruction code (Not executed.)
(3)
Instruction prefetch address (Not executed.)
(5)
SP-2
(7)
SP-4
(1)
Internal
data us
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
φ
Instruction
prefetch
(5)
(7)
(8)
(9)
(10)
Vector fetch
(12)
(11)
Internal
operation
(14)
(13)
Interrupt service
routine instruction
prefetch
(6) (8)
Saved PC and saved CCR
(9) (11) Vector address
(10) (12) Interrupt handling routine start address (vector
address contents)
(13)
Interrupt handling routine start address ((13) = (10) (12))
(14)
First instruction of interrupt handling routine
(6)
Stack
5.4.4
Interrupt level determination
Wait for end of instruction
Interrupt
acceptance
Section 5 Interrupt Controller
Interrupt Exception Handling Sequence
Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Figure 5.7 Interrupt Exception Handling
Section 5 Interrupt Controller
5.4.5
Interrupt Response Times
The H8S/2633 Group is capable of fast word transfer instruction to on-chip memory, and the
program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing.
Table 5.9 shows interrupt response times—the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.9 are explained in table 5.10.
Table 5.9
Interrupt Response Times
Normal Mode*5
Advanced Mode
No.
Execution Status
INTM1 = 0
INTM1 = 1
INTM1 = 0
INTM1 = 1
1
Interrupt priority determination*1
3
3
3
3
2
Number of wait states until executing 1 to
instruction ends*2
(19+2·SI)
1 to
(19+2·SI)
1 to
(19+2·SI)
1 to
(19+2·SI)
3
PC, CCR, EXR stack save
2·SK
3·SK
2·SK
3·SK
4
Vector fetch
SI
SI
2·SI
2·SI
5
Instruction fetch*3
2·SI
2·SI
2·SI
2·SI
6
Internal processing*4
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
5.
2
2
2
2
11 to 31
12 to 32
12 to 32
13 to 33
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and interrupt handling routine prefetch.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Not available in the H8S/2633 Group.
Rev. 5.00 Mar 28, 2005 page 151 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8 Bit Bus
Symbol
Instruction fetch
SI
Branch address read
SJ
Stack manipulation
SK
16 Bit Bus
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
1
4
6+2m
2
3+m
Legend:
m: Number of wait states in an external device access.
5.5
Usage Notes
5.5.1
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.8 shows an example in which the CMIEA bit in the TMR’s TCR register is cleared to 0.
Rev. 5.00 Mar 28, 2005 page 152 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
TCR write cycle by CPU
CMIA exception handling
φ
Internal
address bus
TCR address
Internal
write signal
CMIEA
CMFA
CMIA
interrupt signal
Figure 5.8 Contention between Interrupt Generation and Disabling
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
5.5.2
Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.5.3
Times when Interrupts are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
Rev. 5.00 Mar 28, 2005 page 153 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.5.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1:
5.5.5
EEPMOV.W
MOV.W
R4,R4
BNE
L1
IRQ Interrupt
When operating by clock input, acceptance of input to an IRQ is synchronized with the clock. In
software standby mode, the input is accepted asynchronously. For details on the input conditions,
see section 25.3.2, Control Signal Timing.
5.5.6
NMI Interrupt Usage Notes
The NMI interrupt is part of the exception processing performed cooperatively by the LSI’s
internal interrupt controller and the CPU when the system is operating normally under the
specified electrical conditions. No operations, including NMI interrupts, are guaranteed when
operation is not normal (runaway status) due to software problems or abnormal input to the LSI’s
pins. In such cases, the LSI may be restored to the normal program execution state by applying an
external reset.
Rev. 5.00 Mar 28, 2005 page 154 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.6
DTC and DMAC Activation by Interrupt
(DMAC and DTC functions are not available in the H8S/2695)
5.6.1
Overview
The DTC and DMAC can be activated by an interrupt. In this case, the following options are
available:
•
•
•
•
Interrupt request to CPU
Activation request to DTC
Activation request to DMAC
Selection of a number of the above
For details of interrupt requests that can be used with to activate the DTC and DMAC, see
section 9, Data Transfer Controller (DTC) and section 8, DMA Controller (DMAC).
Rev. 5.00 Mar 28, 2005 page 155 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.6.2
Block Diagram
Figure 5.9 shows a block diagram of the DTC and DMAC interrupt controller.
Interrupt
request
IRQ
interrupt
On-chip
supporting
module
Interrupt source
clear signal
Clear signal
Disenable
signal
DMAC*
DTC activation
request vector
number
Selection
circuit
Select
signal
Clear signal
DTCER
Control logic
DTC*
Clear signal
DTVECR
SWDTE
clear signal
Determination of
priority
CPU interrupt
request vector
number
CPU
I, I2 to I0
Interrupt controller
Note: * This function is not available in the H8S/2695.
Figure 5.9 Interrupt Control for DTC* and DMAC*
Rev. 5.00 Mar 28, 2005 page 156 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
5.6.3
Operation (DMAC and DTC functions are not available in the H8S/2695)
The interrupt controller has three main functions in DTC and DMAC control.
(1) Selection of Interrupt Source: DMAC inputs activation factor directly to each channel. The
activation factors for each channel of DMAC are selected by DTF3 to DTF0 bits of DMACR. The
DTA bit of DMABCR can be used to select whether the selected activation factors are managed
by DMAC. By setting the DTA bit to 1, the interrupt factor which were the activation factor for
that DMAC do not act as the DTC activation factor or the CPU interrupt factor.
Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation
request or CPU interrupt request by the DTCERA to DTCERF of DTC and the DTCE bit of
DTCERI.
By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after
DTC data transfer, and request a CPU interrupt.
If DTC carries out the designate number of data transfers and the transfer counter reads 0, after
DTC data transfer, the DTCE bit is also cleared to 0, and a CPU interrupt requested.
(2) Determination of Priority: The DTC activation source is selected in accordance with the
default priority order, and is not affected by mask or priority levels. See section 8.6, Interrupts,
and section 9.3.3, DTC Vector Table for the respective priority.
(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or
CPU interrupt factor, these operate independently. They operate in accordance with the respective
operating states and bus priorities.
Table 5.11 shows the interrupt factor clear control and selection of interrupt factors by
specification of the DTA bit of DMAC's DMABCR, DTC's DTCERA to DTCERF, DTCERI's
DTCE bits, and the DISEL bit of DTC's MRB.
Rev. 5.00 Mar 28, 2005 page 157 of 1422
REJ09B0234-0500
Section 5 Interrupt Controller
Table 5.11 Interrupt Source Selection and Clearing Control
Settings
*1
DTC*1
DMAC
*1
*1
Interrupt Source Selection/Clearing Control
DTC*1
CPU
*
X
0
∆
∆
DTA
DTCE
DISEL
0
0
1
*1
DMAC*1
1
1
*
*
∆
X
X
∆
X
Legend:
∆: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
: The relevant interrupt is used. The interrupt source is not cleared.
X: The relevant bit cannot be used.
*: Don’t care
Note: 1. This function is not available in the H8S/2695.
(4) Notes on Use: SCI and A/D converter interrupt sources are cleared when the DMAC* or
DTC* reads or writes to the prescribed register, and are not dependent upon the DTA*, DTCE*,
and DISEL* bits.
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 158 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
Section 6 PC Break Controller (PBC)
(This function is not available in the H8S/2695)
6.1
Overview
The PC break controller (PBC) provides functions that simplify program debugging. Using these
functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with
the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC:
instruction fetch, data read, data write, and data read/write.
6.1.1
Features
The PC break controller has the following features:
• Two break channels (A and B)
• The following can be set as break compare conditions:
 24 address bits
Bit masking possible
 Bus cycle
Instruction fetch
Data access: data read, data write, data read/write
 Bus master
Either CPU or CPU/DTC can be selected
• The timing of PC break exception handling after the occurrence of a break condition is as
follows:
 Immediately before execution of the instruction fetched at the set address (instruction
fetch)
 Immediately after execution of the instruction that accesses data at the set address (data
access)
• Module stop mode can be set
 The initial setting is for PBC operation to be halted. Register access is enabled by clearing
module stop mode.
Rev. 5.00 Mar 28, 2005 page 159 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
6.1.2
Block Diagram
Figure 6.1 shows a block diagram of the PC break controller.
BARA
Mask control
Output control
BCRA
Control
logic
Comparator
Match signal
Internal address
Control
logic
Comparator
Match signal
Mask control
BARB
Output control
Access
status
PC break
interrupt
BCRB
Figure 6.1 Block Diagram of PC Break Controller
Rev. 5.00 Mar 28, 2005 page 160 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
6.1.3
Register Configuration
Table 6.1 shows the PC break controller registers.
Table 6.1
PC Break Controller Registers
Initial Value
Name
Abbreviation
R/W
Power-On
Reset
Manual
Reset
Break address register A
BARA
R/W
H'XX000000 Retained
H'FE00
Break address register B
BARB
Break control register A
BCRA
H'FE08
Break control register B
BCRB
R/W
H'XX000000 Retained
R/(W)*2 H'00
Retained
2
R/(W)* H'00
Retained
Module stop control register C
MSTPCRC
R/W
H'FDEA
H'FF
Retained
Address*1
H'FE04
H'FE09
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
6.2
Register Descriptions
6.2.1
Break Address Register A (BARA)
Bit
:
31
•••
24
—
•••
—
Initial value : Undefined
: —
R/W
•••
•••
23
22
21
20
19
18
17
16
BAA BAA BAA BAA BAA BAA BAA BAA
23 22 21 20 19 18 17 16
Unde- 0
0
0
0
0
0
0
0
fined
— R/W R/W R/W R/W R/W R/W R/W R/W
•••
•••
•••
•••
7
6
5
4
3
2
1
0
BAA BAA BAA BAA BAA BAA BAA BAA
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
BARA is a 32-bit readable/writable register that specifies the channel A break address.
BAA23 to BAA0 are initialized to H'000000 by a power-on reset and in hardware standby mode.
Bits 31 to 24—Reserved: These bits return an undefined value if read, and cannot be modified.
Bits 23 to 0—Break Address A23 to A0 (BAA23 to BAA0): These bits hold the channel A PC
break address.
6.2.2
Break Address Register B (BARB)
BARB is the channel B break address register. The bit configuration is the same as for BARA.
Rev. 5.00 Mar 28, 2005 page 161 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
6.2.3
Bit
Break Control Register A (BCRA)
:
Initial value :
R/W
7
6
CMFA
CDA
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: R/(W)*
5
4
3
2
1
BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0
0
BIEA
Note: * Only 0 can be written, for flag clearing.
BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects
the break condition bus master, (2) specifies bits subject to address comparison masking, and (3)
specifies whether the break condition is applied to an instruction fetch or a data access. It also
contains a condition match flag.
BCRA is initialized to H'00 by a power-on reset and in hardware standby mode.
Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is
satisfied. This flag is not cleared to 0.
Bit 7
CMFA
Description
0
[Clearing condition]
When 0 is written to CMFA after reading CMFA = 1
1
(Initial value)
[Setting condition]
When a condition set for channel A is satisfied
Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus
master.
Bit 6
CDA
Description
0
PC break is performed when CPU is bus master
1
PC break is performed when CPU or DTC is bus master
(Initial value)
Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2–BAMRA0): These bits
specify which bits of the break address (BAA23 to BAA0) set in BARA are to be masked.
Rev. 5.00 Mar 28, 2005 page 162 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
Bit 5
Bit 4
Bit 3
BAMRA2 BAMRA1 BAMRA0 Description
0
0
1
1
0
1
0
All BARA bits are unmasked and included in break conditions
(Initial value)
1
BAA0 (lowest bit) is masked, and not included in break
conditions
0
BAA1 to BAA0 (lower 2 bits) are masked, and not included in
break conditions
1
BAA2 to BAA0 (lower 3 bits) are masked, and not included in
break conditions
0
BAA3 to BAA0 (lower 4 bits) are masked, and not included in
break conditions
1
BAA7 to BAA0 (lower 8 bits) are masked, and not included in
break conditions
0
BAA11 to BAA0 (lower 12 bits) are masked, and not included in
break conditions
1
BAA15 to BAA0 (lower 16 bits) are masked, and not included in
break conditions
Bits 2 and 1—Break Condition Select A (CSELA1, CSELA0): These bits selection an
instruction fetch, data read, data write, or data read/write cycle as the channel A break condition.
Bit 2
Bit 1
CSELA1
CSELA0
Description
0
0
Instruction fetch is used as break condition
1
Data read cycle is used as break condition
0
Data write cycle is used as break condition
1
Data read/write cycle is used as break condition
1
(Initial value)
Bit 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts.
Bit 0
BIEA
Description
0
PC break interrupts are disabled
1
PC break interrupts are enabled
(Initial value)
Rev. 5.00 Mar 28, 2005 page 163 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
6.2.4
Break Control Register B (BCRB)
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.2.5
Bit
Module Stop Control Register C (MSTPCRC)
:
7
6
5
4
3
2
1
0
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value :
R/W
:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus
cycle, and module stop mode is entered. Register read/write accesses are not possible in module
stop mode. For details, see section 24.5, Module Stop Mode.
MSTPCRC is initialized to H'FF by a power on reset and in hardware standby mode. It is not
initialized by a manual reset and in software standby mode.
Bit 4—Module Stop (MSTPC4): Specifies the PC break controller module stop mode.
Bit 4
MSTPC4
Description
0
PC break controller module stop mode is cleared
1
PC break controller module stop mode is set
Rev. 5.00 Mar 28, 2005 page 164 of 1422
REJ09B0234-0500
(Initial value)
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
6.3
Operation
The operation flow from break condition setting to PC break interrupt exception handling is
shown in sections 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break
Interrupt Due to Data Access, taking the example of channel A.
6.3.1
PC Break Interrupt Due to Instruction Fetch
(1) Initial settings
 Set the break address in BARA. For a PC break caused by an instruction fetch, set the
address of the first instruction byte as the break address.
 Set the break conditions in BCRA.
BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must
be the CPU. Set 0 to select the CPU.
BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked.
BCRA bits 2 to 1 (CSELA1 to CSELA0): Set 00 to specify an instruction fetch as the
break condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
(2) Satisfaction of break condition
 When the instruction at the set address is fetched, a PC break request is generated
immediately before execution of the fetched instruction, and the condition match flag
(CMFA) is set.
(3) Interrupt handling
 After priority determination by the interrupt controller, PC break interrupt exception
handling is started.
Rev. 5.00 Mar 28, 2005 page 165 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
6.3.2
PC Break Interrupt Due to Data Access
(1) Initial settings
 Set the break address in BARA. For a PC break caused by a data access, set the target
ROM, RAM, I/O, or external address space address as the break address. Stack operations
and branch address reads are included in data accesses.
 Set the break conditions in BCRA.
BCRA bit 6 (CDA): Select the bus master.
BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked.
BCRA bits 2 to 1 (CSELA1 to CSELA0): Set 01, 10, or 11 to specify data access as the
break condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
(2) Satisfaction of break condition
 After execution of the instruction that performs a data access on the set address, a PC break
request is generated and the condition match flag (CMFA) is set.
(3) Interrupt handling
 After priority determination by the interrupt controller, PC break interrupt exception
handling is started.
6.3.3
Notes on PC Break Interrupt Handling
(1) The PC break interrupt is shared by channels A and B. The channel from which the request
was issued must be determined by the interrupt handler.
(2) The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB
after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be
requested after interrupt handling ends.
(3) A PC break interrupt generated when the DTC is the bus master is accepted after the bus has
been transferred to the CPU by the bus controller.
Rev. 5.00 Mar 28, 2005 page 166 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
6.3.4
Operation in Transitions to Power-Down Modes
The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
(1) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
sleep mode, or from subactive mode to subsleep mode:
After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep
mode, and PC break interrupt handling is executed. After execution of PC break interrupt
handling, the instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)).
(2) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
subactive mode:
After execution of the SLEEP instruction, a transition is made to subactive mode via direct
transition exception handling. After the transition, PC break interrupt handling is executed,
then the instruction at the address after the SLEEP instruction is executed (figure 6.2 (B)).
(3) When the SLEEP instruction causes a transition from subactive mode to high-speed (mediumspeed) mode:
After execution of the SLEEP instruction, and following the clock oscillation settling time, a
transition is made to high-speed (medium-speed) mode via direct transition exception
handling. After the transition, PC break interrupt handling is executed, then the instruction at
the address after the SLEEP instruction is executed (figure 6.2 (C)).
(4) When the SLEEP instruction causes a transition to software standby mode or watch mode:
After execution of the SLEEP instruction, a transition is made to the respective mode, and PC
break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2
(D)).
Rev. 5.00 Mar 28, 2005 page 167 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
SLEEP instruction
execution
SLEEP instruction
execution
SLEEP instruction
execution
SLEEP instruction
execution
PC break exception
handling
System clock
→ subclock
Subclock →
system clock,
oscillation settling time
Transition to
respective mode
Execution of instruction
after sleep instruction
Direct transition
exception handling
Direct transition
exception handling
(D)
(A)
PC break exception
handling
Subactive
mode
PC break exception
handling
Execution of instruction
after sleep instruction
Execution of instruction
after sleep instruction
(B)
(C)
High-speed
(medium-speed)
mode
Figure 6.2 Operation in Power-Down Mode Transitions
6.3.5
PC Break Operation in Continuous Data Transfer
If a PC break interrupt is generated when the following operations are being performed, exception
handling is executed on completion of the specified transfer.
(1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction:
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
(2) When a PC break interrupt is generated at a DTC transfer address:
PC break exception handling is executed after the DTC has completed the specified number of
data transfers, or after data for which the DISEL bit is set to 1 has been transferred.
Rev. 5.00 Mar 28, 2005 page 168 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
6.3.6
When Instruction Execution is Delayed by One State
Caution is required in the following cases, as instruction execution is one state later than usual.
(1) When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a
one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in onchip ROM or RAM is always delayed by one state.
(2) When break interruption by instruction fetch is set, the set address indicates on-chip ROM or
RAM space, and that address is used for data access, the instruction that executes the data
access is one state later than in normal operation.
(3) When break interruption by instruction fetch is set and a break interrupt is generated, if the
executing instruction immediately preceding the set instruction has one of the addressing
modes shown below, and that address indicates on-chip ROM or RAM, and that address is
used for data access, the instruction will be one state later than in normal operation.
@ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC),
@(d:16,PC), @@aa:8
(4) When break interruption by instruction fetch is set and a break interrupt is generated, if the
executing instruction immediately preceding the set instruction is NOP or SLEEP, or has
#xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the
instruction will be one state later than in normal operation.
Rev. 5.00 Mar 28, 2005 page 169 of 1422
REJ09B0234-0500
Section 6 PC Break Controller (PBC) (This function is not available in the H8S/2695)
6.3.7
Additional Notes
(1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP,
TRAPA, RTE, or RTS instruction:
Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS
instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the
instruction fetch at the next address.
(2) When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt
becomes valid two states after the end of the executing instruction. If a PC break interrupt is
set for the instruction following one of these instructions, since interrupts, including NMI, are
disabled for a 3-state period in the case of LDC, ANDC, ORC, and XORC, the next instruction
is always executed. For details, see section 5, Interrupt Controller.
(3) When a PC break is set for an instruction fetch at the address following a Bcc instruction:
A PC break interrupt is generated if the instruction at the next address is executed in
accordance with the branch condition, but is not generated if the instruction at the next address
is not executed.
(4) When a PC break is set for an instruction fetch at the branch destination address of a Bcc
instruction:
A PC break interrupt is generated if the instruction at the branch destination is executed in
accordance with the branch condition, but is not generated if the instruction at the branch
destination is not executed.
Rev. 5.00 Mar 28, 2005 page 170 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Section 7 Bus Controller
7.1
Overview
The H8S/2633 Group has a built-in bus controller (BSC) that manages the external address space
divided into eight areas. The bus specifications, such as bus width and number of access states,
can be set independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU, DMA controller (DMAC)*, and data transfer controller (DTC)*.
Note: * This function is not available in the H8S/2695.
7.1.1
Features
The features of the bus controller are listed below.
• Manages external address space in area units
 Manages the external space as 8 areas of 2 Mbytes
 Bus specifications can be set independently for each area
 DRAM/Burst ROM interface can be set
• Basic bus interface
 Chip selects (CS0 to CS7) can be output for areas 0 to 7
 8-bit access or 16-bit access can be selected for each area
 2-state access or 3-state access can be selected for each area
 Program wait states can be inserted for each area
• DRAM interface*
 DRAM interface can be set for areas 2 to 5 (in advanced mode)
 Multiplexed output of row and column addresses (8/9/10 bit)
 2 CAS method
 Burst operation (in high-speed mode)
 Insertion of TP cycle to secure RAS precharge time
 Selection of CAS-before-RAS refresh and self refresh
• Burst ROM interface
 Burst ROM interface can be set for area 0
 Choice of 1- or 2-state burst access
Rev. 5.00 Mar 28, 2005 page 171 of 1422
REJ09B0234-0500
Section 7 Bus Controller
• Idle cycle insertion
 An idle cycle can be inserted in case of an external read cycle between different areas
 An idle cycle can be inserted in case of an external write cycle immediately after an
external read cycle
• Write buffer functions
 External write cycle and internal access can be executed in parallel
 DMAC* single-address mode and internal access can be executed in parallel
• Bus arbitration function
 Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC* and DTC*
• Other features
 Refresh counter* (refresh timer) can be used as an interval timer
 External bus release function
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 172 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.1.2
Block Diagram
Figure 7.1 shows a block diagram of the bus controller.
CS0 to CS7
Internal
address bus
Area decoder
ABWCR
External bus control signals
ASTCR
BCRH
BCRL
BACK
Internal data bus
BREQ
Bus
controller
BREQO
Wait
controller
WAIT
Internal control
signals
Bus mode signal
WCRH
WCRL
DRAM controller
MCR*
External DRAM
control signal
DRAMCR*
RTCNT*
RTCOR*
CPU bus request signal
DTC* bus request signal
Bus arbiter
DMAC* bus request signal
CPU bus acknowledge signal
DTC* bus acknowledge signal
DMAC* bus acknowledge signal
Legend:
ABWCR:
ASTCR:
BCRH:
BCRL:
WCRH:
WCRL:
Bus width control register
Access state control register
Bus control register H
Bus control register L
Wait control register H
Wait control register L
MCR*:
DRAMCR*:
RTCNT*:
RTCOR*:
Memory control register
DRAM control register
Refresh timer counter
Refresh time constand register
Note: * This function is not available in the H8S/2695.
Figure 7.1 Block Diagram of Bus Controller
Rev. 5.00 Mar 28, 2005 page 173 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.1.3
Pin Configuration
Table 7.1 summarizes the pins of the bus controller.
Table 7.1
Bus Controller Pins
Name
Symbol
I/O
Function
Address strobe
AS
Output
Strobe signal indicating that address output on address
bus is enabled.
Read
RD
Output
Strobe signal indicating that external space is being
read.
HWR
Output
Strobe signal indicating that external space is to be
written, and upper half (D15 to D8) of data bus is
enabled. 2CAS method DRAM with enable signal*.
LWR
Output
Strobe signal indicating that external space is to be
written, and lower half (D7 to D0) of data bus is
enabled.
Output
Strobe signal showing selection of area 0
Output
Strobe signal showing selection of area 1
Output
Strobe signal showing selection of area 2.
When area 2 is allocated to DRAM space, this is the
row address strobe signal for DRAM*.
When areas 2 to 5 are contiguous DRAM space, this is
the row address strobe signal for DRAM*.
CS3/OE*
Output
Strobe signal showing selection of area 3.
When area 3 is allocated to DRAM space, this is the
row address strobe signal for DRAM*.
When only area 2 is allocated to DRAM space, or when
areas 2 to 5 are contiguous DRAM space, this is output
enable signal*.
CS4
Output
Strobe signal showing selection of area 4.
When area 4 is allocated to DRAM space, this is the
row address strobe signal for DRAM*.
CS5
Output
Strobe signal showing selection of area 5.
When area 5 is allocated to DRAM space, this is the
row address strobe signal for DRAM*.
Output
Strobe signal showing selection of area 6
Output
Strobe signal showing selection of area 7
Output
2 CAS method DRAM upper column address strobe
signal*
High write/
write enable*
Low write
Chip select 0
Chip select 1
Chip select 2/row
address strobe 2*
Chip select 3/row
address strobe 3*
Chip select 4/row
address strobe 4*
Chip select 5/row
address strobe 5*
Chip select 6
Chip select 7
Upper column
address strobe*
CS0
CS1
CS2
CS6
CS7
CAS*
Rev. 5.00 Mar 28, 2005 page 174 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Name
Lower column
strobe*
Wait
Symbol
I/O
Function
LCAS*
Output
DRAM lower column address strobe signal*
WAIT
Input
Wait request signal when accessing external 3-state
access space.
Input
Request signal that releases bus to external device.
Output
Acknowledge signal indicating that bus has been
released.
Output
External bus request signal used when internal bus
master accesses external space when external bus is
released.
BREQ
BACK
Bus request
Bus request
acknowledge
Bus request output
BREQO
Note: * This function is not available in the H8S/2695.
7.1.4
Register Configuration
Table 7.2 summarizes the registers of the bus controller.
Table 7.2
Bus Controller Registers
Initial Value
Name
Abbreviation
R/W
Power-On
Reset
Manual
Reset
Address*1
Bus width control register
ABWCR
R/W
H'FF/H'00*2
Retained
H'FED0
Access state control register
ASTCR
R/W
H'FF
Retained
H'FED1
Wait control register H
WCRH
R/W
H'FF
Retained
H'FED2
Wait control register L
WCRL
R/W
H'FF
Retained
H'FED3
Bus control register H
BCRH
R/W
H'D0
Retained
H'FED4
Bus control register L
BCRL
R/W
H'08
Retained
H'FED5
Pin function control register
PFCR
MCR*3
R/W
H'0D/H'00
Retained
H'FDEB
Memory control register
R/W
H'00
Retained
H'FED6
R/W
H'00
Retained
H'FED7
Refresh timer counter
DRAMCR*3
RTCNT*3
R/W
H'00
Retained
H'FED8
Refresh time constant register
RTCOR*3
R/W
H'FF
Retained
H'FED9
DRAM control register
Notes: 1. Lower 16 bits of the address.
2. Determined by the MCU operating mode.
3. This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 175 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.2
Register Descriptions
7.2.1
Bus Width Control Register (ABWCR)
Bit
:
Modes 5 to 7
Initial value :
R/W
:
7
6
5
4
3
2
1
0
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode 4
Initial value :
R/W
:
ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or
16-bit access.
ABWCR sets the data bus width for the external memory space. The bus width for on-chip
memory and internal I/O registers is fixed regardless of the settings in ABWCR.
In normal mode, the settings of bits ABW7 to ABW1 have no effect on operation.
After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5
to 7, and to H'00 in mode 4. It is not initialized by a manual reset or in software standby mode.
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the
corresponding area is to be designated for 8-bit access or 16-bit access.
Bit n
ABWn
Description
0
Area n is designated for 16-bit access
1
Area n is designated for 8-bit access
(n = 7 to 0)
Rev. 5.00 Mar 28, 2005 page 176 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.2.2
Bit
Access State Control Register (ASTCR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access
space or a 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
In normal mode, the settings of bits AST7 to AST1 have no effect on operation.
ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is to be designated as a 2-state access space or a 3-state access space.
Wait state insertion is enabled or disabled at the same time.
Bit n
ASTn
Description
0
Area n is designated for 2-state access
Wait state insertion in area n external space is disabled
1
Area n is designated for 3-state access
(Initial value)
Wait state insertion in area n external space is enabled
(n = 7 to 0)
Rev. 5.00 Mar 28, 2005 page 177 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.2.3
Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait
states for each area.
Program waits are not inserted in the case of on-chip memory or internal I/O registers.
WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode.
They are not initialized by a manual reset or in software standby mode.
(1) WCRH
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
W71
W70
W61
W60
W51
W50
W41
W40
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of
program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set
to 1.
Bit 7
Bit 6
W71
W70
Description
0
0
Program wait not inserted when external space area 7 is accessed
1
1 program wait state inserted when external space area 7 is accessed
0
2 program wait states inserted when external space area 7 is accessed
1
3 program wait states inserted when external space area 7 is accessed
(Initial value)
1
Rev. 5.00 Mar 28, 2005 page 178 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of
program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set
to 1.
Bit 5
Bit 4
W61
W60
Description
0
0
Program wait not inserted when external space area 6 is accessed
1
1 program wait state inserted when external space area 6 is accessed
0
2 program wait states inserted when external space area 6 is accessed
1
3 program wait states inserted when external space area 6 is accessed
(Initial value)
1
Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of
program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set
to 1.
Bit 3
Bit 2
W51
W50
Description
0
0
Program wait not inserted when external space area 5 is accessed
1
1 program wait state inserted when external space area 5 is accessed
0
2 program wait states inserted when external space area 5 is accessed
1
3 program wait states inserted when external space area 5 is accessed
(Initial value)
1
Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of
program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set
to 1.
Bit 1
Bit 0
W41
W40
Description
0
0
Program wait not inserted when external space area 4 is accessed
1
1 program wait state inserted when external space area 4 is accessed
0
2 program wait states inserted when external space area 4 is accessed
1
3 program wait states inserted when external space area 4 is accessed
(Initial value)
1
Rev. 5.00 Mar 28, 2005 page 179 of 1422
REJ09B0234-0500
Section 7 Bus Controller
(2) WCRL
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
W31
W30
W21
W20
W11
W10
W01
W00
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of
program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set
to 1.
Bit 7
Bit 6
W31
W30
Description
0
0
Program wait not inserted when external space area 3 is accessed
1
1 program wait state inserted when external space area 3 is accessed
0
2 program wait states inserted when external space area 3 is accessed
1
3 program wait states inserted when external space area 3 is accessed
(Initial value)
1
Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of
program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set
to 1.
Bit 5
Bit 4
W21
W20
Description
0
0
Program wait not inserted when external space area 2 is accessed
1
1 program wait state inserted when external space area 2 is accessed
0
2 program wait states inserted when external space area 2 is accessed
1
3 program wait states inserted when external space area 2 is accessed
(Initial value)
1
Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of
program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set
to 1.
Rev. 5.00 Mar 28, 2005 page 180 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bit 3
Bit 2
W11
W10
Description
0
0
Program wait not inserted when external space area 1 is accessed
1
1 program wait state inserted when external space area 1 is accessed
0
2 program wait states inserted when external space area 1 is accessed
1
3 program wait states inserted when external space area 1 is accessed
(Initial value)
1
Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1
Bit 0
W01
W00
Description
0
0
Program wait not inserted when external space area 0 is accessed
1
1 program wait state inserted when external space area 0 is accessed
0
2 program wait states inserted when external space area 0 is accessed
1
3 program wait states inserted when external space area 0 is accessed
(Initial value)
1
7.2.4
Bit
Bus Control Register H (BCRH)
:
Initial value :
R/W
:
7
6
ICIS1
ICIS0
1
1
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
5
4
3
2
0
1
BRSTRM BRSTS1 BRSTS0 RMTS2* RMTS1* RMTS0*
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for area 0.
BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Note: * DRAM interface is not available in the H8S/2695.
Only a 0 may be written to RMTS2, RMTS1, or RMTS0.
Rev. 5.00 Mar 28, 2005 page 181 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1
Description
0
Idle cycle not inserted in case of successive external read cycles in different areas
1
Idle cycle inserted in case of successive external read cycles in different areas
(Initial value)
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed .
Bit 6
ICIS0
Description
0
Idle cycle not inserted in case of successive external read and external write cycles
1
Idle cycle inserted in case of successive external read and external write cycles
(Initial value)
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM
interface.
Bit 5
BRSTRM
Description
0
Area 0 is basic bus interface
1
Area 0 is burst ROM interface
(Initial value)
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1
Description
0
Burst cycle comprises 1 state
1
Burst cycle comprises 2 states
Rev. 5.00 Mar 28, 2005 page 182 of 1422
REJ09B0234-0500
(Initial value)
Section 7 Bus Controller
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
Description
0
Max. 4 words in burst access
1
Max. 8 words in burst access
(Initial value)
Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): In advanced mode, these bits select the
memory interface for areas 2 to 5.
When DRAM space* is selected, the appropriate area becomes the DRAM interface*.
Note: * This function is not available in the H8S/2695.
Only a 0 may be written to RMTS2, RMTS1, or RMTS0.
Bit 2
Bit 1
Bit 0
RMTS2
RMTS1
RMTS0
Area 5
Area 4
Area 3
Area 2
0
0
0
Normal space
Normal space
Normal space
1
Normal space
Normal space
Normal space
DRAM space*
1
0
1
1
1
1
Description
Normal space
Normal space Normal space DRAM space* DRAM space*
DRAM space* DRAM space* DRAM space* DRAM space*
Contiguous
Contiguous
Contiguous
Contiguous
DRAM space* DRAM space* DRAM space* DRAM space*
Note: When all areas selected in DRAM are 8-bit space, the PF2 pin can be used as an I/O port
and for BREQO and WAIT. When contiguous RAM is selected set the appropriate bus width
and number of access states (the number of programmable waits) to the same values for all
of areas 2 to 5. Do not set other than the above combinations.
* This function is not available in the H8S/2695.
Only a 0 may be written to RMTS2, RMTS1, or RMTS0.
Rev. 5.00 Mar 28, 2005 page 183 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.2.5
Bit
Bus Control Register L (BCRL)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
BRLE
BREQOE
—
OES*
DDS*
RCTS*
WDBE
WAITE
0
0
0
0
1
0
0
0
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
Note: * This function is not available in the H8S/2695. In writing to OES, DDS, RCTS, the initial
value should be written to these bits.
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of
WAIT pin input.
BCRL is initialized to H'08 by a power-on reset and in hardware standby mode. It is not initialized
by a manual reset or in software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
Description
0
External bus release is disabled. BREQ, BACK and BREQO can be used as I/O ports
(Initial value)
1
External bus release is enabled
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE
0
1
Description
BREQO output disabled. BREQO can be used as I/O port
BREQO output enabled
Bit 5—Reserved: This bit cannot be modified and is always read as 0.
Rev. 5.00 Mar 28, 2005 page 184 of 1422
REJ09B0234-0500
(Initial value)
Section 7 Bus Controller
Bit 4—OE Select (OES): Selects the CS3 pin as the OE pin.
Bit 4
OES
Description
0
Uses the CS3 pin as the port or as CS3 signal output
1
(Initial value)
When only area 2 is set for DRAM, or when areas 2 to 5 are set as
contiguous DRAM space, the CS3 pin is used as the OE pin
Bit 3—DACK Timing Select (DDS): When using the DRAM interface, this bit selects the
DMAC single address transfer bus timing.
Bit 3
DDS
Description
0
When performing DMAC single address transfers to DRAM, always execute full
access. The DACK signal is output as a low-level signal from the Tr or T1 cycle
1
Burst access is also possible when performing DMAC single address
tranfers to DRAM. The DACK signal is output as a low-level signal
from the TC1 or T2 cycle
(Initial value)
Bit 2—Read CAS Timing Select (RCTS): Selects the CAS signal output timing.
Bit 2
RCTS
0
1
Description
CAS signal output timing is same when reading and writing
(Initial value)
When reading, CAS signal is asserted half cycle earlier than when writing
Bit 1—Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write
buffer function in the external write cycle or the DMAC* single address cycle.
Bit 1
WDBE
Description
0
Write data buffer function not used
1
Write data buffer function used
(Initial value)
Rev. 5.00 Mar 28, 2005 page 185 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE
Description
0
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port
(Initial value)
Wait input by WAIT pin enabled
1
7.2.6
Bit
Pin Function Control Register (PFCR)
:
7
CSS07
Initial value :
R/W
:
6
5
4
CSS36 BUZZE* LCASS*
3
2
1
0
AE3
AE2
AE1
AE0
0
0
0
0
1/0
1/0
0
1/0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * This function is not available in the H8S/2695. Only 0 should be written to the BUZZE
and LCASS bits.
PFCR is an 8-bit read/write register that controls the CS selection of pins PG4 and PG1, controls
LCAS selection of pins PF2 and PF6, and controls the address output in expanded mode with
ROM.
PFCR is initialized to H'0D/H'00 by a power-on reset and in hardware standby mode. It retains its
previous state by a manual reset or in software standby mode.
Bit 7—CS0/CS7 Select (CSS07): This bit selects the contents of CS output via the PG4 pin. In
modes 4, 5, and 6, setting the corresponding DDR to 1 outputs the selected CS.
Bit 7
CSS07
Description
0
Selects CS0
1
Selects CS7
Rev. 5.00 Mar 28, 2005 page 186 of 1422
REJ09B0234-0500
(Initial value)
Section 7 Bus Controller
Bit 6—CS3/CS6 Select (CSS36): This bit selects the contents of CS output via the PG1 pin. In
modes 4, 5, and 6, setting the corresponding DDR to 1 outputs the selected CS.
Bit 6
CSS36
Description
0
Selects CS3
1
(Initial value)
Selects CS6
Bit 5—BUZZ Output Enable (BUZZE): This bit enables/disables BUZZ output via the PF1 pin.
The WDT1 input clock, selected with PSS and CKS2 to CKS0, is output as the BUZZ signal. See
section 15.2.4, Pin Function Control Register (PFCR) for details of BUZZ output.
Bit 5
BUZZE
Description
0
Functions as PF1 input pin
1
Functions as BUZZ output pin
(Initial value)
Bit 4—LCAS Output Pin Select Bit (LCASS): Selects output pin for LCAS signal.
Bit 4
LCASS
Description
0
Outputs LCAS signal from PF2
1
Outputs LCAS signal from PF6
(Initial value)
Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or
disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When
a pin is enabled for address output, the address is output regardless of the corresponding DDR
setting. When a pin is disabled for address output, it becomes an output port when the
corresponding DDR bit is set to 1.
Rev. 5.00 Mar 28, 2005 page 187 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bit 3
Bit 2
Bit 1
Bit 0
AE3
AE2
AE1
AE0
Description
0
0
0
0
A8 to A23 address output disabled
1
A8 address output enabled; A9 to A23 address output disabled
0
A8, A9 address output enabled; A10 to A23 address output
disabled
1
A8 to A10 address output enabled; A11 to A23 address output
disabled
0
A8 to A11 address output enabled; A12 to A23 address output
disabled
1
A8 to A12 address output enabled; A13 to A23 address output
disabled
0
A8 to A13 address output enabled; A14 to A23 address output
disabled
1
A8 to A14 address output enabled; A15 to A23 address output
disabled
0
A8 to A15 address output enabled; A16 to A23 address output
disabled
1
A8 to A16 address output enabled; A17 to A23 address output
disabled
0
A8 to A17 address output enabled; A18 to A23 address output
disabled
1
A8 to A18 address output enabled; A19 to A23 address output
disabled
0
A8 to A19 address output enabled; A20 to A23 address output
disabled
1
A8 to A20 address output enabled; A21 to A23 address output
disabled
(Initial value*)
0
A8 to A21 address output enabled; A22, A23 address output
disabled
1
A8 to A23 address output enabled
1
1
0
1
1
0
0
1
1
0
1
(Initial value*)
Note: * In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.
In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to
1.
Rev. 5.00 Mar 28, 2005 page 188 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.2.7
Bit
Memory Control Register (MCR)*
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
TPC
BE
RCDM
CW2
MXC1
MXC0
RLW1
RLW0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The MCR is an 8-bit read/write register that, when areas 2 to 5 are set as the DRAM interface,
controls the DRAM strobe method, number of precharge cycles, access mode, address multiplex
shift amount, and number of wait states to be inserted when a refresh is performed.
The MCR is initialized to H'00 at a power-on reset and in hardware standby mode. It is not
initialized at a manual reset or in software standby mode.
Note: * This function is not available in the H8S/2695.
Bit 7—TP Cycle Control (TPC): When accessing areas 2 to 5, allocated to DRAM, this bit
selects whether the precharge cycle (TP) is 1 state or 2 states.
Bit 7
TPC
Description
0
Insert 1 precharge cycle
1
Insert 2 precharge cycles
(Initial value)
Bit 6—Burst Access Enable (BE): This bit enables/disables burst access of areas 2 to 5, allocated
as DRAM space. DRAM space burst access is in high-speed page mode. When using EDO type in
this case, either select OE output or RAS up mode.
Bit 6
BE
Description
0
Burst disabled (always full access)
1
Access DRAM space in high-speed page mode
(Initial value)
Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are allocated to DRAM space, this bit
selects whether the RAS signal level remains Low while waiting for the next DRAM access (RAS
down mode) or the RAS signal level returns to High (RAS up mode), when DRAM access is
discontinued.
Rev. 5.00 Mar 28, 2005 page 189 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bit 5
RCDM
Description
0
DRAM interface: selects RAS up mode
1
DRAM interface: selects RAS down mode
(Initial value)
Bit 4—Reserved (CW2): Only write 0 to this bit.
Bits 3 and 2—Multiplex shift counts 1 and 0 (MXC1 and MXC0): These bits select the shift
amount to the low side of the row address of the multiplexed row/column address in DRAM
interface mode. They also select the row address to be compared in burst operation of the DRAM
interface.
Bit 3
Bit 2
MXC1
MXC0
0
0
Description
8-bit shift
(Initial value)
(1) 8-bit access space: target row addresses for comparison are A23 to A8
(2) 16-bit access space: target row addresses for comparison are A23 to A9
1
9-bit shift
(1) 8-bit access space: target row addresses for comparison are A23 to A9
(2) 16-bit access space: target row addresses for comparison are A23 to A10
1
0
10-bit shift
(1) 8-bit access space: target row addresses for comparison are A23 to A10
(2) 16-bit access space: target row addresses for comparison are A23 to A11
1
—
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1 and RLW0): These bits select the
number of wait states to be inserted in the CAS-before-RAS refresh cycle of the DRAM interface.
The selected number of wait states is applied to all areas set as DRAM space. Wait input via the
WAIT pin is disabled.
Bit 1
Bit 0
RLW1
RLW0
Description
0
0
Do not insert wait state
1
Insert 1 wait state
0
Insert 2 wait states
1
Insert 3 wait states
1
Rev. 5.00 Mar 28, 2005 page 190 of 1422
REJ09B0234-0500
(Initial value)
Section 7 Bus Controller
7.2.8
Bit
DRAM Control Register (DRAMCR)*
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
RFSHE
CBRM
RMODE
CMF
CMIE
CKS2
CKS1
CKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The DRAMCR is an 8-bit read/write register that selects DRAM refresh mode, the refresh counter
clock, and sets the refresh timer control.
The DRAMCR is initialized to H'00 at a power-on reset and in hardware standby mode. It is not
initialized at a manual reset or in software standby mode.
Note: * This function is not available in the H8S/2695.
Bit 7—Refresh Control (RFSHE): This bit selects whether or not to perform refresh control.
When not performing refresh control, the refresh timer can be used as an interval timer.
Bit 7
RFSHE
Description
0
Do not perform refresh control
1
Perform refresh control
(Initial value)
Bit 6—CBR Refresh Mode (CBRM): This bit selects whether CBR refresh is performed in
parallel with other external access, or only CBR refresh is performed.
Bit 6
CBRM
Description
0
Enables external access during CAS-before-RAS refresh
1
Disables external access during CAS-before-RAS refresh
(Initial value)
Bit 5—Refresh Mode (RMODE): This bit selects whether or not to perform a self refresh in
software standby mode when performing refresh control (RFSHE=1).
Bit 5
RMODE
Description
0
Do not perform self-refresh in software standby mode
1
Perform self-refresh in software standby mode
(Initial value)
Rev. 5.00 Mar 28, 2005 page 191 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bit 4—Compare Match Flag (CMF): This status flag shows a match between RTCNT and
RTCOR values.
When performing refresh control (RFSHE=1), write 1 to CMF when writing to the DRAMCR.
Bit 4
CMF
Description
0
[Clearing]
When CMF=1, read the CMF flag, then clear the CMF flag to 0
1
(Initial value)
[Setting]
CMF is set when RTCNT=RTCOR
Bit 3—Compare Match Interrupt Enable (CMIE): This bit enables/disables the CMF flag
interrupt request (CMI) when the DRAMCR CMF flag is set to 1.
CMIE is always 0 when performing refresh control (RFSHE = 1).
Bit 3
CMIE
Description
0
Disables CMF flag interrupt requests (CMI)
1
Enables CMF flag interrupt requests (CMI)
(Initial value)
Bits 2 to 0—Refresh Counter Clock Select (CKS2 to CKS0): These bits select from the seven
internal clocks derived by dividing the system clock (φ) to be input to RTCNT. The RTCNT count
up starts when CKS2 to CKS0 are set to select the input clock.
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
0
0
1
1
0
1
Description
0
Stops count
1
Counts on φ/2
0
Counts on φ/8
1
Counts on φ/32
0
Counts on φ/128
1
Counts on φ/512
0
Counts on φ/2048
1
Counts on φ/4096
Rev. 5.00 Mar 28, 2005 page 192 of 1422
REJ09B0234-0500
(Initial value)
Section 7 Bus Controller
7.2.9
Refresh Timer Counter (RTCNT)*
:
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
R/W
:
RTCNT is an 8-bit read/write up-counter.
RTCNT counts up using the internal clock selected by the DRAMCR CKS2 to CKS0 bits.
When RTCNT matches the value in RTCOR (compare match), the DRAMCR CMF flag is set to 1
and RTCNT is cleared to H'00. If, at this point, DRAMCR RFSHE is set to 1, the refresh cycle
starts. When the DRAMCR CMIE bit is set to 1, a compare match interrupt (CMI) is also
generated.
RTCNT is initialized to H'00 at a power-on reset and in hardware standby mode. It is not
initialized at a manual reset or in software standby mode.
Note: * This function is not available in the H8S/2695.
7.2.10
Refresh Time Constant Register (RTCOR)*
:
7
6
5
4
3
2
1
0
Initial value :
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
R/W
:
RTCOR is an 8-bit read/write register that sets the RTCNT compare match cycle.
The values of RTCOR and RTCNT are constantly compared and, when both value match, the
DRAMCR CMF flag is set to 1 and RTCNT is cleared to H'00.
RTCOR is initialized to H'FF at a power-on reset and in hardware standby mode. It is not
initialized at a manual reset or in software standby mode.
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 193 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.3
Overview of Bus Control
7.3.1
Area Partitioning
In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to
7, in 2-Mbyte units, and performs bus control for external space in area units. A chip select signal
(CS0 to CS7) can be output for each area. In normal mode*, it controls a 64-kbyte address space
comprising part of area 0. Figure 7.2 shows an outline of the memory map.
Note: * Not available in the H8S/2633 Group.
H'000000
H'0000
Area 0
(2 Mbytes)
H'1FFFFF
H'200000
Area 1
(2 Mbytes)
H'3FFFFF
H'400000
Area 2
(2 Mbytes)
H'FFFF
H'5FFFFF
H'600000
Area 3
(2 Mbytes)
H'7FFFFF
H'800000
Area 4
(2 Mbytes)
H'9FFFFF
H'A00000
Area 5
(2 Mbytes)
H'BFFFFF
H'C00000
Area 6
(2 Mbytes)
H'DFFFFF
H'E00000
Area 7
(2 Mbytes)
H'FFFFFF
(1)
Advanced mode
(2)
Normal mode*
Note: * Not available in the H8S/2633 Group.
Figure 7.2 Overview of Area Partitioning
Rev. 5.00 Mar 28, 2005 page 194 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.3.2
Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access
states, and number of program wait states.
The bus width and number of access states for on-chip memory and internal I/O registers are
fixed, and are not affected by the bus controller.
(1) Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an
8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is
selected functions as a16-bit access space.
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit
access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is
always set.
(2) Number of Access States: Two or three access states can be selected with ASTCR. An area
for which 2-state access is selected functions as a 2-state access space, and an area for which 3state access is selected functions as a 3-state access space.
With the DRAM interface* or the burst ROM interface, the number of access states may be
determined without regard to ASTCR.
When 2-state access space is designated, wait insertion is disabled.
Note: * This function is not available in the H8S/2695.
(3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the
number of program wait states to be inserted automatically is selected with WCRH and WCRL.
From 0 to 3 program wait states can be selected.
Table 7.3 shows the bus specifications for each basic bus interface area.
Rev. 5.00 Mar 28, 2005 page 195 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Table 7.3
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR
ASTCR
WCRH, WCRL
ABWn
ASTn
Wn1
Wn0
Bus Width
Program Wait
Access States States
0
0
—
—
16
2
0
1
0
0
3
0
1
1
7.3.3
1
1
0
2
1
3
0
—
—
1
0
0
1
Bus Specifications (Basic Bus Interface)
8
2
0
3
0
1
1
0
2
1
3
Memory Interfaces
The H8S/2633 Group memory interfaces comprise a basic bus interface that allows direct
connection or ROM, SRAM, and so on, DRAM interface* with direct DRAM connection and a
burst ROM interface that allows direct connection of burst ROM. The memory interface can be
selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, and areas set for
DRAM interface are DRAM spaces an area for which the burst ROM interface is designated
functions as burst ROM space.
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 196 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.3.4
Interface Specifications for Each Area
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (section 7.4, Basic Bus Interface, section 7.5,
DRAM Interface, and section 7.7, Burst ROM Interface) should be referred to for further details.
Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is
external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external
space.
A CS0 signal can be output when accessing area 0 external space.
Either basic bus interface or burst ROM interface can be selected for area 0.
Areas 1 and 6: In external expansion mode, all of areas 1 and 6 is external space.
CS1 and CS6 pin signals can be output when accessing the area 1 and 6 external space.
Only the basic bus interface can be used for areas 1 and 6.
Areas 2 to 5: In external expansion mode, all of areas 2 to 5 is external space.
CS2 to CS5 signals can be output when accessing area 2 to 5 external space.
The standard bus interface or DRAM interface* can be selected for areas 2 to 5. In DRAM
interface mode, signals CS2 to CS5 are used as RAS signals.
Note: * This function is not available in the H8S/2695.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode,
the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip
RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes
external space.
A CS7 signal can be output when accessing area 7 external space.
Only the basic bus interface can be used for the area 7.
Rev. 5.00 Mar 28, 2005 page 197 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.3.5
Chip Select Signals
This LSI allows chip select signals (CS0 to CS7) to be output for each of areas 0 to 7. The level of
these signals is set Low when accessing the external space of the respective area.
Figure 7.3 shows example CSn (where n = 0 to 7) signal output timing.
The output of the CSn signal can be enabled or disabled by the data direction register (DDR) of
the port of the corresponding CSn pin.
In ROM-disabled expanded mode, the CS0 pin is set for output after a power-on reset. The CS1 to
CS7 pins are set for input after a power-on reset, so the corresponding DDR must be set to 1 to
allow the output of CS1 to CS7 signals.
In ROM-disabled expanded mode, all of pins CS0 to CS7 are set for input after a power-on reset,
so the corresponding DDR must be set to 1 to allow the output of CS0 to CS7 signals.
See sections 10A and 10B, I/O Ports for details.
When areas 2 to 5 are set as DRAM* space, CS2 to CS5 outputs are used as RAS signals.
Note: * DRAM interface is not available in the H8S/2695.
Bus cycle
T1
T2
T3
φ
Address bus
Area n external address
CSn
Figure 7.3
CSn Signal Output Timing (where n=0 to 7)
Rev. 5.00 Mar 28, 2005 page 198 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.4
Basic Bus Interface
7.4.1
Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see
table 7.3).
7.4.2
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space: Figure 7.4 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word transfer instruction is performed as two
byte accesses, and a longword transfer instruction, as four byte accesses.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
Word size
1st bus cycle
2nd bus cycle
1st bus cycle
Longword size
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 7.4 Access Sizes and Data Alignment Control (8-Bit Access Space)
Rev. 5.00 Mar 28, 2005 page 199 of 1422
REJ09B0234-0500
Section 7 Bus Controller
16-Bit Access Space: Figure 7.5 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword transfer instruction is executed as two word transfer instructions.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Lower data bus
Upper data bus
D15
D8 D7
D0
Byte size
• Even address
Byte size
• Odd address
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 7.5 Access Sizes and Data Alignment Control (16-Bit Access Space)
Rev. 5.00 Mar 28, 2005 page 200 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.4.3
Valid Strobes
Table 7.4 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 7.4
Area
8-bit access
space
Data Buses Used and Valid Strobes
Access Read/
Size
Write
Address
Byte
Read
—
Write
—
16-bit access Byte
space
Read
Even
RD
HWR
RD
Even
Odd
Read
—
Write
—
Upper Data Bus
(D15 to D8)
Lower data bus
(D7 to D0)
Valid
Invalid
Hi-Z
Odd
Write
Word
Valid
Strobe
HWR
LWR
RD
HWR, LWR
Valid
Invalid
Invalid
Valid
Valid
Hi-Z
Hi-Z
Valid
Valid
Valid
Valid
Valid
Notes: Hi-Z: High impedance.
Invalid: Input state; input value is ignored.
Rev. 5.00 Mar 28, 2005 page 201 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.4.4
Basic Timing
8-Bit 2-State Access Space: Figure 7.6 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states cannot be inserted.
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Note: n = 0 to 7
Figure 7.6 Bus Timing for 8-Bit 2-State Access Space
Rev. 5.00 Mar 28, 2005 page 202 of 1422
REJ09B0234-0500
Section 7 Bus Controller
8-Bit 3-State Access Space: Figure 7.7 shows the bus timing for an 8-bit 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Note: n = 0 to 7
Figure 7.7 Bus Timing for 8-Bit 3-State Access Space
Rev. 5.00 Mar 28, 2005 page 203 of 1422
REJ09B0234-0500
Section 7 Bus Controller
16-Bit 2-State Access Space: Figures 7.8 to 7.10 show bus timings for a 16-bit 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address.
Wait states cannot be inserted.
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Note: n = 0 to 7
Figure 7.8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
Rev. 5.00 Mar 28, 2005 page 204 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bus cycle
T1
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
D7 to D0
High impedance
Valid
Note: n = 0 to 7
Figure 7.9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
Rev. 5.00 Mar 28, 2005 page 205 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bus cycle
T1
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Note: n = 0 to 7
Figure 7.10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)
Rev. 5.00 Mar 28, 2005 page 206 of 1422
REJ09B0234-0500
Section 7 Bus Controller
16-Bit 3-State Access Space: Figures 7.11 to 7.13 show bus timings for a 16-bit 3-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address.
Wait states can be inserted.
Bus cycle
T2
T1
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Note: n = 0 to 7
Figure 7.11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
Rev. 5.00 Mar 28, 2005 page 207 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
D7 to D0
High impedance
Valid
Note: n = 0 to 7
Figure 7.12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
Rev. 5.00 Mar 28, 2005 page 208 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Note: n = 0 to 7
Figure 7.13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
Rev. 5.00 Mar 28, 2005 page 209 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.4.5
Wait Control
When accessing external space, the H8S/2633 Group can extend the bus cycle by inserting one or
more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin
wait insertion using the WAIT pin.
Program Wait Insertion
From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an
individual area basis in 3-state access space, according to the settings of WCRH and WCRL.
Pin Wait Insertion
Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. Program
wait insertion is first carried out according to the settings in WCRH and WCRL. Then, if the
WAIT pin is low at the falling edge of φ in the last T2 or Tw state, a Tw state is inserted. If the
WAIT pin is held low, Tw states are inserted until it goes high.
This is useful when inserting four or more Tw states, or when changing the number of Tw states for
different external devices.
The WAITE bit setting applies to all areas.
Rev. 5.00 Mar 28, 2005 page 210 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Figure 7.14 shows an example of wait state insertion timing.
By program wait
T1
T2
Tw
By WAIT pin
Tw
Tw
T3
φ
WAIT
Address bus
AS
RD
Read
Data bus
Read data
HWR, LWR
Write
Data bus
Note:
Write data
indicates the timing of WAIT pin sampling.
Figure 7.14 Example of Wait State Insertion Timing
The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT
input disabled. At a manual reset, the bus control register values are retained and wait control
continues as before the reset.
Rev. 5.00 Mar 28, 2005 page 211 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.5
DRAM Interface (This function is not available in the H8S/2695)
7.5.1
Overview
This LSI allows area 2 to 5 external space to be set as DRAM space and DRAM interfacing to be
performed. With the DRAM interface, DRAM can be directly connected to the LSI. BCRH
RMTS2 to RMTS0 allow the setting up of 2, 4, or 8MB DRAM space. Burst operation is possible
using high-speed page mode.
7.5.2
Setting up DRAM Space
To set up areas 2 to 5 as DRAM space, set the RMTS2 to RMTS0 bits of BCRH. Table 7.5 shows
the relationship between the settings of the RMTS2 to RMTS0 bits and DRAM space. You can
select (1) one area (area 2), (2) two areas (areas 2 and 3), or (3) four areas (areas 2 to 5).
Using 16 64M DRAMs requires a 4M word (8MB) contiguous space. Setting RMTS2 to RMTS0
to 1 allows areas 2 to 5 to be configured as one contiguous DRAM space. The RAS signal can be
output from the CS2 pin, and CS3 to CS5 can be used as input ports. In this configuration, the bus
widths are the same for areas 2 to 5.
Table 7.5
RMTS2 to RMTS0 Settings vs DRAM Space
RMTS2
RMTS1
RMTS0
Area 5
0
0
1
Normal space
1
0
Normal space
1
DRAM space
1
Contiguous
DRAM space
1
1
Rev. 5.00 Mar 28, 2005 page 212 of 1422
REJ09B0234-0500
Area 4
Area 3
Area 2
Normal space
Normal space
DRAM space
Normal space
DRAM space
DRAM space
DRAM space
DRAM space
DRAM space
Contiguous
DRAM space
Contiguous
DRAM space
Contiguous
DRAM space
Section 7 Bus Controller
7.5.3
Address Multiplexing
In the case of DRAM space, the row address and column address are multiplexed. With address
multiplexing, the MXC1 and MXC0 bits of the MCR select the amount of shift in the row address.
Table 7.6 shows the relationship between MXC1 and MXC0 settings and the shift amount.
Table 7.6
MXC1 and MXC0 Settings vs Address Multiplexing
MCR
Shift
MXC1 MXC0 Amount
Address Pin
A23 to A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A8
Row
0
address
0
8 bits
A23 to A13 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
1
9 bits
A23 to A13 A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
1
0
10 bits
A23 to A13 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
1
Do not set
—
—
—
—
—
—
—
—
—
—
—
—
—
A23 to A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Column —
address
7.5.4
—
—
—
Data Bus
Setting the ABWCR bit of an area set as DRAM space to 1 sets the corresponding area as 8-bit
DRAM space. Clearing the ABWCR bit to 0 sets the area as 16-bit DRAM. 16-bit DRAMs can be
directly connected in the case of 16-bit DRAM space.
With 8-bit DRAM space, the high data bus byte (D15 to D8) is valid. With 16-bit DRAM space,
the high and low data bus bytes (D15 to D0) are valid.
The access size and data alignment are the same as for the standard bus interface. See section
7.4.2, Data Size and Data Alignment for details.
Rev. 5.00 Mar 28, 2005 page 213 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.5.5
DRAM Interface Pins
Table 7.7 shows the pins used for the DRAM interface, and their functions.
Table 7.7
DRAM Interface Pin Configuration
Pin
In DRAM
Mode
Name
Direction
Function
HWR
WE
Write enable
Output
Write enable when accessing
DRAM space in 2 CAS mode
LCAS
LCAS
CS2
Lower column address Output
strobe
Lower column address strobe signal
when accessing 16-bit DRAM
space
RAS2
Row address strobe 2 Output
Row address strobe when area 2
set as DRAM space
CS3
RAS3
Row address strobe 3 Output
Row address strobe when area 3
set as DRAM space
CS4
RAS4
Row address strobe 4 Output
Row address strobe when area 4
set as DRAM space
CS5
RAS5
Row address strobe 5 Output
Row address strobe when area 5
set as DRAM space
CAS
UCAS
Upper column address Output
strobe
Upper column address strobe when
accessing DRAM space
WAIT
WAIT
Wait
Input
Wait request signal
A12 to A0
A12 to A0
Address pin
Output
Multiplexed output of row address
and column address
D15 to D0
D15 to D0
OE*
Data pin
Input/output Data input/output pin
Output enable pin
Output
OE
Output enable signal when
accessing DRAM space in read
mode
Note: * Valid when OES bit set to 1.
7.5.6
Basic Timing
Figure 7.15 shows the basic access timing for DRAM space. There are four basic DRAM timing
states. In contrast to the standard bus interface, the corresponding ASTCR bit only controls the
enabling/disabling of wait insertion and has no effect on the number of access states. When the
corresponding ASTCR bit is cleared to 0, no wait states can be inserted in the DRAM access
cycle.
Rev. 5.00 Mar 28, 2005 page 214 of 1422
REJ09B0234-0500
Section 7 Bus Controller
The four basic timing states are as follows: TP (precharge cycle) 1 state, Tr (row address output
cycle) 1 state, Tc1 and Tc2 (column address output cycle) two states.
When RCTS is set to 1, the CAS signal timing differs when reading and writing, being asserted Ω
cycle earlier when reading.
Tp
Tr
Tc1
Tc2
φ
A23 to A0
row
column
AS
CSn (RAS)
RCTS= 0
CAS, LCAS
RCTS= 1
HWR (WE)
Read
RD
D15 toD0
CAS, LCAS
HWR (WE)
Write
RD
D15 to D0
Note: n = 2 to 5
Figure 7.15 Basic Access Timing
Rev. 5.00 Mar 28, 2005 page 215 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.5.7
Precharge State Control
When accessing DRAM, it is essential to secure a time for RAS precharging. In this LSI, it is
therefore necessary to insert 1 TP state when accessing DRAM space. By setting the TPC bit of the
MCR to 1, TP can be changed from 1 state to 2 states. Set the appropriate number of TP cycles
according to the type of DRAM connected and the operation frequency of the LSI. Figure 7.16
shows the timing when TP is set for 2 states.
Setting the TPC bit to 1 also sets the refresh cycle TP to 2 states.
Tp1
Tp2
Tr
Tc1
Tc2
φ
A23 to A0
row
column
CSn (RAS)
RCTS = 0
CAS, LCAS
RCTS = 1
Read
HWR (WE)
D15 to D0
CAS, LCAS
Write
HWR (WE)
D15 to D0
Note: n = 2 to 5
Figure 7.16 Timing With Two Precharge Cycles
Rev. 5.00 Mar 28, 2005 page 216 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.5.8
Wait Control
There are two methods of inserting wait states in DRAM access: (1) insertion of program wait
states, and (2) insertion of pin waits via WAIT pin.
(1) Insertion of Program Wait States
Setting the ASTCR bit of an area set for DRAM to 1 automatically inserts from 0 to 3 wait states,
as set by WCRH and WCRL, between the Tc1 state and Tc2 state.
When a program wait is inserted, the write wait function is activated and only the CAS signal is
output only during the Tc2 state when writing.
Figure 7.17 shows example timing for the insertion of program waits.
Program
waits
Tp
Tr
Tc1
Tw
Tw
Tc2
φ
Address bus
AS
CSn (RAS)
RCTS = 0
CAS, LCAS
RCTS = 1
Read
RD
Data bus
Read data
CAS, LCAS
Write
HWR (WE)
Data bus
Write data
Note: ↓ shows timing for WAIT pin sampling.
n = 2 to 5
Figure 7.17 Example Program Wait Insertion Timing (Wait 2 State Insertion)
Rev. 5.00 Mar 28, 2005 page 217 of 1422
REJ09B0234-0500
Section 7 Bus Controller
(2) Insertion of Pin Waits
When the WAITE bit of BCRH is set to 1, wait input via the WAIT pin is valid regardless of the
ASTCR AST bit. In this state, a program wait is inserted when the DRAM space is accessed. If the
WAIT pin level is Low at the fall in φ in the final Tc1 or Tw state, a further Tw is inserted. If the
level of the WAIT pin is kept Low, Tw is inserted until the level of the WAIT pin changes to High.
When wait states are inserted via the WAIT pin, the CAS when writing is output after the Tw state.
Figure 7.18 shows example timing for the insertion of wait states via the WAIT pin.
Tp
Tr
Program
waits
Tc1
Tw
WAIT pin wait states
Tw
Tc2
φ
Address bus
AS
CSn (RAS)
RCTS = 0
CAS, LCAS
RCTS = 1
Read
RD
Data bus
Read data
CAS, LCAS
Write
HWR (WE)
Data bus
Write data
Note: ↓ shows timing for WAIT pin sampling.
n = 2 to 5
Figure 7.18 Example Timing for Insertion of Wait States via WAIT Pin
Rev. 5.00 Mar 28, 2005 page 218 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.5.9
Byte Access Control
When 16-bit DRAMs are connected, the 2 CAS method can be used as the control signal required
for byte access.
Figure 7.19 shows the 2 CAS method control timing. Figure 7.20 shows an example of connecting
DRAM in high-speed page mode.
When all areas selected as DRAM space are set as 8-bit space, the LCAS pin functions as an I/O
port.
Tp
Tr
Tc1
Tc2
φ
A23 to A0
row
column
CSn (RAS)
CAS
Byte control
LCAS
HWR (WE)
Note: n = 2 to 5
Figure 7.19 2 CAS Method Control Timing (For High Byte Write Access)
When using DRAM EDO page mode, either use OE to control the read data or, as shown in figure
7.20, select RAS up mode. Figure 7.21 is an example of DRAM connection in EDO page mode
when OES=1.
Rev. 5.00 Mar 28, 2005 page 219 of 1422
REJ09B0234-0500
Section 7 Bus Controller
This LSI
(address shift set to 9 bits)
CS (RAS)
2CAS 4-Mbit DRAM
256 kbytes × 16-bit configuration
9-bit column address
RAS
CAS
UCAS
LCAS
LCAS
HWR (WE)
WE
A9
A8
A8
A7
A7
A6
A6
A5 (Column address input: A8 to A0)
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
D15 to D0
(Row address input: A8 to A0)
D15 to D0
OE
Figure 7.20 High-speed Page Mode DRAM
Rev. 5.00 Mar 28, 2005 page 220 of 1422
REJ09B0234-0500
Section 7 Bus Controller
This LSI
(address shift set to 10 bits)
CS2 (RAS)
RAS
CAS
UCAS
LCAS
LCAS
HWR (WE)
A10
CS3 (OE)
2CAS 16-Mbit DRAM
1 Mbyte × 16-bit configuration
10-bit column address
WE
A9
A9
A8
A8
A7
A7
A6
A6 (Row address input: A9 to A0)
A5 (Column address input: A9 to A0)
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
D15 to D0
D15 to D0
OE
Figure 7.21 Example Connection of EDO Page Mode DRAM (OES=1)
7.5.10
Burst Operation
In addition to full DRAM access (normal DRAM access), in which the row address is output each
time the data in DRAM is accessed, there is also a high-speed page mode that allows high-speed
access (burst access). In this method, if the same row address is accessed successively, the row
address is output once and then only the column address is changed. Burst access is selected by
setting the BE bit of the MCR to 1.
Rev. 5.00 Mar 28, 2005 page 221 of 1422
REJ09B0234-0500
Section 7 Bus Controller
(1) Operation Timing for Burst Access (High-Speed Page Mode)
Figure 7.22 shows the operation timing for burst access. When the DRAM space is successively
accessed, the CAS signal and column address output cycle (2 states) are continued as long as the
row address is the same in the preceding and succeeding access cycles. The MXC1 and MXC0
bits of the MCR specify which row address is compared.
Tp
Tr
Tc1
Tc2
Tc1
Tc2
φ
A23 to A0
row
column1
column2
AS
CSn (RAS)
RCTS = 0
CAS, LCAS
RCTS = 1
HWR (WE)
Read
OE*
D15 to D0
CAS, LCAS
HWR (WE)
Write
OE
D15 to D0
Notes: n = 2 to 5
* OE is enabled when OES = 1.
Figure 7.22 Operating Timing in High-Speed Page Mode
The bus cycle can also be extended in burst access by inserting wait states. The method and timing
of inserting the wait states is the same as in full access. For details, see section 7.5.8, Wait
Control.
Rev. 5.00 Mar 28, 2005 page 222 of 1422
REJ09B0234-0500
Section 7 Bus Controller
(2) RAS Down Mode and RAS Up Mode
Even when burst operation is selected, DRAM access may not be continuous, but may be
interrupted by accessing another area. In this case, burst operation can be continued by keeping the
RAS signal level Low while the other area is accessed and then accessing the same row address in
the DRAM space.
• RAS down mode
To select RAS down mode, set the RCDM bit of the MCR to 1. When DRAM access is
interrupted and another area accessed, the RAS signal level is kept Low and, if the row address
is the same as previously when the DRAM space is again accessed, burst access is continued.
Figure 7.23 shows example RAS down mode timing.
Note that if the refresh operation occurs when RAS is down, the RAS signal level changes to
High.
DRAM
read access
Tp
Tr
External space
read access
Tc1
Tc2
T1
T2
DRAM
write access
Tc1
Tc2
φ
A23 to A0
RD
HWR (WE)
CSn (RAS)
RCTS = 0
CAS, LCAS
RCTS = 1
OE*
D15 to D0
Notes: n = 2 to 5
* OE is enabled when OES = 1.
Figure 7.23 Example Operation Timing in RAS Down Mode
Rev. 5.00 Mar 28, 2005 page 223 of 1422
REJ09B0234-0500
Section 7 Bus Controller
• RAS up mode
To select RAS up mode, clear the RCDM bit of the MCR to 0. If DRAM access is interrupted
to access another area, the RAS signal level returns to High. Burst operation is only possible
when the DRAM space is contiguous. Figure 7.24 shows example timing in RAS up mode.
Note that the RAS signal level does not return to High in burst ROM space access.
Tp
DRAM
write access
Tr
Tc1
Tc2
DRAM
read access
Tc1
Tc2
External space
write access
T1
T2
φ
A23 to A0
RD
HWR (WE)
CSn (RAS)
CAS, LCAS
D15 to D0
Note: n = 2 to 5
Figure 7.24 Example Operation Timing in RAS Up Mode
Rev. 5.00 Mar 28, 2005 page 224 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.5.11
Refresh Control
This LSI has a DRAM refresh control function. There are two refresh methods: (1) CAS-beforeRAS (CBR) and (2), self refresh.
(1) CAS-Before-RAS (CBR) Refresh
To select CBR refresh, set the RFSHE bit of DRAMCR to 1 and clear the RMODE bit to 0.
In CBR refresh, the input clock selected with the CKS2 to CKS0 bits of DRAMCR are used for
the RTCNT count-up. Refresh control is performed when the count reaches the value set in
RTCOR (compare match). The RTCNT is then reset and the count again started from H'00. That
is, the refresh is repeated at the set interval determined by RTCOR and CKS2 to CKS0. Set
RTCOR and CKS2 to CKS0 to satisfy the refresh cycle for the DRAM being used.
The RTCNT count up starts when the CKS2 to CKS0 bits are set. The RTCNT and RTCOR
values should therefore be set before setting CKS2 to CKS0. When a value is set in RTCOR,
RTCNT is cleared. When RTCNT is set at the same time that it is reset by a compare match, the
value written to RTCNT takes precedence.
When performing refresh control (RFSHE = 1), do not clear the CMF flag.
Figure 7.25 shows RTCNT operation. Figure 7.26 shows compare match timing. And figure 7.27
show CBR refresh timing.
Some types of DRAM do not allow the WE signal to be changed during the refresh cycle. In this
case, set CBRM to 1. Figure 7.28 shows the timing. The CS signal is not controlled and a Low
level is output when an access request occurs.
Note that other normal spaces are accessed during the CBR refresh cycle.
RTCNT
RTCOR
H'00
Refresh request
Figure 7.25 RTCNT Operation
Rev. 5.00 Mar 28, 2005 page 225 of 1422
REJ09B0234-0500
Section 7 Bus Controller
φ
RTCNT
N
H'00
RTCOR
N
Refresh request
signal and CMF
bit setting signal
Figure 7.26 Compare Match Timing
Read access of
normal space
Write access of
normal space
φ
A23 to A0
CS
AS
RD
HWR (WE)
Refresh cycle
RAS
CAS
Figure 7.27 Example CBR Refresh Timing (CBRM=0)
Rev. 5.00 Mar 28, 2005 page 226 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Normal space access request
φ
A23 to A0
CS
AS
RD
HWR (WE)
Refresh cycle
RAS
CAS
Figure 7.28 Example CBR Refresh Timing (CBRM=1)
Rev. 5.00 Mar 28, 2005 page 227 of 1422
REJ09B0234-0500
Section 7 Bus Controller
(2) Self-Refresh
One of the DRAM standby modes is the self-refresh mode (battery backup mode), in which the
DRAM generates its own refresh timing and refresh address.
To select self-refresh, set the RFSHE bit and RMODE bits of the DRAMCR to 1. Next, execute a
SLEEP instruction to make a transition to software standby mode. As shown in figure 7.29, the
CAS and RAS signals are output and the DRAM enters self-refresh mode.
When you exit software standby mode, the RMODE bit is cleared to 0 and self-refresh mode is
exited.
When making a transition to software standby mode, self-refresh mode starts after a CBR refresh,
providing there is a CBR refresh request. CBR refresh requests occurring immediately before
entering software standby mode are cleared on completion of the self-refresh when the software
standby mode is exited.
Software standby
TRp
TRcr
TRc3
φ
CSn (RAS)
CAS, LCAS
HWR (WE)
High level
Note: n = 2 to 5
Figure 7.29 Self-Refresh Timing
Rev. 5.00 Mar 28, 2005 page 228 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.6
DMAC Single Address Mode and DRAM Interface
(This function is not available in the H8S/2695)
When burst mode is set for the DRAM interface, the DDS bit selects the output timing for the
DACK signal. It also selects whether or not to perform burst access when accessing the DRAM
space in DMAC single address mode.
7.6.1
DDS=1
Burst access is performed on the basis of the address only, regardless of the bus master. The
DACK output level changes to Low afer the Tc1 state in the case of the DRAM interface.
Figure 7.30 shows the DACK output timing for the DRAM interface when DDS = 1.
Tp
Tr
Tc1
Tc2
φ
A23 to A0
row
column
CSn (RAS)
CAS (UCAS)
LCAS (LCAS)
RCTS = 0
RCTS = 1
Read
HWR (WE)
D15 to D0
CAS (UCAS)
LCAS (LCAS)
Write
HWR (WE)
D15 to D0
DACK
Note: n = 2 to 5
Figure 7.30
DACK Output Timing when DDS=1 (Example Showing DRAM Access)
Rev. 5.00 Mar 28, 2005 page 229 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.6.2
DDS=0
When the DRAM space is accessed in DMAC single address mode, always perform full access
(normal access). The DACK output level changes to Low afer the Tr state in the case of the
DRAM interface.
In other than DMAC signle address mode, burst access is possible when the DRAM space is
accessed.
Figure 7.31 shows the DACK output timing for the DRAM interface when DDS = 0.
Tp
Tr
Tc1
Tc2
φ
A23 to A0
row
column
CSn (RAS)
RCTS = 0
CAS (UCAS)
LCAS (LCAS)
RCTS = 1
Read
HWR (WE)
D15 to D0
CAS (UCAS)
LCAS (LCAS)
Write
HWR (WE)
D15 to D0
DACK
Note: n = 2 to 5
Figure 7.31
DACK Output Timing when DDS=0 (Example Showing DRAM Access)
Rev. 5.00 Mar 28, 2005 page 230 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.7
Burst ROM Interface
7.7.1
Overview
In this LSI, the area 0 external space can be set as burst ROM space and burst ROM interfacing
performed. Burst ROM space interfacing allows 16-bit ROM capable of burst access to be
accessed at high-speed.
The BRSTRM bit of BCRH sets area 0 as burst ROM space. CPU instruction fetches (only) can be
performed using a maximum of 4-word or 8-word continuous burst access. 1 state or 2 states can
be selected in the case of burst access.
7.7.2
Basic Timing
The AST0 bit of ASTCR sets the number of access states in the initial cycle (full access) of the
burst ROM interface. Wait states can be inserted when the AST0 bit is set to 1. The burst cycle
can be set for 1 state or 2 sttes by setting the BRSTS1 bit of BCRH. Wait states cannot be inserted.
When area 0 is set as burst ROM space, area 0 is a 16-bit access space regardless of the ABW0 bit
of ABWCR.
When the BRSTS0 bit of BCRH is cleared to 0, 4-word max. burst access is performed. When the
BRSTS0 bit is set to 1, 8-word max. burst access is performed.
Figures 7.32 (a) and (b) show the basic access timing for the burst ROM space.
Figure 7.32 (a) is an example when both the AST0 and BRSTS1 bits are set to 1.
Figure 7.32 (b) is an example when both the AST0 and BRSTS1 bits are set to 0.
Rev. 5.00 Mar 28, 2005 page 231 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Full access
T1
T2
Burst access
T3
T1
T2
T1
T2
φ
Low address only changes
Address bus
CS0
AS
RD
Data bus
Read data
Read data
Read data
Figure 7.32 (a) Example Burst ROM Access Timing (AST0=BRSTS1=1)
Rev. 5.00 Mar 28, 2005 page 232 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Full access
T1
T2
Burst access
T1
T1
φ
Low address only changes
Address bus
CS0
AS
RD
Data bus
Read data
Read data Read data
Figure 7.32 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0)
7.7.3
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.4.5, Wait
Control.
Wait states cannot be inserted in the burst cycle.
Rev. 5.00 Mar 28, 2005 page 233 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.8
Idle Cycle
7.8.1
Operation
When the H8S/2633 Group accesses external space, it can insert a 1-state idle cycle (TI) between
bus cycles in the following two cases: (1) when read accesses between different areas occur
consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an
idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output
floating time, and high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the second read cycle.
Figure 7.33 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Bus cycle A
φ
T1
T2
Bus cycle B
T3
T1
Bus cycle A
T2
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
Data bus
Data bus
Long output
floating time
T1
T2
T3
Bus cycle B
TI
T1
Data
collision
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 7.33 Example of Idle Cycle Operation (1)
Rev. 5.00 Mar 28, 2005 page 234 of 1422
REJ09B0234-0500
T2
Section 7 Bus Controller
(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle.
Figure 7.34 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
φ
T1
T2
T3
Bus cycle B
T1
T2
Bus cycle A
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
T1
T2
T3
Bus cycle B
TI
T1
T2
Possibility of overlap between
CS (area B) and RD
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 7.34 Example of Idle Cycle Operation (2)
Rev. 5.00 Mar 28, 2005 page 235 of 1422
REJ09B0234-0500
Section 7 Bus Controller
(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 7.35.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A
φ
T1
T2
Bus cycle B
T3
T1
Bus cycle A
T2
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
HWR
HWR
Data bus
Data bus
Long output
floating time
T1
T2
T3
Bus cycle B
TI
T1
Data
collision
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 7.35 Relationship between Chip Select (CS) and Read (RD)
Rev. 5.00 Mar 28, 2005 page 236 of 1422
REJ09B0234-0500
T2
Section 7 Bus Controller
(4) Notes
The setting of the ICIS0 and ICIS1 bits is invalid when accessing the DRAM space. For example,
if the 2nd of successive reads of different areas is a DRAM access, only the TP cycle is inserted,
not the T1 cycle. Figure 7.36 shows the timing. Note, however, that ICIS0 and ICIS1 settings are
valid in burst access in RAS down mode, and an idle cycle is inserted. Figures 7.37 (a) and (b)
show the timing.
External read
T1
T2
T3
DRAM space read
Tp
Tr
Tc1
Tc2
φ
Address bus
RD
Data bus
Figure 7.36 Example of DRAM Access after External Read
External read
DRAM space read
Tp
Tr
Tc1
Tc2
T1
T1
T2
DRAM space read
T3
Tc1
Tc1
Tc2
EXTAL
Address
RD
RAS
CAS, LCAS
Data bus
Idle cycle
Figure 7.37 (a) Example Idle Cycle Operation in RAS Down Mode (ICIS1=1)
Rev. 5.00 Mar 28, 2005 page 237 of 1422
REJ09B0234-0500
Section 7 Bus Controller
External read
DRAM space read
Tp
Tr
Tc1
Tc2
T1
T1
T2
DRAM space read
T3
Tc1
Tc1
Tc2
EXTAL
Address
RD
HWR
RAS
CAS, LCAS
Data bus
Idle cycle
Figure 7.37 (b) Example Idle Cycle Operation in RAS Down Mode (ICIS0=1)
7.8.2
Pin States in Idle Cycle
Table 7.8 shows pin states in an idle cycle.
Table 7.8
Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of next bus cycle
D15 to D0
High impedance
High*
CSn
CAS
AS
RD
HWR
LWR
DACKn
High
High
High
High
High
High
Note: * Remains low in DRAM space RAS down mode or a refresh cycle.
Rev. 5.00 Mar 28, 2005 page 238 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.9
Write Data Buffer Function
The H8S/2633 Group has a write data buffer function in the external data bus. Using the write data
buffer function enables external writes and DMA single address mode transmission to be executed
in parallel with internal accesses. The write data buffer function is made available by setting the
WDBE bit in BCRL to 1.
Figure 7.38 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external write and DMA single address mode transmission continues for 2
states or longer, and there is an internal access next, only an external write is executed in the first
state, but from the next state onward an internal access (on-chip memory or internal I/O register
read/write) is executed in parallel with the external write rather than waiting until it ends.
On-chip memory read Internal I/O register read
External write cycle
T1
T2
TW
TW
T3
Internal address bus
Internal memory
Internal I/O register address
Internal read signal
A23 to A0
External
space
write
External address
CSn
HWR, LWR
D15 to D0
Figure 7.38 Example of Timing when Write Data Buffer Function is Used
Rev. 5.00 Mar 28, 2005 page 239 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.10
Bus Release
7.10.1
Overview
The H8S/2633 Group can release the external bus in response to a bus request from an external
device. In the external bus released state, the internal bus master continues to operate as long as
there is no external access.
If an internal bus master wants to make an external access and when a refresh request occurs in the
external bus released state, it can issue a bus request off-chip.
7.10.2
Operation
In external expansion mode, the bus can be released to an external device by setting the BRLE bit
in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2633 Group.
When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the
address bus, data bus, and bus control signals are placed in the high-impedance state, establishing
the external bus-released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus request from the external bus master to be
dropped. Also, when a refresh request occurs in the external bus released state, refresh control is
deferred until the external bus master drops the bus request.
If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external
access and when a refresh request occurs in the external bus released state, the BREQO pin is
driven low and a request can be made off-chip to drop the bus request.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
The following shows the order of priority when an external bus release request, refresh request,
and external access by the internal bus master occur simultaneously:
When CBRM=1
(High) Refresh > External bus release > External access by internal bus master (Low)
When CBRM=0
(High) Refresh > External bus release (Low)
(High) External bus release > External access by internal bus master (Low)
Note: A refresh can be executed at the same time as external access by the internal bus master.
Rev. 5.00 Mar 28, 2005 page 240 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.10.3
Pin States in External Bus Released State
Table 7.9 shows pin states in the external bus released state.
Table 7.9
Pin States in Bus Released State
Pins
Pin State
A23 to A0
High impedance
D15 to D0
High impedance
CSn
CAS
AS
RD
HWR
LWR
DACKn
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High
Rev. 5.00 Mar 28, 2005 page 241 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.10.4
Transition Timing
Figure 7.39 shows the timing for transition to the bus-released state.
CPU cycle
T0
T1
CPU
cycle
External bus released state
T2
φ
High impedance
Address bus
Address
High impedance
Data bus
High impedance
CSn
High impedance
AS
High impedance
RD
High impedance
HWR, LWR
BREQ
BACK
BREQO*
Minimum
1 state
[1]
[2]
[3]
[1]
Low level of BREQ pin is sampled at rise of T2 state.
[2]
BACK pin is driven low at end of CPU read cycle, releasing bus to external
[4]
bus master.
[3]
BREQ pin state is still sampled in external bus released state.
[4]
High level of BREQ pin is sampled.
[5]
BACK pin is driven high, ending bus release cycle.
[6]
BREQO signal goes high 1.5 clocks after BACK signal goes high.
Note: * Output only when BREQOE is set to 1.
Figure 7.39 Bus-Released State Transition Timing
Rev. 5.00 Mar 28, 2005 page 242 of 1422
REJ09B0234-0500
[5]
[6]
Section 7 Bus Controller
DRAM space read access
External bus released
φ
A23 to A0
CS
AS
RD
RAS
CAS
BREQ
BACK
Figure 7.40 Example Bus Release Transition Timing After DRAM Access (Reading
DRAM)
7.10.5
Notes
The external bus release function is deactivated when MSTPCR is set to H'FFFFFF or H'EFFFFF
and a transition is made to sleep mode. To use the external bus release function in sleep mode, do
not set MSTPCR to H'FFFFFF and H'EFFFFF.
When the CBRM bit is set to 1 to use the CBR refresh function, set the BREQ = 1 width greater
than the number of the slowest external access states. Otherwise, CBR refresh requests from the
refresh timer may not be performed.
Rev. 5.00 Mar 28, 2005 page 243 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.11
Bus Arbitration
(DMAC and DTC functions are not available in the H8S/2695)
7.11.1
Overview
The H8S/2633 Group has a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU, DTC, and DMAC which perform read/write operations when
they have possession of the bus. Each bus master requests the bus by means of a bus request
signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by
means of a bus request acknowledge signal. The selected bus master then takes possession of the
bus and begins its operation.
7.11.2
Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master making the request. If there are bus requests
from more than one bus master, the bus request acknowledge signal is sent to the one with the
highest priority. When a bus master receives the bus request acknowledge signal, it takes
possession of the bus until that signal is canceled.
The order of priority of the bus masters is as follows:
(High)
DMAC
>
DTC
>
CPU
(Low)
An internal bus access by an internal bus master, external bus release, and refresh can be executed
in parallel.
In the event of simultaneous external bus release request, refresh request, and internal bus master
external access request generation, the order of priority is as follows:
When CBRM = 1
(High) Refresh > External bus release > External access by internal bus master (Low)
When CBRM = 0
(High) Refresh > External bus release (Low)
(High) External bus release > External access by internal bus master (Low)
Rev. 5.00 Mar 28, 2005 page 244 of 1422
REJ09B0234-0500
Section 7 Bus Controller
7.11.3
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC
and DMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing
for transfer of the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the operations. See appendix A.5, Bus States During Instruction Execution, for timings at
which the bus is not transferred.
• If the CPU is in sleep mode, it transfers the bus immediately.
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
DMAC: When a start request occurs, the DMAC requests the bus arbiter for bus privileges.
The DMAC releases bus privileges on completion of one transmission in short address mode,
normal mode external requests, and cycle steal mode.
The DMAC releases the bus on completion of the transmission of one block in block transmission
mode, or after a transmission in burst mode.
7.12
Resets and the Bus Controller
In a power-on reset, the H8S/2633 Group, including the bus controller, enters the reset state at that
point, and an executing bus cycle is discontinued.
The bus controller registers and internal states are retained at a manual reset. The current external
bus cycle is executed to completion. The WAIT input is ignored. Write data is not retained. Also,
because the DMAC* is initialized at a manual reset, DACK* and TEND* outputs are disabled and
function as I/O ports controlled by DDR and DR.
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 245 of 1422
REJ09B0234-0500
Section 7 Bus Controller
Rev. 5.00 Mar 28, 2005 page 246 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
8.1
Overview
The H8S/2633 Group has a built-in DMA controller (DMAC) which can carry out data transfer on
up to 4 channels.
8.1.1
Features
The features of the DMAC are listed below.
• Choice of short address mode or full address mode
Short address mode
 Maximum of 4 channels can be used
 Choice of dual address mode or single address mode
 In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as16 bits
 In single address mode, transfer source or transfer destination address only is specified as
24 bits
 In single address mode, transfer can be performed in one bus cycle
 Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode
Full address mode
 Maximum of 2 channels can be used
 Transfer source and transfer destination address specified as 24 bits
 Choice of normal mode or block transfer mode
• 16-Mbyte address space can be specified directly
• Byte or word can be set as the transfer unit
• Activation sources: internal interrupt, external request, auto-request (depending on transfer
mode)
 Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts
 Serial communication interface (SCI0, SCI1) transmit-data-empty interrupt, reception
complete interrupt
 A/D converter conversion end interrupt
 External request
Rev. 5.00 Mar 28, 2005 page 247 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
 Auto-request
• Module stop mode can be set
 The initial setting enables DMAC registers to be accessed. DMAC operation is halted by
setting module stop mode
8.1.2
Block Diagram
A block diagram of the DMAC is shown in figure 8.1.
Internal address bus
Address buffer
DMAWER
DMACR0A
DMACR0B
DMACR1A
DMACR1B
DMABCR
Channel 1
DMATCR
Data buffer
Internal data bus
Legend:
DMAWER:
DMATCR:
DMABCR:
DMACR:
MAR:
IOAR:
ETCR:
DMA write enable register
DMA terminal control register
DMA band control register (for all channels)
DMA control register
Memory address register
I/O address register
Executive transfer counter register
Figure 8.1 Block Diagram of DMAC
Rev. 5.00 Mar 28, 2005 page 248 of 1422
REJ09B0234-0500
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
Module data bus
Control logic
Channel 0
Processor
Channel 1B Channel 1A Channel 0B Channel 0A
Internal interrupts
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
TXI0
RXI0
TXI1
RXI1
ADI
External pins
DREQ0
DREQ1
TEND0
TEND1
DACK0
DACK1
Interrupt signals
DEND0A
DEND0B
DEND1A
DEND1B
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.1.3
Overview of Functions
Tables 8.1 (1) and (2) summarize DMAC functions in short address mode and full address mode,
respectively.
Table 8.1 (1) Overview of DMAC Functions (Short Address Mode)
Address Register Bit Length
Transfer Mode
Transfer Source
Dual address mode
•
TPU channel 0 to 24/16
5 compare
match/input
capture A interrupt
•
SCI transmit-dataempty interrupt
•
SCI reception
complete interrupt
•
A/D converter
conversion end
interrupt
•
External request
•
External request
•
Sequential mode
 1-byte or 1-word transfer
executed for one transfer request
 Memory address
incremented/decremented by 1
or 2
 1 to 65536 transfers
•
Idle mode
 1-byte or 1-word transfer
executed for one transfer request
 Memory address fixed
Source
Destination
16/24
 1 to 65536 transfers
•
Repeat mode
 1-byte or 1-word transfer
executed for one transfer request
 Memory address incremented/
decremented by 1 or 2
 After specified number of
transfers (1 to 256), initial state is
restored and operation continues
Single address mode
•
1-byte or 1-word transfer executed
for one transfer request
•
Transfer in 1 bus cycle using DACK
pin in place of address specifying I/O
•
Specifiable for sequential, idle, and
repeat modes
24/DACK
DACK/24
Rev. 5.00 Mar 28, 2005 page 249 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Table 8.1 (2) Overview of DMAC Functions (Full Address Mode)
Address Register Bit Length
Transfer Mode
Transfer Source
Source
Destination
•
•
Auto-request
24
24
•
External request
•
TPU channel 0 to 24
5 compare
match/input
capture A interrupt
24
 Either source or destination
specifiable as block area
•
SCI transmit-dataempty interrupt
 Block size: 1 to 256 bytes or
words
•
SCI reception
complete interrupt
•
External request
•
A/D converter
conversion end
interrupt
Normal mode
Auto-request
 Transfer request retained
internally
 Transfers continue for the
specified number of times (1 to
65536)
 Choice of burst or cycle steal
transfer
External request
 1-byte or 1-word transfer
executed for one transfer request
 1 to 65536 transfers
•
Block transfer mode
 Specified block size transfer
executed for one transfer request
 1 to 65536 transfers
Rev. 5.00 Mar 28, 2005 page 250 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.1.4
Pin Configuration
Table 8.2 summarizes the DMAC pins.
In short address mode, external request transfer, single address transfer, and transfer end output
are not performed for channel A.
The DMA transfer acknowledge function is used in channel B single address mode in short
address mode.
When the DREQ pin is used, do not designate the corresponding port for output.
With regard to the DACK pins, setting single address transfer automatically sets the corresponding
port to output, functioning as a DACK pin.
With regard to the TEND pins, whether or not the corresponding port is used as a TEND pin can
be specified by means of a register setting.
Table 8.2
DMAC Pins
Channel
Pin Name
Symbol
I/O
Function
0
DMA request 0
DREQ0
Input
DMAC channel 0 external
request
DMA transfer acknowledge 0
DACK0
Output
DMAC channel 0 single address
transfer acknowledge
TEND0
DREQ1
Output
DMAC channel 0 transfer end
DMA request 1
Input
DMAC channel 1 external
request
DMA transfer acknowledge 1
DACK1
Output
DMAC channel 1 single address
transfer acknowledge
DMA transfer end 1
TEND1
Output
DMAC channel 1 transfer end
DMA transfer end 0
1
Rev. 5.00 Mar 28, 2005 page 251 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.1.5
Register Configuration
Table 8.3 summarizes the DMAC registers.
Table 8.3
DMAC Registers
Channel Name
Abbreviation R/W
Initial
Value
0
Memory address register 0A
MAR0A
R/W
Undefined H'FEE0
16 bits
I/O address register 0A
IOAR0A
R/W
Undefined H'FEE4
16 bits
Transfer count register 0A
ETCR0A
R/W
Undefined H'FEE6
16 bits
Memory address register 0B
MAR0B
R/W
Undefined H'FEE8
16 bits
I/O address register 0B
IOAR0B
R/W
Undefined H'FEEC
16 bits
Transfer count register 0B
ETCR0B
R/W
Undefined H'FEEE
16 bits
Memory address register 1A
MAR1A
R/W
Undefined H'FEF0
16 bits
I/O address register 1A
IOAR1A
R/W
Undefined H'FEF4
16 bits
Transfer count register 1A
ETCR1A
R/W
Undefined H'FEF6
16 bits
Memory address register 1B
MAR1B
R/W
Undefined H'FEF8
16 bits
I/O address register 1B
IOAR1B
R/W
Undefined H'FEFC
16 bits
Transfer count register 1B
ETCR1B
R/W
Undefined H'FEFE
16 bits
DMA write enable register
DMAWER
R/W
H'00
H'FF60
8 bits
DMA terminal control register DMATCR
R/W
H'00
H'FF61
8 bits
DMA control register 0A
DMACR0A
R/W
H'00
H'FF62
16 bits
DMA control register 0B
DMACR0B
R/W
H'00
H'FF63
16 bits
DMA control register 1A
DMACR1A
R/W
H'00
H'FF64
16 bits
DMA control register 1B
DMACR1B
R/W
H'00
H'FF65
16 bits
DMA band control register
DMABCR
R/W
H'0000
H'FF66
16 bits
R/W
H'3F
H'FDE8
8 bits
1
0, 1
Module stop control register A MSTPCRA
Note: * Lower 16 bits of the address.
Rev. 5.00 Mar 28, 2005 page 252 of 1422
REJ09B0234-0500
Address* Bus Width
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.2
Register Descriptions (1) (Short Address Mode)
Short address mode transfer can be performed for channels A and B independently.
Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to
0, as shown in table 8.4. Short address mode or full address mode can be selected for channels 1
and 0 independently by means of bits FAE1 and FAE0.
Table 8.4
Short Address Mode and Full Address Mode (For 1 Channel: Example of
Channel 0)
0
Short address mode specified (channels A and B operate independently)
MAR0A
MAR0B
Specifies transfer source/transfer destination address
IOAR0A
Specifies transfer destination/transfer source address
ETCR0A
Specifies number of transfers
DMACR0A
Specifies transfer size, mode, activation source, etc.
Specifies transfer source/transfer destination address
IOAR0B
Specifies transfer destination/transfer source address
ETCR0B
Specifies number of transfers
DMACR0B
Specifies transfer size, mode, activation source, etc.
Full address mode specified (channels A and B operate in combination)
Channel 0
1
Channel 0A
Description
Channel 0B
FAE0
MAR0A
Specifies transfer source address
MAR0B
Specifies transfer destination address
IOAR0A
IOAR0B
ETCR0A
ETCR0B
DMACR0A DMACR0B
Not used
Not used
Specifies number of transfers
Specifies number of transfers (used in block transfer
mode only)
Specifies transfer size, mode, activation source, etc.
Rev. 5.00 Mar 28, 2005 page 253 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.2.1
Memory Address Registers (MAR)
Bit
:
31
30
29
28
27
26
25
24
MAR
23
22
21
20
19
18
17
16
*
*
*
*
*
*
*
*
:
—
—
—
—
—
—
—
—
Initial value :
0
0
0
0
0
0
0
0
R/W
:
—
—
—
—
—
—
—
— R/W R/W R/W R/W R/W R/W R/W R/W
Bit
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MAR
:
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Initial value :
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
MAR is a 32-bit readable/writable register that specifies the transfer source address or destination
address.
The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified.
Whether MAR functions as the source address register or as the destination address register can be
selected by means of the DTDIR bit in DMACR.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
address specified by MAR is constantly updated. For details, see section 8.2.4, DMA Control
Register (DMACR).
MAR is not initialized by a reset or in standby mode.
Rev. 5.00 Mar 28, 2005 page 254 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.2.2
I/O Address Register (IOAR)
Bit
:
IOAR
:
Initial value :
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source
address or destination address. The upper 8 bits of the transfer address are automatically set to
H'FF.
Whether IOAR functions as the source address register or as the destination address register can
be selected by means of the DTDIR bit in DMACR.
IOAR is invalid in single address mode.
IOAR is not incremented or decremented each time a transfer is executed, so that the address
specified by IOAR is fixed.
IOAR is not initialized by a reset or in standby mode.
Rev. 5.00 Mar 28, 2005 page 255 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.2.3
Execute Transfer Count Register (ETCR)
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of
this register is different for sequential mode and idle mode on the one hand, and for repeat mode
on the other.
(1) Sequential Mode and Idle Mode
Transfer Counter
Bit
:
ETCR
:
Initial value :
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range
of 1 to 65536). ETCR is decremented by 1 each time a transfer is performed, and when the count
reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends.
Rev. 5.00 Mar 28, 2005 page 256 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
(2) Repeat Mode
Transfer Number Storage
Bit
:
ETCRH
:
Initial value :
R/W
:
15
14
13
12
11
10
9
8
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
5
4
3
2
1
0
Transfer Counter
Bit
:
ETCRL
:
Initial value :
R/W
:
7
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
*: Undefined
In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and
transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is
performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this
point, MAR is automatically restored to the value it had when the count was started. The DTE bit
in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is
cleared by the user.
ETCR is not initialized by a reset or in standby mode.
Rev. 5.00 Mar 28, 2005 page 257 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.2.4
DMA Control Register (DMACR)
Bit
:
7
6
5
4
3
2
1
0
DMACR
:
DTSZ
DTID
RPE
DTDIR
DTF3
DTF2
DTF1
DTF0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value :
R/W
:
DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.
DMACR is initialized to H'00 by a reset, and in standby mode.
Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 7
DTSZ
Description
0
Byte-size transfer
1
Word-size transfer
(Initial value)
Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of
MAR every data transfer in sequential mode or repeat mode.
In idle mode, MAR is neither incremented nor decremented.
Bit 6
DTID
Description
0
MAR is incremented after a data transfer
1
•
When DTSZ = 0, MAR is incremented by 1 after a transfer
•
When DTSZ = 1, MAR is incremented by 2 after a transfer
MAR is decremented after a data transfer
•
When DTSZ = 0, MAR is decremented by 1 after a transfer
•
When DTSZ = 1, MAR is decremented by 2 after a transfer
Rev. 5.00 Mar 28, 2005 page 258 of 1422
REJ09B0234-0500
(Initial value)
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the
mode (sequential, idle, or repeat) in which transfer is to be performed.
Bit 5
DMABCR
RPE
DTIE
Description
0
0
Transfer in sequential mode (no transfer end interrupt)
1
Transfer in sequential mode (with transfer end interrupt)
0
Transfer in repeat mode (no transfer end interrupt)
1
Transfer in idle mode (with transfer end interrupt)
1
(Initial value)
For details of operation in sequential, idle, and repeat mode, see section 8.5.2, Sequential Mode,
section 8.5.3, Idle Mode, and section 8.5.4, Repeat Mode.
Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR
to specify the data transfer direction (source or destination). The function of this bit is therefore
different in dual address mode and single address mode.
DMABCR
Bit 4
SAE
DTDIR
Description
0
0
Transfer with MAR as source address and IOAR as destination
address
(Initial value)
1
Transfer with IOAR as source address and MAR as destination address
0
Transfer with MAR as source address and DACK pin as write strobe
1
1
Transfer with DACK pin as read strobe and MAR as destination address
Rev. 5.00 Mar 28, 2005 page 259 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor
(activation source). There are some differences in activation sources for channel A and for channel
B.
Channel A
Bit 3
Bit 2
Bit 1
Bit 0
DTF3
DTF2
DTF1
DTF0
Description
0
0
0
0
—
1
Activated by A/D converter conversion end interrupt
1
0
—
1
—
0
Activated by SCI channel 0 transmit-data-empty interrupt
1
Activated by SCI channel 0 reception complete interrupt
0
Activated by SCI channel 1 transmit-data-empty interrupt
1
Activated by SCI channel 1 reception complete interrupt
0
Activated by TPU channel 0 compare match/input capture
A interrupt
1
Activated by TPU channel 1 compare match/input capture
A interrupt
0
Activated by TPU channel 2 compare match/input capture
A interrupt
1
Activated by TPU channel 3 compare match/input capture
A interrupt
0
Activated by TPU channel 4 compare match/input capture
A interrupt
1
Activated by TPU channel 5 compare match/input capture
A interrupt
0
—
1
—
1
0
1
1
0
0
1
1
0
1
Rev. 5.00 Mar 28, 2005 page 260 of 1422
REJ09B0234-0500
(Initial value)
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Channel B
Bit 3
Bit 2
Bit 1
Bit 0
DTF3
DTF2
DTF1
DTF0
Description
0
0
0
0
—
1
Activated by A/D converter conversion end interrupt
Activated by DREQ pin falling edge input*
1
1
0
1
1
0
0
1
1
0
1
0
(Initial value)
1
Activated by DREQ pin low-level input
0
Activated by SCI channel 0 transmit-data-empty interrupt
1
Activated by SCI channel 0 reception complete interrupt
0
Activated by SCI channel 1 transmit-data-empty interrupt
1
Activated by SCI channel 1 reception complete interrupt
0
Activated by TPU channel 0 compare match/input capture
A interrupt
1
Activated by TPU channel 1 compare match/input capture
A interrupt
0
Activated by TPU channel 2 compare match/input capture
A interrupt
1
Activated by TPU channel 3 compare match/input capture
A interrupt
0
Activated by TPU channel 4 compare match/input capture
A interrupt
1
Activated by TPU channel 5 compare match/input capture
A interrupt
0
—
1
—
Note: * Detected as a low level in the first transfer after transfer is enabled.
The same factor can be selected for more than one channel. In this case, activation starts with the
highest-priority channel according to the relative channel priorities. For relative channel priorities,
see section 8.5.13, DMAC Multi-Channel Operation.
Rev. 5.00 Mar 28, 2005 page 261 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.2.5
Bit
DMA Band Control Register (DMABCR)
:
15
14
13
12
11
10
9
8
DMABCRH :
FAE1
FAE0
SAE1
SAE0
DTA1B
DTA1A
DTA0B
DTA0A
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
Bit
:
7
6
5
4
3
2
1
0
DMABCRL :
DTE1B
DTE1A
DTE0B
DTE0A
DTIE1B
DTIE1A
DTIE0B
DTIE0A
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC
channel.
DMABCR is initialized to H'0000 by a reset, and in standby mode.
Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short
address mode or full address mode.
In short address mode, channels 1A and 1B are used as independent channels.
Bit 15
FAE1
Description
0
Short address mode
1
Full address mode
(Initial value)
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short
address mode or full address mode.
In short address mode, channels 0A and 0B are used as independent channels.
Bit 14
FAE0
Description
0
Short address mode
1
Full address mode
Rev. 5.00 Mar 28, 2005 page 262 of 1422
REJ09B0234-0500
(Initial value)
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for
transfer in dual address mode or single address mode.
Bit 13
SAE1
Description
0
Transfer in dual address mode
1
Transfer in single address mode
(Initial value)
This bit is invalid in full address mode.
Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for
transfer in dual address mode or single address mode.
Bit 12
SAE0
Description
0
Transfer in dual address mode
1
Transfer in single address mode
(Initial value)
This bit is invalid in full address mode.
Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when
DMA transfer is performed, of the internal interrupt source selected by the data transfer factor
setting.
When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor
setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal
interrupt source selected by the data transfer factor setting does not issue an interrupt request to the
CPU or DTC.
When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor
setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU
or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC
transfer.
When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an
interrupt request to the CPU or DTC regardless of the DTA bit setting.
Rev. 5.00 Mar 28, 2005 page 263 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1B data transfer
factor setting.
Bit 11
DTA1B
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1A data transfer
factor setting.
Bit 10
DTA1A
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0B data transfer
factor setting.
Bit 9
DTA0B
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Rev. 5.00 Mar 28, 2005 page 264 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0A data transfer
factor setting.
Bit 8
DTA0A
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the
activation source selected by the data transfer factor setting is ignored. If the activation source is
an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1
when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer
end interrupt request to the CPU or DTC.
The conditions for the DTE bit being cleared to 0 are as follows:
• When initialization is performed
• When the specified number of transfers have been completed in a transfer mode other than
repeat mode
• When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason
When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation
source selected by the data transfer factor setting. When a request is issued by the activation
source, DMA transfer is executed.
The condition for the DTE bit being set to 1 is as follows:
• When 1 is written to the DTE bit after the DTE bit is read as 0
Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B.
Bit 7
DTE1B
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Rev. 5.00 Mar 28, 2005 page 265 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A.
Bit 6
DTE1A
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B.
Bit 5
DTE0B
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A.
Bit 4
DTE0A
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an
interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to
the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the transfer counter
and address register again, and then setting the DTE bit to 1.
Bit 3—Data Transfer End Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B
transfer end interrupt.
Bit 3
DTIE1B
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
Rev. 5.00 Mar 28, 2005 page 266 of 1422
REJ09B0234-0500
(Initial value)
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bit 2—Data Transfer End Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A
transfer end interrupt.
Bit 2
DTIE1A
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
(Initial value)
Bit 1—Data Transfer End Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B
transfer end interrupt.
Bit 1
DTIE0B
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
(Initial value)
Bit 0—Data Transfer End Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A
transfer end interrupt.
Bit 0
DTIE0A
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
(Initial value)
Rev. 5.00 Mar 28, 2005 page 267 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.3
Register Descriptions (2) (Full Address Mode)
Full address mode transfer is performed with channels A and B together. For details of full address
mode setting, see table 8.4.
8.3.1
Memory Address Register (MAR)
Bit
:
31
30
29
28
27
26
25
24
MAR
:
—
—
—
—
—
—
—
—
23
22
21
20
19
18
17
16
*
*
*
*
*
*
*
*
Initial value :
0
0
0
0
0
0
0
0
R/W
:
—
—
—
—
—
—
—
— R/W R/W R/W R/W R/W R/W R/W R/W
Bit
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MAR
:
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Initial value :
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
MAR is a 32-bit readable/writable register; MARA functions as the transfer source address
register, and MARB as the destination address register.
MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are
reserved: they are always read as 0, and cannot be modified.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination memory address can be updated automatically. For details, see section 8.3.4,
DMA Control Register (DMACR).
MAR is not initialized by a reset or in standby mode.
8.3.2
I/O Address Register (IOAR)
IOAR is not used in full address transfer.
Rev. 5.00 Mar 28, 2005 page 268 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.3.3
Execute Transfer Count Register (ETCR)
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of
this register is different in normal mode and in block transfer mode.
ETCR is not initialized by a reset or in standby mode.
(1) Normal Mode
ETCRA
Transfer Counter
Bit
:
ETCR
:
Initial value :
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each
time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used
at this time.
ETCRB
ETCRB is not used in normal mode.
Rev. 5.00 Mar 28, 2005 page 269 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
(2) Block Transfer Mode
ETCRA
Holds block size
Bit
:
ETCRAH
:
15
14
13
12
11
10
9
8
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value :
R/W
:
Block size counter
Bit
:
ETCRAL
:
Initial value :
R/W
:
*: Undefined
ETCRB
Block Transfer Counter
Bit
:
ETCRB
:
Initial value :
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the
block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when
the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block
size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any
desired number of bytes or words.
ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time a block is transferred, and transfer ends when the count reaches
H'0000.
Rev. 5.00 Mar 28, 2005 page 270 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.3.4
DMA Control Register (DMACR)
DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
In full address mode, DMACRA and DMACRB have different functions.
DMACR is initialized to H'0000 by a reset, and in standby mode.
DMACRA
Bit
15
14
13
12
11
10
9
8
DMACRA :
DTSZ
SAID
SAIDE
BLKDIR
BLKE
—
—
—
Initial value :
0
0
0
0
0
0
0
0
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
7
6
5
4
3
2
1
0
DMACRB :
—
DAID
DAIDE
—
DTF3
DTF2
DTF1
DTF0
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
DMACRB
Bit
R/W
:
Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 15
DTSZ
Description
0
Byte-size transfer
1
Word-size transfer
(Initial value)
Bit 14—Source Address Increment/Decrement (SAID)
Rev. 5.00 Mar 28, 2005 page 271 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether
source address register MARA is to be incremented, decremented, or left unchanged, when data
transfer is performed.
Bit 14
Bit 13
SAID
SAIDE
Description
0
0
MARA is fixed
1
MARA is incremented after a data transfer
1
(Initial value)
•
When DTSZ = 0, MARA is incremented by 1 after a transfer
•
When DTSZ = 1, MARA is incremented by 2 after a transfer
0
MARA is fixed
1
MARA is decremented after a data transfer
•
When DTSZ = 0, MARA is decremented by 1 after a transfer
•
When DTSZ = 1, MARA is decremented by 2 after a transfer
Bit 12—Block Direction (BLKDIR)
Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode
is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side
or the destination side is to be the block area.
Bit 12
Bit 11
BLKDIR
BLKE
Description
0
0
Transfer in normal mode
1
Transfer in block transfer mode, destination side is block area
0
Transfer in normal mode
1
Transfer in block transfer mode, source side is block area
1
For operation in normal mode and block transfer mode, see section 8.5, Operation.
Bits 10 to 7—Reserved: Can be read or written to.
Bit 6—Destination Address Increment/Decrement (DAID)
Rev. 5.00 Mar 28, 2005 page 272 of 1422
REJ09B0234-0500
(Initial value)
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify
whether destination address register MARB is to be incremented, decremented, or left unchanged,
when data transfer is performed.
Bit 6
Bit 5
DAID
DAIDE
Description
0
0
MARB is fixed
1
MARB is incremented after a data transfer
1
(Initial value)
•
When DTSZ = 0, MARB is incremented by 1 after a transfer
•
When DTSZ = 1, MARB is incremented by 2 after a transfer
0
MARB is fixed
1
MARB is decremented after a data transfer
•
When DTSZ = 0, MARB is decremented by 1 after a transfer
•
When DTSZ = 1, MARB is decremented by 2 after a transfer
Bit 4—Reserved: Can be read or written to.
Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor
(activation source). The factors that can be specified differ between normal mode and block
transfer mode.
• Normal Mode
Bit 3
Bit 2
Bit 1
Bit 0
DTF3
DTF2
DTF1
DTF0
Description
0
0
0
0
—
1
—
0
Activated by DREQ pin falling edge input
1
1
1
*
(Initial value)
1
Activated by DREQ pin low-level input
0
*
—
1
0
Auto-request (cycle steal)
1
Auto-request (burst)
*
—
*
*: Don't care
Rev. 5.00 Mar 28, 2005 page 273 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
• Block Transfer Mode
Bit 3
Bit 2
Bit 1
Bit 0
DTF3
DTF2
DTF1
DTF0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Description
0
—
1
Activated by A/D converter conversion end interrupt
Activated by DREQ pin falling edge input*
0
(Initial value)
1
Activated by DREQ pin low-level input
0
Activated by SCI channel 0 transmit-data-empty interrupt
1
Activated by SCI channel 0 reception complete interrupt
0
Activated by SCI channel 1 transmit-data-empty interrupt
1
Activated by SCI channel 1 reception complete interrupt
0
Activated by TPU channel 0 compare match/input capture
A interrupt
1
Activated by TPU channel 1 compare match/input capture
A interrupt
0
Activated by TPU channel 2 compare match/input capture
A interrupt
1
Activated by TPU channel 3 compare match/input capture
A interrupt
0
Activated by TPU channel 4 compare match/input capture
A interrupt
1
Activated by TPU channel 5 compare match/input capture
A interrupt
0
—
1
—
Note: * Detected as a low level in the first transfer after transfer is enabled.
The same factor can be selected for more than one channel. In this case, activation starts with the
highest-priority channel according to the relative channel priorities. For relative channel priorities,
see section 8.5.13, DMAC Multi-Channel Operation.
Rev. 5.00 Mar 28, 2005 page 274 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.3.5
Bit
DMA Band Control Register (DMABCR)
:
15
14
13
12
11
10
9
8
DMABCRH :
FAE1
FAE0
—
—
DTA1
—
DTA0
—
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
Bit
:
7
6
5
4
3
2
1
0
DMABCRL :
DTME1
DTE1
DTME0
DTE0
DTIE1B
DTIE1A
DTIE0B
DTIE0A
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC
channel.
DMABCR is initialized to H'0000 by a reset, and in standby mode.
Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short
address mode or full address mode.
In full address mode, channels 1A and 1B are used together as a single channel.
Bit 15
FAE1
Description
0
Short address mode
1
Full address mode
(Initial value)
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short
address mode or full address mode.
In full address mode, channels 0A and 0B are used together as a single channel.
Bit 14
FAE0
Description
0
Short address mode
1
Full address mode
(Initial value)
Rev. 5.00 Mar 28, 2005 page 275 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bits 13 and 12—Reserved: Can be read or written to.
Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when
DMA transfer is performed, of the internal interrupt source selected by the data transfer factor
setting.
When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor
setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal
interrupt source selected by the data transfer factor setting does not issue an interrupt request to the
CPU or DTC.
When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer
factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the
CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC
transfer.
When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues
an interrupt request to the CPU or DTC regardless of the DTA bit setting.
The state of the DTME bit does not affect the above operations.
Bit 11—Data Transfer Acknowledge 1 (DTA1): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor
setting.
Bit 11
DTA1
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor
setting.
Bit 9
DTA0
Description
0
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
1
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Rev. 5.00 Mar 28, 2005 page 276 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bits 10 and 8—Reserved: Can be read or written to.
Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits
control enabling or disabling of data transfer on the relevant channel. When both the DTME bit
and the DTE bit are set to 1, transfer is enabled for the channel.
If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is
generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the
CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In
block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is
not interrupted.
The conditions for the DTME bit being cleared to 0 are as follows:
• When initialization is performed
• When NMI is input in burst mode
• When 0 is written to the DTME bit
The condition for DTME being set to 1 is as follows:
• When 1 is written to DTME after DTME is read as 0
Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel
1.
Bit 7
DTME1
Description
0
Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt
1
Data transfer enabled
(Initial value)
Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel
0.
Bit 5
DTME0
Description
0
Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value)
1
Data transfer enabled
Rev. 5.00 Mar 28, 2005 page 277 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the
activation source selected by the data transfer factor setting is ignored. If the activation source is
an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1
when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer
end interrupt request to the CPU.
The conditions for the DTE bit being cleared to 0 are as follows:
• When initialization is performed
• When the specified number of transfers have been completed
• When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason
When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the
activation source selected by the data transfer factor setting. When a request is issued by the
activation source, DMA transfer is executed.
The condition for the DTE bit being set to 1 is as follows:
• When 1 is written to the DTE bit after the DTE bit is read as 0
Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1.
Bit 6
DTE1
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0.
Bit 4
DTE0
Description
0
Data transfer disabled
1
Data transfer enabled
(Initial value)
Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an
interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when
DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer
break interrupt request to the CPU or DTC.
Rev. 5.00 Mar 28, 2005 page 278 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the DTME bit to 1.
Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1
transfer break interrupt.
Bit 3
DTIE1B
Description
0
Transfer break interrupt disabled
1
Transfer break interrupt enabled
(Initial value)
Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0
transfer break interrupt.
Bit 1
DTIE0B
Description
0
Transfer break interrupt disabled
1
Transfer break interrupt enabled
(Initial value)
Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable
an interrupt to the CPU or DTC when transfer ends. If DTIEA bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to
the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the transfer counter
and address register again, and then setting the DTE bit to 1.
Bit 2—Data Transfer End Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1
transfer end interrupt.
Bit 2
DTIE1A
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
(Initial value)
Rev. 5.00 Mar 28, 2005 page 279 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bit 0—Data Transfer End Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0
transfer end interrupt.
Bit 0
DTIE0A
Description
0
Transfer end interrupt disabled
1
Transfer end interrupt enabled
8.4
Register Descriptions (3)
8.4.1
DMA Write Enable Register (DMAWER)
(Initial value)
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions
so that only specific bits of DMACR for the specific channel and also DMATCR and DMABCR
can be changed to prevent inadvertent changes being made to registers other than those for the
channel concerned. The restrictions applied by DMAWER are valid for the DTC.
Figure 8.2 shows the transfer areas for activating the DTC with a channel 0A transfer end
interrupt, and reactivating channel 0A. The address register and count register area is re-set by the
first DTC transfer, then the control register area is re-set by the second DTC chain transfer.
When re-setting the control register area, perform masking by setting bits in DMAWER to prevent
modification of the contents of the other channels.
Rev. 5.00 Mar 28, 2005 page 280 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
MAR0A
First transfer area
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
DTC
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
DMAWER
DMATCR
DMACR0A
DMACR0B
DMACR1A
DMACR1B
Second transfer area
using chain transfer
DMABCR
Figure 8.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)
Bit
:
7
6
5
4
3
2
1
0
DMAWER :
—
—
—
—
WE1B
WE1A
WE0B
WE0A
Initial value :
0
0
0
0
0
0
0
0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
:
DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the
DMACR, DMABCR, and DMATCR by the DTC.
DMAWER is initialized to H'00 by a reset, and in standby mode.
Bits 7 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Rev. 5.00 Mar 28, 2005 page 281 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7,
and 3 in DMABCR, and bit 5 in DMATCR by the DTC.
Bit 3
WE1B
Description
0
Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR
are disabled
(Initial value)
1
Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR
are enabled
Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits
10, 6, and 2 in DMABCR by the DTC.
Bit 2
WE1A
Description
0
Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled
(Initial value)
1
Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled
Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5,
and 1 in DMABCR, and bit 4 in DMATCR.
Bit 1
WE0B
Description
0
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are disabled
(Initial value)
1
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are enabled
Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits
8, 4, and 0 in DMABCR.
Bit 0
WE0A
Description
0
Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled
(Initial value)
1
Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled
Rev. 5.00 Mar 28, 2005 page 282 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When
modifying these registers, the channel for which the modification is to be made should be halted.
8.4.2
Bit
DMA Terminal Control Register (DMATCR)
:
7
6
5
4
3
2
1
0
DMATCR :
—
—
TEE1
TEE0
—
—
—
—
Initial value :
0
0
0
0
0
0
0
0
R/W
—
—
R/W
R/W
—
—
—
—
:
DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC
transfer end pin output. A port can be set for output automatically, and a transfer end signal
output, by setting the appropriate bit.
DMATCR is initialized to H'00 by a reset, and in standby mode.
Bits 7 and 6—Reserved: These bits are always read as 0 and cannot be modified.
Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output.
Bit 5
TEE1
0
1
Description
TEND1 pin output disabled
TEND1 pin output enabled
(Initial value)
Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output.
Bit 4
TEE0
0
1
Description
TEND0 pin output disabled
TEND0 pin output enabled
(Initial value)
Rev. 5.00 Mar 28, 2005 page 283 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
The TEND pins are assigned only to channel B in short address mode.
The transfer end signal indicates the transfer cycle in which the transfer counter reached 0,
regardless of the transfer source. An exception is block transfer mode, in which the transfer end
signal indicates the transfer cycle in which the block counter reached 0.
Bits 3 to 0—Reserved: These bits are always read as 0 and cannot be modified.
8.4.3
Bit
Module Stop Control Register (MSTPCR)
:
7
6
5
4
3
2
1
0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
R/W
:
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRA is a 8-bit readable/writable register that performs module stop mode control.
When the MSTPA7 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus
cycle and a transition is made to module stop mode. For details, see section 24.5, Module Stop
Mode.
MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a
manual reset and in software standby mode.
Bit 7—Module Stop (MSTP7): Specifies the DMAC module stop mode.
Bits 7
MSTPA7
Description
0
DMAC module stop mode cleared
1
DMAC module stop mode set
Rev. 5.00 Mar 28, 2005 page 284 of 1422
REJ09B0234-0500
(Initial value)
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5
Operation
8.5.1
Transfer Modes
Table 8.5 lists the DMAC modes.
Table 8.5
DMAC Transfer Modes
Transfer Mode
Short
address
mode
Transfer Source
(1) Sequential mode •
Dual
address (2) Idle mode
mode
(3) Repeat mode
•
TPU channel 0 to 5
compare match/input
capture A interrupt
Remarks
•
Up to 4 channels can
operate independently
•
External request
applies to channel B
only
SCI transmit-dataempty interrupt
•
SCI reception complete •
interrupt
•
A/D converter
conversion end
interrupt
•
External request
•
External request
•
Auto-request
•
TPU channel 0 to 5
compare match/input
capture A interrupt
Single address mode
applies to channel B
only
•
Modes (1), (2), and (3)
can also be specified
for single address
mode
•
Max. 2-channel
operation, combining
channels A and B
•
With auto-request,
burst mode transfer or
cycle steal transfer
can be selected
(4) Single address mode
Full address
mode
(5) Normal mode
(6) Block transfer
mode
•
SCI transmit-dataempty interrupt
•
SCI reception complete
interrupt
•
A/D converter
conversion end interrupt
•
External request
Rev. 5.00 Mar 28, 2005 page 285 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Operation in each mode is summarized below.
(1) Sequential mode
In response to a single transfer request, the specified number of transfers are carried out, one
byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the
specified number of transfers have been completed. One address is specified as 24 bits, and the
other as 16 bits. The transfer direction is programmable.
(2) Idle mode
In response to a single transfer request, the specified number of transfers are carried out, one
byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the
specified number of transfers have been completed. One address is specified as 24 bits, and the
other as 16 bits. The transfer source address and transfer destination address are fixed. The
transfer direction is programmable.
(3) Repeat mode
In response to a single transfer request, the specified number of transfers are carried out, one
byte or one word at a time. When the specified number of transfers have been completed, the
addresses and transfer counter are restored to their original settings, and operation is continued.
No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits, and the
other as 16 bits. The transfer direction is programmable.
(4) Single address mode
In response to a single transfer request, the specified number of transfers are carried out
between external memory and an external device, one byte or one word at a time. Unlike dual
address mode, source and destination accesses are performed in parallel. Therefore, either the
source or the destination is an external device which can be accessed with a strobe alone, using
the DACK pin. One address is specified as 24 bits, and for the other, the pin is set
automatically. The transfer direction is programmable.
Modes (1), (2) and (3) can also be specified for single address mode.
(5) Normal mode
• Auto-request
By means of register settings only, the DMAC is activated, and transfer continues until the
specified number of transfers have been completed. An interrupt request can be sent to the
CPU or DTC when transfer is completed. Both addresses are specified as 24 bits.
 Cycle steal mode: The bus is released to another bus master every byte or word transfer.
 Burst mode: The bus is held and transfer continued until the specified number of transfers
have been completed.
Rev. 5.00 Mar 28, 2005 page 286 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
• External request
In response to a single transfer request, the specified number of transfers are carried out, one
byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the
specified number of transfers have been completed. Both addresses are specified as 24 bits.
(6) Block transfer mode
In response to a single transfer request, a block transfer of the specified block size is carried
out. This is repeated the specified number of times, once each time there is a transfer request.
At the end of each single block transfer, one address is restored to its original setting. An
interrupt request can be sent to the CPU or DTC when the specified number of block transfers
have been completed. Both addresses are specified as 24 bits.
8.5.2
Sequential Mode
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 8.6 summarizes register functions in sequential mode.
Table 8.6
Register Functions in Sequential Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0 Source
address
register
MAR
23
15
H'FF
Destination Start address of
Incremented/
address
transfer destination decremented every
register
or transfer source
transfer
0 Destination Source
IOAR
15
address
register
address
register
0 Transfer counter
ETCR
Operation
Start address of
Fixed
transfer source or
transfer destination
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR: Data transfer direction bit
Rev. 5.00 Mar 28, 2005 page 287 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
Figure 8.3 illustrates operation in sequential mode.
Transfer
Address T
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N–1))
Where: L = Value set in MAR
N = Value set in ETCR
Address B
Figure 8.3 Operation in Sequential Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Rev. 5.00 Mar 28, 2005 page 288 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channels 0 to 5
compare match/input capture A interrupts. External requests can be set for channel B only.
Figure 8.4 shows an example of the setting procedure for sequential mode.
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Sequential mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Sequential mode
Figure 8.4 Example of Sequential Mode Setting Procedure
Rev. 5.00 Mar 28, 2005 page 289 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.3
Idle Mode
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one
byte or word is transferred in response to a single transfer request, and this is executed the number
of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 8.7 summarizes register functions in idle mode.
Table 8.7
Register Functions in Idle Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0 Source
address
register
MAR
23
15
H'FF
Destination Start address of
Fixed
address
transfer destination
register
or transfer source
0 Destination Source
IOAR
15
address
register
address
register
0 Transfer counter
ETCR
Operation
Start address of
Fixed
transfer source or
transfer destination
Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR: Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
Rev. 5.00 Mar 28, 2005 page 290 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.5 illustrates operation in idle mode.
MAR
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Figure 8.5 Operation in Idle Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channels 0 to 5
compare match/input capture A interrupts. External requests can be set for channel B only.
When the DMAC is used in single address mode, only channel B can be set.
Rev. 5.00 Mar 28, 2005 page 291 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.6 shows an example of the setting procedure for idle mode.
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Idle mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Set the DTIE bit to 1.
• Set the DTE bit to 1 to enable transfer.
Read DMABCRL
[5]
Set DMABCRL
[6]
Idle mode
Figure 8.6 Example of Idle Mode Setting Procedure
Rev. 5.00 Mar 28, 2005 page 292 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.4
Repeat Mode
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to
0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer
request, and this is executed the number of times specified in ETCR. On completion of the
specified number of transfers, MAR and ETCRL are automatically restored to their original
settings and operation continues.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 8.8 summarizes register functions in repeat mode.
Table 8.8
Register Functions in Repeat Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0 Source
address
register
MAR
23
15
H'FF
Destination Start address of
Incremented/
address
transfer destination decremented every
register
or transfer source
transfer. Initial
setting is restored
when value reaches
H'0000
0 Destination Source
address
register
IOAR
7
address
register
0 Holds number of
Fixed
Start address of
transfer source or
transfer destination
Number of transfers Fixed
transfers
ETCRH
7
Operation
0
Transfer counter
ETCRL
Number of transfers Decremented every
transfer. Loaded with
ETCRH value when
count reaches H'00
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR: Data transfer direction bit
Rev. 5.00 Mar 28, 2005 page 293 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of
transfers, when H'00 is set in both ETCRH and ETCRL, is 256.
In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number
of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value
reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is
restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR
restoration operation is as shown below.
MAR = MAR – (–1)DTID · 2DTSZ · ETCRH
The same value should be set in ETCRH and ETCRL.
In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation,
therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU
or DTC.
By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the
transfer after that terminated when the DTE bit was cleared.
Rev. 5.00 Mar 28, 2005 page 294 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.7 illustrates operation in repeat mode.
Address T
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Address B
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N–1))
Where: L = Value set in MAR
N = Value set in ETCR
Figure 8.7 Operation in Repeat mode
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channels 0 to 5
compare match/input capture A interrupts. External requests can be set for channel B only.
Rev. 5.00 Mar 28, 2005 page 295 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.8 shows an example of the setting procedure for repeat mode.
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Repeat mode setting
Set DMABCRH
[1]
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in both ETCRH and
ETCRL.
Set transfer source
and transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Set the RPE bit to 1.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Clear the DTIE bit to 0.
• Set the DTE bit to 1 to enable transfer.
Repeat mode
Figure 8.8 Example of Repeat Mode Setting Procedure
Rev. 5.00 Mar 28, 2005 page 296 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.5
Single Address Mode
Single address mode can only be specified for channel B. This mode can be specified by setting
the SAE bit in DMABCR to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR in DMACR.
Table 8.9 summarizes register functions in single address mode.
Table 8.9
Register Functions in Single Address Mode
Function
Register
DTDIR = 0 DTDIR = 1 Initial Setting
23
0 Source
MAR
DACK pin
15
Operation
Destination Start address of
address
transfer destination
register
or transfer source
*
address
register
Write
strobe
Read
strobe
(Set automatically by
SAE bit; IOAR is
invalid)
Strobe for external
device
Number of transfers
*
0 Transfer counter
ETCR
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Transfer count register
DTDIR: Data transfer direction bit
DACK: Data transfer acknowledge
Note: * See the operation descriptions in sections 8.5.2, Sequential Mode, 8.5.3, Idle Mode, and
8.5.4, Repeat Mode.
MAR specifies the start address of the transfer source or transfer destination as 24 bits.
IOAR is invalid; in its place the strobe for external devices (DACK) is output.
Rev. 5.00 Mar 28, 2005 page 297 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.9 illustrates operation in single address mode (when sequential mode is specified).
Address T
Transfer
DACK
1 byte or word transfer performed in
response to 1 transfer request
Address B
Legend:
Address T = L
Address B = L + (–1)DTID · (2DTSZ · (N–1))
Where: L = Value set in MAR
N = Value set in ETCR
Figure 8.9 Operation in Single Address Mode (When Sequential Mode is Specified)
Rev. 5.00 Mar 28, 2005 page 298 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.10 shows an example of the setting procedure for single address mode (when sequential
mode is specified).
Single address
mode setting
Set DMABCRH
Set transfer source and
transfer destination
addresses
[1]
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Set the SAE bit to 1 to select single address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
[2] Set the transfer source address/transfer
destination address in MAR.
[2]
Set number of transfers
[3]
Set DMACR
[4]
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Single address mode
Figure 8.10 Example of Single Address Mode Setting Procedure (When Sequential Mode is
Specified)
Rev. 5.00 Mar 28, 2005 page 299 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.6
Normal Mode
In normal mode, transfer is performed with channels A and B used in combination. Normal mode
can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA
to 0.
In normal mode, MAR is updated after each byte or word transfer in response to a single transfer
request, and this is executed the number of times specified in ETCRA. The transfer source is
specified by MARA, and the transfer destination by MARB.
Table 8.10 summarizes register functions in normal mode.
Table 8.10 Register Functions in Normal Mode
Register
Function
23
0 Source address
MARA
23
register
0 Destination
MARB
15
address register
0 Transfer counter
ETCRA
Initial Setting
Operation
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
Start address of
transfer destination
Incremented/decremented
every transfer, or fixed
Number of transfers Decremented every
transfer; transfer ends
when count reaches
H'0000
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Transfer count register A
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed.
Incrementing, decrementing, or holding a fixed value can be set separately for MARA and
MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a
transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
Rev. 5.00 Mar 28, 2005 page 300 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.11 illustrates operation in normal mode.
Address TA
Transfer
Address TB
Address BB
Address BA
Legend:
Address
Address
Address
Address
Where:
TA
TB
BA
BB
LA
LB
N
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (N–1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (N–1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRA
Figure 8.11 Operation in Normal Mode
Transfer requests (activation sources) are external requests and auto-requests.
With auto-request, the DMAC is only activated by register setting, and the specified number of
transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be
selected. In cycle steal mode, the bus is released to another bus master each time a transfer is
performed. In burst mode, the bus is held continuously until transfer ends.
Rev. 5.00 Mar 28, 2005 page 301 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
For setting details, see section 8.3.4, DMA Controller Register (DMACR).
Figure 8.12 shows an example of the setting procedure for normal mode.
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Normal mode setting
Set DMABCRH
[1]
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the number of transfers in ETCRA.
Set transfer source and
transfer destination
addresses
[2]
Set number of transfers
[3]
Set DMACR
[4]
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Clear the BLKE bit to 0 to select normal
mode.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
Read DMABCRL
[5]
Set DMABCRL
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Normal mode
Figure 8.12 Example of Normal Mode Setting Procedure
Rev. 5.00 Mar 28, 2005 page 302 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.7
Block Transfer Mode
In block transfer mode, transfer is performed with channels A and B used in combination. Block
transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in
DMACRA to 1.
In block transfer mode, a transfer of the specified block size is carried out in response to a single
transfer request, and this is executed the specified number of times. The transfer source is
specified by MARA, and the transfer destination by MARB. Either the transfer source or the
transfer destination can be selected as a block area (an area composed of a number of bytes or
words).
Table 8.11 summarizes register functions in block transfer mode.
Table 8.11 Register Functions in Block Transfer Mode
Register
Function
23
0 Source address
register
MARA
23
0 Destination
address register
MARB
7
0 Holds block
ETCRAH
Initial Setting
Operation
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
Start address of
Incremented/decremented
transfer destination every transfer, or fixed
Block size
Fixed
Block size
Decremented every
transfer; ETCRH value
copied when count
reaches H'00
Number of block
transfers
Decremented every block
transfer; transfer ends
when count reaches
H'0000
size
Block size
0 counter
7
ETCRAL
15
0 Block transfer
ETCRB
Legend:
MARA:
MARB:
ETCRA:
ETCRB:
counter
Memory address register A
Memory address register B
Transfer count register A
Transfer count register B
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed.
Rev. 5.00 Mar 28, 2005 page 303 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Incrementing, decrementing, or holding a fixed value can be set separately for MARA and
MARB.
Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in
DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
Figure 8.13 illustrates operation in block transfer mode when MARB is designated as a block area.
Address TB
Address TA
1st block
2nd block
Transfer
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Block area
Address BB
Nth block
Address BA
Legend:
Address
Address
Address
Address
Where:
TA
TB
BA
BB
LA
LB
N
M
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (M·N–1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (N–1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 8.13 Operation in Block Transfer Mode (BLKDIR = 0)
Rev. 5.00 Mar 28, 2005 page 304 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.14 illustrates operation in block transfer mode when MARA is designated as a block area.
Address TA
Address TB
Block area
1st block
Transfer
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Address BA
2nd block
Nth block
Address BB
Legend:
Address
Address
Address
Address
Where:
TA
TB
BA
BB
LA
LB
N
M
= LA
= LB
= LA + SAIDE · (–1)SAID · (2DTSZ · (N–1))
= LB + DAIDE · (–1)DAID · (2DTSZ · (M·N–1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 8.14 Operation in Block Transfer Mode (BLKDIR = 1)
Rev. 5.00 Mar 28, 2005 page 305 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit
is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to
the CPU or DTC.
Figure 8.15 shows the operation flow in block transfer mode.
Rev. 5.00 Mar 28, 2005 page 306 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Start
(DTE = DTME = 1)
Transfer request?
No
Yes
Acquire bus
Read address specified by MARA
MARA=MARA+SAIDE·(–1)SAID·2DTSZ
Write to address specified by MARB
MARB=MARB+DAIDE·(–1)DAID ·2DTSZ
ETCRAL=ETCRAL–1
ETCRAL=H'00
No
Yes
Release bus
ETCRAL=ETCRAH
No
BLKDIR=0
Yes
MARB=MARB–DAIDE·(–1)DAID·2DTSZ·ETCRAH
MARA=MARA–SAIDE·(–1)SAID·2DTSZ·ETCRAH
ETCRB=ETCRB–1
No
ETCRB=H'0000
Yes
Clear DTE bit to 0
to end transfer
Figure 8.15 Operation Flow in Block Transfer Mode
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission complete and reception complete interrupts, and TPU channels 0 to 5
compare match/input capture A interrupts.
For details, see section 8.3.4, DMA Control Register (DMACR).
Rev. 5.00 Mar 28, 2005 page 307 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.16 shows an example of the setting procedure for block transfer mode.
[1] Set each bit in DMABCRH.
• Set the FAE bit to 1 to select full address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Block transfer
mode setting
Set DMABCRH
Set transfer source
and transfer destination
addresses
[1]
[2]
Set number of transfers
[3]
Set DMACR
[4]
Read DMABCRL
[5]
[2] Set the transfer source address in MARA, and
the transfer destination address in MARB.
[3] Set the block size in both ETCRAH and
ETCRAL. Set the number of transfers in
ETCRB.
[4] Set each bit in DMACRA and DMACRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
decremented, or fixed, with the SAID and
SAIDE bits.
• Set the BLKE bit to 1 to select block transfer
mode.
• Specify whether the transfer source or the
transfer destination is a block area with the
BLKDIR bit.
• Specify whether MARB is to be incremented,
decremented, or fixed, with the DAID and
DAIDE bits.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
Set DMABCRL
Block transfer mode
[6]
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts to the CPU with the DTIE bit.
• Set both the DTME bit and the DTE bit to 1 to
enable transfer.
Figure 8.16 Example of Block Transfer Mode Setting Procedure
Rev. 5.00 Mar 28, 2005 page 308 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.8
DMAC Activation Sources
DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The
activation sources that can be specified depend on the transfer mode and the channel, as shown in
table 8.12.
Table 8.12 DMAC Activation Sources
Short Address Mode
Activation Source
Internal
Interrupts
External
Requests
Channels
0A and 1A
Channels
0B and 1B
Full Address Mode
Normal
Mode
ADI
X
TXI0
X
RXI0
X
TXI1
X
RXI1
X
TGI0A
X
TGI1A
X
TGI2A
X
TGI3A
X
TGI4A
X
TGI5A
X
DREQ pin falling edge input
DREQ pin low-level input
Auto-request
Block
Transfer
Mode
X
X
X
X
X
Legend:
: Can be specified
X: Cannot be specified
Activation by Internal Interrupt: An interrupt request selected as a DMAC activation source
can be sent simultaneously to the CPU and DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt, the DMAC accepts the request independently of the
interrupt controller. Consequently, interrupt controller priority settings are not accepted.
If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a
DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA
transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared
Rev. 5.00 Mar 28, 2005 page 309 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an
activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated first. Transfer requests for other channels are held pending in the
DMAC, and activation is carried out in order of priority.
When DTE = 0, such as after completion of a transfer, a request from the selected activation
source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt
request is sent to the CPU or DTC.
In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt
request flag is not cleared by the DMAC.
Activation by External Request: If an external request (DREQ pin) is specified as an activation
source, the relevant port should be set to input mode in advance.
Level sensing or edge sensing can be used for external requests.
External request operation in normal mode (short address mode or full address mode) is described
below.
When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low
transition is detected on the DREQ pin. The next transfer may not be performed if the next edge is
input before transfer is completed.
When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is
held high. While the DREQ pin is held low, transfers continue in succession, with the bus being
released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
Activation by Auto-Request: Auto-request activation is performed by register setting only, and
transfer continues to the end.
With auto-request activation, cycle steal mode or burst mode can be selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles usually alternate.
In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is
performed continuously.
Single Address Mode: The DMAC can operate in dual address mode in which read cycles and
write cycles are separate cycles, or single address mode in which read and write cycles are
executed in parallel.
Rev. 5.00 Mar 28, 2005 page 310 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
In dual address mode, transfer is performed with the source address and destination address
specified separately.
In single address mode, on the other hand, transfer is performed between external space in which
either the transfer source or the transfer destination is specified by an address, and an external
device for which selection is performed by means of the DACK strobe, without regard to the
address. Figure 8.17 shows the data bus in single address mode.
RD
HWR, LWR
A23 to A0
Address bus
External
memory
H8S/2633
D15 to D0
(high impedance)
Data bus
(Read)
(Write)
External
device
DACK
Figure 8.17 Data Bus in Single Address Mode
When using the DMAC for single address mode reading, transfer is performed from external
memory to the external device, and the DACK pin functions as a write strobe for the external
device. When using the DMAC for single address mode writing, transfer is performed from the
external device to external memory, and the DACK pin functions as a read strobe for the external
device. Since there is no directional control for the external device, one or other of the above
single directions should be used.
Bus cycles in single address mode are in accordance with the settings of the bus controller for the
external memory area. On the external device side, DACK is output in synchronization with the
address strobe. For details of bus cycles, see section 8.5.11, DMAC Bus Cycles (Single Address
Mode).
Do not specify internal space for transfer addresses in single address mode.
Rev. 5.00 Mar 28, 2005 page 311 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.9
Basic DMAC Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 8.18. In this example, wordsize transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between
these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller
settings.
CPU cycle
DMAC cycle (1-word transfer)
T1
T2
T1
T2
T3
T1
T2
CPU cycle
T3
φ
Source
address
Destination address
Address bus
RD
HWR
LWR
Figure 8.18 Example of DMA Transfer Bus Timing
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
Rev. 5.00 Mar 28, 2005 page 312 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.10
DMAC Bus Cycles (Dual Address Mode)
Short Address Mode: Figure 8.19 shows a transfer example in which TEND output is enabled
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Bus release
Bus release
Last transfer
cycle
Bus
release
Figure 8.19 Example of Short Address Mode Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in
which the transfer counter reaches 0.
Rev. 5.00 Mar 28, 2005 page 313 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Full Address Mode (Cycle Steal Mode): Figure 8.20 shows a transfer example in which TEND
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Bus release
Bus release
Last transfer
cycle
Bus
release
Figure 8.20 Example of Full Address Mode (Cycle Steal) Transfer
A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the
bus is released one bus cycle is inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Rev. 5.00 Mar 28, 2005 page 314 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Full Address Mode (Burst Mode): Figure 8.21 shows a transfer example in which TEND output
is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Last transfer cycle
Bus release
Bus release
Burst transfer
Figure 8.21 Example of Full Address Mode (Burst Mode) Transfer
In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that
channel has to wait until the burst transfer ends.
If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state,
the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer
has already been activated inside the DMAC, the bus is released on completion of a one-byte or
one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer
cycle of the burst transfer has already been activated inside the DMAC, execution continues to the
end of the transfer even if the DTME bit is cleared.
Rev. 5.00 Mar 28, 2005 page 315 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Full Address Mode (Block Transfer Mode): Figure 8.22 shows a transfer example in which
TEND output is enabled and word-size full address mode transfer (block transfer mode) is
performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Address bus
RD
HWR
LWR
TEND
Bus release
Block transfer
Bus release
Last block transfer
Bus
release
Figure 8.22 Example of Full Address Mode (Block Transfer Mode) Transfer
A one-block transfer is performed for one transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle.
One block is transmitted without interruption. NMI generation does not affect block transfer
operation.
Rev. 5.00 Mar 28, 2005 page 316 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the
DREQ pin is selected to 1.
Figure 8.23 shows an example of DREQ pin falling edge activated normal mode transfer.
DMA
read
DMA
write
Transfer
source
Transfer
destination
Bus release
Bus
release
DMA
read
DMA
write
Transfer
source
Transfer
destination
Bus
release
φ
DREQ
Address bus
DMA control
Channel
Read
Idle
[2]
[3]
Read
Idle
Request clear period
Request
Minimum of 2 cycles
[1]
Write
Write
Idle
Request clear period
Request
Minimum of 2 cycles
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of φ, and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the
write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request
is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 8.23 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA write cycle ends, acceptance
resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
Rev. 5.00 Mar 28, 2005 page 317 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.24 shows an example of DREQ pin falling edge activated block transfer mode transfer.
1 block transfer
1 block transfer
DMA
read
Bus release
DMA
write
DMA Bus
dead release
DMA
read
DMA
write
Transfer
source
Transfer
destination
DMA
dead
Bus
release
φ
DREQ
Transfer
source
Address bus
DMA control
Channel
Read
Idle
Request
[2]
Dead
Write
Request clear period
Minimun of 2 cycles
[1]
Transfer
destination
[3]
Idle Read
Write
Dead
Idle
Request clear period
Request
Minimun of 2 cycles
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 8.24 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA dead cycle ends, acceptance
resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this
operation is repeated until the transfer ends.
Rev. 5.00 Mar 28, 2005 page 318 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the
DREQ pin is selected to 1.
Figure 8.25 shows an example of DREQ level activated normal mode transfer.
DMA
read
DMA
write
Transfer
source
Transfer
destination
Bus
release
Bus
release
DMA
read
DMA
write
Transfer
source
Transfer
destination
Bus
release
φ
DREQ
Address bus
DMA control
Channel
Read
Idle
Request
[2]
[3]
Read
Idle
Request clear period
Minimum of 2 cycles
[1]
Write
Write
Idle
Request clear period
Request
Minimum of 2 cycles
[4]
[5]
[6]
Acceptance resumes
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of φ, and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 8.25 Example of DREQ Level Activated Normal Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Rev. 5.00 Mar 28, 2005 page 319 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.26 shows an example of DREQ level activated block transfer mode transfer.
1 block transfer
DMA
read
Bus release
1 block transfer
DMA
right
DMA Bus
dead release
DMA
read
DMA
right
DMA
dead
Bus
release
φ
DREQ
Transfer
source
Address bus
DMA control
Channel
Read
Idle
Transfer
destination
Dead
Write
Request clear period
Request
Minimum of 2 cycles
[1]
[2]
Transfer
source
Idle Read
Write
Transfer
destination
Dead
Idle
Request clear period
Request
Minimum of 2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of φ, and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 8.26 Example of DREQ Level Activated Block Transfer Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Rev. 5.00 Mar 28, 2005 page 320 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.11
DMAC Bus Cycles (Single Address Mode)
Single Address Mode (Read): Figure 8.27 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state
access space to an external device.
DMA read
DMA read
DMA read
DMA
DMA read dead
φ
Address bus
RD
DACK
TEND
Bus
release
Bus
release
Bus
release
Bus Last transfer
release
cycle
Bus
release
Figure 8.27 Example of Single Address Mode (Byte Read) Transfer
Rev. 5.00 Mar 28, 2005 page 321 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.28 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
DMA read
DMA read
DMA read
DMA
dead
φ
Address bus
RD
DACK
TEND
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Bus
release
Figure 8.28 Example of Single Address Mode (Word Read) Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or
DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Rev. 5.00 Mar 28, 2005 page 322 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Single Address Mode (Write): Figure 8.29 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (write) is performed from an external device to
external 8-bit, 2-state access space.
DMA write
DMA write
DMA write
DMA
DMA write dead
φ
Address bus
HWR
LWR
DACK
TEND
Bus
release
Bus
release
Bus
release
Bus Last transfer
release
cycle
Bus
release
Figure 8.29 Example of Single Address Mode (Byte Write) Transfer
Rev. 5.00 Mar 28, 2005 page 323 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.30 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
DMA write
DMA write
DMA write
DMA
dead
φ
Address bus
HWR
LWR
DACK
TEND
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Bus
release
Figure 8.30 Example of Single Address Mode (Word Write) Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Rev. 5.00 Mar 28, 2005 page 324 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the
DREQ pin is selected to 1.
Figure 8.31 shows an example of DREQ pin falling edge activated single address mode transfer.
Bus release
DMA single
Bus release
DMA single
Bus release
φ
DREQ
Transfer source/
destination
Address bus
Transfer source/
destination
DACK
DMA control
Channel
Idle
Single
Request
Idle
Request clear
period
Single
[1]
[2]
Request clear
period
Request
Minimum of
2 cycles
Idle
Minimum of
2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of φ, and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single
cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 8.31 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA single cycle ends, acceptance
resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
Rev. 5.00 Mar 28, 2005 page 325 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ
pin is selected to 1.
Figure 8.32 shows an example of DREQ pin low level activated single address mode transfer.
Bus release
DMA single
Bus release
Bus
release
DMA single
φ
DREQ
Transfer source/
destination
Address bus
Transfer source/
destination
DACK
DMA control
Channel
Idle
Single
Idle
Request clear
period
Request
Single
[1]
[2]
Request clear
period
Request
Minimum of
2 cycles
Idle
Minimum of
2 cycles
[3]
[4]
[5]
Acceptance resumes
[6]
[7]
Acceptance resumes
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of φ, and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
[1]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 8.32 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Rev. 5.00 Mar 28, 2005 page 326 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.12
Write Data Buffer Function
DMAC internal-to-external dual address transfers and single address transfers can be executed at
high speed using the write data buffer function, enabling system throughput to be improved.
When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer
function, dual address transfer external write cycles or single address transfers and internal
accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are
independent of the bus master, and DMAC dead cycles are regarded as internal accesses.
A low level can always be output from the TEND pin if the bus cycle in which a low level is to be
output is an external bus cycle. However, a low level is not output from the TEND pin if the bus
cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an
external write cycle is executed in parallel with this cycle.
Figure 8.33 shows an example of burst mode transfer from on-chip RAM to external memory
using the write data buffer function.
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
φ
Internal address
Internal read signal
External address
HWR, LWR
TEND
Figure 8.33 Example of Dual Address Transfer Using Write Data Buffer Function
Figure 8.34 shows an example of single address transfer using the write data buffer function. In
this example, the CPU program area is in on-chip memory.
Rev. 5.00 Mar 28, 2005 page 327 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
DMA
read
DMA
single
CPU
read
DMA
single
CPU
read
φ
Internal address
Internal read signal
External address
RD
DACK
Figure 8.34 Example of Single Address Transfer Using Write Data Buffer Function
When the write data buffer function is activated, the DMAC recognizes that the bus cycle
concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one
state after the start of the DMA write cycle or single address transfer.
8.5.13
DMAC Multi-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B.
Table 8.13 summarizes the priority order for DMAC channels.
Table 8.13 DMAC Channel Priority Order
Short Address Mode
Full Address Mode
Priority
Channel 0A
Channel 0
High
Channel 0B
Channel 1A
Channel 1
Channel 1B
Rev. 5.00 Mar 28, 2005 page 328 of 1422
REJ09B0234-0500
Low
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 8.13.
During burst transfer, or when one block is being transferred in block transfer, the channel will not
be changed until the end of the transfer.
Figure 8.35 shows a transfer example in which transfer requests are issued simultaneously for
channels 0A, 0B, and 1.
DMA read
DMA write
DMA read
DMA write
DMA read
DMA
DMA write read
φ
Address bus
RD
HWR
LWR
DMA control Idle Read
Channel 0A
Idle
Write
Read
Write
Idle
Read
Write
Read
Request clear
Channel 0B
Request
hold
Selection
Channel 1
Request
hold
Nonselection
Bus
release
Channel 0A
transfer
Request clear
Request
hold
Bus
release
Selection
Channel 0B
transfer
Request clear
Bus
release
Channel 1 transfer
Figure 8.35 Example of Multi-Channel Transfer
8.5.14
Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC
There can be no break between a DMA cycle read and a DMA cycle write. This means that a
refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read
and external write in a DMA cycle.
In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh
or external bus released state may be inserted after a write cycle. Since the DTC has a lower
priority than the DMAC, the DTC does not operate until the DMAC releases the bus.
Rev. 5.00 Mar 28, 2005 page 329 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these
DMA cycles can be executed at the same time as refresh cycles or external bus release. However,
simultaneous operation may not be possible when a write buffer is used.
8.5.15
NMI Interrupts and DMAC
When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An
NMI interrupt does not affect the operation of the DMAC in other modes.
In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit
are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on
completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the
CPU.
The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again.
Figure 8.36 shows the procedure for continuing transfer when it has been interrupted by an NMI
interrupt on a channel designated for burst mode transfer.
Resumption of
transfer on interrupted
channel
DTE= 1
DTME= 0
[1]
Check that DTE = 1 and
DTME = 0 in DMABCRL
[2]
Write 1 to the DTME bit.
[1]
No
Yes
Set DTME bit to 1
[2]
Transfer continues
Transfer ends
Figure 8.36 Example of Procedure for Continuing Transfer on Channel Interrupted by
NMI Interrupt
Rev. 5.00 Mar 28, 2005 page 330 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.16
Forced Termination of DMAC Operation
If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion
of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to
1 again.
In full address mode, the same applies to the DTME bit.
Figure 8.37 shows the procedure for forcibly terminating DMAC operation by software.
[1]
Forced termination
of DMAC
Clear DTE bit to 0
Clear the DTE bit in DMABCRL to 0.
If you want to prevent interrupt generation after
forced termination of DMAC operation, clear the
DTIE bit to 0 at the same time.
[1]
Forced termination
Figure 8.37 Example of Procedure for Forcibly Terminating DMAC Operation
Rev. 5.00 Mar 28, 2005 page 331 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.5.17
Clearing Full Address Mode
Figure 8.38 shows the procedure for releasing and initializing a channel designated for full address
mode. After full address mode has been cleared, the channel can be set to another transfer mode
using the appropriate setting procedure.
Clearing full
address mode
Stop the channel
[1]
[1] Clear both the DTE bit and the DTME bit in
DMABCRL to 0; or wait until the transfer ends
and the DTE bit is cleared to 0, then clear the
DTME bit to 0.
Also clear the corresponding DTIE bit to 0 at the
same time.
[2] Clear all bits in DMACRA and DMACRB to 0.
[3] Clear the FAE bit in DMABCRH to 0.
Initialize DMACR
[2]
Clear FAE bit to 0
[3]
Initialization;
operation halted
Figure 8.38 Example of Procedure for Clearing Full Address Mode
Rev. 5.00 Mar 28, 2005 page 332 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.6
Interrupts
The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 8.14
shows the interrupt sources and their priority order.
Table 8.14 Interrupt Source Priority Order
Interrupt
Name
Interrupt Source
Interrupt
Priority Order
Short Address Mode
Full Address Mode
DEND0A
Interrupt due to end of
transfer on channel 0A
Interrupt due to end of
transfer on channel 0
DEND0B
Interrupt due to end of
transfer on channel 0B
Interrupt due to break in
transfer on channel 0
DEND1A
Interrupt due to end of
transfer on channel 1A
Interrupt due to end of
transfer on channel 1
DEND1B
Interrupt due to end of
transfer on channel 1B
Interrupt due to break in
transfer on channel 1
High
Low
Enabling or disabling of each interrupt source is set by means of the DTIE bit for the
corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt
controller independently.
The relative priority of transfer end interrupts on each channel is decided by the interrupt
controller, as shown in table 8.14.
Figure 8.39 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is
always generated when the DTIE bit is set to 1 while DTE bit is cleared to 0.
DTE/
DTME
Transfer end/transfer
break interrupt
DTIE
Figure 8.39 Block Diagram of Transfer End/Transfer Break Interrupt
In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0
while DTIEB bit is set to 1.
In both short address mode and full address mode, DMABCR should be set so as to prevent the
occurrence of a combination that constitutes a condition for interrupt generation during setting.
Rev. 5.00 Mar 28, 2005 page 333 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
8.7
Usage Notes
DMAC Register Access during Operation: Except for forced termination, the operating
(including transfer waiting state) channel setting should not be changed. The operating channel
setting should only be changed when transfer is disabled.
Also, the DMAC register should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
(a) DMAC control starts one cycle before the bus cycle, with output of the internal address.
Consequently, MAR is updated in the bus cycle before DMAC transfer.
Figure 8.40 shows an example of the update timing for DMAC registers in dual address
transfer mode.
DMA last transfer cycle
DMA transfer cycle
DMA read
DMA read
DMA write
DMA write
DMA
dead
φ
DMA Internal
address
DMA control
DMA register
operation
Idle
[1]
Transfer
source
Transfer
destination
Read
Write
[2]
Transfer
destination
Transfer
source
Read
Idle
[1]
Write
[2]'
Dead
[3]
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of a block
in block transfer mode)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
Notes: 1. In single address transfer mode, the update timing is the same as [1].
2. The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Figure 8.40 DMAC Register Update Timing
Rev. 5.00 Mar 28, 2005 page 334 of 1422
REJ09B0234-0500
Idle
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
(b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
register is read as shown in figure 8.41.
DMA transfer cycle
CPU longword read
MAR upper
word read
MAR lower
word read
DMA read
DMA write
φ
DMA internal
address
DMA control
DMA register
operation
Idle
[1]
Transfe
source
Transfer
destination
Read
Write
Idle
[2]
Note: The lower word of MAR is the updated value after the operation in [1].
Figure 8.41 Contention between DMAC Register Update and CPU Read
Module Stop: When the MSTPA7 bit in MSTPCR is set to 1, the DMAC clock stops, and the
module stop state is entered. However, 1 cannot be written to the MSTPA7 bit if any of the
DMAC channels is enabled. This setting should therefore be made when DMAC operation is
stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
• Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)
• TEND pin enable (TEE = 1)
• DACK pin enable (FAE = 0 and SAE = 1)
Medium-Speed Mode: When the DTA bit is 0, internal interrupt signals specified as DMAC
transfer sources are edge-detected.
In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting
modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt
source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is
generated, is less than one state with respect to the DMAC clock (bus master clock), edge
detection may not be possible and the interrupt may be ignored.
Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the mediumspeed clock.
Rev. 5.00 Mar 28, 2005 page 335 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1,
enabling the write data buffer function, dual address transfer external write cycles or single
address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in
parallel.
(a) Write Data Buffer Function and DMAC Register Setting
If the setting of is changed during execution of an external access by means of the write data
buffer function, the external access may not be performed normally. The register that controls
external accesses should only be manipulated when external reads, etc., are used with DMAC
operation disabled, and the operation is not performed in parallel with external access.
(b) Write Data Buffer Function and DMAC Operation Timing
The DMAC can start its next operation during external access using the write data buffer function.
Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the
case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden,
and not visible.
(c) Write Data Buffer Function and TEND Output
A low level is not output from the TEND pin if the bus cycle in which a low level is to be output
from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with
this cycle. Note, for example, that a low level may not be output from the TEND pin if the write
data buffer function is used when data transfer is performed between an internal I/O register and
on-chip memory.
If at least one of the DMAC transfer addresses is an external address, a low level is output from
the TEND pin.
Rev. 5.00 Mar 28, 2005 page 336 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Figure 8.42 shows an example in which a low level is not output at the TEND pin.
DMA
read
DMA
write
φ
Internal address
Internal read signal
Internal write signal
External address
HWR, LWR
TEND
Not output
External write by CPU, etc.
Figure 8.42 Example in Which Low Level is Not Output at TEND Pin
Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in
synchronization with DMAC internal operations. The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
switches to [1].
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer
is enabled is performed by detection of a low level.
Rev. 5.00 Mar 28, 2005 page 337 of 1422
REJ09B0234-0500
Section 8 DMA Controller (DMAC) (This function is not available in the H8S/2695)
Activation Source Acceptance: At the start of activation source acceptance, a low level is
detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an
internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an
internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to
enable transfer.
When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ
pin low level remaining from the end of the previous transfer, etc.
Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 by the end of
transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if
DTA is set to 1.
Also, if internal DMAC activation has already been initiated when operation is aborted, the
transfer is executed but flag clearing is not performed for the selected internal interrupt even if
DTA is set to 1.
An internal interrupt request following the end of transfer or an abort should be handled by the
CPU as necessary.
Channel Re-Setting: To reactivate a number of channels when multiple channels are enabled, use
exclusive handling of transfer end interrupts, and perform DMABCR control bit operations
exclusively.
Note, in particular, that in cases where multiple interrupts are generated between reading and
writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the
DMABCR write data in the original interrupt handling routine will be incorrect, and the write may
invalidate the results of the operations by the multiple interrupts. Ensure that overlapping
DMABCR operations are not performed by multiple interrupts, and that there is no separation
between read and write operations by the use of a bit-manipulation instruction.
Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must
first be read while cleared to 0 before the CPU can write a 1 to them.
Rev. 5.00 Mar 28, 2005 page 338 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
Section 9 Data Transfer Controller (DTC)
(This function is not available in the H8S/2695)
9.1
Overview
The H8S/2633 Group includes a data transfer controller (DTC). The DTC can be activated by an
interrupt or software, to transfer data.
9.1.1
Features
The features of the DTC are:
• Transfer possible over any number of channels
 Transfer information is stored in memory
 One activation source can trigger a number of data transfers (chain transfer)
• Wide range of transfer modes
 Normal, repeat, and block transfer modes available
 Incrementing, decrementing, and fixing of source and destination addresses can be selected
• Direct specification of 16-Mbyte address space possible
 24-bit transfer source and destination addresses can be specified
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
 An interrupt request can be issued to the CPU after one data transfer ends
 An interrupt request can be issued to the CPU after the specified data transfers have
completely ended
• Activation by software is possible
• Module stop mode can be set
 The initial setting enables DTC registers to be accessed. DTC operation is halted by setting
module stop mode
Rev. 5.00 Mar 28, 2005 page 339 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.1.2
Block Diagram
Figure 9.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Internal address bus
On-chip
RAM
CPU interrupt
request
Register information
MRA MRB
CRA
CRB
DAR
SAR
DTC
Control logic
DTC service
request
DTVECR
Interrupt
request
DTCERA to
DTCERF,
DTCERI
Interrupt controller
Internal data bus
Legend:
MRA, MRB: DTC mode registers A and B
CRA, CRB: DTC transfer count registers A and B
SAR:
DTC source address register
DAR:
DTC destination address register
DTCERA to DTCERF,
DTCERI:
DTC enable registers A to F and I
DTVECR:
DTC vector register
Figure 9.1 Block Diagram of DTC
Rev. 5.00 Mar 28, 2005 page 340 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.1.3
Register Configuration
Table 9.1 summarizes the DTC registers.
Table 9.1
DTC Registers
Name
Abbreviation
R/W
Initial Value
Address*1
DTC mode register A
MRA
Undefined
DTC mode register B
MRB
—*2
—*2
—*3
—*3
SAR
—*2
Undefined
DTC destination address register
DAR
—
*2
Undefined
DTC transfer count register A
CRA
Undefined
DTC transfer count register B
CRB
—*2
—*2
Undefined
—*3
—*3
DTC enable registers
DTCER
R/W
H'00
H'FE16 to H'FE1E
DTC vector register
DTVECR
R/W
H'00
H'FE1F
Module stop control register
MSTPCRA
R/W
H'3F
H'FDE8
DTC source address register
Undefined
—*3
—*3
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot
be located in external memory space. When the DTC is used, do not clear the RAME
bit in SYSCR to 0.
Rev. 5.00 Mar 28, 2005 page 341 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.2
Register Descriptions
9.2.1
DTC Mode Register A (MRA)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
SM1
SM0
DM1
DM0
MD1
MD0
DTS
Sz
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7
Bit 6
SM1
SM0
Description
0
—
SAR is fixed
1
0
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
1
SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5
Bit 4
DM1
DM0
Description
0
—
DAR is fixed
1
0
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
1
DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Rev. 5.00 Mar 28, 2005 page 342 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Bit 3
Bit 2
MD1
MD0
Description
0
0
Normal mode
1
Repeat mode
0
Block transfer mode
1
—
1
Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination
side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Bit 1
DTS
Description
0
Destination side is repeat area or block area
1
Source side is repeat area or block area
Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.
Bit 0
Sz
Description
0
Byte-size transfer
1
Word-size transfer
9.2.2
Bit
DTC Mode Register B (MRB)
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
CHNE
DISEL
—
—
—
—
—
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
MRB is an 8-bit register that controls the DTC operating mode.
Rev. 5.00 Mar 28, 2005 page 343 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a
number of data transfers can be performed consecutively in response to a single transfer request.
In data transfer with CHNE set to 1, determination of the end of the specified number of transfers,
clearing of the interrupt source flag, and clearing of DTCER is not performed.
Bit 7
CHNE
Description
0
End of DTC data transfer (activation waiting state is entered)
1
DTC chain transfer (new register information is read, then data is transferred)
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL
Description
0
After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
1
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2633 Group, and
should always be written with 0.
9.2.3
Bit
DTC Source Address Register (SAR)
:
Initial value:
R/W
:
23
22
21
20
19
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
4
3
2
1
0
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
Rev. 5.00 Mar 28, 2005 page 344 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.2.4
DTC Destination Address Register (DAR)
Bit
:
Initial value :
R/W
:
23
22
21
20
19
4
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
3
2
1
0
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
9.2.5
Bit
DTC Transfer Count Register A (CRA)
:
Initial value:
R/W
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
— — — — — — — — — — — — — — — —
CRAH
CRAL
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is
repeated.
Rev. 5.00 Mar 28, 2005 page 345 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.2.6
Bit
DTC Transfer Count Register B (CRB)
15
:
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
— — — — — — — — — — — — — — — —
Initial value:
R/W
14
:
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
9.2.7
Bit
DTC Enable Registers (DTCER)
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to DTCERF
and DTCERI, with bits corresponding to the interrupt sources that can control enabling and
disabling of DTC activation. These bits enable or disable DTC service for the corresponding
interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
Description
0
DTC activation by this interrupt is disabled
(Initial value)
[Clearing conditions]
1
•
When the DISEL bit is 1 and the data transfer has ended
•
When the specified number of transfers have ended
DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
(n = 7 to 0)
Rev. 5.00 Mar 28, 2005 page 346 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 9.4, together with the vector number
generated for each interrupt controller.
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and
writing. If all interrupts are masked, multiple activation sources can be set at one time by writing
data after executing a dummy read on the relevant register.
9.2.8
Bit
DTC Vector Register (DTVECR)
:
7
6
5
4
3
2
1
0
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
Initial value:
R/W
:
0
0
0
0
0
0
0
0
R/(W)*1
R/W*2
R/W*2
R/W*2
R/W*2
R/W*2
R/W*2
R/W*2
Notes: 1. Only 1 can be written to the SWDTE bit.
2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
Bit 7
SWDTE
Description
0
DTC software activation is disabled
(Initial value)
[Clearing conditions]
1
•
When the DISEL bit is 0 and the specified number of transfers have not ended
•
When 0 s written to the DISEL bit after a software-activated data transfer end
interrupt (SWDTEND) request has been sent to the CPU
DTC software activation is enabled
[Holding conditions]
•
When the DISEL bit is 1 and data transfer has ended
•
When the specified number of transfers have ended
•
During data transfer due to software activation
Rev. 5.00 Mar 28, 2005 page 347 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number for DTC software activation.
The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit leftshift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
9.2.9
Bit
Module Stop Control Register A (MSTPCRA)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
MSTPA7
MSTPA6
MSTPA5
MSTPA4
MSTPA3
MSTPA2
MSTPA1
MSTPA0
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRA is a 8-bit readable/writable register that performs module stop mode control.
When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operation stops at the end of the bus
cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTPA6
bit while the DTC is operating. For details, see section 24.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a power-on reset and in hardware standby mode. It is not
initialized in manual reset and software standby mode.
Bit 6—Module Stop (MSTPA6): Specifies the DTC module stop mode.
Bit 6
MSTPA6
Description
0
DTC module stop mode cleared
1
DTC module stop mode set
Rev. 5.00 Mar 28, 2005 page 348 of 1422
REJ09B0234-0500
(Initial value)
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3
Operation
9.3.1
Overview
When activated, the DTC reads register information that is already stored in memory and transfers
data on the basis of that register information. After the data transfer, it writes updated register
information back to memory. Pre-storage of register information in memory makes it possible to
transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to
perform a number of transfers with a single activation.
Figure 9.2 shows a flowchart of DTC operation.
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE=1
Yes
No
Transfer Counter= 0
or DISEL= 1
Yes
No
Clear an activation flag
Clear DTCER
End
Interrupt exception
handling
Figure 9.2 Flowchart of DTC Operation
Rev. 5.00 Mar 28, 2005 page 349 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 9.2 outlines the functions of the DTC.
Table 9.2
DTC Functions
Address Registers
Transfer Mode
Activation Source
Transfer
Source
Transfer
Destination
•
Normal mode
•
IRQ
24 bits
24 bits
 One transfer request transfers one
byte or one word
•
TPU TGI
•
8-bit timer CMI
 Memory addresses are incremented
or decremented by 1 or 2
•
SCI TXI or RXI
•
A/D converter ADI
 Up to 65,536 transfers possible
•
DMAC DEND
•
Software
•
Repeat mode
 One transfer request transfers one
byte or one word
 Memory addresses are incremented
or decremented by 1 or 2
 After the specified number of
transfers (1 to 256), the initial state
resumes and operation continues
•
Block transfer mode
 One transfer request transfers a
block of the specified size
 Block size is from 1 to 256 bytes or
words
 Up to 65,536 transfers possible
 A block area can be designated at
either the source or destination
Rev. 5.00 Mar 28, 2005 page 350 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3.2
Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER
bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a
CPU interrupt source when the bit is cleared to 0.
At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source or corresponding DTCER bit is cleared. Table 9.3 shows activation source and
DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag
of SCI0.
Table 9.3
Activation Source and DTCER Clearance
When the DISEL Bit Is 0 and
the Specified Number of
Activation Source Transfers Have Not Ended
When the DISEL Bit Is 1, or when
the Specified Number of Transfers
Have Ended
Software activation The SWDTE bit is cleared to 0
The SWDTE bit remains set to 1
An interrupt is issued to the CPU
Interrupt activation
The corresponding DTCER bit
remains set to 1
The activation source flag is
cleared to 0
The corresponding DTCER bit is cleared
to 0
The activation source flag remains set to 1
A request is issued to the CPU for the
activation source interrupt
Figure 9.3 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
Rev. 5.00 Mar 28, 2005 page 351 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
Source flag cleared
Clear
controller
Clear
DTCER
Clear request
On-chip
supporting
module
IRQ interrupt
Interrupt
request
Selection circuit
Select
DTVECR
DTC
Interrupt controller
CPU
Interrupt mask
Figure 9.3 Block Diagram of DTC Activation Source Control
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
Rev. 5.00 Mar 28, 2005 page 352 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3.3
DTC Vector Table
Figure 9.4 shows the correspondence between DTC vector addresses and register information.
Table 9.4 shows the correspondence between activation and vector addresses. When the DTC is
activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where
<< 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420.
The DTC reads the start address of the register information from the vector address set for each
activation source, and then reads the register information from that start address. The register
information can be placed at predetermined addresses in the on-chip RAM. The start address of
the register information should be an integral multiple of four.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip
RAM.
Note: * Not available in the H8S/2633 Group.
DTC vector
address
Register information
start address
Register information
Chain transfer
Figure 9.4 Correspondence between DTC Vector Address and Register Information
Rev. 5.00 Mar 28, 2005 page 353 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
Table 9.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Interrupt Source
Origin of
Interrupt
Source
Vector
Number
Vector
Address
Write to DTVECR
Software
DTVECR
IRQ0
External pin
DTCE*
Priority
H'0400+
(DTVECR
[6:0]
<<1)
—
High
16
H'0420
DTCEA7
IRQ1
17
H'0422
DTCEA6
IRQ2
18
H'0424
DTCEA5
IRQ3
19
H'0426
DTCEA4
IRQ4
20
H'0428
DTCEA3
IRQ5
21
H'042A
DTCEA2
IRQ6
22
H'042C
DTCEA1
IRQ7
23
H'042E
DTCEA0
ADI (A/D conversion end)
A/D
28
H'0438
DTCEB6
TGI0A (GR0A compare match/
input capture)
TPU
channel 0
32
H'0440
DTCEB5
TGI0B (GR0B compare match/
input capture)
33
H'0442
DTCEB4
TGI0C (GR0C compare match/
input capture)
34
H'0444
DTCEB3
TGI0D (GR0D compare match/
input capture)
35
H'0446
DTCEB2
40
H'0450
DTCEB1
41
H'0452
DTCEB0
44
H'0458
DTCEC7
45
H'045A
DTCEC6
TGI1A (GR1A compare match/
input capture)
TPU
channel 1
TGI1B (GR1B compare match/
input capture)
TGI2A (GR2A compare match/
input capture)
TPU
channel 2
TGI2B (GR2B compare match/
input capture)
Rev. 5.00 Mar 28, 2005 page 354 of 1422
REJ09B0234-0500
Low
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
Interrupt Source
Origin of
Interrupt
Source
TGI3A (GR3A compare match/
input capture)
TPU
channel 3
Vector
Number
Vector
Address
DTCE*
Priority
48
H'0460
DTCEC5
High
TGI3B (GR3B compare match/
input capture)
49
H'0462
DTCEC4
TGI3C (GR3C compare match/
input capture)
50
H'0464
DTCEC3
TGI3D (GR3D compare match/
input capture)
51
H'0466
DTCEC2
56
H'0470
DTCEC1
57
H'0472
DTCEC0
60
H'0478
DTCED5
61
H'047A
DTCED4
TGI4A (GR4A compare match/
input capture)
TPU
channel 4
TGI4B (GR4B compare match/
input capture)
TGI5A (GR5A compare match/
input capture)
TPU
channel 5
TGI5B (GR5B compare match/
input capture)
CMIA0 (compare match A0)
8-bit timer
channel 0
64
H'0480
DTCED3
65
H'0482
DTCED2
8-bit timer
channel 1
68
H'0488
DTCED1
69
H'048A
DTCED0
DMAC
72
H'0490
DTCEE7
DEND0B (channel 0B transfer end)
73
H'0492
DTCEE6
DEND1A (channel 1/channel 1A
transfer end)
74
H'0494
DTCEE5
DEND1B (channel 1B transfer end)
75
H'0496
DTCEE4
RXI0 (reception complete 0)
SCI channel 0 81
H'04A2
DTCEE3
TXI0 (transmit data empty 0)
82
H'04A4
DTCEE2
RXI1 (reception complete 1)
SCI channel 1 85
H'04AA
DTCEE1
TXI1 (transmit data empty 1)
86
H'04AC
DTCEE0
RXI2 (reception complete 2)
SCI channel 2 89
H'04B2
DTCEF7
TXI2 (transmit data empty 2)
90
H'04B4
DTCEF6
CMIB0 (compare match B0)
CMIA1 (compare match A1)
CMIB1 (compare match B1)
DEND0A (channel 0/channel 0A
transfer end)
Low
Rev. 5.00 Mar 28, 2005 page 355 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
Interrupt Source
CMIA2 (compare match A2)
CMIB2 (compare match B2)
Origin of
Interrupt
Source
8-bit timer
channel 2
Vector
Number
Vector
Address
DTCE*
Priority
92
H'04B8
DTCEF5
High
93
H'04BA
DTCEF4
96
H'04C0
DTCEF3
97
H'04C2
DTCEF2
CMIB3 (compare match B3)
8-bit timer
channel 3
IICI0 (1-byte transmit/reception
complete)
IIC channel 0
(option)
100
H'04C8
DTCEF1
IICI1 (1-byte transmit/reception
complete)
IIC channel 1
(option)
102
H'04CC
DTCEF0
RXI3 (reception complete 3)
SCI channel 3 121
H'04F2
DTCEI7
CMIA3 (compare match A3)
TXI3 (transmit data empty 3)
122
H'04F4
DTCEI6
RXI4 (reception complete 4)
SCI channel 4 125
H'04FA
DTCEI5
TXI4 (transmit data empty 4)
126
H'04FC
DTCEI4
Low
Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
Rev. 5.00 Mar 28, 2005 page 356 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3.4
Location of Register Information in Address Space
Figure 9.5 shows how the register information should be located in the address space.
Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address
of the register information (contents of the vector address). In the case of chain transfer, register
information should be located in consecutive areas.
Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).
Lower address
Register
information
start address
Chain
transfer
0
1
2
3
MRA
SAR
MRB
DAR
CRA
Register information
CRB
MRA
SAR
MRB
DAR
CRA
Register information
for 2nd transfer in
chain transfer
CRB
4 bytes
Figure 9.5 Location of Register Information in Address Space
Rev. 5.00 Mar 28, 2005 page 357 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3.5
Normal Mode
In normal mode, one operation transfers one byte or one word of data.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt can be requested.
Table 9.5 lists the register information in normal mode and figure 9.6 shows memory mapping in
normal mode.
Table 9.5
Register Information in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register A
CRA
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR
DAR
Transfer
Figure 9.6 Memory Mapping in Normal Mode
Rev. 5.00 Mar 28, 2005 page 358 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3.6
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial state of the transfer counter and the address register specified as the repeat area is restored,
and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and
therefore CPU interrupts cannot be requested when DISEL = 0.
Table 9.6 lists the register information in repeat mode and figure 9.7 shows memory mapping in
repeat mode.
Table 9.6
Register Information in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR or
DAR
DAR or
SAR
Repeat area
Transfer
Figure 9.7 Memory Mapping in Repeat Mode
Rev. 5.00 Mar 28, 2005 page 359 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3.7
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified as the block area is restored. The other address register
is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt is requested.
Table 9.7 lists the register information in block transfer mode and figure 9.8 shows memory
mapping in block transfer mode.
Table 9.7
Register Information in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Designates block size count
DTC transfer count register B
CRB
Transfer count
Rev. 5.00 Mar 28, 2005 page 360 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
First block
SAR or
DAR
·
·
·
Block area
DAR or
SAR
Transfer
Nth block
Figure 9.8 Memory Mapping in Block Transfer Mode
Rev. 5.00 Mar 28, 2005 page 361 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3.8
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 9.9 shows the memory map for chain transfer.
Source
Destination
Register information
CHNE = 1
DTC vector
address
Register information
start address
Register information
CHNE = 0
Source
Destination
Figure 9.9 Chain Transfer Memory Map
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Rev. 5.00 Mar 28, 2005 page 362 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3.9
Operation Timing
Figures 9.10 to 9.12 show an example of DTC operation timing.
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Address
Read Write
Transfer
information read
Transfer
information write
Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
φ
DTC activation
request
DTC request
Data transfer
Vector read
Address
Read Write Read Write
Transfer
information read
Transfer
information write
Figure 9.11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
Rev. 5.00 Mar 28, 2005 page 363 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
φ
DTC activation
request
DTC
request
Data transfer
Data transfer
Read Write
Read Write
Vector read
Address
Transfer
information
read
Transfer
Transfer
information information
write
read
Transfer
information
write
Figure 9.12 DTC Operation Timing (Example of Chain Transfer)
9.3.10
Number of DTC Execution States
Table 9.8 lists execution statuses for a single DTC data transfer, and table 9.9 shows the number
of states required for each execution status.
Table 9.8
DTC Execution Statuses
Mode
Vector Read
I
Register Information
Read/Write
Data Read
J
K
Data Write
L
Internal
Operations
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
N: Block size (initial setting of CRAH and CRAL)
Rev. 5.00 Mar 28, 2005 page 364 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
Table 9.9
Number of States Required for Each Execution Status
Object to be Accessed
Bus width
Access states
OnChip
RAM
OnChip
ROM
32
16
On-Chip I/O
Registers
8
External Devices
16
8
16
1
1
2
2
2
3
2
3
SI
—
1
—
—
4
6+2m
2
3+m
SJ
1
—
—
—
—
—
—
—
Byte data read
SK
1
1
2
2
2
3+m
2
3+m
Word data read
SK
1
1
4
2
4
6+2m
2
3+m
Byte data write
SL
1
1
2
2
2
3+m
2
3+m
Word data write
SL
1
1
4
2
4
6+2m
2
3+m
Internal operation
SM
Execution Vector read
status
Register
information
read/write
1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev. 5.00 Mar 28, 2005 page 365 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3.11
Procedures for Using DTC
Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
[5] After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue
transferring data, set the DTCE bit to 1.
Activation by Software: The procedure for using the DTC with software activation is as follows:
[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
[2] Set the start address of the register information in the DTC vector address.
[3] Check that the SWDTE bit is 0.
[4] Write 1 to SWDTE bit and the vector number to DTVECR.
[5] Check the vector number written to DTVECR.
[6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested.
Rev. 5.00 Mar 28, 2005 page 366 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.3.12
Examples of Use of the DTC
(1) Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
[1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start address of the RAM area where the data will be received in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
[2] Set the start address of the register information at the DTC vector address.
[3] Set the corresponding bit in DTCER to 1.
[4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
[5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
[6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
Rev. 5.00 Mar 28, 2005 page 367 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
(2) Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG.
Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle
updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain
transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing
of the activation source and interrupt generation at the end of the specified number of transfers are
restricted to the second half of the chain transfer (transfer when CHNE = 0).
[1] Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to
chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH
address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.
[2] Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 =
MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address
in DAR, and the data table size in CRA. CRB can be set to any value.
[3] Locate the TPU transfer register information consecutively after the NDR transfer register
information.
[4] Set the start address of the NDR transfer register information to the DTC vector address.
[5] Set the bit corresponding to TGIA in DTCER to 1.
[6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
interrupt with TIER.
[7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to
be used as the output trigger.
[8] Set the CST bit in TSTR to 1, and start the TCNT count operation.
[9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and
the set value of the next output trigger period is transferred to TGRA. The activation source
TGFA flag is cleared.
[10]When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to
the CPU. Termination processing should be performed in the interrupt handling routine.
Rev. 5.00 Mar 28, 2005 page 368 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
(3) Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
[2] Set the start address of the register information at the DTC vector address (H'04C0).
[3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
[4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
[5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
[6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
[7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
Rev. 5.00 Mar 28, 2005 page 369 of 1422
REJ09B0234-0500
Section 9 Data Transfer Controller (DTC) (This function is not available in the H8S/2695)
9.4
Interrupts
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,
the interrupt set as the activation source is generated. These interrupts to the CPU are subject to
CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers
have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
9.5
Usage Notes
Module Stop: When the MSTPA6 bit in MSTPCRA is set to 1, the DTC clock stops, and the
DTC enters the module stop state. However, 1 cannot be written in the MSTPA6 bit while the
DTC is operating.
On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip
RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0.
DMAC Transfer End Interrupt: When the DTC is activated with a DMAC transfer end
interrupt, the DMAC's DTE bit is not controlled by the DTC regardless of the transfer counter and
DISEL bit, and write data takes precedence. For this reason, there may be no interrupt generated
by the CPU even if the DTC transfer counter is cleared to 0.
DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing
data after executing a dummy read on the relevant register.
Rev. 5.00 Mar 28, 2005 page 370 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Section 10A I/O Ports
(H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.1 Overview
The H8S/2633 Group has 10 I/O ports (ports 1, 3, 7 and A to G), and two input-only port (ports 4
and 9).
Table 10A.1 summarizes the port functions. The pins of each port also have other functions.
Each I/O port includes a data direction register (DDR) that controls input/output, a data register
(DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only
ports do not have a DR or DDR register.
Ports A to E have a built-in pull-up MOS function, and in addition to DR and DDR, have a MOS
input pull-up control register (PCR) to control the on/off state of MOS input pull-up.
Ports 3, and A to C include an open-drain control register (ODR) that controls the on/off state of
the output buffer PMOS.
When ports 10 to 13, 70 to 73, and A to G are used as the output pins for expanded bus control
signals, they can drive one TTL load plus a 50pF capacitance load. Those ports in other cases, and
ports 14 to 17, 3, and 74 to 77, can drive one TTL load and a 30pF capacitance load. All I/O ports
can drive Darlington transistors when set to output.
See appendix C, I/O Port Block Diagrams, for a block diagram of each port.
Rev. 5.00 Mar 28, 2005 page 371 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Table 10A.1 Port Functions
Port
Description
Port 1 • 8-bit I/O
port
• Schmitttriggered
input (P16,
P14)
Pins
P17/PO15/TIOCB2/
PWM3/TCLKD
P16/PO14/TIOCA2/
PWM2/IRQ1
P15/PO13/TIOCB1/
TCLKC
P14/PO12/TIOCA1/
Mode 4
P13/PO11/TIOCD0/
TCLKB/A23
P12/PO10/TIOCC0/
TCLKA/A22
P11/PO9/TIOCB0/
DACK1/A21
P10/PO8/TIOCA0/
/A20
DACK0
P37 /TxD4
P36/RxD4
• Open-drain P35/SCK1/SCK4/
output
SCL0/IRQ5
capability
P34 /RxD1/SDA0
• SchmittP33 /TxD1/SCL1
triggered
input (P35,
P32)
Mode 6
8-bit I/O port also functioning as DMA
controller output pins (DACK0, DACK1), TPU
I/O pins (TCLKA, TCLKB, TCLKC, TCLKD,
TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1,
TIOCB1, TIOCA2, TIOCB2), PPG output pins
(PO15 to PO8), interrupt input pins (IRQ0,
IRQ1), 14-bit PWM output pins (PWM2,
PWM3), and address outputs (A20 to A23)
IRQ0
Port 3 • 8-bit I/O
port
Mode 5
Mode 7
8-bit I/O port
also functioning as DMA
controller
output pins
(DACK0,
DACK1), TPU
I/O pins
(TCLKA,
TCLKB,
TCLKC,
TCLKD,
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0,
TIOCA1,
TIOCB1,
TIOCA2,
TIOCB2), PPG
output pins
(PO15 to
PO8), interrupt
input pins
(IRQ0, IRQ1),
and 14-bit
PWM output
pins (PWM2,
PWM3)
8-bit I/O port also functioning as SCI (channel 0, 1, and 4) I/O
pins (TxD0, RxD0, SCK0, IrTxD, IrRxD, TxD1, RxD1, SCK1,
TxD4, RxD4, SCK4), interrupt input pins (IRQ4, IRQ5), and IIC
(channel 0 and 1) I/O pins (SCL0, SDA0, SCL1, SDA1)
P32 /SCK0/SDA1/IRQ4
P31 /RxD0/IrRxD
P30 /TxD0/IrTxD
Rev. 5.00 Mar 28, 2005 page 372 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port
Description
Port 4 • 8-bit input
port
Pins
P47 /AN7/DA1
P46 /AN6/DA0
Mode 4
Mode 5
Mode 6
Mode 7
8-bit input port also functioning as A/D converter analog inputs
(AN7 to AN0) and D/A converter analog outputs (DA1, DA0)
P45 /AN5
P44 /AN4
P43 /AN3
P42 /AN2
P41 /AN1
P40/AN0
Port 7 • 8-bit I/O
port
P77/TxD3
P76/RxD3
P75/TMO3/SCK3
P74/TMO2/MRES
P73/TMO1/TEND1/
CS7
P72/TMO0/TEND0/
CS6
P71/TMRI23/TMCI23/
DREQ1/ CS5
P70/TMRI01/TMCI01/
DREQ0/ CS4
Port 9 • 8-bit input
port
P97/AN15/DA3
P96/AN14/DA2
8-bit I/O port also functioning as 8-bit timer I/O
pins (TMRI01, TMCI01, TMRI23, TMCI23,
TMO0, TMO1, TMO2, TMO3), DMAC I/O pins
(DREQ0, TEND0, DREQ1, TEND1), bus
control output pins (CS4 to CS7), SCI I/O pins
(SCK3, RxD3, TxD3), and the manual reset
input pin (MRES)
8-bit I/O port
also functioning as 8-bit
timer I/O pins
(TMRI01,
TMCI01,
TMRI23,
TMCI23,
TMO0, TMO1,
TMO2, TMO3),
DMAC I/O pins
(DREQ0,
TEND0,
DREQ1,
TEND1), SCI
I/O pins
(SCK3, RxD3,
TxD3), and the
manual reset
input pin
(MRES)
8-bit input port also functioning as A/D converter analog inputs
(AN15 to AN8) and D/A converter analog outputs (DA3, DA2)
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
Rev. 5.00 Mar 28, 2005 page 373 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port
Description
Port A • 4-bit I/O
port
• Built-in
MOS input
pull-up
Pins
PA3/A19/SCK2
PA2/A18/RxD2
Mode 4
Mode 5
Mode 6
Mode 7
4-bit I/O port also functioning as SCI (channel
2) I/O pins (TxD2, RxD2, SCK2) and address
outputs (A19 to A16)
4-bit I/O port
also functioning as SCI
(channel 2)
I/O pins (TxD2,
RxD2, SCK2)
8-bit I/O port also functioning as TPU I/O pins
(TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3,
TIOCC3, TIOCB3, TIIOCA3) and address
outputs (A15 to A8)
8-bit I/O port
also
functioning as
TPU I/O pins
(TIOCB5,
TIOCA5,
TIOCB4,
TIOCA4,
TIOCD3,
TIOCC3,
TIOCB3,
TIIOCA3)
PA1/A17/TxD2
PA0/A16
• Open-drain
output
capability
Port B • 8-bit I/O
port
• Built-in
MOS input
pull-up
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
• Open-drain PB3/A11/TIOCD3
output
PB2/A10/TIOCC3
capability
PB1/A9/TIOCB3
PB0/A8/TIOCA3
Port C • 8-bit I/O
port
• Built-in
MOS input
pull-up
PC7/A7/PWM1
PC6/A6/PWM0
PC5/A5
PC4/A4
• Open-drain PC3/A3
output
PC2/A2
capability
PC1/A1
8-bit I/O port also functioning as 14-bit PWM
8-bit I/O port
(channel 1 and 0) output pins (PWM1, PWM0) also functionand address outputs (A7 to A0)
ing as 14-bit
PWM (channel
1 and 0) output
pins (PWM1,
PWM0)
PC0 /A0
Port D • 8-bit I/O
port
• Built-in
MOS input
pull-up
PD7 /D15
Data bus input/output
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0 /D8
Rev. 5.00 Mar 28, 2005 page 374 of 1422
REJ09B0234-0500
I/O port
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port
Description
Port E • 8-bit I/O
port
• Built-in
MOS input
pull-up
Pins
Mode 4
Mode 5
Mode 6
PE7/D7
In 8-bit-bus mode: I/O port
PE6/D6
In 16-bit-bus mode: data bus input/output
Mode 7
I/O port
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0 /D0
Port F • 8-bit I/O
port
PF7/φ
When DDR = 0: input port
When DDR = 1 (after reset): φ output
When
DDR = 0 (after
reset): input
port
When
DDR = 1: φ
output
PF6 /AS/LCAS
RD HWR
PF5 /RD
ADTRG
PF4 /HWR
When LCASS = 0: AS output
PF3/LWR/ADTRG/
When RMTS2 to RMTS0 = B'001 to B'011,
CW2 = 0, and LCASS = 1: LCAS output
IRQ3
PF2/LCAS/WAIT/
BREQO
,
, LWR outputs
, IRQ3 input
When WAITE = 0 and BREQOE = 0 (after
reset): I/O port
I/O port
, IRQ3
ADTRG
input
I/O port
When WAITE = 1 and BREQOE = 0: WAIT
input
When WAITE = 0 and BREQOE = 1: BREQO
input
When RMTS2 to RMTS0 = B'001 to B'011,
CW2 = 0, and LCASS = 0: LCAS output
PF1/BACK/BUZZ
When BRLE = 0 (after reset): I/O port
BUZZ output
PF0/BREQ/IRQ2
When BRLE = 1: BREQ input, BACK output
IRQ2
BUZZ output, IRQ2 input
I/O port
input
Rev. 5.00 Mar 28, 2005 page 375 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port
Description
Port G • 5-bit I/O
port
Pins
PG4 /CS0
Mode 4
Mode 5
Mode 6
When DDR = 0*1: input port
Mode 7
I/O port
When DDR = 1*2: CS0 output
PG3 /CS1
When DDR = 0 (after reset): input port
PG2 /CS2
When DDR = 1: CS1, CS2, CS3 outputs
PG1 /CS3/ OE/IRQ7
OE
PG0 /CAS/ IRQ6
DRAM space set: CAS output
output, IRQ7 input
Otherwise (after reset): I/O port
IRQ6
Notes: 1. After a reset in mode 6
2. After a reset in modes 4 or 5
Rev. 5.00 Mar 28, 2005 page 376 of 1422
REJ09B0234-0500
I/O port, IRQ7
input
input
I/O port, IRQ6
input
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.2 Port 1
10A.2.1 Overview
Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O
pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1,
TIOCB1, TIOCA2, and TIOCB2), DMAC output pins (DACK0 and DACK1), 14-bit PWM
output pins (PWM2 and PWM3), external interrupt input pins (IRQ0 and IRQ1), and address bus
output pins (A23 to A20). Port 1 pin functions change according to the operating mode.
Figure 10A.1 shows the port 1 pin configuration.
Port 1 pins
Pin functions in modes 4 to 6
P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / PWM3 (output) / TCLKD (input)
P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / PWM2 (output) / IRQ1 (input)
P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input)
Port 1
P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input)
P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input) / A23 (output)
P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input) / A22 (output)
P11 (I/O) / PO9 (output) / TIOCB0 (I/O) / DACK1 (output) / A21 (output)
P10 (I/O) / PO8 (output) / TIOCA0 (I/O) / DACK0 (output) / A20 (output)
Pin functions in mode 7
P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / PWM3 (output) / TCLKD (input)
P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / PWM2 (output) / IRQ1 (input)
P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input)
P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input)
P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input)
P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input)
P11 (I/O) / PO9 (output) / TIOCB0 (I/O) / DACK1 (output)
P10 (I/O) / PO8 (output) / TIOCA0 (I/O) / DACK0 (output)
Figure 10A.1 Port 1 Pin Functions
Rev. 5.00 Mar 28, 2005 page 377 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.2.2 Register Configuration
Table 10A.2 shows the port 1 register configuration.
Table 10A.2 Port 1 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 1 data direction register
P1DDR
W
H'00
H'FE30
Port 1 data register
P1DR
R/W
H'00
H'FF00
Port 1 register
PORT1
R
Undefined
H'FFB0
Note: * Lower 16 bits of the address.
Port 1 Data Direction Register (P1DDR)
Bit
:
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode. Because PPG, TPU, DMAC, and PWM
are initialized at a manual reset, pin states are determined by P1DDR and P1DR.
Port 1 Data Register (P1DR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10).
P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Rev. 5.00 Mar 28, 2005 page 378 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port 1 Register (PORT1)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P17
—*
P16
—*
P15
—*
P14
—*
P13
—*
P12
—*
P11
—*
P10
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins P17 to P10.
PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 1 pins (P17 to P10) must always be performed on P1DR.
If a PORT1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a
PORT1 read is performed while P1DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin
states, as P1DDR and P1DR are initialized. PORT1 retains its prior state by a manual reset or in
software standby mode.
10A.2.3 Pin Functions
Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB,
TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and
TIOCB2), DMAC output pins (DACK0 and DACK1), external interrupt input pins (IRQ0 and
IRQ1), 14-bit PWM output pins (PWM2 and PWM3), and address bus output pins (A23 to A20).
Port 1 pin functions are shown in table 10A.3.
Rev. 5.00 Mar 28, 2005 page 379 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Table 10A.3 Port 1 Pin Functions
Pin
Selection Method and Pin Functions
P17/PO15/
TIOCB2/PWM3/
TCLKD
The pin function is switched as shown below according to the combination of
the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0
in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in
TCR0 and TCR5, OEB bit in DACR3, bit NDER15 in NDERH, and bit
P17DDR.
TPU Channel
2 Setting
Table Below (1)
Table Below (2)
OEB
—
0
0
0
1
P17DDR
—
0
1
1
—
NDER15
—
—
0
1
—
Pin function
TIOCB2 output
P17
P17
PO15
PWM3
input
output
output
output
TIOCB2 input*1
TCLKD input*2
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 =
1.
2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2
to TPSC0 = B'111.
TCLKD input when channels 2 and 4 are set to phase counting
mode.
TPU Channel
2 Setting
MD3 to MD0
IOB3 to IOB0
CCLR1,
CCLR0
Output
function
(2)
(1)
(2)
B'0000, B'01xx
B'0010
B'0000 B'0001 to
—
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Rev. 5.00 Mar 28, 2005 page 380 of 1422
REJ09B0234-0500
Output
compare
output
—
(2)
B'xx00
—
—
(1)
(2)
B'0011
Other than B'xx00
Other
B'10
than B'10
PWM
—
mode 2
output
x: Don’t care
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P16/PO14/
TIOCA2/PWM2/
The pin function is switched as shown below according to the combination of
the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0
in TIOR2, and bits CCLR1 and CCLR0 in TCR2), OEA bit in DACR3, bit
NDER14 in NDERH, and bit P16DDR.
IRQ1
TPU Channel
2 Setting
Table Below (1)
Table Below (2)
OEA
—
0
0
0
1
P16DDR
—
0
1
1
—
NDER14
—
—
0
1
—
TIOCA2 output
P16
input
P16
output
Pin function
IRQ1
TPU Channel
2 Setting
MD3 to MD0
IOA3 to IOA0
CCLR1,
CCLR0
Output
function
(2)
(1)
(2)
B'0000, B'01xx
B'001x
B'0000 B'0001 to B'xx00
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
PO14
output
TIOCA2 input*1
PWM2
output
input
(1)
(1)
(2)
B'0010
B'0011
Other than B'xx00
—
Other
B'01
than B'01
—
PWM
PWM
mode 1 mode 2
output*2 output
x: Don’t care
Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 =
1.
2. TIOCB2 output is disabled.
Rev. 5.00 Mar 28, 2005 page 381 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P15/PO13/
TIOCB1/TCLKC
The pin function is switched as shown below according to the combination of
the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0
in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in
TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.
TPU Channel
1 Setting
Table Below (1)
Table Below (2)
P15DDR
—
0
1
1
NDER13
—
—
0
1
TIOCB1 output
P15
input
P15
output
PO13
output
Pin function
TIOCB1 input*1
TCLKC input
*2
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3
to IOB0 = B'10xx.
2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2
to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is
TPSC2 to TPSC0 = B'101.
TCLKC input when channels 2 and 4 are set to phase counting
mode.
TPU Channel
1 Setting
MD3 to MD0
IOB3 to IOB0
CCLR1,
CCLR0
Output
function
(2)
(1)
(2)
B'0000, B'01xx
B'0010
B'0000 B'0001 to
—
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Rev. 5.00 Mar 28, 2005 page 382 of 1422
REJ09B0234-0500
Output
compare
output
—
(2)
B'xx00
—
—
(1)
(2)
B'0011
Other than B'xx00
Other
B'10
than
B'10
—
PWM
mode 2
output
x: Don’t care
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P14/PO12/
TIOCA1/IRQ0
The pin function is switched as shown below according to the combination of
the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0
in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and
bit P14DDR.
TPU Channel
1 Setting
Table Below (1)
Table Below (2)
P14DDR
—
0
1
1
NDER12
—
—
0
1
TIOCA1 output
P14
input
P14
output
PO12
output
Pin function
TIOCA1 input*1
IRQ0
TPU Channel
1 Setting
MD3 to MD0
IOA3 to IOA0
CCLR1,
CCLR0
Output
function
(2)
(1)
(2)
B'0000, B'01xx
B'001x
B'0000 B'0001 to B'xx00
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
input
(1)
B'0010
Other
than
B'xx00
(1)
(2)
B'0011
Other than B'xx00
—
Other
B'01
than B'01
PWM
PWM
—
mode 1 mode 2
output*2 output
x: Don’t care
Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to
IOA0 = B'10xx.
2. TIOCB1 output is disabled.
Rev. 5.00 Mar 28, 2005 page 383 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P13/PO11/
TIOCD0/TCLKB/
A23
The pin function is switched as shown below according to the combination of
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0),
bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, bit
NDER11 in NDERH, and bit P13DDR.
Modes 4 to 6
Operating
mode
AE3 to AE0
TPU Channel
0 Setting
B'0000 to B'1110
Table
Below (1)
B'1111
Table Below (2)
—
P13DDR
—
0
1
1
—
NDER11
—
—
0
1
—
TIOCD0
output
P13 input
P13 output
PO11
output
A23 output
Pin function
TIOCD0 input*1
TCLKB input*2
Mode 7
Operating
mode
AE3 to AE0
TPU Channel
0 Setting
—
Table
Below (1)
Table Below (2)
P13DDR
—
0
1
1
NDER11
—
—
0
1
TIOCD0
output
P13 input
P13 output
PO11 output
Pin function
TIOCD0 input*1
TCLKB input*2
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 =
B'10xx.
2. TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to
TPSC0 = B'101.
TCLKB input when channels 1 and 5 are set to phase counting
mode.
Rev. 5.00 Mar 28, 2005 page 384 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P13/PO11/
TIOCD0/TCLKB/
A23 (cont)
TPU Channel
0 Setting
MD3 to MD0
IOD3 to IOD0
CCLR2 to
CCLR0
Output
function
(2)
(1)
(2)
B'0000
B'0010
B'0000 B'0001 to
—
B'0011
B'0100
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
(2)
B'xx00
—
—
(1)
(2)
B'0011
Other than B'xx00
Other
than
B'110
B'110
—
PWM
mode 2
output
x: Don’t care
Rev. 5.00 Mar 28, 2005 page 385 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P12/PO10/
TIOCC0/TCLKA/
A22
The pin function is switched as shown below according to the combination of
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0),
bits TPSC2 to TPSC0 in TCR0 to TCR5, bits AE3 to AE0 in PFCR, bit
NDER10 in NDERH, and bit P12DDR.
Modes 4 to 6
Operating
mode
AE3 to AE0
TPU Channel
0 Setting
B'0000 to B'1110
Table
Below (1)
B'1111
Table Below (2)
—
P12DDR
—
0
1
1
—
NDER10
—
—
0
1
—
TIOCC0
output
P12
input
P12
output
PO10
output
A22 output
Pin function
TIOCC0 input*1
TCLKA input*2
Mode 7
Operating
mode
AE3 to AE0
TPU Channel
0 Setting
—
Table
Below (1)
Table Below (2)
P12DDR
—
0
1
1
NDER10
—
—
0
1
TIOCC0
output
P12 input
P12 output
PO10 output
Pin function
TIOCC0 input*1
TCLKA input*2
Rev. 5.00 Mar 28, 2005 page 386 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P12/PO10/
TIOCC0/TCLKA/
A22 (cont)
TPU Channel
0 Setting
MD3 to MD0
IOC3 to IOC0
CCLR2 to
CCLR0
Output
function
(2)
(1)
(2)
B'0000
B'001x
B'0000 B'0001 to B'xx00
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
(1)
(1)
(2)
B'0010
B'0011
Other than B'xx00
—
PWM
mode 1
3
output*
Other
than
B'101
B'101
—
PWM
mode 2
output
x: Don’t care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 =
B'10xx.
2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to
TPSC0 = B'100.
TCLKA input when channels 1 and 5 are set to phase counting
mode.
3. TIOCD0 output is disabled.
When BFA = 1 or BFB = 1 in TMDR0, output is disabled and
setting (2) applies.
Rev. 5.00 Mar 28, 2005 page 387 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P11/PO9/TIOCB0/ The pin function is switched as shown below according to the combination of
DACK1/A21
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, and bits IOB3 to IOB0 in TIOR0H), bits AE3 to AE0 in PFCR, bit
NDER9 in NDERH, SAE1 bit in DMABCRH, and bit P11DDR.
Modes 4 to 6
Operating
mode
AE3 to AE0
B'0000 to B'1101
SAE1
B'1110 to
B'1111
0
TPU Channel
0 Setting
Table
Below (1)
Table Below (2)
1
—
—
—
P11DDR
—
0
1
1
—
—
NDER9
—
—
0
1
—
—
TIOCB0
output
P11
input
P11
output
PO9
output
DACK1
A21
output
Pin function
output
*
TIOCB0 input
Mode 7
Operating
mode
AE3 to AE0
—
SAE1
0
TPU Channel
0 Setting
Table
Below (1)
1
Table Below (2)
—
P11DDR
—
0
1
1
—
NDER9
—
—
0
1
—
TIOCB0
output
P11
input
P11
output
Pin function
Note: *
PO9
output
TIOCB0 input*
DACK1
output
TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 =
B'10xx.
Rev. 5.00 Mar 28, 2005 page 388 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P11/PO9/TIOCB0/ TPU Channel
DACK1/A21 (cont)
0 Setting
MD3 to MD0
IOB3 to IOB0
CCLR2 to
CCLR0
Output
function
(2)
(1)
(2)
B'0000
B'0010
B'0000 B'0001 to
—
B'0011
B'0100
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
(2)
B'xx00
—
—
(1)
(2)
B'0011
Other than B'xx00
Other
than
B'010
B'010
—
PWM
mode 2
output
x: Don’t care
Rev. 5.00 Mar 28, 2005 page 389 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P10/PO8/TIOCA0/ The pin function is switched as shown below according to the combination of
DACK0/A20
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0),
bits AE3 to AE0 in PFCR, bit NDER8 in NDERH, SAE0 bit in DMABCRH, and
bit P10DDR.
Modes 4 to 6
Operating
mode
AE3 to AE0
B'0000 to B'1110
SAE0
TPU Channel
0 Setting
B'1101 to
B'1111
0
Table
Below (1)
Table Below (2)
1
—
—
—
P10DDR
—
0
1
1
—
—
NDER8
—
—
0
1
—
—
TIOCA0
output
P10
input
P10
output
DACK0
A20
output
Pin function
PO8
output
TIOCA0 input*1
Mode 7
Operating
mode
AE3 to AE0
—
SAE0
TPU Channel
0 Setting
P10DDR
NDER8
Pin function
output
0
Table
Below (1)
—
1
Table Below (2)
0
1
1
1
—
—
0
TIOCA0
output
P10
input
P10
output
Rev. 5.00 Mar 28, 2005 page 390 of 1422
REJ09B0234-0500
—
PO8
output
TIOCA0 input*1
—
—
DACK0
output
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P10/PO8/TIOCA0/ TPU Channel
DACK0/A20 (cont)
0 Setting
MD3 to MD0
IOA3 to IOA0
CCLR2 to
CCLR0
Output
function
(2)
(1)
(2)
B'0000
B'001x
B'0000 B'0001 to B'xx00
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
(1)
(1)
(2)
B'0010
B'0011
Other than B'xx00
—
PWM
mode 1
2
output*
Other
than
B'001
B'001
—
PWM
mode 2
output
x: Don’t care
Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 =
B'10xx.
2. TIOCB0 output is disabled.
Rev. 5.00 Mar 28, 2005 page 391 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.3 Port 3
10A.3.1 Overview
Port 3 is an 8-bit I/O port. Port 3 is a multi-purpose port for SCI I/O pins (TxD0, RxD0, SCK0,
IrTxD, IrRxD, TxD1, RxD1, SCK1, TxD4, RxD4, and SCK4), external interrupt input pins (IRQ4
and IRQ5) and IIC I/O pins (SCL0, SDA0, SCL1, and SDA1). All of the port 3 pin functions have
the same operating mode. The configuration for each of the port 3 pins is shown in figure 10A.2.
Port 3 pins
P37 (I/O) / TxD4 (output)
P36 (I/O) / RxD4 (input)
P35 (I/O) / SCK1 (I/O) /
SCK4 (I/O) / SCL0 (I/O) / IRQ5 (input)
Port 3
P34 (I/O) / RxD1 (input) / SDA0 (I/O)
P33 (I/O) / TxD1 (input) / SCL1 (I/O)
P32 (I/O) / SCK0 (I/O) / SDA1 (I/O) / IRQ4 (input)
P31 (I/O) / RxD0 (input) / IrRxD (input)
P30 (I/O) / TxD0 (output) / IrTxD (output)
Figure 10A.2 Port 3 Pin Functions
10A.3.2 Register Configuration
Table 10A.4 shows the configuration of port 3 registers.
Table 10A.4 Port 3 Register Configuration
Name
Abbreviation
R/W
Initial Value
Address*
Port 3 data direction register
P3DDR
W
H'00
H'FE32
Port 3 data register
P3DR
R/W
H'00
H'FF02
Port 3 register
PORT3
R
Undefined
H'FFB2
Port 3 open drain control register
P3ODR
R/W
H'00
H'FE46
Note: * Lower 16 bits of the address.
Rev. 5.00 Mar 28, 2005 page 392 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port 3 Data Direction Register (P3DDR)
Bit
7
:
6
5
4
3
2
1
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit.
Read is disenabled. If a read is carried out, undefined values are read out.
By setting P3DDR to 1, the corresponding port 3 pins become output, and be clearing to 0 they
become input.
P3DDR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode. In manual reset SCI and IIC
are initialized, so the pin state is determined by the specification of P3DDR and P3DR.
Port 3 Data Register (P3DR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P37DR
P36DR
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3DR is an 8-bit readable/writable register, which stores the output data of port 3 pins (P35 to
P30).
P3DR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous state
is maintained by a manual reset and in software standby mode.
Port 3 Register (PORT3)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P37
P36
P35
P34
P33
P32
P31
P30
—*
—*
—*
—*
—*
—*
—*
—*
R
R
R
R
R
R
R
R
Note: * Determined by the state of pins P37 to P30.
Rev. 5.00 Mar 28, 2005 page 393 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled.
Always carry out writing off output data of port 3 pins (P37 to P30) to P3DR without fail.
When P3DDR is set to 1, if PORT3 is read, the values of P3DR are read. When P3DDR is cleared
to 0, if PORT3 is read, the states of pins are read out.
P3DDR and P3DR are initialized by a power-on reset and in hardware standby mode, so PORT3 is
determined by the state of the pins. The previous state is maintained by a manual reset and in
software standby mode.
Port 3 Open Drain Control Register (P3ODR)
Bit
:
7
6
5
4
3
2
1
0
P37ODR P36ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3ODR is an 8-bit readable/writable register, which controls the on/off of port 3 pins (P37 to
P30).
By setting P3ODR to 1, the port 3 pins become an open drain out, and when cleared to 0 they
become CMOS output.
P3ODR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode.
10A.3.3 Pin Functions
The port 3 pins double as SCI I/O input pins (TxD0, RxD0, SCK0, IrTxD, IrRxD, TxD1, RxD1,
SCK1, TxD4, RxD4, SCK4), external interrupt input pins (IRQ4, IRQ5), and IIC I/O pins (SCL0,
SDA0, SCL1, SDA1). The functions of port 3 pins are shown in table 10A.5.
Rev. 5.00 Mar 28, 2005 page 394 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Table 10A.5 Port 3 Pin Functions
Pin
Selection Method and Pin Functions
P37/TxD4
Switches as follows according to combinations of SCR TE bit of SCI4 and the
P37DDR bit.
TE
0
P37DDR
Pin function
1
0
1
—
P37 input pin
P37 output pin*
TxD4 output pin
Note: * When P37ODR = 1, it becomes NMOS open drain output.
P36/RxD4
Switches as follows according to combinations of SCR RE bit of SCI4 and the
P36DDR bit.
RE
0
P36DDR
Pin function
1
0
1
—
P36 input pin
P36 output pin*
RxD4 input pin
Note: * When P36ODR = 1, it becomes NMOS open drain output.
P35/SCK1/
SCK4/SCL0/
Switches as follows according to combinations of ICCR0 ICE bit of IIC0, SMR C/A
bit of SCI1 or SCI4, SCR CKE0 and CKE1 bits, and the P35DDR bit.
IRQ5
When used as a SCL0 I/O pin, always be sure to clear the following bits to 0: SMR
C/A bits of SCI1 or SCI4, and SCR CKE0 and CKE1 bits. Do not set SCK1 and
SCK4 to simultaneous output.
The SCL0 output format is NMOS open drain output, enabling direct bus driving.
ICE
0
CKE1 (SCI1)
CKE1 (SCI4)
0
0
C/A (SCI1)
C/A (SCI4)
Pin function
0, 1, 1
1, 0, 1
0
0
1
1
—
0
0
0, 1, 1*2
1, 0, 1*2
—
—
0
0
—
—
—
—
0
0
CKE0 (SCI1)
CKE0 (SCI4)
P35DDR
1
0
0
0
P35
input pin
1
P35
SCK1/SCK4 SCK1/SCK4 SCK1/SCK4 SCL0
output pin*1 output pin*1 output pin*1
input pin
I/O pin
IRQ5
input
Notes: 1. Output type is NMOS push-pull. When P35ODR = 1, it becomes NMOS open
drain output.
2. SCK1 and SCK4 must not be output simultaneously.
Rev. 5.00 Mar 28, 2005 page 395 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P34/RxD1/
SDA0
Switches as follows according to combinations of ICCR0 ICE bit of IIC0, SCR RE bit
of SCI1, and the P34DDR bit.
The SDA0 output format becomes NMOS open drain output, enabling direct bus
driving.
ICE
0
RE
0
P34DDR
Pin function
1
1
0
1
—
—
—
P34 output pin* RxD1 input pin
P34 input pin
SDA0 I/O pin
Note: * Output type is NMOS push-pull. When P34ODR = 1, it becomes NMOS
open drain tray.
P33/TxD1/
SCL1
Switches as follows according to combinations of ICCR1 ICE bit of IIC1, SCR TE bit
of SCI1 and the P33DDR bit.
The SCL1 output format becomes NMOS open drain output, enabling direct bus
driving.
ICE
0
TE
0
P33DDR
Pin function
1
0
1
—
1
—
—
*
*
P33 output pin TxD1 output pin SCL1 I/O pin*
P33 input pin
Note: * When P33ODR = 1, it becomes NMOS open drain output.
P32/SCK0/
SDA1/IRQ4
Switches as follows according to combinations of ICCR1 ICE bit of IIC1, SMR C/A
bit of SCI0, SCR CKE0 and CKE1 bits, and the P32DDR bit.
If using as an SDA1 input pin, always set SMR C/A bit of SCI0 and SCR CKE0 and
CKE1 bits to 0 without fail.
The SDA1 output format becomes NMOS open drain output, enabling direct bus
driving.
ICE
0
CKE1
0
C/A
0
CKE0
P32DDR
Pin function
1
0
0
P32
input pin
1
1
0
1
—
0
1
—
—
0
—
—
—
—
P32
SCK0
SCK0
SCK0
output pin output pin* output pin* input pin
IRQ4
input
Note: * When P32ODR = 1, it becomes NMOS open drain output.
Rev. 5.00 Mar 28, 2005 page 396 of 1422
REJ09B0234-0500
SDA1
I/O pin
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P31/RxD0/
IrRxD
Switches as follows according to combinations of SCR RE bit of SCI0 and the
P31DDR bit.
RE
P31DDR
Pin function
0
1
0
1
—
P31 input pin
P31 output pin*
RxD0/IrRxD input pin
Note: * When P31ODR = 1, it becomes NMOS open drain output.
P30/TxD0/
IrTxD
Switches as follows according to combinations of SCR TE bit of SCI0 and the
P30DDR bit.
TE
P30DDR
Pin function
0
1
0
1
—
P30 input pin
P30 output pin*
TxD0/IrTxD output pin*
Note: * When P30ODR = 1, it becomes NMOS open drain output.
Rev. 5.00 Mar 28, 2005 page 397 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.4 Port 4
10A.4.1 Overview
Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins
(AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the
same in all operating modes. Figure 10A.3 shows the port 4 pin configuration.
Port 4 pins
P47 (input) / AN7 (input) / DA1 (output)
P46 (input) / AN6 (input) / DA0 (output)
P45 (input) / AN5 (input)
Port 4
P44 (input) / AN4 (input)
P43 (input) / AN3 (input)
P42 (input) / AN2 (input)
P41 (input) / AN1 (input)
P40 (input) / AN0 (input)
Figure 10A.3 Port 4 Pin Functions
Rev. 5.00 Mar 28, 2005 page 398 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.4.2 Register Configuration
Table 10A.6 shows the port 4 register configuration. Port 4 is an input-only port, and does not
have a data direction register or data register.
Table 10A.6 Port 4 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 4 register
PORT4
R
Undefined
H'FFB3
Note: * Lower 16 bits of the address.
Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed.
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P47
—*
P46
—*
P45
—*
P44
—*
P43
—*
P42
—*
P41
—*
P40
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins P47 to P40.
10A.4.3 Pin Functions
Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter
analog output pins (DA0 and DA1).
Rev. 5.00 Mar 28, 2005 page 399 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.5 Port 7
10A.5.1 Overview
Port 7 is an 8-bit I/O port. Port 7 is a multipurpose port for the 8-bit timer I/O pins (TMRI01,
TMCI01, TMRI23, TMCI23, TMO0, TMO1, TMO2, and TMO3), DMAC I/O pins (DREQ0,
TEND0, DREQ1, and TEND1), bus control output pins (CS4 to CS7), SCI I/O pins (SCK3,
RxD3, and TxD3) and manual reset input pin (MRES). The pin functions for P77 to P74 are the
same in all operating modes. P73 to P70 pin functions are switched according to operating mode.
Figure 10A.4 shows the configuration for port 7 pins.
Port 7
Port 7 pins
Pin functions in modes 4 to 6
P77 / TxD3
P77 (I/O) / TxD3 (output)
P76 / RxD3
P76 (I/O) / RxD3 (input)
P75 / TMO3 / SCK3
P75 (I/O) / TMO3 (output) / SCK3 (I/O)
P74 / TMO2 / MRES
P74 (I/O) / TMO2 (output) / MRES (input)
P73 / TMO1 / TEND1 / CS7
P73 (input) / TMO1 (output) / TEND1 (output) / CS7 (output)
P72 / TMO0 / TEND0 / CS6
P72 (input) / TMO0 (output) / TEND0 (output) / CS6 (output)
P71 / TMRI23 / TMCI23 / DREQ1 / CS5
P71 (input) / TMRI23 (input) / TMCI23 (input) / DREQ1 (input) / CS5 (output)
P70 / TMRI01 / TMCI01 / DREQ0 / CS4
P70 (input) / TMRI01 (input) / TMCI01 (input) / DREQ0 (input) / CS4 (output)
Pin functions in mode 7
P77 (I/O) / TxD3 (output)
P76 (I/O) / RxD3 (input)
P75 (I/O) / TMO3 (output) / SCK3 (I/O)
P74 (I/O) / TMO2 (output) / MRES (input)
P73 (I/O) / TMO1 (output) / TEND1 (output)
P72 (I/O) / TMO0 (output) / TEND0 (output)
P71 (I/O) / TMRI23 (input) / TMCI23 (input) / DREQ1 (input)
P70 (I/O) / TMRI01 (input) / TMCI01 (input) / DREQ0 (input)
Figure 10A.4 Port 7 Pin Functions
Rev. 5.00 Mar 28, 2005 page 400 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.5.2 Register Configuration
Table 10A.7 shows the port 7 register configuration.
Table 10A.7 Port 7 Register Configuration
Name
Abbreviation
R/W
Initial Value
Address*
Port 7 data direction register
P7DDR
W
H'00
H'FE36
Port 7 data register
P7DR
R/W
H'00
H'FF06
Port 7 register
PORT7
R
Undefined
H'FFB6
Note: * Lower 16 bits of the address.
Port 7 Data Direction Register (P7DDR)
Bit
:
7
6
5
4
3
2
1
0
P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
P7DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 7 pin by bit.
Read is disenabled. If a read is carried out, undefined values are read out.
By setting P7DDR to 1, the corresponding port 7 pins become output, and by clearing to 0 they
become input.
P7DDR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode. DMAC, 8-bit timer and SCI
are initialized by a manual reset, so the pin state is determined by the specification of P7DDR and
P7DR.
Rev. 5.00 Mar 28, 2005 page 401 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port 7 Data Register (P7DR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P77DR
P76DR
P75DR
P74DR
P73DR
P72DR
P71DR
P70DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P7DR is an 8-bit readable/writable register, which stores the output data of port 7 pins (P77 to
P70).
P7DR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous state
is maintained by a manual reset and in software standby mode.
Port 7 Register (PORT7)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
—*
—*
—*
—*
—*
—*
—*
—*
R
R
R
R
R
R
R
R
Note: * Determined by the state of pins P77 to P70.
PORT7 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled.
Always carry out writing off output data of port 7 pins (P77 to P70) to P7DR without fail.
When P7DDR is set to 1, if PORT7 is read, the values of P7DR are read. When P7DDR is cleared
to 0, if PORT7 is read, the states of pins are read out.
P7DDR and P7DR are initialized by a power-on reset and in hardware standby mode, so PORT7 is
determined by the state of the pins. The previous state is maintained by a manual reset and in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 402 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.5.3 Pin Functions
The pins of port 7 are multipurpose pins which function as 8-bit timer I/O pins, (TMRI01,
TMCI01, TMRI23, TMCI23, TMO0, TMO1, TMO2, and TMO3), DMAC I/O pins (DREQ0,
TEND0, DREQ1, and TEND1), bus control output pins (CS4 to CS7), SCI I/O pins (SCK3,
RxD3, and TxD3) and manual reset input pin (MRES). Table 10A.8 shows the functions of port 7
pins.
Table 10A.8 Port 7 Pin Functions
Pin
Selection Method and Pin Functions
P77/TxD3
Switches as follows according to combinations of SCR TE bit of SCI3, and the
P77DDR bit.
TE
0
P77DDR
Pin function
P76/RxD3
0
1
—
P77 input pin
P77 output pin
TxD3 output pin
Switches as follows according to combinations of SCR RE bit of SCI3 and the
P76DDR bit.
RE
0
P76DDR
Pin function
P75/TMO3/
SCK3
1
1
0
1
—
P76 input pin
P76 output pin
RxD3 I/O pin
Switches as follows according to combinations of SMR C/A bit of SCI3, SCR CKE0
and CKE1 bits, TCSR3 OS3 to OS0 bits of the 8-bit timer, and the P75DDR bit.
OS3 to OS0
All 0
CKE1
0
C/A
Pin function
1
—
1
—
—
1
—
—
—
—
—
—
—
SCK3
input pin
TMO3
output
0
CKE0
P75DDR
Any is 1
0
0
P75
input pin
1
P75
SCK3
SCK3
output pin output pin output pin
Rev. 5.00 Mar 28, 2005 page 403 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P74/TMO2/
Switches as follows according to combinations of TCSR2 OS3 to OS0 bits of the 8bit timer, SYSCR MRESE bit and the P74DDR bit.
MRES
MRESE
0
OS3 to OS0
All 0
P74DDR
Pin function
P73/TMO1/
TEND1/CS7
Any is 1
—
—
0
1
—
P74 input pin
P74 output pin
TMO2 output
MRES
input pin
Switches as follows according to combinations of operating mode and DMATCR
TEE1 bit of DMAC, TCSR1 OS3 to OS0 bits of the 8-bit timer, and the P73DDR bit.
Operating
Mode
Modes 4 to 6
TEE1
0
OS3 to OS0
P73DDR
Pin function
P72/TMO0/
TEND0/CS6
1
All 0
Mode 7
1
Any is 1
—
0
All 0
1
Any is 1
—
0
1
—
—
0
1
—
—
P73
input
pin
CS7
TMO1
output
TEND1
P73
input
pin
P73
output
pin
TMO1
output
TEND1
output
pin
output
output
Switches as follows according to combinations of operating mode and DMATCR
TEE0 bit of DMAC, OS3 to OS0 bits of 8-bit timer TCSR0, and the P72DDR bit.
Operating
Mode
Modes 4 to 6
TEE0
0
OS3 to OS0
P72DDR
Pin function
All 0
Mode 7
1
Any is 1
—
0
All 0
1
Any is 1
—
0
1
—
—
0
1
—
—
P72
input
pin
CS6
TMO0
output
TEND1
P72
input
pin
P72
output
pin
TMO0
output
TEND1
output
pin
Rev. 5.00 Mar 28, 2005 page 404 of 1422
REJ09B0234-0500
output
output
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
P71/TMRI23/ Switches as follows according to operating mode and P71DDR.
TMCI23/
Operating
Modes 4 to 6
Mode 7
DREQ1/CS5
Mode
P71DDR
Pin function
0
P71 input Pin
1
CS5
output
—
DREQ0,
TMRI23,
TMCI23 input
0
1
P71 input pin
P71 output pin
, TMRI23, TMCI23 input
DREQ0
P70/TMRI01/ Switches as follows according to operating mode and P70DDR.
TMCI01/
Operating
Modes 4 to 6
Mode 7
DREQ0/CS4
Mode
P70DDR
Pin function
0
P70 input pin
DREQ0,
TMRI01,
TMCI01 input
1
CS4
output
—
0
1
P70 input pin
P70 output pin
, TMRI01, TMCI01 input
DREQ0
Rev. 5.00 Mar 28, 2005 page 405 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.6 Port 9
10A.6.1 Overview
Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins
(AN8 to AN15) and D/A converter analog output pins (DA2 and DA3). Port 9 pin functions are
the same in all operating modes. Figure 10A.5 shows the port 9 pin configuration.
Port 9 pins
P97 (input) / AN15 (input) / DA3 (output)
P96 (input) / AN14 (input) / DA2 (output)
P95 (input) / AN13 (input)
Port 9
P94 (input) / AN12 (input)
P93 (input) / AN11 (input)
P92 (input) / AN10 (input)
P91 (input) / AN9 (input)
P90 (input) / AN8 (input)
Figure 10A.5 Port 9 Pin Functions
Rev. 5.00 Mar 28, 2005 page 406 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.6.2 Register Configuration
Table 10A.9 shows the port 9 register configuration. Port 9 is an input-only port, and does not
have a data direction register or data register.
Table 10A.9 Port 9 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 9 register
PORT9
R
Undefined
H'FFB8
Note: * Lower 16 bits of the address.
Port 9 Register (PORT9): The pin states are always read when a port 9 read is performed.
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P97
—*
P96
—*
P95
—*
P94
—*
P93
—*
P92
—*
P91
—*
P90
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins P97 to P90.
10A.6.3 Pin Functions
Port 9 pins are multipurpose pins which function as A/D converter analog input pins (AN8 to
AN15) and D/A converter analog output pins (DA2 and DA3).
Rev. 5.00 Mar 28, 2005 page 407 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.7 Port A
10A.7.1 Overview
Port A is a 4-bit I/O port. Port A pins also function as SCI2 I/O pins (SCK2, RxD2, and TxD2)
and as address bus outputs. The pin functions change according to the operating mode.
Port A has a built-in MOS input pull-up function that can be controlled by software.
Figure 10A.6 shows the port A pin configuration.
Port A
Port A pins
Pin functions in modes 4 to 6
PA3/A19/SCK2
PA3 (I/O) / A19 (output) / SCK2 (I/O)
PA2/A18/RxD2
PA2 (I/O) / A18 (output) / RxD2 (input)
PA1/A17/TxD2
PA1 (I/O) / A17 (output) / TxD2 (output)
PA0/A16
PA0 (I/O) / A16 (output)
Pin functions in mode 7
PA3 (I/O) / SCK2 (output)
PA2 (I/O) / RxD2 (input)
PA1 (I/O) / TxD2 (output)
PA0 (I/O)
Figure 10A.6 Port A Pin Functions
Rev. 5.00 Mar 28, 2005 page 408 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.7.2 Register Configuration
Table 10A.10 shows the port A register configuration.
Table 10A.10 Port A Registers
Name
Abbreviation
R/W
Initial Value*2
Address*1
Port A data direction register
PADDR
W
H'0
H'FE39
Port A data register
PADR
R/W
H'0
H'FF09
Port A register
PORTA
R
Undefined
H'FFB9
Port A MOS pull-up control register
PAPCR
R/W
H'0
H'FE40
Port A open-drain control register
PAODR
R/W
H'0
H'FE47
Notes: 1. Lower 16 bits of the address.
2. Value of bits 3 to 0.
Port A Data Direction Register (PADDR)
Bit
:
7
6
5
4
—
—
—
—
3
2
1
0
PA3DDR PA2DDR PA1DDR PA0DDR
Initial value : Undefined Undefined Undefined Undefined
0
0
0
0
R/W
W
W
W
W
:
—
—
—
—
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
Bits 7 and 6 are reserved; they return an undetermined value if read.
PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode. The OPE bit in SBYCR is
used to select whether the address output pins retain their output state or become high-impedance
when a transition is made to software standby mode. See section 24.2.1, Standby Control Register
(SBYCR), for details.
• Modes 4 to 6
The corresponding port A pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of bits PA3DDR to PA0DDR. When pins are
not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 409 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
• Mode 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
Port A Data Register (PADR)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
PA3DR
PA2DR
PA1DR
PA0DR
0
0
0
0
R/W
R/W
R/W
R/W
Initial value : Undefined Undefined Undefined Undefined
R/W
:
—
—
—
—
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to
PA0).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 3 to 0) by a powr-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode.
Port A Register (PORTA)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
PA3
—*
PA2
—*
PA1
—*
PA0
—*
R
R
R
R
Initial value : Undefined Undefined Undefined Undefined
R/W
:
—
—
—
—
Note: * Determined by state of pins PA3 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA3 to PA0) must always be performed on PADR.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
If a PORTA read is performed while PADDR bits are set to 1, the PADR values are read. If a
PORTA read is performed while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin
states, as PADDR and PADR are initialized. PORTA retains its prior state by a manual reset or in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 410 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port A MOS Pull-Up Control Register (PAPCR)
Bit
:
7
6
5
4
—
—
—
—
3
:
—
—
—
1
0
PA3PCR PA2PCR PA1PCR PA0PCR
Initial value : Undefined Undefined Undefined Undefined
R/W
2
—
0
0
0
0
R/W
R/W
R/W
R/W
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on an individual bit basis.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. In
modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI’s
SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS
input pull-up for that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the SCI’s SCMR, SMR,
and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up
for that pin.
PAPCR is initialized by a manual reset or to H'0 (bits 3 to 0) by a power-on reset, and in hardware
standby mode. It retains its prior state in software standby mode.
Port A Open Drain Control Register (PAODR)
Bit
:
7
6
5
4
—
—
—
—
3
:
—
—
—
—
1
0
PA3ODR PA2ODR PA1ODR PA0ODR
Initial value : Undefined Undefined Undefined Undefined
R/W
2
0
0
0
0
R/W
R/W
R/W
R/W
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each
port A pin (PA3 to PA0).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR,
setting a PAODR bit makes the corresponding port A pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode.
Rev. 5.00 Mar 28, 2005 page 411 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.7.3 Pin Functions
Modes 4 to 6: In modes 4 to 6, port A pins function as address outputs according to the setting of
AE3 to AE0 in PFCR; when they do not function as address outputs, the pins function as SCI I/O
pins and I/O ports.
Port A pin functions in modes 4 to 6 are shown in figure 10A.7.
PA3 (I/O) / A19 (output) / SCK2 (I/O)
PA2 (I/O) / A18 (output) / RxD2 (input)
Port A
PA1 (I/O) / A17 (output) / TxD2 (output)
PA0 (I/O) / A16 (output)
Figure 10A.7 Port A Pin Functions (Modes 4 to 6)
Mode 7: In mode 7, port A pins function as I/O ports and SCI2 I/O pins (SCK2, TxD2, and
RxD2). Input or output can be specified for each pin on an individual bit basis. Setting a PADDR
bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the
pin an input port.
Port A pin functions are shown in figure 10A.8.
PA3 (I/O) / SCK2 (I/O)
Port A
PA2 (I/O) / RxD2 (input)
PA1 (I/O) / TxD2 (output)
PA0 (I/O)
Figure 10A.8 Port A Pin Functions (Mode 7)
Rev. 5.00 Mar 28, 2005 page 412 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.7.4 MOS Input Pull-Up Function
Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input
pull-up can be specified as on or off on an individual bit basis.
In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI’s
SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS
input pull-up for that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the SCI’s SCMR, SMR,
and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up
for that pin.
The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby
mode. The prior state is retained by a manual reset or in software standby mode.
Table 10A.11 summarizes the MOS input pull-up states.
Table 10A.11 MOS Input Pull-Up States (Port A)
Pin States
Power-On
Reset
Address output or OFF
SCI output
Other than above
Hardware
Standby Mode
Manual
Reset
Software
Standby Mode
In Other
Operations
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PADDR = 0 and PAPCR = 1; otherwise off.
Rev. 5.00 Mar 28, 2005 page 413 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.8 Port B
10A.8.1 Overview
Port B is an 8-bit I/O port. Port B pins also function as TPU I/O pins (TIOCA3, TIOCB3,
TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5) and as address outputs; the pin
functions change according to the operating mode.
Port B has a built-in MOS input pull-up function that can be controlled by software.
Figure 10A.9 shows the port B pin configuration.
Port B
Port B pins
Pin functions in modes 4 to 6
PB7/A15/TIOCB5
PB7 (I/O) / A15 (output) / TIOCB5 (I/O)
PB6/A14/TIOCA5
PB6 (I/O) / A14 (output) / TIOCA5 (I/O)
PB5/A13/TIOCB4
PB5 (I/O) / A13 (output) / TIOCB4 (I/O)
PB4/A12/TIOCA4
PB4 (I/O) / A12 (output) / TIOCA4 (I/O)
PB3/A11/TIOCD3
PB3 (I/O) / A11 (output) / TIOCD3 (I/O)
PB2/A10/TIOCC3
PB2 (I/O) / A10 (output) / TIOCC3 (I/O)
PB1/A9 /TIOCB3
PB1 (I/O) / A9 (output) / TIOCB3 (I/O)
PB0/A8 /TIOCA3
PB0 (I/O) / A8 (output) / TIOCA3 (I/O)
Pin functions in mode 7
PB7 (I/O) / TIOCB5 (I/O)
PB6 (I/O) / TIOCA5 (I/O)
PB5 (I/O) / TIOCB4 (I/O)
PB4 (I/O) / TIOCA4 (I/O)
PB3 (I/O) / TIOCD3 (I/O)
PB2 (I/O) / TIOCC3 (I/O)
PB1 (I/O) / TIOCB3 (I/O)
PB0 (I/O) / TIOCA3 (I/O)
Figure 10A.9 Port B Pin Functions
Rev. 5.00 Mar 28, 2005 page 414 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.8.2 Register Configuration
Table 10A.12 shows the port B register configuration.
Table 10A.12 Port B Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port B data direction register
PBDDR
W
H'00
H'FE3A
Port B data register
PBDR
R/W
H'00
H'FF0A
Port B register
PORTB
R
Undefined
H'FFBA
Port B MOS pull-up control register
PBPCR
R/W
H'00
H'FE41
Port B open-drain control register
PBODR
R/W
H'00
H'FE48
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
Bit
:
7
6
5
4
3
2
1
0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode. The OPE bit in SBYCR is used to select
whether the address output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
• Modes 4 to 6
The corresponding port B pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of the PBDDR bits. When pins are not used as
address outputs, setting a PBDDR bit to 1 makes the corresponding port B pin an output port,
while clearing the bit to 0 makes the pin an input port.
• Mode 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 415 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port B Data Register (PBDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PB7DR
PB6DR
PB5DR
PB4DR
PB3DR
PB2DR
PB1DR
PB0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to
PB0). PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains
its prior state by a manual reset or in software standby mode.
Port B Register (PORTB)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PB7
—*
PB6
—*
PB5
—*
PB4
—*
PB3
—*
PB2
—*
PB1
—*
PB0
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PB7 to PB0.
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port B pins (PB7 to PB0) must always be performed on PBDR.
If a PORTB read is performed while PBDDR bits are set to 1, the PBDR values are read. If a
PORTB read is performed while PBDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin
states, as PBDDR and PBDR are initialized. PORTB retains its prior state in software standby
mode.
Rev. 5.00 Mar 28, 2005 page 416 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port B MOS Pull-Up Control Register (PBPCR)
Bit
:
7
6
5
4
3
2
1
0
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port B on an individual bit basis.
In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s
TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for
that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the TPU’s TIOR and in
DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.
PBPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
Port B Open Drain Control Register (PBODR)
Bit
:
7
6
5
4
3
2
1
0
PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PBODR is an 8-bit readable/writable register that controls the PMOS on/off state for each port B
pin (PB7 to PB0).
When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR,
setting a PBODR bit makes the corresponding port B pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PBODR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
Rev. 5.00 Mar 28, 2005 page 417 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.8.3 Pin Functions
Modes 4 to 6: In modes 4 to 6, the corresponding port B pins become address outputs in
accordance with the setting of bits AE3 to AE0 in PFCR. When pins are not used as address
outputs, they function as TPU I/O pins and I/O ports.
Port B pin functions in modes 4 to 6 are shown in figure 10A.10.
PB7 (I/O) / A15 (output) / TIOCB5 (I/O)
PB6 (I/O) / A14 (output) / TIOCA5 (I/O)
PB5 (I/O) / A13 (output) / TIOCB4 (I/O)
PB4 (I/O) / A12 (output) / TIOCA4 (I/O)
Port B
PB3 (I/O) / A11 (output) / TIOCD3 (I/O)
PB2 (I/O) / A10 (output) / TIOCC3 (I/O)
PB1 (I/O) / A9 (output) / TIOCB3 (I/O)
PB0 (I/O) / A8 (output) / TIOCA3 (I/O)
Figure 10A.10 Port B Pin Functions (Modes 4 to 6)
Mode 7: In mode 7, port B pins function as I/O ports and TPU I/O pins (TIOCA3, TIOCB3,
TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5). Input or output can be specified
for each pin on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B
pin an output port, while clearing the bit to 0 makes the pin an input port.
Port B pin functions in mode 7 are shown in figure 10A.11.
PB7 (I/O) / TIOCB5 (I/O)
PB6 (I/O) / TIOCA5 (I/O)
PB5 (I/O) / TIOCB4 (I/O)
Port B
PB4 (I/O) / TIOCA4 (I/O)
PB3 (I/O) / TIOCD3 (I/O)
PB2 (I/O) / TIOCC3 (I/O)
PB1 (I/O) / TIOCB3 (I/O)
PB0 (I/O) / TIOCA3 (I/O)
Figure 10A.11 Port B Pin Functions (Mode 7)
Rev. 5.00 Mar 28, 2005 page 418 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.8.4 MOS Input Pull-Up Function
Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input
pull-up can be specified as on or off on an individual bit basis.
In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s
TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for
that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the TPU’s TIOR and in
DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby
mode. The prior state is retained by a manual reset or in software standby mode.
Table 10A.13 summarizes the MOS input pull-up states.
Table 10A.13 MOS Input Pull-Up States (Port B)
Pin States
Address output or
TPU output
Other than above
Power-On
Reset
Hardware
Standby Mode
Manual
Reset
Software
Standby Mode
In Other
Operations
OFF
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PBDDR = 0 and PBPCR = 1; otherwise off.
Rev. 5.00 Mar 28, 2005 page 419 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.9 Port C
10A.9.1 Overview
Port C is an 8-bit I/O port. Port C pins also function as a 14-bit PWM output (PWM0 and PWM1)
and as an address bus outputs. The pin functions change according to the operating mode.
Port C has a built-in MOS input pull-up function that can be controlled by software.
Figure 10A.12 shows the port C pin configuration.
Port C
Port C pins
Pin functions in modes 4 and 5
PC7/A7/PWM1
A7 (output)
PC6/A6/PWM0
A6 (output)
PC5/A5
A5 (output)
PC4/A4
A4 (output)
PC3/A3
A3 (output)
PC2/A2
A2 (output)
PC1/A1
A1 (output)
PC0/A0
A0 (output)
Pin functions in mode 6
Pin functions in mode 7
When PCDDR = 1
When PCDDR = 0
PC7 (I/O) / PWM1 (output)
A7 (output)
PC7 (input) / PWM1 (output)
PC6 (I/O) / PWM0 (output)
A6 (output)
PC6 (input) / PWM0 (output)
PC5 (I/O)
A5 (output)
PC5 (input)
PC4 (I/O)
A4 (output)
PC4 (input)
PC3 (I/O)
A3 (output)
PC3 (input)
PC2 (I/O)
A2 (output)
PC2 (input)
PC1 (I/O)
A1 (output)
PC1 (input)
PC0 (I/O)
A0 (output)
PC0 (input)
Figure 10A.12 Port C Pin Functions
Rev. 5.00 Mar 28, 2005 page 420 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.9.2 Register Configuration
Table 10A.14 shows the port C register configuration.
Table 10A.14 Port C Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port C data direction register
PCDDR
W
H'00
H'FE3B
Port C data register
PCDR
R/W
H'00
H'FF0B
Port C register
PORTC
R
Undefined
H'FFBB
Port C MOS pull-up control register
PCPCR
R/W
H'00
H'FE42
Port C open-drain control register
PCODR
R/W
H'00
H'FE49
Note: * Lower 16 bits of the address.
Port C Data Direction Register (PCDDR)
Bit
:
7
6
5
4
3
2
1
0
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.
PCDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode. The OPE bit in SBYCR is used to select
whether the address output pins retain their output state or become high-impedance when the
mode is changed to software standby mode.
• Modes 4 and 5
The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits.
• Mode 6
Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while
clearing the bit to 0 makes the pin an input port.
• Mode 7
Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing
the bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 421 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port C Data Register (PCDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PC7DR
PC6DR
PC5DR
PC4DR
PC3DR
PC2DR
PC1DR
PC0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to
PC0).
PCDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port C Register (PORTC)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PC7
—*
PC6
—*
PC5
—*
PC4
—*
PC3
—*
PC2
—*
PC1
—*
PC0
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PC7 to PC0.
PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port C pins (PC7 to PC0) must always be performed on PCDR.
If a PORTC read is performed while PCDDR bits are set to 1, the PCDR values are read. If a
PORTC read is performed while PCDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTC contents are determined by the pin
states, as PCDDR and PCDR are initialized. PORTC retains its prior state by a manual reset or in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 422 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port C MOS Pull-Up Control Register (PCPCR)
Bit
:
7
6
5
4
3
2
1
0
PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port C on an individual bit basis.
In modes 6 and 7, if PCPCR is set to 1 when the port is in the input state in accordance with the
settings of DACR and PCDDR in PWM, the MOS input pull-up is set to ON.
PCPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
Port C Open Drain Control Register (PCODR)
Bit
:
7
6
5
4
3
2
1
0
PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCDDR is an 8-bit read/write register and controls PMOS on/off of each pin (PC7 to PC0) of
port C.
If PCODR is set to 1 by setting AE3 to AE0 in PFCR in mode other than address output mode,
port C pins function as NMOS open drain outputs and when the setting is cleared to 0, the pins
function as CMOS outputs.
PCODR is initialized to H'00 in power-on reset mode or hardware standby mode. PCODR retains
the last state in manual reset mode or software standby mode.
Rev. 5.00 Mar 28, 2005 page 423 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.9.3 Pin Functions for Each Mode
(1) Modes 4 and 5
In modes 4 and 5, port C pins function as address outputs automatically.
Figure 10A.13 shows the port C pin functions.
A7 (output)
A6 (output)
A5 (output)
Port C
A4 (output)
A3 (output)
A2 (output)
A1 (output)
A0 (output)
Figure 10A.13 Port C Pin Functions (Modes 4 and 5)
(2) Mode 6
In mode 6, port C pints function as address outputs or input ports and I/O can be specified in bit
units. When each bit in PCDDR is set to 1, the corresponding pin functions as an address output
and when the bit cleared to 0, the pin functions as a PWM output and an input port.
Figure 10A.14 shows the port C pin functions.
Rev. 5.00 Mar 28, 2005 page 424 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port C
PCDDR= 1
PCDDR= 0
A7 (output)
PC7 (input) / PWM1 (output)
A6 (output)
PC6 (input) / PWM0 (output)
A5 (output)
PC5 (input)
A4 (output)
PC4 (input)
A3 (output)
PC3 (input)
A2 (output)
PC2 (input)
A1 (output)
PC1 (input)
A0 (output)
PC0 (input)
Figure 10A.14 Port C Pin Functions (Mode 6)
(3) Mode 7
In mode 7, port C pins function as PWM outputs and I/O ports and I/O can be specified for each
pin in bit units. When each bit in PCDDR is set to 1, the corresponding pin functions as an output
port and when the bit is cleared to 0, the pin functions as an input port.
Figure 10A.15 shows the port C pin functions.
PC7 (I/O) / PWM1 (output)
PC6 (I/O) / PWM0 (output)
PC5 (I/O)
Port C
PC4 (I/O)
PC3 (I/O)
PC2 (I/O)
PC1 (I/O)
PC0 (I/O)
Figure 10A.15 Port C Pin Functions (Mode 7)
Rev. 5.00 Mar 28, 2005 page 425 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.9.4 MOS Input Pull-Up Function
Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an
individual bit basis.
In modes 6 and 7, when PCPCR is set to 1 in the input state by setting of DACR and PCDDR, the
MOS input pull-up is set to ON.
The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby
mode. The prior state is retained by a manual reset or in software standby mode.
Table 10A.15 summarizes the MOS input pull-up states.
Table 10A.15 MOS Input Pull-Up States (Port C)
Pin States
Address output or
PWM output
Power-On
Reset
Hardware
Standby Mode
Manual
Reset
Software
Standby Mode
In Other
Operations
OFF
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
Other than above
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PCDDR = 0 and PCPCR = 1; otherwise off.
Rev. 5.00 Mar 28, 2005 page 426 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.10 Port D
10A.10.1 Overview
Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change
according to the operating mode.
Port D has a built-in MOS input pull-up function that can be controlled by software.
Figure 10A.16 shows the port D pin configuration.
Port D
Port D pins
Pin functions in modes 4 to 6
PD7/D15
D15 (I/O)
PD6/D14
D14 (I/O)
PD5/D13
D13 (I/O)
PD4/D12
D12 (I/O)
PD3/D11
D11 (I/O)
PD2/D10
D10 (I/O)
PD1/D9
D9
(I/O)
PD0/D8
D8
(I/O)
Pin functions in mode 7
PD7 (I/O)
PD6 (I/O)
PD5 (I/O)
PD4 (I/O)
PD3 (I/O)
PD2 (I/O)
PD1 (I/O)
PD0 (I/O)
Figure 10A.16 Port D Pin Functions
Rev. 5.00 Mar 28, 2005 page 427 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.10.2 Register Configuration
Table 10A.16 shows the port D register configuration.
Table 10A.16 Port D Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port D data direction register
PDDDR
W
H'00
H'FE3C
Port D data register
PDDR
R/W
H'00
H'FF0C
Port D register
PORTD
R
Undefined
H'FFBC
Port D MOS pull-up control register
PDPCR
R/W
H'00
H'FE43
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR)
Bit
:
7
6
5
4
3
2
1
0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
• Modes 4 to 6
The input/output direction specification by PDDDR is ignored, and port D is automatically
designated for data I/O.
• Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing
the bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 428 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port D Data Register (PDDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PD7DR
PD6DR
PD5DR
PD4DR
PD3DR
PD2DR
PD1DR
PD0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to
PD0).
PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port D Register (PORTD)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PD7
—*
PD6
—*
PD5
—*
PD4
—*
PD3
—*
PD2
—*
PD1
—*
PD0
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PD7 to PD0.
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port D pins (PD7 to PD0) must always be performed on PDDR.
If a PORTD read is performed while PDDDR bits are set to 1, the PDDR values are read. If a
PORTD read is performed while PDDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin
states, as PDDDR and PDDR are initialized. PORTD retains its prior state by a manual reset or in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 429 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port D MOS Pull-Up Control Register (PDPCR)
Bit
:
7
6
5
4
3
2
1
0
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port D on an individual bit basis.
When a PDDDR bit is cleared to 0 (input port setting) in mode 7, setting the corresponding
PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
PDPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
10A.10.3 Pin Functions
Modes 4 to 6: In modes 4 to 6, port D pins are automatically designated as data I/O pins.
Port D pin functions in modes 4 to 6 are shown in figure 10A.17.
D15 (I/O)
D14 (I/O)
D13 (I/O)
Port D
D12 (I/O)
D11 (I/O)
D10 (I/O)
D9
(I/O)
D8
(I/O)
Figure 10A.17 Port D Pin Functions (Modes 4 to 6)
Mode 7: In mode 7, port D pins function as I/O ports. Input or output can be specified for each pin
on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output
port, while clearing the bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 430 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port D pin functions in mode 7 are shown in figure 10A.18.
PD7 (I/O)
PD6 (I/O)
PD5 (I/O)
Port D
PD4 (I/O)
PD3 (I/O)
PD2 (I/O)
PD1 (I/O)
PD0 (I/O)
Figure 10A.18 Port D Pin Functions (Mode 7)
10A.10.4 MOS Input Pull-Up Function
Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit
basis.
When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR bit to 1 turns on
the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby
mode. The prior state is retained by a manual reset or in software standby mode.
Table 10A.17 summarizes the MOS input pull-up states.
Table 10A.17 MOS Input Pull-Up States (Port D)
Modes
Power-On
Reset
Hardware
Standby Mode
Manual
Reset
Software
Standby Mode
In Other
Operations
4 to 6
OFF
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
7
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PDDDR = 0 and PDPCR = 1; otherwise off.
Rev. 5.00 Mar 28, 2005 page 431 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.11 Port E
10A.11.1 Overview
Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change
according to the operating mode and whether 8-bit or 16-bit bus mode is selected.
Port E has a built-in MOS input pull-up function that can be controlled by software.
Figure 10A.19 shows the port E pin configuration.
Port E
Port E pins
Pin functions in modes 4 to 6
PE7/D7
PE7 (I/O) / D7 (I/O)
PE6/D6
PE6 (I/O) / D6 (I/O)
PE5/D5
PE5 (I/O) / D5 (I/O)
PE4/D4
PE4 (I/O) / D4 (I/O)
PE3/D3
PE3 (I/O) / D3 (I/O)
PE2/D2
PE2 (I/O) / D2 (I/O)
PE1/D1
PE1 (I/O) / D1 (I/O)
PE0/D0
PE0 (I/O) / D0 (I/O)
Pin functions in mode 7
PE7 (I/O)
PE6 (I/O)
PE5 (I/O)
PE4 (I/O)
PE3 (I/O)
PE2 (I/O)
PE1 (I/O)
PE0 (I/O)
Figure 10A.19 Port E Pin Functions
Rev. 5.00 Mar 28, 2005 page 432 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.11.2 Register Configuration
Table 10A.18 shows the port E register configuration.
Table 10A.18 Port E Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port E data direction register
PEDDR
W
H'00
H'FE3D
Port E data register
PEDR
R/W
H'00
H'FF0D
Port E register
PORTE
R
Undefined
H'FFBD
Port E MOS pull-up control register
PEPCR
R/W
H'00
H'FE44
Note: * Lower 16 bits of the address.
Port E Data Direction Register (PEDDR)
Bit
:
7
6
5
4
3
2
1
0
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
• Modes 4 to 6
When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit
to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the
pin an input port.
When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is
ignored, and port E is designated for data I/O.
For details of 8-bit and 16-bit bus modes, see section 7, Bus Controller.
• Mode 7
Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the
bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 433 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Port E Data Register (PEDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PE7DR
PE6DR
PE5DR
PE4DR
PE3DR
PE2DR
PE1DR
PE0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to
PE0).
PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port E Register (PORTE)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PE7
—*
PE6
—*
PE5
—*
PE4
—*
PE3
—*
PE2
—*
PE1
—*
PE0
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PE7 to PE0.
PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port E pins (PE7 to PE0) must always be performed on PEDR.
If a PORTE read is performed while PEDDR bits are set to 1, the PEDR values are read. If a
PORTE read is performed while PEDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin
states, as PEDDR and PEDR are initialized. PORTE retains its prior state by a manual reset or in
software standby mode.
Port E MOS Pull-Up Control Register (PEPCR)
Bit
:
7
6
5
4
3
2
1
0
PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Mar 28, 2005 page 434 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port E on an individual bit basis.
When a PEDDR bit is cleared to 0 (input port setting) with 8-bit bus mode selected in modes 4, 5,
or 6, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for
the corresponding pin.
PEPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
10A.11.3 Pin Functions
Modes 4 to 6: In modes 4 to 6, when 8-bit access is designated and 8-bit bus mode is selected,
port E pins are automatically designated as I/O ports. Setting a PEDDR bit to 1 makes the
corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.
When 16-bit bus mode is selected, the input/output direction specification by PEDDR is ignored,
and port E is designated for data I/O.
Port E pin functions in modes 4 to 6 are shown in figure 10A.20.
Port E
8-bit bus mode
16-bit bus mode
PE7 (I/O)
D7 (I/O)
PE6 (I/O)
D6 (I/O)
PE5 (I/O)
D5 (I/O)
PE4 (I/O)
D4 (I/O)
PE3 (I/O)
D3 (I/O)
PE2 (I/O)
D2 (I/O)
PE1 (I/O)
D1 (I/O)
PE0 (I/O)
D0 (I/O)
Figure 10A.20 Port E Pin Functions (Modes 4 to 6)
Mode 7: In mode 7, port E pins function as I/O ports. Input or output can be specified for each pin
on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port,
while clearing the bit to 0 makes the pin an input port.
Port E pin functions in mode 7 are shown in figure 10A.21.
Rev. 5.00 Mar 28, 2005 page 435 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
PE7 (I/O)
PE6 (I/O)
PE5 (I/O)
Port E
PE4 (I/O)
PE3 (I/O)
PE2 (I/O)
PE1 (I/O)
PE0 (I/O)
Figure 10A.21 Port E Pin Functions (Mode 7)
10A.11.4 MOS Input Pull-Up Function
Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7,
and can be specified as on or off on an individual bit basis.
When a PEDDR bit is cleared to 0 in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7,
setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby
mode. The prior state is retained by a manual reset or in software standby mode.
Table 10A.19 summarizes the MOS input pull-up states.
Table 10A.19 MOS Input Pull-Up States (Port E)
Modes
Power-On
Reset
Hardware
Standby Mode
Manual
Reset
Software
Standby Mode
In Other
Operations
7
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
OFF
OFF
OFF
4 to 6
8-bit bus
16-bit bus
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PEDDR = 0 and PEPCR = 1; otherwise off.
Rev. 5.00 Mar 28, 2005 page 436 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.12 Port F
10A.12.1 Overview
Port F is an 8-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and
IRQ3), BUZZ output pin, A/D trigger input pin (ADTRG), bus control signal input/output pins
(AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (φ)
output pin.
Figure 10A.22 shows the port F pin configuration.
Port F
Port F pins
Pin functions in modes 4 to 6
PF7/φ
PF7 (input) / φ (output)
PF6/AS/LCAS
AS (output) / LCAS (output)
PF5/RD
RD (output)
PF4/HWR
HWR (output)
PF3/LWR/ADTRG/IRQ3
PF3 (I/O) / LWR (output) / ADTRG (input) / IRQ3 (input)
PF2/LCAS/WAIT/BREQO
PF2 (I/O) / LCAS (output) / WAIT (input) / BREQO (output)
PF1/BACK/BUZZ
PF1 (I/O) / BACK (output) / BUZZ (output)
PF0/BREQ/IRQ2
PF0 (I/O) / BREQ (input) / IRQ2 (input)
Pin functions in mode 7
PF7 (input) / φ (output)
PF6 (I/O)
PF5 (I/O)
PF4 (I/O)
PF3 (I/O) / ADTRG (input) / IRQ3 (input)
PF2 (I/O)
PF1 (I/O) / BUZZ (output)
PF0 (I/O) / IRQ2 (input)
Figure 10A.22 Port F Pin Functions
Rev. 5.00 Mar 28, 2005 page 437 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.12.2 Register Configuration
Table 10A.20 shows the port F register configuration.
Table 10A.20 Port F Registers
Name
Abbreviation
R/W
Initial Value
Address*1
Port F data direction register
PFDDR
W
H'80/H'00*2
H'FE3E
Port F data register
PFDR
R/W
H'00
H'FF0E
Port F register
PORTF
R
Undefined
H'FFBE
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Port F Data Direction Register (PFDDR)
Bit
:
7
6
5
4
3
2
1
0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 4 to 6
Initial value :
1
0
0
0
0
0
0
0
R/W
:
W
W
W
W
W
W
W
W
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Mode 7
:
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 4 to
6, and to H'00 in mode 7. It retains its prior state by a manual reset or in software standby mode.
The OPE bit in SBYCR is used to select whether the bus control output pins retain their output
state or become high-impedance when a transition is made to software standby mode.
• Modes 4 to 6
Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR). PF6 functions as
a bus control output (LCAS) by setting of the bus controller.
Rev. 5.00 Mar 28, 2005 page 438 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pins PF2 to PF0 are designated as bus control input/output pins (LCAS, WAIT, BREQO,
BACK, and BREQ) by means of bus controller settings. At other times, setting a PFDDR bit
to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the
pin an input port.
• Mode 7
Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in
the case of pin PF7, the φ output pin. Clearing the bit to 0 makes the pin an input port.
Port F Data Register (PFDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PF7DR
PF6DR
PF5DR
PF4DR
PF3DR
PF2DR
PF1DR
PF0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port F Register (PORTF)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PF7
—*
PF6
—*
PF5
—*
PF4
—*
PF3
—*
PF2
—*
PF1
—*
PF0
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
If a PORTF read is performed while PFDDR bits are set to 1, the PFDR values are read. If a
PORTF read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin
states, as PFDDR and PFDR are initialized. PORTF retains its prior state by a manual reset or in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 439 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.12.3 Pin Functions
Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), BUZZ output pin, A/D
trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR, LCAS,
WAIT, BREQO, BREQ, and BACK) and the system clock (φ) output pin. The pin functions differ
between modes 4 to 6, and mode 7. Port F pin functions are shown in table 10A.21.
Table 10A.21 Port F Pin Functions
Pin
Selection Method and Pin Functions
PF7/φ
The pin function is switched as shown below according to bit PF7DDR.
PF7DDR
Pin function
PF6/AS/LCAS
0
1
PF7 input pin
φ output pin
The pin function is switched as shown below according to the combination of
the operating mode and bits RMTS2 to RMTS0, LCASS, BREQOE, WAITE,
ABW5 to ABW2, and PF2DDR.
Operating
Mode
Modes 4 to 6
Mode 7
LCASS
0
1*
PF6DDR
—
—
Pin function
AS
output pin
—
0
1
PF6 input pin PF6 output pin
LCAS
output pin
Note: * Restricted to RMTS2 to RMTS0=B'001 to B'011, DRAM space 16-bit
access in modes 4 to 6 only
PF5/RD
The pin function is switched as shown below according to the operating mode
and bit PF5DDR.
Operating
Mode
Modes 4 to 6
PF5DDR
—
Pin function
RD
Rev. 5.00 Mar 28, 2005 page 440 of 1422
REJ09B0234-0500
output pin
Mode 7
0
1
PF5 input pin
PF5 output pin
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
PF4/HWR
The pin function is switched as shown below according to the operating mode
and bit PF4DDR.
Operating
Mode
Modes 4 to 6
PF4DDR
—
Pin function
HWR
Mode 7
output pin
0
1
PF4 input pin
PF4 output pin
PF3/LWR/ADTRG/ The pin function is switched as shown below according to the operating mode,
IRQ3
the bus mode, A/D converter bits TRGS1 and TRGS0, and bit PF3DDR.
Modes 4 to 6
Operating
mode
Bus mode
16-bit bus
mode
PF3DDR
—
Pin function
Mode 7
8-bit bus mode
0
—
1
0
1
output PF3 input PF3 output PF3 input PF3 output
pin
pin
pin
pin
pin
1
ADTRG input pin*
LWR
IRQ3
input pin*2
Notes: 1. ADTRG input when TRGS0 = TRGS1 = 1.
2. When used as an external interrupt input pin, do not use as an I/O
pin for another function.
PF2/LCAS/WAIT/
BREQO
The pin function is switched as shown below according to the combination of
the operating mode and bits RMTS2 to RMTS0, LCASS, BREQOE, WAITE,
ABW5 to ABW2, and PF2DDR.
Modes 4 to 6
Operating
Mode
LCASS
0*
BREQOE
—
WAITE
—
PF2DDR
—
Mode 7
1
—
0
0
0
1
1
—
1
—
—
—
—
0
1
Pin function
LCAS
PF2
PF2
WAIT
BREQO
PF2
PF2
output input output
input output input output
pin
pin
pin
pin
pin
pin
pin
Note: * Restricted to RMTS2 to RMTS0=B'001 to B'011, DRAM space 16-bit
access in modes 4 to 6 only.
Rev. 5.00 Mar 28, 2005 page 441 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
PF1/BACK/
BUZZ
The pin function is switched as shown below according to the combination of
the operating mode and bits BRLE, BUZZE, and PF1DDR.
Operating
Mode
Modes 4 to 6
BRLE
0
BUZZE
PF1DDR
Pin function
PF0/BREQ/IRQ2
Mode 7
1
0
—
1
—
0
1
—
—
0
0
1
—
1
PF1
input
pin
PF1
output
pin
BUZZ
output
pin
BACK
output
pin
PF1
input
pin
PF1
output
pin
BUZZ
output
pin
The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE and PF0DDR.
Operating
Mode
Modes 4 to 6
BRLE
0
PF0DDR
Pin function
Mode 7
1
—
0
1
—
0
1
PF0
input pin
PF0
output pin
BREQ
input pin
PF0
input pin
PF0
output pin
IRQ2
Rev. 5.00 Mar 28, 2005 page 442 of 1422
REJ09B0234-0500
input pin
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.13 Port G
10A.13.1 Overview
Port G is a 5-bit I/O port and also used as external interrupt input pins (IRQ6 and IRQ7) and bus
control signal output pins (CS0 to CS3, CAS, and OE).
Figure 10A.23 shows the configuration of port G pins.
Port G pin
Port G
Pin Functions in Modes 4 to 6
PG4 / CS0
PG4 (input) / CS0 (output)
PG3 / CS1
PG3 (input) / CS1 (output)
PG2 / CS2
PG2 (input) / CS2 (output)
PG1 / CS3 / OE / IRQ7
PG1 (input) / CS3 (output) / OE (output) / IRQ7 (input)
PG0 / CAS / IRQ6
PG0 (I/O) / CAS (output) / IRQ6 (input)
Pin Functions in Mode 7
PG4 (I/O)
PG3 (I/O)
PG2 (I/O)
PG1 (I/O) / IRQ7 (input)
PG0 (I/O) / IRQ6 (input)
Figure 10A.23 Port G Pin Functions
Rev. 5.00 Mar 28, 2005 page 443 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
10A.13.2 Register Configuration
Table 10A.22 shows the port G register configuration.
Table 10A.22 Port G Registers
Name
Abbreviation
R/W
Initial Value*2 Address*1
Port G data direction register
PGDDR
W
H'10/H'00*3
H'FE3F
Port G data register
PGDR
R/W
H'00
H'FF0F
Port G register
PORTG
R
Undefined
H'FFBF
Notes: 1. Lower 16 bits of the address.
2. Value of bits 4 to 0.
3. The initial value varies according to the mode.
Port G Data Direction Register (PGDDR)
Bit
:
7
6
5
—
—
—
4
3
2
1
0
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
Modes 4 and 5
Initial value
: Undefined Undefined Undefined
1
0
0
0
0
R/W
:
W
W
W
W
W
—
—
—
Modes 6 and 7
Initial value
: Undefined Undefined Undefined
0
0
0
0
0
R/W
:
W
W
W
W
W
—
—
—
PGDDR is an 8-bit write only register and specifies I/O of each pin of port G in bit units. Read
processing is invalid. Bits 7 to 5 are reserved bits. When the contents are read, undefined values
are read.
In modes 4 and 5, the PGDDR bits are initialized to H'10 (bits 4 to 0) in power-on reset or
hardware standby mode, in modes 6 and 7, the bits are initialized to H'00 (bits 4 to 0). In manual
reset or software standby mode, PGDDR retains the last status. Use the OPE bit of SBYCR to
select whether the bus control output pin retains the output state or becomes the high-impedance
when the mode is changed to a software standby mode.
• Modes 4 to 6
When PGDDR is set to 1, pins PG4 to PG1 function as bus control signal output pins (CS0 to
CS3 and OE). When PGDDR is cleared to 0, the pins function as input ports.
Rev. 5.00 Mar 28, 2005 page 444 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
When the DRAM interface is set, pin PG0 functions as the CAS output pin. When PGDDR is
set to 1, the pin functions as an output port. When PGDDR is cleared to 0, the pin functions as
an input port.
See section 7, Bus Controller, for the DRAM interface.
• Mode 7
PGDDR to 1 it becomes an output port, and by clearing it to 0 it becomes an input port.
Port G Data Register (PGDR)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
PG4DR
PG3DR
PG2DR
PG1DR
PG0DR
Initial value : Undefined Undefined Undefined
R/W
:
—
—
—
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
PGDR is an 8-bit read/write register and stores output data of port G output pins (PG4 to PG0).
Bits 7 to 5 are reserved bits. When the contents are read, undefined values are read. Write
processing is invalid.
In power-on reset or hardware standby mode, PGDR is initialized to H'00 (bits 4 to 0). In manual
reset or software standby mode, PGDR retains the last state.
(3) Port G Register (PORTG)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
PG4
PG3
PG2
PG1
PG0
—*
—*
—*
—*
—*
R
R
R
R
R
Initial value : Undefined Undefined Undefined
R/W
:
—
—
—
Note: * Determined by the state of PG4 to PG0
PORTG is an 8-bit read only register and reflects the pin state. Write processing is invalid. Write
processing of output data of port G pins (PG4 to PG0) must be performed for PGDR.
Bits 7 to 5 are reserved bits. When the contents are read, undefined values are read. Write
processing is invalid.
If PORTG is read when PGDDR is set to 1, the value in PGDR is read. If PORTG is read when
PGDDR is cleared to 0, the pin state is read.
Rev. 5.00 Mar 28, 2005 page 445 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
In power-on reset or hardware standby mode, port G is determined by the pin state because
PGDDR and PGDR are initialized. In manual reset or software standby mode, the last state is
retained.
10A.13.3 Pin Functions
Port G is used also as external interrupt input pins (IRQ6 and IRQ7) and bus control signal output
pins (CS0 to CS3, CAS, and OE). The pin functions are different between modes 4 and 6, and
mode 7. Table 10A.23 shows the port G pin functions.
Table 10A.23 Port G Pin Functions
Pin
Selection Method and Pin Functions
PG4/CS0
The pin function is switched as shown below according to the operating mode and
bit PG4DDR.
Modes 4 to 6
Operating
Mode
PG4DDR
Pin function
PG3/CS1
0
1
PG4 input pin
CS0
output pin
0
1
PG4 input pin
PG4 output pin
The pin function is switched as shown below according to the operating mode and
bit PG3DDR.
Modes 4 to 6
Operating
Mode
PG3DDR
Pin function
PG2/CS2
Mode 7
0
Mode 7
1
PG3 input pin
CS1
output pin
0
1
PG3 input pin
PG3 output pin
The pin function is switched as shown below according to the operating mode and
bit PG2DDR.
Operating
Mode
PG2DDR
Pin function
Modes 4 to 6
0
PG2 input pin
Rev. 5.00 Mar 28, 2005 page 446 of 1422
REJ09B0234-0500
Mode 7
1
CS2
output pin
0
1
PG2 input pin
PG2 output pin
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Pin
Selection Method and Pin Functions
PG1/CS3/
OE/IRQ7
The pin function is switched as shown below according to the operating mode and
bits OES and PG1DDR in BCRL.
Operating
Mode
Modes 4 to 6
PG1DDR
0
OES
—
0
PG1
input pin
Pin function
Mode 7
1
0
1
1
—
—
CS3
OE
output pin
output pin
PG1
input pin
PG1
output pin
IRQ7
PG0/CAS/
IRQ6
input
The pin function is switched as shown below according to the operating mode and
bits RMTS2 to RMTS0 in BCRH.
Modes 4 to 6
Operating
Mode
B'000
RMTS2 to
RMTS0
PG0DDR
Pin function
Mode 7
—
B'001 to
B'011
0
1
—
0
1
PG0
input pin
PG0
output pin
CAS
PG0
input pin
PG0
output pin
output pin
IRQ6
input
Rev. 5.00 Mar 28, 2005 page 447 of 1422
REJ09B0234-0500
Section 10A I/O Ports (H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Rev. 5.00 Mar 28, 2005 page 448 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Section 10B I/O Ports
(H8S/2695)
10B.1 Overview
The H8S/2633 Group has 10 I/O ports (ports 1, 3, 7 and A to G), and two input-only port (ports 4
and 9).
Table 10B.1 summarizes the port functions. The pins of each port also have other functions.
Each I/O port includes a data direction register (DDR) that controls input/output, a data register
(DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only
ports do not have a DR or DDR register.
Ports A to E have a built-in pull-up MOS function, and in addition to DR and DDR, have a MOS
input pull-up control register (PCR) to control the on/off state of MOS input pull-up.
Ports 3, and A to C include an open-drain control register (ODR) that controls the on/off state of
the output buffer PMOS.
When ports 10 to 13, 70 to 73, and A to G are used as the output pins for expanded bus control
signals, they can drive one TTL load plus a 50pF capacitance load. Those ports in other cases, and
ports 14 to 17, 3, and 74 to 77, can drive one TTL load and a 30pF capacitance load. All I/O ports
can drive Darlington transistors when set to output.
See Appendix C, I/O Port Block Diagrams, for a block diagram of each port.
Rev. 5.00 Mar 28, 2005 page 449 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Table 10B.1 Port Functions
Port
Description
Port 1 • 8-bit I/O
port
• Schmitttriggered
input (P16,
P14)
Pins
P17/TIOCB2/TCLKD
P16/TIOCA2//IRQ1
P15/TIOCB1/TCLKC
P14/TIOCA1/IRQ0
Mode 4
P13/TIOCD0/TCLKB/
A23
P11/TIOCB0/A21
P10/TIOCA0/A20
P37/TxD4
P36/RxD4
• Open-drain P35/SCK1/SCK4/
IRQ5
output
P34
/RxD1
capability
• Schmitttriggered
input (P35,
P32)
Mode 6
8-bit I/O port also functioning as TPU I/O pins
(TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0,
TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1,
TIOCA2, TIOCB2), interrupt input pins (IRQ0,
IRQ1), and address outputs (A20 to A23)
P12/TIOCC0/TCLKA/
A22
Port 3 • 8-bit I/O
port
Mode 5
Mode 7
8-bit I/O port
also functioning as TPU I/O
pins (TCLKA,
TCLKB,
TCLKC,
TCLKD,
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0,
TIOCA1,
TIOCB1,
TIOCA2,
TIOCB2) and
interrupt input
pins (IRQ0,
IRQ1)
8-bit I/O port also functioning as SCI (channel 0, 1, and 4) I/O
pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1, TxD4, RxD4,
SCK4) and interrupt input pins (IRQ4, IRQ5)
P33 /TxD1
P32 /SCK0/IRQ4
P31 /RxD0
P30 /TxD0
Port 4 • 8-bit input
port
P47 /AN7
P46 /AN6
8-bit input port also functioning as A/D converter analog inputs
(AN7 to AN0)
P45 /AN5
P44 /AN4
P43 /AN3
P42 /AN2
P41 /AN1
P40/AN0
Rev. 5.00 Mar 28, 2005 page 450 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port
Description
Port 7 8-bit I/O port
Pins
P77/TxD3
P76/RxD3
P75/SCK3
Mode 4
Mode 5
Mode 6
8-bit I/O port also functioning as bus control
output pins (CS4 to CS7), SCI I/O pins (SCK3,
RxD3, TxD3), and the manual reset input pin
(MRES)
P74/MRES
P73/CS7
P72/CS6
P71/CS5
Mode 7
8-bit I/O port
also functioning as SCI I/O
pins (SCK3,
RxD3, TxD3)
and the
manual reset
input pin
(MRES)
P70/CS4
Port 9 • 8-bit input
port
P97/AN15
P96/AN14
8-bit input port also functioning as A/D converter analog inputs
(AN15 to AN8)
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
Port A • 4-bit I/O
port
• Built-in
MOS input
pull-up
PA3/A19/SCK2
PA2/A18/RxD2
4-bit I/O port also functioning as SCI (channel
2) I/O pins (TxD2, RxD2, SCK2) and address
outputs (A19 to A16)
4-bit I/O port
also functioning as SCI
(channel 2)
I/O pins (TxD2,
RxD2, SCK2)
8-bit I/O port also functioning as TPU I/O pins
(TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3,
TIOCC3, TIOCB3, TIIOCA3) and address
outputs (A15 to A8)
8-bit I/O port
also
functioning as
TPU I/O pins
(TIOCB5,
TIOCA5,
TIOCB4,
TIOCA4,
TIOCD3,
TIOCC3,
TIOCB3,
TIIOCA3)
PA1/A17/TxD2
PA0/A16
• Open-drain
output
capability
Port B 8-bit I/O port
PB7/A15/TIOCB5
Built-in MOS PB6/A14/TIOCA5
input pull-up PB5/A13/TIOCB4
Open-drain
PB4/A12/TIOCA4
output
PB3/A11/TIOCD3
capability
PB2/A10/TIOCC3
PB1/A9/TIOCB3
PB0/A8/TIOCA3
Rev. 5.00 Mar 28, 2005 page 451 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port
Description
Port C 8-bit I/O port
Pins
Mode 4
Mode 5
Mode 6
Mode 7
8-bit I/O port also functioning as address
outputs (A7 to A0)
8-bit I/O port
also functioning
Data bus input/output
I/O port
PE7/D7
In 8-bit-bus mode: I/O port
I/O port
PE6/D6
In 16-bit-bus mode: data bus input/output
PC7/A7
Built-in MOS PC6/A6
input pull-up PC5/A5
Open-drain
PC4/A4
output
PC3/A3
capability
PC2/A2
PC1/A1
PC0 /A0
Port D • 8-bit I/O
port
• Built-in
MOS input
pull-up
PD7 /D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0 /D8
Port E • 8-bit I/O
port
• Built-in
MOS input
pull-up
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0 /D0
Rev. 5.00 Mar 28, 2005 page 452 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port
Description
Port F • 8-bit I/O
port
Pins
PF7/φ
Mode 4
Mode 5
Mode 6
When DDR = 0: input port
When DDR = 1 (after reset): φ output
Mode 7
When
DDR = 0 (after
reset): input
port
When
DDR = 1: φ
output
PF6/AS
RD HWR
PF5/RD
ADTRG
,
, LWR outputs
, IRQ3 input
I/O port
, IRQ3
ADTRG
input
PF4/HWR
PF3/LWR/ADTRG/
IRQ3
PF2/WAIT/BREQO
When WAITE = 0 and BREQOE = 0 (after
reset): I/O port
I/O port
When WAITE = 1 and BREQOE = 0: WAIT
input
When WAITE = 0 and BREQOE = 1: BREQO
input
PF1/BACK
When BRLE = 0 (after reset): I/O port
IRQ2
PF0/BREQ/IRQ2
When BRLE = 1: BREQ input, BACK output
I/O port
IRQ2
Port G • 5-bit I/O
port
input
input
PG4/CS0
When DDR = 0*1: input port
When DDR = 1*2: CS0 output
I/O port
PG3/CS1
When DDR = 0 (after reset): input port
PG2/CS2
When DDR = 1: CS1, CS2, CS3 outputs
I/O port, IRQ7
input
PG1/CS3/IRQ7
IRQ7
PG0/IRQ6
After reset: I/O port
IRQ6
input
input
I/O port, IRQ6
input
Notes: 1. After a reset in mode 6
2. After a reset in modes 4 or 5
Rev. 5.00 Mar 28, 2005 page 453 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.2 Port 1
10B.2.1 Overview
Port 1 is an 8-bit I/O port. Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC,
TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2),
external interrupt pins (IRQ0 and IRQ1), and address bus output pins (A23 to A20). Port 1 pin
functions change according to the operating mode.
Figure 10B.1 shows the port 1 pin configuration.
Port 1 pins
Pin functions in modes 4 to 6
P17 (I/O) / TIOCB2 (I/O) / TCLKD (input)
P16 (I/O) / TIOCA2 (I/O) / IRQ1 (input)
P15 (I/O) / TIOCB1 (I/O) / TCLKC (input)
Port 1
P14 (I/O) / TIOCA1 (I/O) / IRQ0 (input)
P13 (I/O) / TIOCD0 (I/O) / TCLKB (input) / A23 (output)
P12 (I/O) / TIOCC0 (I/O) / TCLKA (input) / A22 (output)
P11 (I/O) / TIOCB0 (I/O) / A21 (output)
P10 (I/O) / TIOCA0 (I/O) / A20 (output)
Pin functions in mode 7
P17 (I/O) / TIOCB2 (I/O) / TCLKD (input)
P16 (I/O) / TIOCA2 (I/O) / IRQ1 (input)
P15 (I/O) / TIOCB1 (I/O) / TCLKC (input)
P14 (I/O) / TIOCA1 (I/O) / IRQ0 (input)
P13 (I/O) / TIOCD0 (I/O) / TCLKB (input)
P12 (I/O) / TIOCC0 (I/O) / TCLKA (input)
P11 (I/O) / TIOCB0 (I/O)
P10 (I/O) / TIOCA0 (I/O)
Figure 10B.1 Port 1 Pin Functions
Rev. 5.00 Mar 28, 2005 page 454 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.2.2 Register Configuration
Table 10B.2 shows the port 1 register configuration.
Table 10B.2 Port 1 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 1 data direction register
P1DDR
W
H'00
H'FE30
Port 1 data register
P1DR
R/W
H'00
H'FF00
Port 1 register
PORT1
R
Undefined
H'FFB0
Note: * Lower 16 bits of the address.
Port 1 Data Direction Register (P1DDR)
Bit
:
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode. Because TPU is initialized at a manual
reset, pin states are determined by P1DDR and P1DR.
Port 1 Data Register (P1DR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10).
P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Rev. 5.00 Mar 28, 2005 page 455 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port 1 Register (PORT1)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P17
—*
P16
—*
P15
—*
P14
—*
P13
—*
P12
—*
P11
—*
P10
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins P17 to P10.
PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 1 pins (P17 to P10) must always be performed on P1DR.
If a PORT1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a
PORT1 read is performed while P1DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin
states, as P1DDR and P1DR are initialized. PORT1 retains its prior state by a manual reset or in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 456 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.2.3 Pin Functions
Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0,
TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), external interrupt input
pins (IRQ0 and IRQ1), and address bus output pins (A23 to A20). Port 1 pin functions are shown
in table 10B.3.
Table 10B.3 Port 1 Pin Functions
Pin
Selection Method and Pin Functions
P17/TIOCB2/
TCLKD
The pin function is switched as shown below according to the combination of
the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0
in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in
TCR0 and TCR5, and bit P17DDR.
TPU Channel
2 Setting
Table Below (1)
Table Below (2)
P17DDR
—
0
1
Pin function
TIOCB2 output
P17 input
P17 output
TIOCB2 input*1
TCLKD input*2
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 =
1.
2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2
to TPSC0 = B'111.
TCLKD input when channels 2 and 4 are set to phase counting
mode.
TPU Channel
2 Setting
MD3 to MD0
IOB3 to IOB0
CCLR1,
CCLR0
Output
function
(2)
(1)
(2)
B'0000, B'01xx
B'0010
B'0000 B'0001 to
—
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
(2)
B'xx00
—
—
(1)
(2)
B'0011
Other than B'xx00
Other
B'10
than B'10
PWM
—
mode 2
output
x: Don’t care
Rev. 5.00 Mar 28, 2005 page 457 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P16/TIOCA2/
The pin function is switched as shown below according to the combination of
the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0
in TIOR2, and bits CCLR1 and CCLR0 in TCR2), and bit P16DDR.
IRQ1
TPU Channel
2 Setting
Table Below (1)
P16DDR
Pin function
Table Below (2)
—
0
1
TIOCA2 output
P16 input
P16 output
TIOCA2 input*1
IRQ1
TPU Channel
2 Setting
MD3 to MD0
IOA3 to IOA0
CCLR1,
CCLR0
Output
function
(2)
(1)
(2)
B'0000, B'01xx
B'001x
B'0000 B'0001 to B'xx00
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
input
(1)
(1)
(2)
B'0010
B'0011
Other than B'xx00
—
Other
B'01
than B'01
PWM
PWM
—
mode 1 mode 2
output*2 output
x: Don’t care
Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 =
1.
2. TIOCB2 output is disabled.
Rev. 5.00 Mar 28, 2005 page 458 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P15/TIOCB1/
TCLKC
The pin function is switched as shown below according to the combination of
the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0
in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in
TCR0, TCR2, TCR4, and TCR5, and bit P15DDR.
TPU Channel
1 Setting
Table Below (1)
P15DDR
Pin function
Table Below (2)
—
0
TIOCB1 output
P15 input
1
P15 output
TIOCB1 input*1
TCLKC input*2
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3
to IOB0 = B'10xx.
2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2
to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is
TPSC2 to TPSC0 = B'101.
TCLKC input when channels 2 and 4 are set to phase counting
mode.
TPU Channel
1 Setting
MD3 to MD0
IOB3 to IOB0
CCLR1,
CCLR0
Output
function
(2)
(1)
(2)
B'0000, B'01xx
B'0010
B'0000 B'0001 to
—
B'0011
B'0100
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
(2)
B'xx00
—
—
(1)
(2)
B'0011
Other than B'xx00
Other
B'10
than
B'10
PWM
—
mode 2
output
x: Don’t care
Rev. 5.00 Mar 28, 2005 page 459 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P14/TIOCA1/
The pin function is switched as shown below according to the combination of
the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0
in TIOR1, and bits CCLR1 and CCLR0 in TCR1), and bit P14DDR.
IRQ0
TPU Channel
1 Setting
Table Below (1)
P14DDR
Pin function
Table Below (2)
—
0
1
TIOCA1 output
P14 input
P14 output
TIOCA1 input*1
IRQ0
TPU Channel
1 Setting
MD3 to MD0
IOA3 to IOA0
CCLR1,
CCLR0
Output
function
(2)
(1)
(2)
B'0000, B'01xx
B'001x
B'0000 B'0001 to B'xx00
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
input
(1)
B'0010
Other
than
B'xx00
(1)
(2)
B'0011
Other than B'xx00
—
Other
B'01
than B'01
PWM
PWM
—
mode 1 mode 2
output*2 output
x: Don’t care
Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to
IOA0 = B'10xx.
2. TIOCB1 output is disabled.
Rev. 5.00 Mar 28, 2005 page 460 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P13/TIOCD0/
TCLKB/A23
The pin function is switched as shown below according to the combination of
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0),
bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, and bit
P13DDR.
Modes 4 to 6
Operating
mode
AE3 to AE0
TPU Channel
0 Setting
P13DDR
Pin function
B'0000 to B'1110
Table
Below (1)
B'1111
Table Below (2)
—
0
TIOCD0
output
P13
input
—
1
P13
output
TIOCD0 input*1
—
A23
output
TCLKB input*2
Operating
mode
Mode 7
AE3 to AE0
TPU Channel
0 Setting
P13DDR
Pin function
—
Table Below (1)
Table Below (2)
—
0
1
TIOCD0 output
P13 input
P13 output
TIOCD0 input*1
TCLKB input*2
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 =
B'10xx.
2. TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to
TPSC0 = B'101.
TCLKB input when channels 1 and 5 are set to phase counting
mode.
Rev. 5.00 Mar 28, 2005 page 461 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P13/TIOCD0/
TCLKB/A23 (cont)
TPU Channel
0 Setting
MD3 to MD0
IOD3 to IOD0
CCLR2 to
CCLR0
Output
function
(2)
(1)
(2)
B'0000
B'0010
B'0000 B'0001 to
—
B'0011
B'0100
B'1xxx B'0101 to
B'0111
—
—
—
—
Rev. 5.00 Mar 28, 2005 page 462 of 1422
REJ09B0234-0500
Output
compare
output
—
(2)
B'xx00
—
—
(1)
(2)
B'0011
Other than B'xx00
Other
than
B'110
B'110
—
PWM
mode 2
output
x: Don’t care
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P12/TIOCC0/
TCLKA/A22
The pin function is switched as shown below according to the combination of
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0),
bits TPSC2 to TPSC0 in TCR0 to TCR5, bits AE3 to AE0 in PFCR, and bit
P12DDR.
Modes 4 to 6
Operating
mode
AE3 to AE0
TPU Channel
0 Setting
P12DDR
Pin function
B'0000 to B'1110
Table
Below (1)
B'1111
Table Below (2)
—
0
TIOCC0
output
P12
input
—
1
P12
output
TIOCC0 input*1
—
A22
output
TCLKA input*2
Operating
mode
Mode 7
AE3 to AE0
TPU Channel
0 Setting
P12DDR
Pin function
—
Table Below (1)
Table Below (2)
—
0
1
TIOCC0 output
P12 input
P12 output
TIOCC0 input*1
TCLKA input*2
Rev. 5.00 Mar 28, 2005 page 463 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P12/TIOCC0/
TCLKA/A22 (cont)
TPU Channel
0 Setting
MD3 to MD0
IOC3 to IOC0
CCLR2 to
CCLR0
Output
function
(2)
(1)
(2)
B'0000
B'001x
B'0000 B'0001 to B'xx00
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
(1)
(1)
(2)
B'0010
B'0011
Other than B'xx00
—
PWM
mode 1
3
output*
Other
than
B'101
B'101
—
PWM
mode 2
output
x: Don’t care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 =
B'10xx.
2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to
TPSC0 = B'100.
TCLKA input when channels 1 and 5 are set to phase counting
mode.
3. TIOCD0 output is disabled.
When BFA = 1 or BFB = 1 in TMDR0, output is disabled and
setting (2) applies.
Rev. 5.00 Mar 28, 2005 page 464 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P11/TIOCB0/A21
The pin function is switched as shown below according to the combination of
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, and bits IOB3 to IOB0 in TIOR0H), bits AE3 to AE0 in PFCR, and bit
P11DDR.
Modes 4 to 6
Operating
mode
AE3 to AE0
TPU Channel
0 Setting
P11DDR
Pin function
B'0000 to B'1101
Table
Below (1)
B'1110 to
B'1111
Table Below (2)
—
—
0
1
—
TIOCB0
output
P11
input
P11
output
A21
output
TIOCB0 input*
Operating
mode
Mode 7
AE3 to AE0
TPU Channel
0 Setting
P11DDR
Pin function
Note: *
—
Table Below (1)
Table Below (2)
—
0
TIOCB0 output
P11 input
1
P11 output
TIOCB0 input*
TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 =
B'10xx.
Rev. 5.00 Mar 28, 2005 page 465 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P11/TIOCB0/A21
(cont)
TPU Channel
0 Setting
MD3 to MD0
IOB3 to IOB0
CCLR2 to
CCLR0
Output
function
(2)
(1)
(2)
B'0000
B'0010
B'0000 B'0001 to
—
B'0011
B'0100
B'1xxx B'0101 to
B'0111
—
—
—
—
Rev. 5.00 Mar 28, 2005 page 466 of 1422
REJ09B0234-0500
Output
compare
output
—
(2)
B'xx00
—
—
(1)
(2)
B'0011
Other than B'xx00
Other
than
B'010
B'010
—
PWM
mode 2
output
x: Don’t care
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P10/TIOCA0/A20
The pin function is switched as shown below according to the combination of
the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in
TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0),
bits AE3 to AE0 in PFCR, and bit P10DDR.
Modes 4 to 6
Operating
mode
AE3 to AE0
TPU Channel
0 Setting
P10DDR
Pin function
B'0000 to B'1110
Table
Below (1)
—
0
P10
input
P10DDR
Pin function
—
1
P10
output
TIOCA0 input*1
—
A20 output
Mode 7
AE3 to AE0
TPU Channel
0 Setting
Table Below (2)
TIOCA0
output
Operating
mode
B'1101 to
B'1111
—
Table Below (1)
Table Below (2)
—
0
1
TIOCA0
output
P10
input
P10
output
TIOCA0 input*1
Rev. 5.00 Mar 28, 2005 page 467 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P10/TIOCA0/A20
(cont)
TPU Channel
0 Setting
MD3 to MD0
IOA3 to IOA0
CCLR2 to
CCLR0
Output
function
(2)
(1)
(2)
B'0000
B'001x
B'0000 B'0001 to B'xx00
B'0100 B'0011
B'1xxx B'0101 to
B'0111
—
—
—
—
Output
compare
output
—
(1)
(1)
(2)
B'0010
B'0011
Other than B'xx00
—
PWM
mode 1
2
output*
Other
than
B'001
B'001
—
PWM
mode 2
output
x: Don’t care
Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 =
B'10xx.
2. TIOCB0 output is disabled.
Rev. 5.00 Mar 28, 2005 page 468 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.3 Port 3
10B.3.1 Overview
Port 3 is an 8-bit I/O port. Port 3 is a multi-purpose port for SCI I/O pins (TxD0, RxD0, SCK0,
TxD1, RxD1, SCK1, TxD4, RxD4, and SCK4) and external interrupt input pins (IRQ4 and IRQ5).
All of the port 3 pin functions have the same operating mode. The configuration for each of the
port 3 pins is shown in figure 10B.2.
Port 3 pins
P37 (I/O) / TxD4 (output)
P36 (I/O) / RxD4 (input)
P35 (I/O) / SCK1 (I/O) /
SCK4 (I/O) / IRQ5 (input)
Port 3
P34 (I/O) / RxD1 (input)
P33 (I/O) / TxD1 (input)
P32 (I/O) / SCK0 (I/O) / IRQ4 (input)
P31 (I/O) / RxD0 (input)
P30 (I/O) / TxD0 (output)
Figure 10B.2 Port 3 Pin Functions
10B.3.2 Register Configuration
Table 10B.4 shows the configuration of port 3 registers.
Table 10B.4 Port 3 Register Configuration
Name
Abbreviation
R/W
Initial Value
Address*
Port 3 data direction register
P3DDR
W
H'00
H'FE32
Port 3 data register
P3DR
R/W
H'00
H'FF02
Port 3 register
PORT3
R
Undefined
H'FFB2
Port 3 open drain control register
P3ODR
R/W
H'00
H'FE46
Note: * Lower 16 bits of the address.
Rev. 5.00 Mar 28, 2005 page 469 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port 3 Data Direction Register (P3DDR)
Bit
:
7
6
5
4
3
2
1
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit.
Read is disenabled. If a read is carried out, undefined values are read out.
By setting P3DDR to 1, the corresponding port 3 pins become output, and be clearing to 0 they
become input.
P3DDR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode. SCI is initialized, so the pin
state is determined by the specification of P3DDR and P3DR.
Port 3 Data Register (P3DR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P37DR
P36DR
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3DR is an 8-bit readable/writable register, which stores the output data of port 3 pins (P35 to
P30).
P3DR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous state
is maintained by a manual reset and in software standby mode.
Rev. 5.00 Mar 28, 2005 page 470 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port 3 Register (PORT3)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P37
P36
P35
P34
P33
P32
P31
P30
—*
—*
—*
—*
—*
—*
—*
—*
R
R
R
R
R
R
R
R
Note: * Determined by the state of pins P37 to P30.
PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled.
Always carry out writing off output data of port 3 pins (P37 to P30) to P3DR without fail.
When P3DDR is set to 1, if PORT3 is read, the values of P3DR are read. When P3DDR is cleared
to 0, if PORT3 is read, the states of pins are read out.
P3DDR and P3DR are initialized by a power-on reset and in hardware standby mode, so PORT3 is
determined by the state of the pins. The previous state is maintained by a manual reset and in
software standby mode.
Port 3 Open Drain Control Register (P3ODR)
Bit
:
7
6
5
4
3
2
1
0
P37ODR P36ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3ODR is an 8-bit readable/writable register, which controls the on/off of port 3 pins (P37 to
P30).
By setting P3ODR to 1, the port 3 pins become an open drain out, and when cleared to 0 they
become CMOS output.
P3ODR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode.
Rev. 5.00 Mar 28, 2005 page 471 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.3.3 Pin Functions
The port 3 pins double as SCI I/O input pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1, TxD4,
RxD4, SCK4), external interrupt input pins (IRQ4, IRQ5). The functions of port 3 pins are shown
in table 10B.5.
Table 10B.5 Port 3 Pin Functions
Pin
Selection Method and Pin Functions
P37/TxD4
Switches as follows according to combinations of SCR TE bit of SCI4 and the
P37DDR bit.
TE
0
P37DDR
Pin function
1
0
1
—
P37 input pin
P37 output pin*
TxD4 output pin
Note: * When P37ODR = 1, it becomes NMOS open drain output.
P36/RxD4
Switches as follows according to combinations of SCR RE bit of SCI4 and the
P36DDR bit.
RE
0
P36DDR
Pin function
1
0
1
—
P36 input pin
P36 output pin*
RxD4 input pin
Note: * When P36ODR = 1, it becomes NMOS open drain output.
P35/SCK1/
SCK4/IRQ5
Switches as follows according to combinations of the SMR C/A bit of SCI1 or SCI4,
the SCR CKE0 and CKE1 bits, and the P35DDR bit.
SCK1 and SCK4 should not be set to output simultaneously.
CKE1 (SCI1)
CKE1 (SCI4)
C/A (SCI1)
C/A (SCI4)
0
0
CKE0 (SCI1)
CKE0 (SCI4)
P35DDR
Pin function
0*1
1*1
1*1
0*1
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
0
0
0, 1, 1*3
1, 0, 1*3
0
0
0
1
—
*3
SCK1/SCK4
P35 input P35
output pin output pin
pin
—
*3
SCK1/SCK4
output pin
*3
0*2
SCK1/SCK4
input pin
IRQ5 input
Notes: 1. These settings are prohibited.
2. If SCK1 and SCK4 are used as input (clock input) pins on the H8S/2695, P35DDR must be
cleared to 0.
3. The output format is CMOS output. It becomes NMOS open drain output if P35ODR is set to 1.
Rev. 5.00 Mar 28, 2005 page 472 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P34/RxD1
Switches as follows according to combinations of ICCR0 ICE bit of IIC0, SCR RE bit
of SCI1, and the P34DDR bit.
RE
0
P34DDR
Pin function
1
0
1
—
P34 input pin
P34 output pin*
RxD1 input pin
Note: * Output type is NMOS push-pull. When P34ODR = 1, it becomes NMOS
open drain tray.
P33/TxD1
Switches as follows according to combinations of ICCR1 ICE bit of IIC1, SCR TE bit
of SCI1 and the P33DDR bit.
TE
0
P33DDR
Pin function
1
0
1
—
P33 input pin
P33 output pin*
TxD1 output pin*
Note: * When P33ODR = 1, it becomes NMOS open drain output.
P32/SCK0/
IRQ4
Switches as follows according to combinations of SMR C/A bit of SCI0, SCR CKE0
and CKE1 bits, and the P32DDR bit.
If using as an SDA1 input pin, always set SMR C/A bit of SCI0 and SCR CKE0 and
CKE1 bits to 0 without fail.
CKE1
0
C/A
0
CKE0
P32DDR
Pin function
1
0
0
1
P32
input pin
P32
output pin
1
—
1
—
—
—
—
—
SCK0 output SCK0 output
pin*
pin*
IRQ4
SCK0
input pin
input
Note: * When P32ODR = 1, it becomes NMOS open drain output.
Rev. 5.00 Mar 28, 2005 page 473 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P31/RxD0
Switches as follows according to combinations of SCR RE bit of SCI0 and the
P31DDR bit.
RE
P31DDR
Pin function
0
1
0
1
—
P31 input pin
P31 output pin*
RxD0 input pin
Note: * When P31ODR = 1, it becomes NMOS open drain output.
P30/TxD0
Switches as follows according to combinations of SCR TE bit of SCI0 and the
P30DDR bit.
TE
P30DDR
Pin function
0
1
0
1
—
P30 input pin
P30 output pin*
TxD0 output pin*
Note: * When P30ODR = 1, it becomes NMOS open drain output.
Rev. 5.00 Mar 28, 2005 page 474 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.4 Port 4
10B.4.1 Overview
Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins
(AN0 to AN7). Port 4 pin functions are the same in all operating modes. Figure 10B.3 shows the
port 4 pin configuration.
Port 4 pins
P47 (input) / AN7 (input)
P46 (input) / AN6 (input)
P45 (input) / AN5 (input)
Port 4
P44 (input) / AN4 (input)
P43 (input) / AN3 (input)
P42 (input) / AN2 (input)
P41 (input) / AN1 (input)
P40 (input) / AN0 (input)
Figure 10B.3 Port 4 Pin Functions
Rev. 5.00 Mar 28, 2005 page 475 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.4.2 Register Configuration
Table 10B.6 shows the port 4 register configuration. Port 4 is an input-only port, and does not
have a data direction register or data register.
Table 10B.6 Port 4 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 4 register
PORT4
R
Undefined
H'FFB3
Note: * Lower 16 bits of the address.
Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed.
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P47
—*
P46
—*
P45
—*
P44
—*
P43
—*
P42
—*
P41
—*
P40
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins P47 to P40.
10B.4.3 Pin Functions
Port 4 pins function as A/D converter analog input pins (AN0 to AN7).
Rev. 5.00 Mar 28, 2005 page 476 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.5 Port 7
10B.5.1 Overview
Port 7 is an 8-bit I/O port. Port 7 is a multipurpose port for the bus control output pins (CS4 to
CS7), SCI I/O pins (SCK3, RxD3, and TxD3), and manual reset input pin (MRES). The pin
functions for P77 to P74 are the same in all operating modes. P73 to P70 pin functions are
switched according to operating mode.
Figure 10B.4 shows the configuration for port 7 pins.
Port 7
Port 7 pins
Pin functions in modes 4 to 6
P77 / TxD3
P77 (I/O) / TxD3 (output)
P76 / RxD3
P76 (I/O) / RxD3 (input)
P75 / SCK3
P75 (I/O) / SCK3 (I/O)
P74 / MRES
P74 (I/O) / MRES (input)
P73 / CS7
P73 (I/O) / CS7 (output)
P72 / CS6
P72 (I/O) / CS6 (output)
P71 / CS5
P71 (I/O) / CS5 (output)
P70 / CS4
P70 (I/O) / CS4 (output)
Pin functions in mode 7
P77 (I/O) / TxD3 (output)
P76 (I/O) / RxD3 (input)
P75 (I/O) / SCK3 (I/O)
P74 (I/O) / MRES (input)
P73 (I/O)
P72 (I/O)
P71 (I/O)
P70 (I/O)
Figure 10B.4 Port 7 Pin Functions
Rev. 5.00 Mar 28, 2005 page 477 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.5.2 Register Configuration
Table 10B.7 shows the port 7 register configuration.
Table 10B.7 Port 7 Register Configuration
Name
Abbreviation
R/W
Initial Value
Address*
Port 7 data direction register
P7DDR
W
H'00
H'FE36
Port 7 data register
P7DR
R/W
H'00
H'FF06
Port 7 register
PORT7
R
Undefined
H'FFB6
Note: * Lower 16 bits of the address.
Port 7 Data Direction Register (P7DDR)
Bit
:
7
6
5
4
3
2
1
0
P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
P7DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 7 pin by bit.
Read is disenabled. If a read is carried out, undefined values are read out.
By setting P7DDR to 1, the corresponding port 7 pins become output, and by clearing to 0 they
become input.
P7DDR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode. SCI is initialized by a manual
reset, so the pin state is determined by the specification of P7DDR and P7DR.
Rev. 5.00 Mar 28, 2005 page 478 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port 7 Data Register (P7DR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P77DR
P76DR
P75DR
P74DR
P73DR
P72DR
P71DR
P70DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P7DR is an 8-bit readable/writable register, which stores the output data of port 7 pins (P77 to
P70).
P7DR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous state
is maintained by a manual reset and in software standby mode.
Port 7 Register (PORT7)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
—*
—*
—*
—*
—*
—*
—*
—*
R
R
R
R
R
R
R
R
Note: * Determined by the state of pins P77 to P70.
PORT7 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled.
Always carry out writing off output data of port 7 pins (P77 to P70) to P7DR without fail.
When P7DDR is set to 1, if PORT7 is read, the values of P7DR are read. When P7DDR is cleared
to 0, if PORT7 is read, the states of pins are read out.
P7DDR and P7DR are initialized by a power-on reset and in hardware standby mode, so PORT7 is
determined by the state of the pins. The previous state is maintained by a manual reset and in
software standby mode.
10B.5.3 Pin Functions
The pins of port 7 are multipurpose pins which function as bus control output pins (CS4 to CS7),
SCI I/O pins (SCK3, RxD3, and TxD3), and manual reset input pin (MRES). Table 10B.8 shows
the functions of port 7 pins.
Rev. 5.00 Mar 28, 2005 page 479 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Table 10B.8 Port 7 Pin Functions
Pin
Selection Method and Pin Functions
P77/TxD3
Switches as follows according to combinations of SCR TE bit of SCI3, and the
P77DDR bit.
TE
0
P77DDR
Pin function
P76/RxD3
0
1
—
P77 input pin
P77 output pin
TxD3 output pin
Switches as follows according to combinations of SCR RE bit of SCI3 and the
P76DDR bit.
RE
0
P76DDR
Pin function
P75/SCK3
1
1
0
1
—
P76 input pin
P76 output pin
RxD3 I/O pin
Switches as follows according to combinations of SMR C/A bit of SCI3, SCR CKE0
and CKE1 bits, and the P75DDR bit.
CKE1
0
C/A
0
CKE0
P75DDR
Pin function
P74/MRES
1
0
1
—
1
—
—
0
1
—
—
—
P75
input pin
P75
output pin
SCK3
output pin
SCK3
output pin
SCK3
input pin
Switches as follows according to combinations of SYSCR MRESE bit and the
P74DDR bit.
MRESE
P74DDR
Pin function
0
1
0
1
P74 input pin
P74 output pin
Rev. 5.00 Mar 28, 2005 page 480 of 1422
REJ09B0234-0500
—
MRES
input pin
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
P73/CS7
Switches as follows according to combinations of operating mode and the P73DDR
bit.
Operating
Mode
P73DDR
Pin function
P72/CS6
Modes 4 to 6
0
output
pin
CS7
0
1
P73 input
pin
P73 output
pin
Switches as follows according to combinations of operating mode and the P72DDR
bit.
P72DDR
Pin function
Modes 4 to 6
Mode 7
0
1
P72 input
pin
output
pin
CS6
0
1
P72 input
pin
P72 output
pin
Switches as follows according to operating mode and P71DDR.
Operating
Mode
P71DDR
Pin function
P70/CS4
1
P73 input
pin
Operating
Mode
P71/CS5
Mode 7
Modes 4 to 6
0
Mode 7
1
P71 input Pin
CS5
output
0
1
P71 input pin
P71 output pin
Switches as follows according to operating mode and P70DDR.
Operating
Mode
P70DDR
Pin function
Modes 4 to 6
0
P70 input pin
Mode 7
1
CS4
output
0
1
P70 input pin
P70 output pin
Rev. 5.00 Mar 28, 2005 page 481 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.6 Port 9
10B.6.1 Overview
Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins
(AN8 to AN15). Port 9 pin functions are the same in all operating modes. Figure 10B.5 shows the
port 9 pin configuration.
Port 9 pins
P97 (input) / AN15 (input)
P96 (input) / AN14 (input)
P95 (input) / AN13 (input)
Port 9
P94 (input) / AN12 (input)
P93 (input) / AN11 (input)
P92 (input) / AN10 (input)
P91 (input) / AN9 (input)
P90 (input) / AN8 (input)
Figure 10B.5 Port 9 Pin Functions
Rev. 5.00 Mar 28, 2005 page 482 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.6.2 Register Configuration
Table 10B.9 shows the port 9 register configuration. Port 9 is an input-only port, and does not
have a data direction register or data register.
Table 10B.9 Port 9 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 9 register
PORT9
R
Undefined
H'FFB8
Note: * Lower 16 bits of the address.
Port 9 Register (PORT9): The pin states are always read when a port 9 read is performed.
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P97
—*
P96
—*
P95
—*
P94
—*
P93
—*
P92
—*
P91
—*
P90
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins P97 to P90.
10B.6.3 Pin Functions
Port 9 pins function as A/D converter analog input pins (AN8 to AN15).
Rev. 5.00 Mar 28, 2005 page 483 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.7 Port A
10B.7.1 Overview
Port A is a 4-bit I/O port. Port A pins also function as SCI2 I/O pins (SCK2, RxD2, and TxD2)
and address bus outputs. The pin functions change according to the operating mode.
Port A has a built-in MOS input pull-up function that can be controlled by software.
Figure 10B.6 shows the port A pin configuration.
Port A
Port A pins
Pin functions in modes 4 to 6
PA3/A19/SCK2
PA3 (I/O) / A19 (output) / SCK2 (I/O)
PA2/A18/RxD2
PA2 (I/O) / A18 (output) / RxD2 (input)
PA1/A17/TxD2
PA1 (I/O) / A17 (output) / TxD2 (output)
PA0/A16
PA0 (I/O) / A16 (output)
Pin functions in mode 7
PA3 (I/O) / SCK2 (output)
PA2 (I/O) / RxD2 (input)
PA1 (I/O) / TxD2 (output)
PA0 (I/O)
Figure 10B.6 Port A Pin Functions
Rev. 5.00 Mar 28, 2005 page 484 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.7.2 Register Configuration
Table 10B.10 shows the port A register configuration.
Table 10B.10 Port A Registers
Name
Abbreviation
R/W
Initial Value*2
Address*1
Port A data direction register
PADDR
W
H'0
H'FE39
Port A data register
PADR
R/W
H'0
H'FF09
Port A register
PORTA
R
Undefined
H'FFB9
Port A MOS pull-up control register
PAPCR
R/W
H'0
H'FE40
Port A open-drain control register
PAODR
R/W
H'0
H'FE47
Notes: 1. Lower 16 bits of the address.
2. Value of bits 3 to 0.
Port A Data Direction Register (PADDR)
Bit
:
7
6
5
4
—
—
—
—
3
2
1
0
PA3DDR PA2DDR PA1DDR PA0DDR
Initial value : Undefined Undefined Undefined Undefined
0
0
0
0
R/W
W
W
W
W
:
—
—
—
—
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
Bits 7 and 6 are reserved; they return an undetermined value if read.
PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode. The OPE bit in SBYCR is
used to select whether the address output pins retain their output state or become high-impedance
when a transition is made to software standby mode. See section 24.2.1, Standby Control Register
(SBYCR), for details.
• Modes 4 to 6
The corresponding port A pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of bits PA4DDR to PA0DDR. When pins are
not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 485 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
• Mode 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
Port A Data Register (PADR)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
PA3DR
PA2DR
PA1DR
PA0DR
0
0
0
0
R/W
R/W
R/W
R/W
Initial value : Undefined Undefined Undefined Undefined
R/W
:
—
—
—
—
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to
PA0).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 3 to 0) by a powr-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode.
Port A Register (PORTA)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
PA3
—*
PA2
—*
PA1
—*
PA0
—*
R
R
R
R
Initial value : Undefined Undefined Undefined Undefined
R/W
:
—
—
—
—
Note: * Determined by state of pins PA3 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA3 to PA0) must always be performed on PADR.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
If a PORTA read is performed while PADDR bits are set to 1, the PADR values are read. If a
PORTA read is performed while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin
states, as PADDR and PADR are initialized. PORTA retains its prior state by a manual reset or in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 486 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port A MOS Pull-Up Control Register (PAPCR)
Bit
:
7
6
5
4
—
—
—
—
3
:
—
—
—
1
0
PA3PCR PA2PCR PA1PCR PA0PCR
Initial value : Undefined Undefined Undefined Undefined
R/W
2
—
0
0
0
0
R/W
R/W
R/W
R/W
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on an individual bit basis.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. In
modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI’s
SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS
input pull-up for that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the SCI’s SCMR, SMR,
and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up
for that pin.
PAPCR is initialized by a manual reset or to H'0 (bits 3 to 0) by a power-on reset, and in hardware
standby mode. It retains its prior state in software standby mode.
Port A Open Drain Control Register (PAODR)
Bit
:
7
6
5
4
—
—
—
—
3
:
—
—
—
—
1
0
PA3ODR PA2ODR PA1ODR PA0ODR
Initial value : Undefined Undefined Undefined Undefined
R/W
2
0
0
0
0
R/W
R/W
R/W
R/W
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each
port A pin (PA3 to PA0).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR,
setting a PAODR bit makes the corresponding port A pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode.
Rev. 5.00 Mar 28, 2005 page 487 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.7.3 Pin Functions
Modes 4 to 6: In modes 4 to 6, port A pins function as address outputs according to the setting of
AE3 to AE0 in PFCR; when they do not function as address outputs, the pins function as SCI I/O
pins and I/O ports.
Port A pin functions in modes 4 to 6 are shown in figure 10B.7.
PA3 (I/O) / A19 (output) / SCK2 (I/O)
PA2 (I/O) / A18 (output) / RxD2 (input)
Port A
PA1 (I/O) / A17 (output) / TxD2 (output)
PA0 (I/O) / A16 (output)
Figure 10B.7 Port A Pin Functions (Modes 4 to 6)
Mode 7: In mode 7, port A pins function as I/O ports and SCI2 I/O pins (SCK2, TxD2, and
RxD2). Input or output can be specified for each pin on an individual bit basis. Setting a PADDR
bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the
pin an input port.
Port A pin functions are shown in figure 10B.8.
PA3 (I/O) / SCK2 (I/O)
Port A
PA2 (I/O) / RxD2 (input)
PA1 (I/O) / TxD2 (output)
PA0 (I/O)
Figure 10B.8 Port A Pin Functions (Mode 7)
Rev. 5.00 Mar 28, 2005 page 488 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.7.4 MOS Input Pull-Up Function
Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input
pull-up can be specified as on or off on an individual bit basis.
In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI’s
SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS
input pull-up for that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the SCI’s SCMR, SMR,
and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up
for that pin.
The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby
mode. The prior state is retained by a manual reset or in software standby mode.
Table 10B.11 summarizes the MOS input pull-up states.
Table 10B.11 MOS Input Pull-Up States (Port A)
Pin States
Power-On
Reset
Address output or OFF
SCI output
Other than above
Hardware
Standby Mode
Manual
Reset
Software
Standby Mode
In Other
Operations
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PADDR = 0 and PAPCR = 1; otherwise off.
Rev. 5.00 Mar 28, 2005 page 489 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.8 Port B
10B.8.1 Overview
Port B is an 8-bit I/O port. Port B pins also function as TPU I/O pins (TIOCA3, TIOCB3,
TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5) and as address outputs; the pin
functions change according to the operating mode.
Port B has a built-in MOS input pull-up function that can be controlled by software.
Figure 10B.9 shows the port B pin configuration.
Port B
Port B pins
Pin functions in modes 4 to 6
PB7/A15/TIOCB5
PB7 (I/O) / A15 (output) / TIOCB5 (I/O)
PB6/A14/TIOCA5
PB6 (I/O) / A14 (output) / TIOCA5 (I/O)
PB5/A13/TIOCB4
PB5 (I/O) / A13 (output) / TIOCB4 (I/O)
PB4/A12/TIOCA4
PB4 (I/O) / A12 (output) / TIOCA4 (I/O)
PB3/A11/TIOCD3
PB3 (I/O) / A11 (output) / TIOCD3 (I/O)
PB2/A10/TIOCC3
PB2 (I/O) / A10 (output) / TIOCC3 (I/O)
PB1/A9 /TIOCB3
PB1 (I/O) / A9 (output) / TIOCB3 (I/O)
PB0/A8 /TIOCA3
PB0 (I/O) / A8 (output) / TIOCA3 (I/O)
Pin functions in mode 7
PB7 (I/O) / TIOCB5 (I/O)
PB6 (I/O) / TIOCA5 (I/O)
PB5 (I/O) / TIOCB4 (I/O)
PB4 (I/O) / TIOCA4 (I/O)
PB3 (I/O) / TIOCD3 (I/O)
PB2 (I/O) / TIOCC3 (I/O)
PB1 (I/O) / TIOCB3 (I/O)
PB0 (I/O) / TIOCA3 (I/O)
Figure 10B.9 Port B Pin Functions
Rev. 5.00 Mar 28, 2005 page 490 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.8.2 Register Configuration
Table 10B.12 shows the port B register configuration.
Table 10B.12 Port B Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port B data direction register
PBDDR
W
H'00
H'FE3A
Port B data register
PBDR
R/W
H'00
H'FF0A
Port B register
PORTB
R
Undefined
H'FFBA
Port B MOS pull-up control register
PBPCR
R/W
H'00
H'FE41
Port B open-drain control register
PBODR
R/W
H'00
H'FE48
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
Bit
:
7
6
5
4
3
2
1
0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode. The OPE bit in SBYCR is used to select
whether the address output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
• Modes 4 to 6
The corresponding port B pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of the PBDDR bits. When pins are not used as
address outputs, setting a PBDDR bit to 1 makes the corresponding port B pin an output port,
while clearing the bit to 0 makes the pin an input port.
• Mode 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 491 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port B Data Register (PBDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PB7DR
PB6DR
PB5DR
PB4DR
PB3DR
PB2DR
PB1DR
PB0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to
PB0). PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains
its prior state by a manual reset or in software standby mode.
Port B Register (PORTB)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PB7
—*
PB6
—*
PB5
—*
PB4
—*
PB3
—*
PB2
—*
PB1
—*
PB0
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PB7 to PB0.
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port B pins (PB7 to PB0) must always be performed on PBDR.
If a PORTB read is performed while PBDDR bits are set to 1, the PBDR values are read. If a
PORTB read is performed while PBDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin
states, as PBDDR and PBDR are initialized. PORTB retains its prior state in software standby
mode.
Rev. 5.00 Mar 28, 2005 page 492 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port B MOS Pull-Up Control Register (PBPCR)
Bit
:
7
6
5
4
3
2
1
0
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port B on an individual bit basis.
In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s
TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for
that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the TPU’s TIOR and in
DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.
PBPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
Port B Open Drain Control Register (PBODR)
Bit
:
7
6
5
4
3
2
1
0
PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PBODR is an 8-bit readable/writable register that controls the PMOS on/off state for each port B
pin (PB7 to PB0).
When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR,
setting a PBODR bit makes the corresponding port B pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PBODR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
Rev. 5.00 Mar 28, 2005 page 493 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.8.3 Pin Functions
Modes 4 to 6: In modes 4 to 6, the corresponding port B pins become address outputs in
accordance with the setting of bits AE3 to AE0 in PFCR. When pins are not used as address
outputs, they function as TPU I/O pins and I/O ports.
Port B pin functions in modes 4 to 6 are shown in figure 10B.10.
PB7 (I/O) / A15 (output) / TIOCB5 (I/O)
PB6 (I/O) / A14 (output) / TIOCA5 (I/O)
PB5 (I/O) / A13 (output) / TIOCB4 (I/O)
PB4 (I/O) / A12 (output) / TIOCA4 (I/O)
Port B
PB3 (I/O) / A11 (output) / TIOCD3 (I/O)
PB2 (I/O) / A10 (output) / TIOCC3 (I/O)
PB1 (I/O) / A9 (output) / TIOCB3 (I/O)
PB0 (I/O) / A8 (output) / TIOCA3 (I/O)
Figure 10B.10 Port B Pin Functions (Modes 4 to 6)
Mode 7: In mode 7, port B pins function as I/O ports and TPU I/O pins (TIOCA3, TIOCB3,
TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5). Input or output can be specified
for each pin on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B
pin an output port, while clearing the bit to 0 makes the pin an input port.
Port B pin functions in mode 7 are shown in figure 10B.11.
PB7 (I/O) / TIOCB5 (I/O)
PB6 (I/O) / TIOCA5 (I/O)
PB5 (I/O) / TIOCB4 (I/O)
Port B
PB4 (I/O) / TIOCA4 (I/O)
PB3 (I/O) / TIOCD3 (I/O)
PB2 (I/O) / TIOCC3 (I/O)
PB1 (I/O) / TIOCB3 (I/O)
PB0 (I/O) / TIOCA3 (I/O)
Figure 10B.11 Port B Pin Functions (Mode 7)
Rev. 5.00 Mar 28, 2005 page 494 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.8.4 MOS Input Pull-Up Function
Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input
pull-up can be specified as on or off on an individual bit basis.
In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s
TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for
that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the TPU’s TIOR and in
DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby
mode. The prior state is retained by a manual reset or in software standby mode.
Table 10B.13 summarizes the MOS input pull-up states.
Table 10B.13 MOS Input Pull-Up States (Port B)
Pin States
Address output or
TPU output
Other than above
Power-On
Reset
Hardware
Standby Mode
Manual
Reset
Software
Standby Mode
In Other
Operations
OFF
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PBDDR = 0 and PBPCR = 1; otherwise off.
Rev. 5.00 Mar 28, 2005 page 495 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.9 Port C
10B.9.1 Overview
Port C is an 8-bit I/O port. Port C has an address bus output function. The pin functions change
according to the operating mode.
Port C has a built-in MOS input pull-up function that can be controlled by software.
Figure 10B.12 shows the port C pin configuration.
Port C
Port C pins
Pin functions in modes 4 and 5
PC7/A7
A7 (output)
PC6/A6
A6 (output)
PC5/A5
A5 (output)
PC4/A4
A4 (output)
PC3/A3
A3 (output)
PC2/A2
A2 (output)
PC1/A1
A1 (output)
PC0/A0
A0 (output)
Pin functions in mode 6
Pin functions in mode 7
When PCDDR = 1
When PCDDR = 0
PC7 (I/O)
A7 (output)
PC7 (input)
PC6 (I/O)
A6 (output)
PC6 (input)
PC5 (I/O)
A5 (output)
PC5 (input)
PC4 (I/O)
A4 (output)
PC4 (input)
PC3 (I/O)
A3 (output)
PC3 (input)
PC2 (I/O)
A2 (output)
PC2 (input)
PC1 (I/O)
A1 (output)
PC1 (input)
PC0 (I/O)
A0 (output)
PC0 (input)
Figure 10B.12 Port C Pin Functions
Rev. 5.00 Mar 28, 2005 page 496 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.9.2 Register Configuration
Table 10B.14 shows the port C register configuration.
Table 10B.14 Port C Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port C data direction register
PCDDR
W
H'00
H'FE3B
Port C data register
PCDR
R/W
H'00
H'FF0B
Port C register
PORTC
R
Undefined
H'FFBB
Port C MOS pull-up control register
PCPCR
R/W
H'00
H'FE42
Port C open-drain control register
PCODR
R/W
H'00
H'FE49
Note: * Lower 16 bits of the address.
Port C Data Direction Register (PCDDR)
Bit
:
7
6
5
4
3
2
1
0
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.
PCDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode. The OPE bit in SBYCR is used to select
whether the address output pins retain their output state or become high-impedance when the
mode is changed to software standby mode.
• Modes 4 and 5
The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits.
• Mode 6
Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while
clearing the bit to 0 makes the pin an input port.
• Mode 7
Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing
the bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 497 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port C Data Register (PCDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PC7DR
PC6DR
PC5DR
PC4DR
PC3DR
PC2DR
PC1DR
PC0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to
PC0).
PCDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port C Register (PORTC)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PC7
—*
PC6
—*
PC5
—*
PC4
—*
PC3
—*
PC2
—*
PC1
—*
PC0
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PC7 to PC0.
PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port C pins (PC7 to PC0) must always be performed on PCDR.
If a PORTC read is performed while PCDDR bits are set to 1, the PCDR values are read. If a
PORTC read is performed while PCDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTC contents are determined by the pin
states, as PCDDR and PCDR are initialized. PORTC retains its prior state by a manual reset or in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 498 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port C MOS Pull-Up Control Register (PCPCR)
Bit
:
7
6
5
4
3
2
1
0
PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port C on an individual bit basis.
In modes 6 and 7, if PCPCR is set to 1 when the port is in the input state in accordance with the
settings of PCDDR, the MOS input pull-up is set to ON.
PCPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
Port C Open Drain Control Register (PCODR)
Bit
:
7
6
5
4
3
2
1
0
PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCDDR is an 8-bit read/write register and controls PMOS on/off of each pin (PC7 to PC0) of port
C.
If PCODR is set to 1 by setting AE3 to AE0 in PFCR in mode other than address output mode,
port C pins function as NMOS open drain outputs and when the setting is cleared to 0, the pins
function as CMOS outputs.
PCODR is initialized to H'00 in power-on reset mode or hardware standby mode. PCODR retains
the last state in manual reset mode or software standby mode.
Rev. 5.00 Mar 28, 2005 page 499 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.9.3 Pin Functions for Each Mode
(1) Modes 4 and 5
In modes 4 and 5, port C pins function as address outputs automatically.
Figure 10B.13 shows the port C pin functions.
A7 (output)
A6 (output)
A5 (output)
Port C
A4 (output)
A3 (output)
A2 (output)
A1 (output)
A0 (output)
Figure 10B.13 Port C Pin Functions (Modes 4 and 5)
(2) Mode 6
In mode 6, port C pints function as address outputs or input ports and I/O can be specified in bit
units. When each bit in PCDDR is set to 1, the corresponding pin functions as an address output
and when the bit cleared to 0, the pin functions as an input port.
Figure 10B.14 shows the port C pin functions.
Rev. 5.00 Mar 28, 2005 page 500 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port C
PCDDR= 1
PCDDR= 0
A7 (output)
PC7 (input)
A6 (output)
PC6 (input)
A5 (output)
PC5 (input)
A4 (output)
PC4 (input)
A3 (output)
PC3 (input)
A2 (output)
PC2 (input)
A1 (output)
PC1 (input)
A0 (output)
PC0 (input)
Figure 10B.14 Port C Pin Functions (Mode 6)
(3) Mode 7
In mode 7, port C pins function as I/O ports and I/O can be specified for each pin in bit units.
When each bit in PCDDR is set to 1, the corresponding pin functions as an output port and when
the bit is cleared to 0, the pin functions as an input port.
Figure 10B.15 shows the port C pin functions.
PC7 (I/O)
PC6 (I/O)
PC5 (I/O)
Port C
PC4 (I/O)
PC3 (I/O)
PC2 (I/O)
PC1 (I/O)
PC0 (I/O)
Figure 10B.15 Port C Pin Functions (Mode 7)
Rev. 5.00 Mar 28, 2005 page 501 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.9.4 MOS Input Pull-Up Function
Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an
individual bit basis.
In modes 6 and 7, when PCPCR is set to 1 in the input state by setting of PCDDR, the MOS input
pull-up is set to ON.
The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby
mode. The prior state is retained by a manual reset or in software standby mode.
Table 10B.15 summarizes the MOS input pull-up states.
Table 10B.15 MOS Input Pull-Up States (Port C)
Pin States
Power-On
Reset
Hardware
Standby Mode
Address output
OFF
OFF
Other than above
Manual
Reset
In Other
Operations
OFF
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PCDDR = 0 and PCPCR = 1; otherwise off.
Rev. 5.00 Mar 28, 2005 page 502 of 1422
REJ09B0234-0500
Software
Standby Mode
Section 10B I/O Ports (H8S/2695)
10B.10 Port D
10B.10.1 Overview
Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change
according to the operating mode.
Port D has a built-in MOS input pull-up function that can be controlled by software.
Figure 10B.16 shows the port D pin configuration.
Port D
Port D pins
Pin functions in modes 4 to 6
PD7/D15
D15 (I/O)
PD6/D14
D14 (I/O)
PD5/D13
D13 (I/O)
PD4/D12
D12 (I/O)
PD3/D11
D11 (I/O)
PD2/D10
D10 (I/O)
PD1/D9
D9
(I/O)
PD0/D8
D8
(I/O)
Pin functions in mode 7
PD7 (I/O)
PD6 (I/O)
PD5 (I/O)
PD4 (I/O)
PD3 (I/O)
PD2 (I/O)
PD1 (I/O)
PD0 (I/O)
Figure 10B.16 Port D Pin Functions
Rev. 5.00 Mar 28, 2005 page 503 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.10.2 Register Configuration
Table 10B.16 shows the port D register configuration.
Table 10B.16 Port D Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port D data direction register
PDDDR
W
H'00
H'FE3C
Port D data register
PDDR
R/W
H'00
H'FF0C
Port D register
PORTD
R
Undefined
H'FFBC
Port D MOS pull-up control register
PDPCR
R/W
H'00
H'FE43
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR)
Bit
:
7
6
5
4
3
2
1
0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
• Modes 4 to 6
The input/output direction specification by PDDDR is ignored, and port D is automatically
designated for data I/O.
• Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing
the bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 504 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port D Data Register (PDDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PD7DR
PD6DR
PD5DR
PD4DR
PD3DR
PD2DR
PD1DR
PD0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to
PD0).
PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port D Register (PORTD)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PD7
—*
PD6
—*
PD5
—*
PD4
—*
PD3
—*
PD2
—*
PD1
—*
PD0
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PD7 to PD0.
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port D pins (PD7 to PD0) must always be performed on PDDR.
If a PORTD read is performed while PDDDR bits are set to 1, the PDDR values are read. If a
PORTD read is performed while PDDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin
states, as PDDDR and PDDR are initialized. PORTD retains its prior state by a manual reset or in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 505 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port D MOS Pull-Up Control Register (PDPCR)
Bit
:
7
6
5
4
3
2
1
0
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port D on an individual bit basis.
When a PDDDR bit is cleared to 0 (input port setting) in mode 7, setting the corresponding
PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.
PDPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
10B.10.3 Pin Functions
Modes 4 to 6: In modes 4 to 6, port D pins are automatically designated as data I/O pins.
Port D pin functions in modes 4 to 6 are shown in figure 10B.17.
D15 (I/O)
D14 (I/O)
D13 (I/O)
Port D
D12 (I/O)
D11 (I/O)
D10 (I/O)
D9
(I/O)
D8
(I/O)
Figure 10B.17 Port D Pin Functions (Modes 4 to 6)
Mode 7: In mode 7, port D pins function as I/O ports. Input or output can be specified for each pin
on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output
port, while clearing the bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 506 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port D pin functions in mode 7 are shown in figure 10B.18.
PD7 (I/O)
PD6 (I/O)
PD5 (I/O)
Port D
PD4 (I/O)
PD3 (I/O)
PD2 (I/O)
PD1 (I/O)
PD0 (I/O)
Figure 10B.18 Port D Pin Functions (Mode 7)
10B.10.4 MOS Input Pull-Up Function
Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit
basis.
When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR bit to 1 turns on
the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby
mode. The prior state is retained by a manual reset or in software standby mode.
Table 10B.17 summarizes the MOS input pull-up states.
Table 10B.17 MOS Input Pull-Up States (Port D)
Modes
Power-On
Reset
Hardware
Standby Mode
Manual
Reset
Software
Standby Mode
In Other
Operations
4 to 6
OFF
OFF
OFF
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
7
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PDDDR = 0 and PDPCR = 1; otherwise off.
Rev. 5.00 Mar 28, 2005 page 507 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.11 Port E
10B.11.1 Overview
Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change
according to the operating mode and whether 8-bit or 16-bit bus mode is selected.
Port E has a built-in MOS input pull-up function that can be controlled by software.
Figure 10B.19 shows the port E pin configuration.
Port E
Port E pins
Pin functions in modes 4 to 6
PE7/D7
PE7 (I/O) / D7 (I/O)
PE6/D6
PE6 (I/O) / D6 (I/O)
PE5/D5
PE5 (I/O) / D5 (I/O)
PE4/D4
PE4 (I/O) / D4 (I/O)
PE3/D3
PE3 (I/O) / D3 (I/O)
PE2/D2
PE2 (I/O) / D2 (I/O)
PE1/D1
PE1 (I/O) / D1 (I/O)
PE0/D0
PE0 (I/O) / D0 (I/O)
Pin functions in mode 7
PE7 (I/O)
PE6 (I/O)
PE5 (I/O)
PE4 (I/O)
PE3 (I/O)
PE2 (I/O)
PE1 (I/O)
PE0 (I/O)
Figure 10B.19 Port E Pin Functions
Rev. 5.00 Mar 28, 2005 page 508 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.11.2 Register Configuration
Table 10B.18 shows the port E register configuration.
Table 10B.18 Port E Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port E data direction register
PEDDR
W
H'00
H'FE3D
Port E data register
PEDR
R/W
H'00
H'FF0D
Port E register
PORTE
R
Undefined
H'FFBD
Port E MOS pull-up control register
PEPCR
R/W
H'00
H'FE44
Note: * Lower 16 bits of the address.
Port E Data Direction Register (PEDDR)
Bit
:
7
6
5
4
3
2
1
0
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
• Modes 4 to 6
When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit
to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the
pin an input port.
When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is
ignored, and port E is designated for data I/O.
For details of 8-bit and 16-bit bus modes, see section 7, Bus Controller.
• Mode 7
Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the
bit to 0 makes the pin an input port.
Rev. 5.00 Mar 28, 2005 page 509 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Port E Data Register (PEDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PE7DR
PE6DR
PE5DR
PE4DR
PE3DR
PE2DR
PE1DR
PE0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to
PE0).
PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port E Register (PORTE)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PE7
—*
PE6
—*
PE5
—*
PE4
—*
PE3
—*
PE2
—*
PE1
—*
PE0
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PE7 to PE0.
PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port E pins (PE7 to PE0) must always be performed on PEDR.
If a PORTE read is performed while PEDDR bits are set to 1, the PEDR values are read. If a
PORTE read is performed while PEDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin
states, as PEDDR and PEDR are initialized. PORTE retains its prior state by a manual reset or in
software standby mode.
Port E MOS Pull-Up Control Register (PEPCR)
Bit
:
7
6
5
4
3
2
1
0
PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Mar 28, 2005 page 510 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port E on an individual bit basis.
When a PEDDR bit is cleared to 0 (input port setting) with 8-bit bus mode selected in modes 4, 5,
or 6, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for
the corresponding pin.
PEPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
10B.11.3 Pin Functions
Modes 4 to 6: In modes 4 to 6, when 8-bit access is designated and 8-bit bus mode is selected,
port E pins are automatically designated as I/O ports. Setting a PEDDR bit to 1 makes the
corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.
When 16-bit bus mode is selected, the input/output direction specification by PEDDR is ignored,
and port E is designated for data I/O.
Port E pin functions in modes 4 to 6 are shown in figure 10B.20.
Port E
8-bit bus mode
16-bit bus mode
PE7 (I/O)
D7 (I/O)
PE6 (I/O)
D6 (I/O)
PE5 (I/O)
D5 (I/O)
PE4 (I/O)
D4 (I/O)
PE3 (I/O)
D3 (I/O)
PE2 (I/O)
D2 (I/O)
PE1 (I/O)
D1 (I/O)
PE0 (I/O)
D0 (I/O)
Figure 10B.20 Port E Pin Functions (Modes 4 to 6)
Mode 7: In mode 7, port E pins function as I/O ports. Input or output can be specified for each pin
on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port,
while clearing the bit to 0 makes the pin an input port.
Port E pin functions in mode 7 are shown in figure 10B.21.
Rev. 5.00 Mar 28, 2005 page 511 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
PE7 (I/O)
PE6 (I/O)
PE5 (I/O)
Port E
PE4 (I/O)
PE3 (I/O)
PE2 (I/O)
PE1 (I/O)
PE0 (I/O)
Figure 10B.21 Port E Pin Functions (Mode 7)
10B.11.4 MOS Input Pull-Up Function
Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7,
and can be specified as on or off on an individual bit basis.
When a PEDDR bit is cleared to 0 in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7,
setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby
mode. The prior state is retained by a manual reset or in software standby mode.
Table 10B.19 summarizes the MOS input pull-up states.
Table 10B.19 MOS Input Pull-Up States (Port E)
Modes
Power-On
Reset
Hardware
Standby Mode
Manual
Reset
Software
Standby Mode
In Other
Operations
7
OFF
OFF
ON/OFF
ON/OFF
ON/OFF
OFF
OFF
OFF
4 to 6
8-bit bus
16-bit bus
Legend:
OFF:
MOS input pull-up is always off.
ON/OFF: On when PEDDR = 0 and PEPCR = 1; otherwise off.
Rev. 5.00 Mar 28, 2005 page 512 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.12 Port F
10B.12.1 Overview
Port F is an 8-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and
IRQ3), A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR,
LWR, WAIT, BREQO, BREQ, and BACK), and the system clock (φ) output pin.
Figure 10B.22 shows the port F pin configuration.
Port F
Port F pins
Pin functions in modes 4 to 6
PF7/φ
PF7 (input) / φ (output)
PF6/AS
AS (output)
PF5/RD
RD (output)
PF4/HWR
HWR (output)
PF3/LWR/ADTRG/IRQ3
PF3 (I/O) / LWR (output) / ADTRG (input) / IRQ3 (input)
PF2/WAIT/BREQO
PF2 (I/O) / WAIT (input) / BREQO (output)
PF1/BACK
PF1 (I/O) / BACK (output)
PF0/BREQ/IRQ2
PF0 (I/O) / BREQ (input) / IRQ2 (input)
Pin functions in mode 7
PF7 (input) / φ (output)
PF6 (I/O)
PF5 (I/O)
PF4 (I/O)
PF3 (I/O) / ADTRG (input) / IRQ3 (input)
PF2 (I/O)
PF1 (I/O)
PF0 (I/O) / IRQ2 (input)
Figure 10B.22 Port F Pin Functions
Rev. 5.00 Mar 28, 2005 page 513 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.12.2 Register Configuration
Table 10B.20 shows the port F register configuration.
Table 10B.20 Port F Registers
Name
Abbreviation
R/W
Initial Value
Address*1
Port F data direction register
PFDDR
W
H'80/H'00*2
H'FE3E
Port F data register
PFDR
R/W
H'00
H'FF0E
Port F register
PORTF
R
Undefined
H'FFBE
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Port F Data Direction Register (PFDDR)
Bit
:
7
6
5
4
3
2
1
0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 4 to 6
Initial value :
1
0
0
0
0
0
0
0
R/W
:
W
W
W
W
W
W
W
W
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Mode 7
:
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 4 to
6, and to H'00 in mode 7. It retains its prior state by a manual reset or in software standby mode.
The OPE bit in SBYCR is used to select whether the bus control output pins retain their output
state or become high-impedance when a transition is made to software standby mode.
• Modes 4 to 6
Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
Rev. 5.00 Mar 28, 2005 page 514 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pins PF2 to PF0 are designated as bus control input/output pins (WAIT, BREQO, BACK, and
BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes
the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input
port.
• Mode 7
Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in
the case of pin PF7, the φ output pin. Clearing the bit to 0 makes the pin an input port.
Port F Data Register (PFDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PF7DR
PF6DR
PF5DR
PF4DR
PF3DR
PF2DR
PF1DR
PF0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state by a manual reset or in software standby mode.
Port F Register (PORTF)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PF7
—*
PF6
—*
PF5
—*
PF4
—*
PF3
—*
PF2
—*
PF1
—*
PF0
—*
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
If a PORTF read is performed while PFDDR bits are set to 1, the PFDR values are read. If a
PORTF read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin
states, as PFDDR and PFDR are initialized. PORTF retains its prior state by a manual reset or in
software standby mode.
Rev. 5.00 Mar 28, 2005 page 515 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.12.3 Pin Functions
Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), A/D trigger input pin
(ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQO, BREQ,
and BACK), and the system clock (φ) output pin. The pin functions differ between modes 4 to 6,
and mode 7. Port F pin functions are shown in table 10B.21.
Table 10B.21 Port F Pin Functions
Pin
Selection Method and Pin Functions
PF7/φ
The pin function is switched as shown below according to bit PF7DDR.
PF7DDR
Pin function
PF6/AS
PF7 input pin
φ output pin
Operating
Mode
Modes 4 to 6
PF6DDR
—
AS
output pin
Mode 7
0
1
PF6 input pin
PF6 output pin
The pin function is switched as shown below according to the operating mode
and bit PF5DDR.
Operating
Mode
Modes 4 to 6
PF5DDR
Pin function
PF4/HWR
1
The pin function is switched as shown below according to the combination of
the operating mode and bits BREQOE, WAITE, ABW5 to ABW2, and
PF2DDR.
Pin function
PF5/RD
0
—
RD
output pin
Mode 7
0
1
PF5 input pin
PF5 output pin
The pin function is switched as shown below according to the operating mode
and bit PF4DDR.
Operating
Mode
Modes 4 to 6
PF4DDR
—
Pin function
HWR
Rev. 5.00 Mar 28, 2005 page 516 of 1422
REJ09B0234-0500
output pin
Mode 7
0
1
PF4 input pin
PF4 output pin
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
PF3/LWR/ADTRG/ The pin function is switched as shown below according to the operating mode,
IRQ3
the bus mode, A/D converter bits TRGS1 and TRGS0, and bit PF3DDR.
Operating
mode
Modes 4 to 6
Bus mode
16-bit bus
mode
PF3DDR
—
Pin function
Mode 7
8-bit bus mode
0
—
1
0
1
output PF3 input PF3 output PF3 input PF3 output
pin
pin
pin
pin
pin
1
*
ADTRG input pin
LWR
IRQ3
input pin*2
Notes: 1. ADTRG input when TRGS0 = TRGS1 = 1.
2. When used as an external interrupt input pin, do not use as an I/O
pin for another function.
PF2/ WAIT/
BREQO
The pin function is switched as shown below according to the combination of
the operating mode and bits BREQOE, WAITE, ABW5 to ABW2, and
PF2DDR.
Operating
Mode
Modes 4 to 6
BREQOE
0
WAITE
PF2DDR
Pin function
PF1/BACK
Mode 7
0
1
1
—
—
—
0
1
—
—
0
1
PF2
input
pin
PF2
output
pin
WAIT
BREQO
input
pin
output
pin
PF2
input
pin
PF2
output
pin
The pin function is switched as shown below according to the combination of
the operating mode and bits BRLE and PF1DDR.
Operating
Mode
Modes 4 to 6
BRLE
0
PF1DDR
Pin function
0
Mode 7
1
1
—
PF1 input PF1 output
BACK
pin
pin
output pin
—
0
1
PF1 input PF1 output
pin
pin
Rev. 5.00 Mar 28, 2005 page 517 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
PF0/BREQ/IRQ2
The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE and PF0DDR.
Operating
Mode
Modes 4 to 6
BRLE
Mode 7
0
PF0DDR
Pin function
1
—
0
1
—
0
1
PF0
input pin
PF0
output pin
BREQ
input pin
PF0
input pin
PF0
output pin
IRQ2
input pin
10B.13 Port G
10B.13.1 Overview
Port G is a 5-bit I/O port and also used as external interrupt input pins (IRQ6 and IRQ7) and bus
control signal output pins (CS0 to CS3).
Figure 10B.23 shows the configuration of port G pins.
Port G pin
Port G
Pin Functions in Modes 4 to 6
PG4 / CS0
PG4 (input) / CS0 (output)
PG3 / CS1
PG3 (input) / CS1 (output)
PG2 / CS2
PG2 (input) / CS2 (output)
PG1 / CS3 / IRQ7
PG1 (input) / CS3 (output) / IRQ7 (input)
PG0 / IRQ6
PG0 (I/O) / IRQ6 (input)
Pin Functions in Mode 7
PG4 (I/O)
PG3 (I/O)
PG2 (I/O)
PG1 (I/O) / IRQ7 (input)
PG0 (I/O) / IRQ6 (input)
Figure 10B.23 Port G Pin Functions
Rev. 5.00 Mar 28, 2005 page 518 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
10B.13.2 Register Configuration
Table 10B.22 shows the port G register configuration.
Table 10B.22 Port G Registers
Name
Abbreviation
R/W
Initial Value*2 Address*1
Port G data direction register
PGDDR
W
H'10/H'00*3
H'FE3F
Port G data register
PGDR
R/W
H'00
H'FF0F
Port G register
PORTG
R
Undefined
H'FFBF
Notes: 1. Lower 16 bits of the address.
2. Value of bits 4 to 0.
3. The initial value varies according to the mode.
Port G Data Direction Register (PGDDR)
Bit
:
7
6
5
—
—
—
4
3
2
1
0
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
Modes 4 and 5
Initial value
: Undefined Undefined Undefined
1
0
0
0
0
R/W
:
W
W
W
W
W
—
—
—
Modes 6 and 7
Initial value
: Undefined Undefined Undefined
0
0
0
0
0
R/W
:
W
W
W
W
W
—
—
—
PGDDR is an 8-bit write only register and specifies I/O of each pin of port G in bit units. Read
processing is invalid. Bits 7 to 5 are reserved bits. When the contents are read, undefined values
are read.
In modes 4 and 5, the PGDDR bits are initialized to H'10 (bits 4 to 0) in power-on reset or
hardware standby mode, in modes 6 and 7, the bits are initialized to H'00 (bits 4 to 0). In manual
reset or software standby mode, PGDDR retains the last status. Use the OPE bit of SBYCR to
select whether the bus control output pin retains the output state or becomes the high-impedance
when the mode is changed to a software standby mode.
• Modes 4 to 6
When PGDDR is set to 1, pins PG4 to PG1 function as bus control signal output pins (CS0 to
CS3). When PGDDR is cleared to 0, the pins function as input ports.
Rev. 5.00 Mar 28, 2005 page 519 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
When PGDDR is set to 1, the PG0 pin functions as an output port, and when PGDDR is
cleared to 0, it functions as an input port.
• Mode 7
PGDDR to 1 it becomes an output port, and by clearing it to 0 it becomes an input port.
Port G Data Register (PGDR)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
PG4DR
PG3DR
PG2DR
PG1DR
PG0DR
Initial value : Undefined Undefined Undefined
R/W
:
—
—
—
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
PGDR is an 8-bit read/write register and stores output data of port G output pins (PG4 to PG0).
Bits 7 to 5 are reserved bits. When the contents are read, undefined values are read. Write
processing is invalid.
In power-on reset or hardware standby mode, PGDR is initialized to H'00 (bits 4 to 0). In manual
reset or software standby mode, PGDR retains the last state.
(3) Port G Register (PORTG)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
PG4
PG3
PG2
PG1
PG0
—*
—*
—*
—*
—*
R
R
R
R
R
Initial value : Undefined Undefined Undefined
R/W
:
—
—
—
Note: * Determined by the state of PG4 to PG0
PORTG is an 8-bit read only register and reflects the pin state. Write processing is invalid. Write
processing of output data of port G pins (PG4 to PG0) must be performed for PGDR.
Bits 7 to 5 are reserved bits. When the contents are read, undefined values are read. Write
processing is invalid.
If PORTG is read when PGDDR is set to 1, the value in PGDR is read. If PORTG is read when
PGDDR is cleared to 0, the pin state is read.
Rev. 5.00 Mar 28, 2005 page 520 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
In power-on reset or hardware standby mode, port G is determined by the pin state because
PGDDR and PGDR are initialized. In manual reset or software standby mode, the last state is
retained.
10B.13.3 Pin Functions
Port G is used also as external interrupt input pins (IRQ6 and IRQ7) and bus control signal output
pins (CS0 to CS3). The pin functions are different between modes 4 and 6, and
mode 7. Table 10B.23 shows the port G pin functions.
Table 10B.23 Port G Pin Functions
Pin
Selection Method and Pin Functions
PG4/CS0
The pin function is switched as shown below according to the operating mode and
bit PG4DDR.
Modes 4 to 6
Operating
Mode
PG4DDR
Pin function
PG3/CS1
0
1
PG4 input pin
CS0
output pin
0
1
PG4 input pin
PG4 output pin
The pin function is switched as shown below according to the operating mode and
bit PG3DDR.
Modes 4 to 6
Operating
Mode
PG3DDR
Pin function
PG2/CS2
Mode 7
0
Mode 7
1
PG3 input pin
CS1
output pin
0
1
PG3 input pin
PG3 output pin
The pin function is switched as shown below according to the operating mode and
bit PG2DDR.
Operating
Mode
PG2DDR
Pin function
Modes 4 to 6
0
PG2 input pin
Mode 7
1
CS2
output pin
0
1
PG2 input pin
PG2 output pin
Rev. 5.00 Mar 28, 2005 page 521 of 1422
REJ09B0234-0500
Section 10B I/O Ports (H8S/2695)
Pin
Selection Method and Pin Functions
PG1/CS3/
The pin function is switched as shown below according to the operating mode and
bits OES and PG1DDR in BCRL.
IRQ7
Operating
Mode
PG1DDR
Pin function
Modes 4 to 6
Mode 7
0
1
0
1
PG1
input pin
CS3
output pin
PG1
input pin
PG1
output pin
IRQ7
PG0/IRQ6
input
The pin function is switched as shown below according to the operating mode and
bits RMTS2 to RMTS0 in BCRH.
Operating
Mode
PG0DDR
Pin function
Modes 4 to 6
Mode 7
0
1
0
1
PG0
input pin
PG0
output pin
PG0
input pin
PG0
output pin
IRQ6
Rev. 5.00 Mar 28, 2005 page 522 of 1422
REJ09B0234-0500
input
Section 11 16-Bit Timer Pulse Unit (TPU)
Section 11 16-Bit Timer Pulse Unit (TPU)
11.1
Overview
The H8S/2633 Group has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer
channels.
11.1.1
Features
• Maximum 16-pulse input/output
 A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,
and two each for channels 1, 2, 4, and 5), each of which can be set independently as an
output compare/input capture register
 TGRC and TGRD for channels 0 and 3 can also be used as buffer registers
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
 Waveform output at compare match: Selection of 0, 1, or toggle output
 Input capture function: Selection of rising edge, falling edge, or both edge detection
 Counter clear operation: Counter clearing possible by compare match or input capture
 Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously
 Simultaneous clearing by compare match and input capture possible
 Register simultaneous input/output possible by counter synchronous operation
•
•
•
•
 PWM mode: Any PWM output duty can be set
 Maximum of 15-phase PWM output possible by combination with synchronous operation
Buffer operation settable for channels 0 and 3
 Input capture register double-buffering possible
 Automatic rewriting of output compare register possible
Phase counting mode settable independently for each of channels 1, 2, 4, and 5
 Two-phase encoder pulse up/down-count possible
Cascaded operation
 Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel
4) overflow/underflow
Fast access via internal 16-bit bus
 Fast access is possible via a 16-bit bus interface
Rev. 5.00 Mar 28, 2005 page 523 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
• 26 interrupt sources
 For channels 0 and 3, four compare match/input capture dual-function interrupts and one
overflow interrupt can be requested independently
 For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one
overflow interrupt, and one underflow interrupt can be requested independently
• Automatic transfer of register data
 Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer
controller (DTC)* or DMA controller (DMAC)*
• Programmable pulse generator (PPG)* output trigger can be generated
 Channels 0 to 3 compare match/input capture signals can be used as PPG output trigger
• A/D converter conversion start trigger can be generated
 Channels 0 to 5 compare match A/input capture A signals can be used as A/D converter
conversion start trigger
• Module stop mode can be set
 As the initial setting, TPU operation is halted. Register access is enabled by exiting module
stop mode
Table 11.1 lists the functions of the TPU.
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 524 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.1 TPU Functions
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
Count clock
φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
TCLKA
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKC
TCLKD
General registers
TGR0A
TGR0B
TGR1A
TGR1B
TGR2A
TGR2B
TGR3A
TGR3B
TGR4A
TGR4B
TGR5A
TGR5B
General registers/
buffer registers
TGR0C
TGR0D
—
—
TGR3C
TGR3D
—
—
I/O pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Counter clear
function
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
—
—
Compare 0 output
match
1 output
output
Toggle
output
Input capture
function
Synchronous
operation
PWM mode
Phase counting
mode
Buffer operation
—
—
—
—
Rev. 5.00 Mar 28, 2005 page 525 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
DMAC
TGR0A
activation* compare
match or
input capture
TGR1A
compare
match or
input capture
TGR2A
compare
match or
input capture
TGR3A
compare
match or
input capture
TGR4A
compare
match or
input capture
TGR5A
compare
match or
input capture
DTC
TGR
activation* compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
A/D
converter
trigger
TGR0A
compare
match or
input capture
TGR1A
compare
match or
input capture
TGR2A
compare
match or
input capture
TGR3A
compare
match or
input capture
TGR4A
compare
match or
input capture
TGR5A
compare
match or
input capture
PPG
trigger*
TGR0A/
TGR0B
compare
match or
input capture
TGR1A/
TGR1B
compare
match or
input capture
TGR2A/
TGR2B
compare
match or
input capture
—
TGR3A/
TGR3B
compare
match or
input capture
—
Interrupt
sources
5 sources
4 sources
4 sources
5 sources
4 sources
4 sources
• Compare
• Compare
• Compare
• Compare
• Compare
• Compare
match or
match or
match or
match or
match or
match or
input
input
input
input
input
input
capture 0A
capture 1A
capture 2A
capture 3A
capture 4A
capture 5A
• Compare
• Compare
• Compare
• Compare
• Compare
• Compare
match or
match or
match or
match or
match or
match or
input
input
input
input
input
input
capture 0B
capture 1B
capture 2B
capture 3B
capture 4B
capture 5B
• Compare
• Overflow
match or
• Underflow
input
capture 0C
• Overflow
• Underflow
• Compare
• Overflow
match or
• Underflow
input
capture 3C
• Compare
match or
input
capture 0D
• Compare
match or
input
capture 3D
• Overflow
• Overflow
Legend:
: Possible
—: Not possible
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 526 of 1422
REJ09B0234-0500
• Overflow
• Underflow
Section 11 16-Bit Timer Pulse Unit (TPU)
11.1.2
Block Diagram
TGRD
TGRB
TGRC
TGRB
A/D converter convertion start signal
TGRB
PPG output trigger signal
TGRD
TGRB
TGRB
TCNT
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TCI4V
TCI4U
Channel 5: TGI5A
TGI5B
TCI5V
TCI5U
Internal data bus
TGRC
TGRA
TCNT
TCNT
TGRA
Bus interface
TGRB
TCNT
TCNT
TGRA
TCNT
TGRA
Module data bus
TGRA
TSR
TSR
TIER
TIER
TSR
TIOR
TIORH TIORL
TGRA
TSR
TIER
TSR
TSTR TSYR
TIER
TSR
TIER
TIOR
TIOR
Control logic
TIOR
TIER
TMDR
TIORH TIORL
TCR
TMDR
Channel 4
TCR
TMDR
Channel 5
Common
TCR
TMDR
TCR
TMDR
Channel 1
TCR
Channel 0
TIOR (H, L):
TIER:
TSR:
TGR (A, B, C, D):
TMDR
Channel 2
Legend:
TSTR: Timer start register
TSYR: Timer synchro register
TCR:
Timer control register
TMDR: Timer mode register
Control logic for channels 0 to 2
Input/output pins
TIOCA0
Channel 0:
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Channel 1:
TIOCB1
TIOCA2
Channel 2:
TIOCB2
TCR
Clock input
Internal clock: ø/1
ø/4
ø/16
ø/64
ø/256
ø/1024
ø/4096
External clock: TCLKA
TCLKB
TCLKC
TCLKD
Control logic for channels 3 to 5
Input/output pins
Channel 3:
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
Channel 4:
TIOCB4
TIOCA5
Channel 5:
TIOCB5
Channel 3
Figure 11.1 shows a block diagram of the TPU.
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Timer I/O control registers (H, L)
Timer interrupt enable register
Timer status register
Timer general registers (A, B, C, D)
Figure 11.1 Block Diagram of TPU
Rev. 5.00 Mar 28, 2005 page 527 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.1.3
Pin Configuration
Table 11.2 summarizes the TPU pins.
Table 11.2 TPU Pins
Channel
Name
Symbol
I/O
Function
All
Clock input A
TCLKA
Input
External clock A input pin
(Channel 1 and 5 phase counting mode A
phase input)
Clock input B
TCLKB
Input
External clock B input pin
(Channel 1 and 5 phase counting mode B
phase input)
Clock input C
TCLKC
Input
External clock C input pin
(Channel 2 and 4 phase counting mode A
phase input)
Clock input D
TCLKD
Input
External clock D input pin
(Channel 2 and 4 phase counting mode B
phase input)
Input capture/out
compare match A0
TIOCA0
I/O
TGR0A input capture input/output compare
output/PWM output pin
Input capture/out
compare match B0
TIOCB0
I/O
TGR0B input capture input/output compare
output/PWM output pin
Input capture/out
compare match C0
TIOCC0
I/O
TGR0C input capture input/output compare
output/PWM output pin
Input capture/out
compare match D0
TIOCD0
I/O
TGR0D input capture input/output compare
output/PWM output pin
Input capture/out
compare match A1
TIOCA1
I/O
TGR1A input capture input/output compare
output/PWM output pin
Input capture/out
compare match B1
TIOCB1
I/O
TGR1B input capture input/output compare
output/PWM output pin
Input capture/out
compare match A2
TIOCA2
I/O
TGR2A input capture input/output compare
output/PWM output pin
Input capture/out
compare match B2
TIOCB2
I/O
TGR2B input capture input/output compare
output/PWM output pin
0
1
2
Rev. 5.00 Mar 28, 2005 page 528 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Channel
Name
Symbol
I/O
Function
3
Input capture/out
compare match A3
TIOCA3
I/O
TGR3A input capture input/output compare
output/PWM output pin
Input capture/out
compare match B3
TIOCB3
I/O
TGR3B input capture input/output compare
output/PWM output pin
Input capture/out
compare match C3
TIOCC3
I/O
TGR3C input capture input/output compare
output/PWM output pin
Input capture/out
compare match D3
TIOCD3
I/O
TGR3D input capture input/output compare
output/PWM output pin
Input capture/out
compare match A4
TIOCA4
I/O
TGR4A input capture input/output compare
output/PWM output pin
Input capture/out
compare match B4
TIOCB4
I/O
TGR4B input capture input/output compare
output/PWM output pin
Input capture/out
compare match A5
TIOCA5
I/O
TGR5A input capture input/output compare
output/PWM output pin
Input capture/out
compare match B5
TIOCB5
I/O
TGR5B input capture input/output compare
output/PWM output pin
4
5
Rev. 5.00 Mar 28, 2005 page 529 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.1.4
Register Configuration
Table 11.3 summarizes the TPU registers.
Table 11.3 TPU Registers
Address*1
Channel Name
Abbreviation
R/W
Initial Value
0
Timer control register 0
TCR0
R/W
H'00
H'FF10
Timer mode register 0
TMDR0
R/W
H'C0
H'FF11
Timer I/O control register 0H
TIOR0H
R/W
H'00
H'FF12
Timer I/O control register 0L
TIOR0L
R/W
H'00
H'FF13
Timer interrupt enable register 0
TIER0
R/W
H'FF14
Timer status register 0
TSR0
H'40
2
*
R/(W)
H'C0
Timer counter 0
TCNT0
R/W
H'0000
H'FF16
Timer general register 0A
TGR0A
R/W
H'FFFF
H'FF18
Timer general register 0B
TGR0B
R/W
H'FFFF
H'FF1A
Timer general register 0C
TGR0C
R/W
H'FFFF
H'FF1C
Timer general register 0D
TGR0D
R/W
H'FFFF
H'FF1E
1
2
H'FF15
Timer control register 1
TCR1
R/W
H'00
H'FF20
Timer mode register 1
TMDR1
R/W
H'C0
H'FF21
Timer I/O control register 1
TIOR1
R/W
H'00
H'FF22
Timer interrupt enable register 1
TIER1
R/W
H'FF24
Timer status register 1
TSR1
H'40
2
*
R/(W)
H'C0
Timer counter 1
TCNT1
R/W
H'0000
H'FF26
Timer general register 1A
TGR1A
R/W
H'FFFF
H'FF28
Timer general register 1B
TGR1B
R/W
H'FFFF
H'FF2A
Timer control register 2
TCR2
R/W
H'00
H'FF30
Timer mode register 2
TMDR2
R/W
H'C0
H'FF31
Timer I/O control register 2
TIOR2
R/W
H'00
H'FF32
H'FF25
Timer interrupt enable register 2
TIER2
R/W
H'40
H'FF34
Timer status register 2
TSR2
R/(W) *2 H'C0
H'FF35
Timer counter 2
TCNT2
R/W
H'0000
H'FF36
Timer general register 2A
TGR2A
R/W
H'FFFF
H'FF38
Timer general register 2B
TGR2B
R/W
H'FFFF
H'FF3A
Rev. 5.00 Mar 28, 2005 page 530 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Channel Name
Abbreviation
R/W
Initial Value
Address*1
3
Timer control register 3
TCR3
R/W
H'00
H'FE80
Timer mode register 3
TMDR3
R/W
H'C0
H'FE81
Timer I/O control register 3H
TIOR3H
R/W
H'00
H'FE82
Timer I/O control register 3L
TIOR3L
R/W
H'00
H'FE83
Timer interrupt enable register 3
TIER3
R/W
H'FE84
Timer status register 3
TSR3
H'40
2
*
R/(W)
H'C0
H'FE85
Timer counter 3
TCNT3
R/W
H'0000
H'FE86
Timer general register 3A
TGR3A
R/W
H'FFFF
H'FE88
Timer general register 3B
TGR3B
R/W
H'FFFF
H'FE8A
Timer general register 3C
TGR3C
R/W
H'FFFF
H'FE8C
Timer general register 3D
TGR3D
R/W
H'FFFF
H'FE8E
Timer control register 4
TCR4
R/W
H'00
H'FE90
4
5
All
Timer mode register 4
TMDR4
R/W
H'C0
H'FE91
Timer I/O control register 4
TIOR4
R/W
H'00
H'FE92
Timer interrupt enable register 4
TIER4
R/W
H'40
H'FE94
H'C0
H'FE95
*2
Timer status register 4
TSR4
R/(W)
Timer counter 4
TCNT4
R/W
H'0000
H'FE96
Timer general register 4A
TGR4A
R/W
H'FFFF
H'FE98
Timer general register 4B
TGR4B
R/W
H'FFFF
H'FE9A
Timer control register 5
TCR5
R/W
H'00
H'FEA0
Timer mode register 5
TMDR5
R/W
H'C0
H'FEA1
Timer I/O control register 5
TIOR5
R/W
H'00
H'FEA2
Timer interrupt enable register 5
TIER5
R/W
H'FEA4
Timer status register 5
TSR5
H'40
2
*
R/(W)
H'C0
H'FEA5
Timer counter 5
TCNT5
R/W
H'0000
H'FEA6
Timer general register 5A
TGR5A
R/W
H'FFFF
H'FEA8
Timer general register 5B
TGR5B
R/W
H'FFFF
H'FEAA
Timer start register
TSTR
R/W
H'00
H'FEB0
Timer synchro register
TSYR
R/W
H'00
H'FEB1
Module stop control register A
MSTPCRA
R/W
H'3F
H'FDE8
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
Rev. 5.00 Mar 28, 2005 page 531 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2
Register Descriptions
11.2.1
Timer Control Register (TCR)
Channel 0: TCR0
Channel 3: TCR3
Bit
:
7
6
5
4
3
2
1
0
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value :
R/W
:
Channel 1: TCR1
Channel 2: TCR2
Channel 4: TCR4
Channel 5: TCR5
Bit
:
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial value :
0
0
0
0
0
0
0
0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR
registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset, and
in hardware standby mode.
TCR register settings should be made only when TCNT operation is stopped.
Rev. 5.00 Mar 28, 2005 page 532 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bits 7, 6, and 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the
TCNT counter clearing source.
Bit 7
Bit 6
Bit 5
Channel
CCLR2
CCLR1
CCLR0
Description
0, 3
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *1
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input
2
capture *
0
TCNT cleared by TGRD compare match/input
capture *2
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *1
1
1
0
1
Bit 7
Channel
Reserved
1, 2, 4, 5
0
*3
(Initial value)
Bit 6
Bit 5
CCLR1
CCLR0
Description
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *1
1
(Initial value)
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Rev. 5.00 Mar 28, 2005 page 533 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both
edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is
ignored and the phase counting mode setting has priority.
Bit 4
Bit 3
CKEG1
CKEG0
Description
0
0
Count at rising edge
1
Count at falling edge
—
Count at both edges
1
(Initial value)
Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected.
(The clock is counted at the falling edge when φ/1 is selected.)
Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter
clock. The clock source can be selected independently for each channel. Table 11.4 shows the
clock sources that can be set for each channel.
Table 11.4 TPU Clock Sources
Internal Clock
Channel
φ/1
φ/4
φ/16 φ/64 φ/256 φ/1024
0
1
2
3
4
5
Legend:
:
Setting
Blank: No setting
Rev. 5.00 Mar 28, 2005 page 534 of 1422
REJ09B0234-0500
φ/4096
Overflow/
Underflow
External Clock
on Another
TCLKA TCLKB TCLKC TCLKD Channel
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 2
Bit 1
Bit 0
Channel
TPSC2
TPSC1
TPSC0
Description
0
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
1
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
External clock: counts on TCLKC pin input
1
External clock: counts on TCLKD pin input
1
0
1
(Initial value)
Bit 2
Bit 1
Bit 0
Channel
TPSC2
TPSC1
TPSC0
Description
1
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
Internal clock: counts on φ/256
1
Counts on TCNT2 overflow/underflow
1
1
0
1
(Initial value)
Note: This setting is ignored when channel 1 is in phase counting mode.
Bit 2
Bit 1
Bit 0
Channel
TPSC2
TPSC1
TPSC0
2
0
0
1
1
0
1
Description
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
External clock: counts on TCLKC pin input
1
Internal clock: counts on φ/1024
(Initial value)
Note: This setting is ignored when channel 2 is in phase counting mode.
Rev. 5.00 Mar 28, 2005 page 535 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 2
Bit 1
Bit 0
Channel
TPSC2
TPSC1
TPSC0
Description
3
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
Internal clock: counts on φ/1024
0
Internal clock: counts on φ/256
1
Internal clock: counts on φ/4096
1
1
0
1
(Initial value)
Bit 2
Bit 1
Bit 0
Channel
TPSC2
TPSC1
TPSC0
Description
4
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
0
Internal clock: counts on φ/1024
1
Counts on TCNT5 overflow/underflow
1
1
0
1
(Initial value)
Note: This setting is ignored when channel 4 is in phase counting mode.
Bit 2
Bit 1
Bit 0
Channel
TPSC2
TPSC1
TPSC0
5
0
0
1
1
0
1
Description
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
(Initial value)
1
External clock: counts on TCLKC pin input
0
Internal clock: counts on φ/256
1
External clock: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase counting mode.
Rev. 5.00 Mar 28, 2005 page 536 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2.2
Timer Mode Register (TMDR)
Channel 0: TMDR0
Channel 3: TMDR3
Bit
:
7
6
5
4
3
2
1
0
—
—
BFB
BFA
MD3
MD2
MD1
MD0
Initial value :
1
1
0
0
0
0
0
0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
—
—
—
—
MD3
MD2
MD1
MD0
:
Channel 1: TMDR1
Channel 2: TMDR2
Channel 4: TMDR4
Channel 5: TMDR5
Bit
:
Initial value :
1
1
0
0
0
0
0
0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
:
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers
are initialized to H'C0 by a reset, and in hardware standby mode.
TMDR register settings should be made only when TCNT operation is stopped.
Bits 7 and 6—Reserved: These bits are always read as 1 and cannot be modified.
Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and
cannot be modified.
Rev. 5.00 Mar 28, 2005 page 537 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 5
BFB
Description
0
TGRB operates normally
1
TGRB and TGRD used together for buffer operation
(Initial value)
Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and
cannot be modified.
Bit 4
BFA
Description
0
TGRA operates normally
1
TGRA and TGRC used together for buffer operation
(Initial value)
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Bit 3
Bit 2
Bit 1
Bit 0
MD3*1
MD2*2
MD1
MD0
Description
0
0
0
0
Normal operation
1
Reserved
0
PWM mode 1
1
PWM mode 2
0
Phase counting mode 1
1
Phase counting mode 2
0
Phase counting mode 3
1
Phase counting mode 4
*
—
1
1
0
1
1
*
*
(Initial value)
*: Don’t care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
Rev. 5.00 Mar 28, 2005 page 538 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2.3
Timer I/O Control Register (TIOR)
Channel 0: TIOR0H
Channel 1: TIOR1
Channel 2: TIOR2
Channel 3: TIOR3H
Channel 4: TIOR4
Channel 5: TIOR5
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
Channel 0: TIOR0L
Channel 3: TIOR3L
Bit
:
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR
registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR
registers are initialized to H'00 by a reset, and in hardware standby mode.
Care is required since TIOR is affected by the TMDR setting. The initial output specified by
TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in
PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.
Rev. 5.00 Mar 28, 2005 page 539 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0)
I/O Control D3 to D0 (IOD3 to IOD0):
Bits IOB3 to IOB0 specify the function of TGRB.
Bits IOD3 to IOD0 specify the function of TGRD.
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOB3 IOB2 IOB1 IOB0 Description
0
0
0
0
0
1
1
0
TGR0B
is output
compare
register
Output disabled
Initial output is 0
output
1
1
0
1
0
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
Note:
1
*
*
*
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR0B
is input
capture
register
Capture input
source is
TIOCB0 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
Input capture at TCNT1
1
source is channel count- up/count-down*
1/count clock
*: Don’t care
1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the TCNT1
count clock, this setting is invalid and input capture is not generated.
Rev. 5.00 Mar 28, 2005 page 540 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOD3 IOD2 IOD1 IOD0 Description
0
0
0
0
0
1
1
0
Output disabled
TGR0D
is output Initial output is 0
compare output
2
register*
1
1
0
1
0
Output disabled
Initial output is 1
output
1
1
0
0
0
1
1
1
*
*
*
1 output at compare match
Toggle output at compare
match
1
0
(Initial value)
0 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR0D
Capture input
is input
source is
capture
TIOCD0 pin
register*2
Capture input
source is channel
1/count clock
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1
1
count-up/count-down*
*: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the TCNT1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 5.00 Mar 28, 2005 page 541 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOB3 IOB2 IOB1 IOB0 Description
1
0
0
0
0
1
1
0
TGR1B
is output
compare
register
Output disabled
1
1
0
1
Toggle output at compare
match
0
Output disabled
1
Initial output is 1
output
0
1
1
0
0
0
1
1
1
*
*
*
(Initial value)
Initial output is 0 0 output at compare match
output
1 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR1B
is input
capture
register
Capture input
source is
TIOCB1 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
Input capture at generation of
source is TGR0C TGR0C compare match/input
compare match/ capture
input capture
*: Don’t care
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOB3 IOB2 IOB1 IOB0 Description
2
0
0
0
0
1
1
0
TGR2B
is output
compare
register
Output disabled
1
1
0
1
Toggle output at compare
match
0
Output disabled
1
Initial output is 1
output
0
1
1
*
0
0
1
1
*
(Initial value)
Initial output is 0 0 output at compare match
output
1 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR2B
is input
capture
register
Capture input
source is
TIOCB2 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
*: Don’t care
Rev. 5.00 Mar 28, 2005 page 542 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOB3 IOB2 IOB1 IOB0 Description
3
0
0
0
0
1
1
0
TGR3B
is output
compare
register
Output disabled
Initial output is 0
output
1
1
0
1
0
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
Note:
1
*
*
*
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR3B
is input
capture
register
Capture input
source is
TIOCB3 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
Input capture at TCNT4
source is channel count-up/count-down*1
4/count clock
*: Don’t care
1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4
count clock, this setting is invalid and input capture is not generated.
Rev. 5.00 Mar 28, 2005 page 543 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOD3 IOD2 IOD1 IOD0 Description
3
0
0
0
0
1
1
0
Output disabled
TGR3D
is output Initial output is 0
compare output
2
register*
1
1
0
1
0
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
1
*
*
*
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR3D
Capture input
is input
source is
capture
TIOCD3 pin
register*2
Capture input
source is channel
4/count clock
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4
1
count-up/count-down*
*: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 5.00 Mar 28, 2005 page 544 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOB3 IOB2 IOB1 IOB0 Description
4
0
0
0
0
1
1
0
TGR4B
is output
compare
register
Output disabled
Initial output is 0
output
1
1
0
1
0
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
1
*
*
*
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR4B
is input
capture
register
Capture input
source is
TIOCB4 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
Input capture at generation of
source is TGR3C TGR3C compare match/
compare match/ input capture
input capture
*: Don’t care
Bit 7 Bit 6 Bit 5 Bit 4
Channel
IOB3 IOB2 IOB1 IOB0 Description
5
0
0
0
0
1
1
0
TGR5B
is output
compare
register
Output disabled
Initial output is 0
output
1
1
0
1
*
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
*
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR5B
is input
capture
register
Capture input
source is
TIOCB5 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
*: Don’t care
Rev. 5.00 Mar 28, 2005 page 545 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0)
I/O Control C3 to C0 (IOC3 to IOC0):
IOA3 to IOA0 specify the function of TGRA.
IOC3 to IOC0 specify the function of TGRC.
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOA3 IOA2 IOA1 IOA0 Description
0
0
0
0
0
1
1
0
TGR0A
is output
compare
register
Output disabled
Initial output is 0
output
1
1
0
1
0
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
1
*
*
*
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR0A
is input
capture
register
Capture input
source is
TIOCA0 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
Input capture at TCNT1
source is channel count-up/count-down
1/ count clock
*: Don’t care
Rev. 5.00 Mar 28, 2005 page 546 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOC3 IOC2 IOC1 IOC0 Description
0
0
0
0
0
1
1
0
Output disabled
TGR0C
is output Initial output is 0
compare output
1
register*
0
1
0
Output disabled
1
Initial output is 1
output
0
1
1
0
0
0
1
1
Note:
1
*
*
*
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR0C
Capture input
is input
source is
capture
TIOCC0 pin
register*1
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
Input capture at TCNT1
source is channel count-up/count-down
1/count clock
*: Don’t care
1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 5.00 Mar 28, 2005 page 547 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOA3 IOA2 IOA1 IOA0 Description
1
0
0
0
0
1
0
1
TGR1A
is output
compare
register
Output disabled
Initial output is 0
output
0
0
Output disabled
1
1
0
Initial output is 1
output
1
1
0
0
0
1
*
*
*
1
1
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR1A
is input
capture
register
Capture input
source is
TIOCA1 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
Input capture at generation of
source is TGR0A channel 0/TGR0A compare
compare match/ match/input capture
input capture
*: Don’t care
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOA3 IOA2 IOA1 IOA0 Description
2
0
0
0
0
1
1
0
TGR2A
is output
compare
register
Output disabled
Initial output is 0
output
1
1
0
1
*
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
*
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR2A
is input
capture
register
Capture input
source is
TIOCA2 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
*: Don’t care
Rev. 5.00 Mar 28, 2005 page 548 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOA3 IOA2 IOA1 IOA0 Description
3
0
0
0
0
1
1
0
TGR3A
is output
compare
register
Output disabled
Initial output is 0
output
1
1
0
1
0
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
1
*
*
*
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR3A
is input
capture
register
Capture input
source is
TIOCA3 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
Input capture at TCNT4
source is channel count-up/count-down
4/count clock
*: Don’t care
Rev. 5.00 Mar 28, 2005 page 549 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOC3 IOC2 IOC1 IOC0 Description
3
0
0
0
0
1
1
0
TGR3C
Output disabled
is output Initial output is 0
compare output
register*1
1
1
0
1
0
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
Note:
1
*
*
*
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR3C
Capture input
source is
is input
capture
TIOCC3 pin
register*1
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
Input capture at TCNT4
source is channel count-up/count-down
4/count clock
*: Don’t care
1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 5.00 Mar 28, 2005 page 550 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOA3 IOA2 IOA1 IOA0 Description
4
0
0
0
0
1
1
0
TGR4A
is output
compare
register
Output disabled
Initial output is 0
output
1
1
0
1
0
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
1
*
*
*
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR4A
is input
capture
register
Capture input
source is
TIOCA4 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input
Input capture at generation of
source is TGR3A TGR3A compare match/input
compare match/ capture
input capture
*: Don’t care
Bit 3 Bit 2 Bit 1 Bit 0
Channel
IOA3 IOA2 IOA1 IOA0 Description
5
0
0
0
0
1
1
0
TGR5A
is output
compare
register
Output disabled
Initial output is 0
output
1
1
0
1
*
0
0
Output disabled
1
Initial output is 1
output
0
0
1
1
*
0 output at compare match
1 output at compare match
Toggle output at compare
match
1
1
(Initial value)
0 output at compare match
1 output at compare match
Toggle output at compare
match
TGR5A
is input
capture
register
Capture input
source is
TIOCA5 pin
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
*: Don’t care
Rev. 5.00 Mar 28, 2005 page 551 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2.4
Timer Interrupt Enable Register (TIER)
Channel 0: TIER0
Channel 3: TIER3
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
TTGE
—
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
0
1
0
0
0
0
0
0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
TTGE
—
TCIEU
TCIEV
—
—
TGIEB
TGIEA
0
1
0
0
0
0
0
0
R/W
—
R/W
R/W
—
—
R/W
R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has six TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset, and in hardware standby mode.
Rev. 5.00 Mar 28, 2005 page 552 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D
conversion start requests by TGRA input capture/compare match.
Bit 7
TTGE
Description
0
A/D conversion start request generation disabled
1
A/D conversion start request generation enabled
(Initial value)
Bit 6—Reserved: This bit is always read as 1 and cannot be modified.
Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by
the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5
TCIEU
Description
0
Interrupt requests (TCIU) by TCFU disabled
1
Interrupt requests (TCIU) by TCFU enabled
(Initial value)
Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by
the TCFV flag when the TCFV flag in TSR is set to 1.
Bit 4
TCIEV
Description
0
Interrupt requests (TCIV) by TCFV disabled
1
Interrupt requests (TCIV) by TCFV enabled
(Initial value)
Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3
TGIED
Description
0
Interrupt requests (TGID) by TGFD bit disabled
1
Interrupt requests (TGID) by TGFD bit enabled
(Initial value)
Rev. 5.00 Mar 28, 2005 page 553 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2
TGIEC
Description
0
Interrupt requests (TGIC) by TGFC bit disabled
1
Interrupt requests (TGIC) by TGFC bit enabled
(Initial value)
Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
Bit 1
TGIEB
Description
0
Interrupt requests (TGIB) by TGFB bit disabled
1
Interrupt requests (TGIB) by TGFB bit enabled
(Initial value)
Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
Bit 0
TGIEA
Description
0
Interrupt requests (TGIA) by TGFA bit disabled
1
Interrupt requests (TGIA) by TGFA bit enabled
Rev. 5.00 Mar 28, 2005 page 554 of 1422
REJ09B0234-0500
(Initial value)
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2.5
Timer Status Register (TSR)
Channel 0: TSR0
Channel 3: TSR3
Bit
:
7
6
5
4
3
2
1
0
—
—
—
TCFV
TGFD
TGFC
TGFB
TGFA
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
Initial value :
1
1
0
R/W
—
—
—
:
Note: * Only 0 can be written, for flag clearing.
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
TCFD
—
TCFU
TCFV
—
—
TGFB
TGFA
1
1
0
0
0
0
0
0
—
R/(W)*
R/(W)*
—
R/(W)*
R/(W)*
R
—
Note: * Only 0 can be written, for flag clearing.
The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR
registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in
hardware standby mode.
Rev. 5.00 Mar 28, 2005 page 555 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT
counts in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.
Bit 7
TCFD
Description
0
TCNT counts down
1
TCNT counts up
(Initial value)
Bit 6—Reserved: This bit is always read as 1 and cannot be modified.
Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred
when channels 1, 2, 4, and 5 are set to phase counting mode.
In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 5
TCFU
Description
0
[Clearing condition]
(Initial value)
When 0 is written to TCFU after reading TCFU = 1
1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred.
Bit 4
TCFV
Description
0
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
Rev. 5.00 Mar 28, 2005 page 556 of 1422
REJ09B0234-0500
(Initial value)
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the
occurrence of TGRD input capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Bit 3
TGFD
Description
0
[Clearing conditions]
1
(Initial value)
•
When DTC* is activated by TGID interrupt while DISEL bit of MRB in DTC* is 0
•
When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
•
When TCNT = TGRD while TGRD is functioning as output compare register
•
When TCNT value is transferred to TGRD by input capture signal while TGRD is
functioning as input capture register
Note: * This function is not available in the H8S/2695.
Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the
occurrence of TGRC input capture or compare match in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Bit 2
TGFC
Description
0
[Clearing conditions]
1
(Initial value)
•
When DTC* is activated by TGIC interrupt while DISEL bit of MRB in DTC* is 0
•
When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
•
When TCNT = TGRC while TGRC is functioning as output compare register
•
When TCNT value is transferred to TGRC by input capture signal while TGRC is
functioning as input capture register
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 557 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the
occurrence of TGRB input capture or compare match.
Bit 1
TGFB
Description
0
[Clearing conditions]
1
(Initial value)
•
When DTC* is activated by TGIB interrupt while DISEL bit of MRB in DTC* is 0
•
When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
•
When TCNT = TGRB while TGRB is functioning as output compare register
•
When TCNT value is transferred to TGRB by input capture signal while TGRB is
functioning as input capture register
Note: * This function is not available in the H8S/2695.
Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the
occurrence of TGRA input capture or compare match.
Bit 0
TGFA
Description
0
[Clearing conditions]
•
•
(Initial value)
When DTC* is activated by TGIA interrupt while DISEL bit of MRB in DTC* is 0
When DMAC* is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*
is 1
•
1
When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
•
When TCNT = TGRA while TGRA is functioning as output compare register
•
When TCNT value is transferred to TGRA by input capture signal while TGRA is
functioning as input capture register
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 558 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2.6
Timer Counter (TCNT)
Channel 0: TCNT0 (up-counter)
Channel 1: TCNT1 (up/down-counter*)
Channel 2: TCNT2 (up/down-counter*)
Channel 3: TCNT3 (up-counter)
Channel 4: TCNT4 (up/down-counter*)
Channel 5: TCNT5 (up/down-counter*)
Bit
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: * These counters can be used as up/down-counters only in phase counting mode or when
counting overflow/underflow on another channel. In other cases they function as upcounters.
The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel.
The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
Rev. 5.00 Mar 28, 2005 page 559 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2.7
Bit
Timer General Register (TGR)
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value :
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The TGR registers are 16-bit registers with a dual function as output compare and input capture
registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels
1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as
buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and in hardware standby
mode.
The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
Note: * TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.
Rev. 5.00 Mar 28, 2005 page 560 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2.8
Bit
Timer Start Register (TSTR)
:
7
6
5
4
3
2
1
0
—
—
CST5
CST4
CST3
CST2
CST1
CST0
Initial value :
0
0
0
0
0
0
0
0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
:
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5.
TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating
mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bits 7 and 6—Reserved: Should always be written with 0.
Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for
TCNT.
Bit n
CSTn
Description
0
TCNTn count operation is stopped
1
TCNTn performs count operation
(Initial value)
n = 5 to 0
Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the
counter stops but the TIOC pin output compare output level is retained. If TIOR is written to
when the CST bit is cleared to 0, the pin output level will be changed to the set initial output
value.
Rev. 5.00 Mar 28, 2005 page 561 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2.9
Bit
Timer Synchro Register (TSYR)
:
7
6
5
4
3
2
1
0
—
—
SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
Initial value :
0
0
0
0
0
0
0
0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
:
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channels 0 to 5 TCNT counters. A channel performs synchronous operation
when the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 and 6—Reserved: Should always be written with 0.
Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels*1, and
synchronous clearing through counter clearing on another channel*2 are possible.
Bit n
SYNCn
Description
0
TCNTn operates independently (TCNT presetting/clearing is unrelated to
other channels)
(Initial value)
1
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is possible
n = 5 to 0
Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source
must also be set by means of bits CCLR2 to CCLR0 in TCR.
Rev. 5.00 Mar 28, 2005 page 562 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.2.10 Module Stop Control Register A (MSTPCRA)
Bit
:
7
6
5
4
3
2
1
0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
R/W
:
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPA5 bit in MSTPCRA is set to 1, TPU operation stops at the end of the bus cycle
and a transition is made to module stop mode. Registers cannot be read or written to in module
stop mode. For details, see section 24.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset and in software standby mode.
Bit 5—Module Stop (MSTPA5): Specifies the TPU module stop mode.
Bit 5
MSTPA5
Description
0
TPU module stop mode cleared
1
TPU module stop mode set
(Initial value)
Rev. 5.00 Mar 28, 2005 page 563 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.3
Interface to Bus Master
11.3.1
16-Bit Registers
TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these
registers can be read and written to in 16-bit units.
These registers cannot be read or written to in 8-bit units; 16-bit access must always be used.
An example of 16-bit register access operation is shown in figure 11.2.
Internal data bus
H
Bus
master
L
Module
data bus
Bus interface
TCNTH
TCNTL
Figure 11.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)]
11.3.2
8-Bit Registers
Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these
registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit
units.
Rev. 5.00 Mar 28, 2005 page 564 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of 8-bit register access operation are shown in figures 11.3, 11.4, and 11.5.
Internal data bus
H
Bus
master
L
Module
data bus
Bus interface
TCR
Figure 11.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
Internal data bus
H
Bus
master
L
Module
data bus
Bus interface
TMDR
Figure 11.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
Internal data bus
H
Bus
master
L
Module
data bus
Bus interface
TCR
TMDR
Figure 11.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]
Rev. 5.00 Mar 28, 2005 page 565 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.4
Operation
11.4.1
Overview
Operation in each mode is outlined below.
Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting,
and is also capable of free-running operation, synchronous counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Synchronous Operation: When synchronous operation is designated for a channel, TCNT for
that channel performs synchronous presetting. That is, when TCNT for a channel designated for
synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at
the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer
synchronization bits in TSYR for channels designated for synchronous operation.
Buffer Operation:
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the relevant channel is
transferred to TGR.
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transfer to TGR and the value previously
held in TGR is transferred to the buffer register.
Cascaded Operation: The channel 1 counter (TCNT1), channel 2 counter (TCNT2), channel 4
counter (TCNT4), and channel 5 counter (TCNT5) can be connected together to operate as a 32bit counter.
PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of
TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the
setting of each TGR register.
Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the
phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. When
phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT
performs up- or down-counting.
This can be used for two-phase encoder pulse input.
Rev. 5.00 Mar 28, 2005 page 566 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.2
Basic Functions
Counter Operation
When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding
channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.
Example of count operation setting procedure: Figure 11.6 shows an example of the count
operation setting procedure.
[1] Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
Operation selection
Select counter clock
[1]
Periodic counter
Select counter clearing source
[2]
Select output compare register
[3]
Set period
[4]
Start count operation
[5]
<Periodic counter>
[2] For periodic counter
operation, select the
TGR to be used as
the TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
Free-running counter
[3] Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
[4] Set the periodic
counter cycle in the
TGR selected in [2].
Start count operation
<Free-running counter>
[5]
[5] Set the CST bit in
TSTR to 1 to start
the counter
operation.
Figure 11.6 Example of Counter Operation Setting Procedure
Rev. 5.00 Mar 28, 2005 page 567 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Free-running count operation and periodic count operation: Immediately after a reset, the
TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR
is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter.
When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of
the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After
overflow, TCNT starts counting up again from H'0000.
Figure 11.7 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
CST bit
TCFV
Figure 11.7 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs periodic count operation. The TGR register for setting the period is designated
as an output compare register, and counter clearing by compare match is selected by means of bits
CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as
periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches
the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt.
After a compare match, TCNT starts counting up again from H'0000.
Rev. 5.00 Mar 28, 2005 page 568 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Figure 11.8 illustrates periodic counter operation.
TCNT value
TGR
Counter cleared by TGR
compare match
H'0000
Time
CST bit
Flag cleared by software or
DTC*/DMAC* activation
TGF
Note: * DMAC and DTC functions are not available in the H8S/2695.
Figure 11.8 Periodic Counter Operation
Rev. 5.00 Mar 28, 2005 page 569 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Waveform Output by Compare Match
The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare
match.
Example of setting procedure for waveform output by compare match: Figure 11.9 shows an
example of the setting procedure for waveform output by compare match
Output selection
Select waveform output mode
[1]
[1] Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TIOC pin until the
first compare match occurs.
[2] Set the timing for compare match generation in
TGR.
Set output timing
[2]
Start count operation
[3]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
<Waveform output>
Figure 11.9 Example of Setting Procedure for Waveform Output by Compare Match
Rev. 5.00 Mar 28, 2005 page 570 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of waveform output operation: Figure 11.10 shows an example of 0 output/1 output.
In this example TCNT has been designated as a free-running counter, and settings have been made
so that 1 is output by compare match A, and 0 is output by compare match B. When the set level
and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
TGRA
TGRB
Time
H'0000
No change
No change
1 output
TIOCA
TIOCB
No change
No change
0 output
Figure 11.10 Example of 0 Output/1 Output Operation
Figure 11.11 shows an example of toggle output.
In this example TCNT has been designated as a periodic counter (with counter clearing performed
by compare match B), and settings have been made so that output is toggled by both compare
match A and compare match B.
TCNT value
Counter cleared by TGRB compare match
H'FFFF
TGRB
TGRA
Time
H'0000
Toggle output
TIOCB
Toggle output
TIOCA
Figure 11.11 Example of Toggle Output Operation
Rev. 5.00 Mar 28, 2005 page 571 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Input Capture Function
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge.
Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3,
and 4, it is also possible to specify another channel’s counter input clock or compare match signal
as the input capture source.
Note: When another channel’s counter input clock is used as the input capture input for channels
0 and 3, φ/1 should not be selected as the counter input clock used for input capture input.
Input capture will not be generated if φ/1 is selected.
Example of input capture operation setting procedure: Figure 11.12 shows an example of the
input capture operation setting procedure.
[1] Designate TGR as an input capture register by
means of TIOR, and select rising edge, falling
edge, or both edges as the input capture source
and input signal edge.
Input selection
Select input capture input
[1]
Start count
[2]
[2] Set the CST bit in TSTR to 1 to start the count
operation.
<Input capture operation>
Figure 11.12 Example of Input Capture Operation Setting Procedure
Rev. 5.00 Mar 28, 2005 page 572 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Example of input capture operation: Figure 11.13 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input capture
input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter
clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB
input (falling edge)
TCNT value
H'0180
H'0160
H'0010
H'0005
Time
H'0000
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB
TGRB
H'0180
Figure 11.13 Example of Input Capture Operation
11.4.3
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten
simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared
simultaneously by making the appropriate setting in TCR (synchronous clearing).
Synchronous operation enables TGR to be incremented with respect to a single time base.
Channels 0 to 5 can all be designated for synchronous operation.
Rev. 5.00 Mar 28, 2005 page 573 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation Setting Procedure: Figure 11.14 shows an example of the
synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous presetting
Set TCNT
Synchronous clearing
[2]
Clearing
source generation
channel?
No
Yes
<Synchronous presetting>
Select counter
clearing source
[3]
Set synchronous
counter clearing
[4]
Start count
[5]
Start count
[5]
<Counter clearing>
<Synchronous clearing>
[1]
Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
operation.
[2]
When the TCNT counter of any of the channels designated for synchronous operation is
written to, the same value is simultaneously written to the other TCNT counters.
[3]
Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare,
etc.
[4]
Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing
source.
[5]
Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 11.14 Example of Synchronous Operation Setting Procedure
Rev. 5.00 Mar 28, 2005 page 574 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation: Figure 11.15 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous
clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this
time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed
for channels 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle.
For details of PWM modes, see section 11.4.6, PWM Modes.
Synchronous clearing by TGR0B compare match
TCNT0 to TCNT2 values
TGR0B
TGR1B
TGR0A
TGR2B
TGR1A
TGR2A
Time
H'0000
TIOC0A
TIOC1A
TIOC2A
Figure 11.15 Example of Synchronous Operation
Rev. 5.00 Mar 28, 2005 page 575 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.4
Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 11.5 shows the register combinations used in buffer operation.
Table 11.5 Register Combinations in Buffer Operation
Channel
Timer General Register
0
TGR0A
TGR0C
TGR0B
TGR0D
TGR3A
TGR3C
TGR3B
TGR3D
3
Buffer Register
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 11.16.
Compare match signal
Buffer register
Timer general
register
Comparator
Figure 11.16 Compare Match Buffer Operation
Rev. 5.00 Mar 28, 2005 page 576 of 1422
REJ09B0234-0500
TCNT
Section 11 16-Bit Timer Pulse Unit (TPU)
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 11.17.
Input capture
signal
Timer general
register
Buffer register
TCNT
Figure 11.17 Input Capture Buffer Operation
Example of Buffer Operation Setting Procedure
Figure 11.18 shows an example of the buffer operation setting procedure.
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
Buffer operation
[1]
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
Set buffer operation
[2]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
Start count
[3]
Select TGR function
<Buffer operation>
Figure 11.18 Example of Buffer Operation Setting Procedure
Rev. 5.00 Mar 28, 2005 page 577 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of Buffer Operation
• When TGR is an output compare register
Figure 11.19 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details of PWM modes, see section 11.4.6, PWM Modes.
TCNT value
TGR0B
H'0520
H'0450
H'0200
TGR0A
Time
H'0000
TGR0C H'0200
H'0450
H'0520
Transfer
TGR0A
H'0200
H'0450
TIOCA
Figure 11.19 Example of Buffer Operation (1)
Rev. 5.00 Mar 28, 2005 page 578 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
• When TGR is an input capture register
Figure 11.20 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'0F07
H'09FB
H'0532
H'0000
Time
TIOCA
TGRA
TGRC
H'0532
H'0F07
H'09FB
H'0532
H'0F07
Figure 11.20 Example of Buffer Operation (2)
Rev. 5.00 Mar 28, 2005 page 579 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.5
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow
of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 11.6 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channels 1 or 4, the counter clock setting is invalid
and the counter operates independently in phase counting mode.
Table 11.6 Cascaded Combinations
Combination
Upper 16 Bits
Lower 16 Bits
Channels 1 and 2
TCNT1
TCNT2
Channels 4 and 5
TCNT4
TCNT5
Example of Cascaded Operation Setting Procedure: Figure 11.21 shows an example of the
setting procedure for cascaded operation.
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'111 to select TCNT2
(TCNT5) overflow/underflow counting.
Cascaded operation
Set cascading
[1]
Start count
[2]
[2] Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
<Cascaded operation>
Figure 11.21 Cascaded Operation Setting Procedure
Rev. 5.00 Mar 28, 2005 page 580 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of Cascaded Operation: Figure 11.22 illustrates the operation when counting upon
TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated
as input capture registers, and TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
TCNT1
clock
TCNT1
H'03A1
H'03A2
TCNT2
clock
TCNT2
H'FFFF
H'0000
H'0001
TIOCA1,
TIOCA2
TGR1A
H'03A2
TGR2A
H'0000
Figure 11.22 Example of Cascaded Operation (1)
Figure 11.23 illustrates the operation when counting upon TCNT2 overflow/underflow has been
set for TCNT1, and phase counting mode has been designated for channel 2.
TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.
TCLKC
TCLKD
TCNT2
TCNT1
FFFD
FFFE
0000
FFFF
0000
0001
0002
0001
0001
0000
FFFF
0000
Figure 11.23 Example of Cascaded Operation (2)
Rev. 5.00 Mar 28, 2005 page 581 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.6
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be
selected as the output level in response to compare match of each TGR.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is
output from the TIOCA and TIOCC pins at compare matches A and C, and the output
specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B
and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired
TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output specified in TIOR is performed by means of compare matches. Upon counter
clearing by a synchronization register compare match, the output value of each pin is the initial
value set in TIOR. If the set values of the cycle and duty registers are identical, the output
value does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 11.7.
Rev. 5.00 Mar 28, 2005 page 582 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.7 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
PWM Mode 1
PWM Mode 2
0
TGR0A
TIOCA0
TIOCA0
TGR0B
TGR0C
TIOCB0
TIOCC0
TGR0D
1
TGR1A
TIOCD0
TIOCA1
TGR1B
2
TGR2A
TGR3A
TIOCA2
TIOCA3
TGR4A
TIOCC3
TGR5A
TGR5B
TIOCC3
TIOCD3
TIOCA4
TGR4B
5
TIOCA3
TIOCB3
TGR3D
4
TIOCA2
TIOCB2
TGR3B
TGR3C
TIOCA1
TIOCB1
TGR2B
3
TIOCC0
TIOCA4
TIOCB4
TIOCA5
TIOCA5
TIOCB5
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Rev. 5.00 Mar 28, 2005 page 583 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Example of PWM Mode Setting Procedure: Figure 11.24 shows an example of the PWM mode
setting procedure.
PWM mode
Select counter clock
[1]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
[2] Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Select counter clearing source
Select waveform output level
Set TGR
[2]
[3]
[4]
[3] Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
[4] Set the cycle in the TGR selected in [2], and set
the duty in the other the TGR.
[5] Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set PWM mode
[5]
Start count
[6]
[6] Set the CST bit in TSTR to 1 to start the count
operation.
<PWM mode>
Figure 11.24 Example of PWM Mode Setting Procedure
Rev. 5.00 Mar 28, 2005 page 584 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of PWM Mode Operation: Figure 11.25 shows an example of PWM mode 1
operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as
the duty.
TCNT value
TGRA
Counter cleared by
TGRA compare match
TGRB
H'0000
Time
TIOCA
Figure 11.25 Example of PWM Mode Operation (1)
Rev. 5.00 Mar 28, 2005 page 585 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Figure 11.26 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM
waveform.
In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as
the duty.
Counter cleared by TGR1B
compare match
TCNT value
TGR1B
TGR1A
TGR0D
TGR0C
TGR0B
TGR0A
H'0000
Time
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 11.26 Example of PWM Mode Operation (2)
Rev. 5.00 Mar 28, 2005 page 586 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Figure 11.27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM
mode.
TCNT value
TGRB rewritten
TGRA
TGRB
TGRB
rewritten
TGRB rewritten
H'0000
Time
0% duty
TIOCA
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB rewritten
TGRB
H'0000
Time
100% duty
TIOCA
Output does not change when cycle register and duty
register compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB
TGRB rewritten
Time
H'0000
TIOCA
100% duty
0% duty
Figure 11.27 Example of PWM Mode Operation (3)
Rev. 5.00 Mar 28, 2005 page 587 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.4.7
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 11.8 shows the correspondence between external clock pins and channels.
Table 11.8 Phase Counting Mode Clock Input Pins
External Clock Pins
Channels
A-Phase
B-Phase
When channel 1 or 5 is set to phase counting mode
TCLKA
TCLKB
When channel 2 or 4 is set to phase counting mode
TCLKC
TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 11.28 shows an example of the
phase counting mode setting procedure.
[1] Select phase counting mode with bits MD3 to
MD0 in TMDR.
Phase counting mode
Select phase counting mode
[1]
Start count
[2]
[2] Set the CST bit in TSTR to 1 to start the count
operation.
<Phase counting mode>
Figure 11.28 Example of Phase Counting Mode Setting Procedure
Rev. 5.00 Mar 28, 2005 page 588 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or
down according to the phase difference between two external clocks. There are four modes,
according to the count conditions.
• Phase counting mode 1
Figure 11.29 shows an example of phase counting mode 1 operation, and table 11.9
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 11.29 Example of Phase Counting Mode 1 Operation
Table 11.9 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Up-count
Low level
Low level
High level
High level
Down-count
Low level
High level
Low level
Legend:
: Rising edge
: Falling edge
Rev. 5.00 Mar 28, 2005 page 589 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
• Phase counting mode 2
Figure 11.30 shows an example of phase counting mode 2 operation, and table 11.10
summarizes the TCNT up/down-count conditions.
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 11.30 Example of Phase Counting Mode 2 Operation
Table 11.10
Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
Operation
High level
Don’t care
Low level
Don’t care
Low level
Don’t care
High level
Up-count
High level
Don’t care
Low level
Don’t care
High level
Don’t care
Low level
Down-count
Legend:
: Rising edge
: Falling edge
Rev. 5.00 Mar 28, 2005 page 590 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
• Phase counting mode 3
Figure 11.31 shows an example of phase counting mode 3 operation, and table 11.11
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 11.31 Example of Phase Counting Mode 3 Operation
Table 11.11
Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
Operation
High level
Don’t care
Low level
Don’t care
Low level
Don’t care
High level
Up-count
High level
Down-count
Low level
Don’t care
High level
Don’t care
Low level
Don’t care
Legend:
: Rising edge
: Falling edge
Rev. 5.00 Mar 28, 2005 page 591 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
• Phase counting mode 4
Figure 11.32 shows an example of phase counting mode 4 operation, and table 11.12
summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 11.32 Example of Phase Counting Mode 4 Operation
Table 11.12
Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Up-count
Low level
Low level
Don’t care
High level
High level
Down-count
Low level
High level
Low level
Legend:
: Rising edge
: Falling edge
Rev. 5.00 Mar 28, 2005 page 592 of 1422
REJ09B0234-0500
Don’t care
Section 11 16-Bit Timer Pulse Unit (TPU)
Phase Counting Mode Application Example: Figure 11.33 shows an example in which phase
counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo
motor 2-phase encoder pulses in order to detect the position or speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C
are used for the compare match function, and are set with the speed control period and position
control period. TGR0B is used for input capture, with TGR0B and TGR0D operating in buffer
mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and
detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed.
TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and
TGR0C compare matches are selected as the input capture source, and store the up/down-counter
values for the control periods.
This procedure enables accurate position/speed detection to be achieved.
Rev. 5.00 Mar 28, 2005 page 593 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Channel 1
TCLKA
TCLKB
Edge
detection
circuit
TCNT1
TGR1A
(speed period capture)
TGR1B
(position period capture)
TCNT0
+
TGR0A (speed control period)
TGR0C
(position control period)
TGR0B (pulse width capture)
TGR0D (buffer operation)
Channel 0
Figure 11.33 Phase Counting Mode Application Example
Rev. 5.00 Mar 28, 2005 page 594 of 1422
REJ09B0234-0500
–
+
–
Section 11 16-Bit Timer Pulse Unit (TPU)
11.5
Interrupts
11.5.1
Interrupt Sources and Priorities
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
Table 11.13 lists the TPU interrupt sources.
Rev. 5.00 Mar 28, 2005 page 595 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.13
TPU Interrupts
Channel
Interrupt
Source Description
DMAC*
Activation
DTC*
Activation
Priority
0
TGI0A
TGR0A input capture/compare match
Possible
Possible
High
TGI0B
TGR0B input capture/compare match
Not possible Possible
TGI0C
TGR0C input capture/compare match
Not possible Possible
TGI0D
TGR0D input capture/compare match
Not possible Possible
TCI0V
TCNT0 overflow
Not possible Not possible
TGI1A
TGR1A input capture/compare match
Possible
TGI1B
TGR1B input capture/compare match
Not possible Possible
TCI1V
TCNT1 overflow
Not possible Not possible
TCI1U
TCNT1 underflow
Not possible Not possible
TGI2A
TGR2A input capture/compare match
Possible
TGI2B
TGR2B input capture/compare match
Not possible Possible
TCI2V
TCNT2 overflow
Not possible Not possible
TCI2U
TCNT2 underflow
Not possible Not possible
TGI3A
TGR3A input capture/compare match
Possible
TGI3B
TGR3B input capture/compare match
Not possible Possible
TGI3C
TGR3C input capture/compare match
Not possible Possible
TGI3D
TGR3D input capture/compare match
Not possible Possible
TCI3V
TCNT3 overflow
Not possible Not possible
1
2
3
4
5
Possible
Possible
Possible
TGI4A
TGR4A input capture/compare match
Possible
TGI4B
TGR4B input capture/compare match
Not possible Possible
Possible
TCI4V
TCNT4 overflow
Not possible Not possible
TCI4U
TCNT4 underflow
Not possible Not possible
TGI5A
TGR5A input capture/compare match
Possible
TGI5B
TGR5B input capture/compare match
Not possible Possible
TCI5V
TCNT5 overflow
Not possible Not possible
TCI5U
TCNT5 underflow
Not possible Not possible Low
Possible
Notes: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
* DMAC and DTC functions are not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 596 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each
for channels 1, 2, 4, and 5.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one
each for channels 1, 2, 4, and 5.
11.5.2
DTC/DMAC Activation (This function is not available in the H8S/2695)
DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt
for a channel. For details, see section 9, Data Transfer Controller (DTC).
A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources,
four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
DMAC Activation: It is possible to activate the DMAC by the TGRA input capture/compare
match interrupt for each channel. See section 8, DMA Controller (DMAC) for details.
In TPU, it is possible to set the TGRA input capture/compare match interrupts for each channel,
giving a total of 6, as DMAC activation factors.
11.5.3
A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to start A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is started.
In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
Rev. 5.00 Mar 28, 2005 page 597 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.6
Operation Timing
11.6.1
Input/Output Timing
TCNT Count Timing: Figure 11.34 shows TCNT count timing in internal clock operation, and
figure 11.35 shows TCNT count timing in external clock operation.
φ
Internal clock
Rising edge
Falling edge
TCNT
input clock
TCNT
N–1
N
N+1
N+2
Figure 11.34 Count Timing in Internal Clock Operation
φ
External clock
Falling edge
Rising edge
Falling edge
TCNT
input clock
TCNT
N–1
N
N+1
Figure 11.35 Count Timing in External Clock Operation
Rev. 5.00 Mar 28, 2005 page 598 of 1422
REJ09B0234-0500
N+2
Section 11 16-Bit Timer Pulse Unit (TPU)
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match
signal is not generated until the TCNT input clock is generated.
Figure 11.36 shows output compare output timing.
φ
TCNT
input clock
N
TCNT
N+1
N
TGR
Compare
match signal
TIOC pin
Figure 11.36 Output Compare Output Timing
Input Capture Signal Timing: Figure 11.37 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
TCNT
TGR
N
N+1
N+2
N
N+2
Figure 11.37 Input Capture Input Signal Timing
Rev. 5.00 Mar 28, 2005 page 599 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Timing for Counter Clearing by Compare Match/Input Capture: Figure 11.38 shows the
timing when counter clearing by compare match occurrence is specified, and figure 11.39 shows
the timing when counter clearing by input capture occurrence is specified.
φ
Compare
match signal
Counter
clear signal
TCNT
N
TGR
N
H'0000
Figure 11.38 Counter Clear Timing (Compare Match)
φ
Input capture
signal
Counter clear
signal
TCNT
N
H'0000
N
TGR
Figure 11.39 Counter Clear Timing (Input Capture)
Rev. 5.00 Mar 28, 2005 page 600 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Buffer Operation Timing: Figures 11.40 and 11.41 show the timing in buffer operation.
φ
n
TCNT
n+1
Compare
match signal
TGRA,
TGRB
n
TGRC,
TGRD
N
N
Figure 11.40 Buffer Operation Timing (Compare Match)
φ
Input capture
signal
TCNT
N
TGRA,
TGRB
n
TGRC,
TGRD
N+1
N
N+1
n
N
Figure 11.41 Buffer Operation Timing (Input Capture)
Rev. 5.00 Mar 28, 2005 page 601 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.6.2
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 11.42 shows the timing for
setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal
timing.
φ
TCNT input
clock
TCNT
N
TGR
N
N+1
Compare
match signal
TGF flag
TGI interrupt
Figure 11.42 TGI Interrupt Timing (Compare Match)
Rev. 5.00 Mar 28, 2005 page 602 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
TGF Flag Setting Timing in Case of Input Capture: Figure 11.43 shows the timing for setting
of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing.
φ
Input capture
signal
TCNT
TGR
N
N
TGF flag
TGI interrupt
Figure 11.43 TGI Interrupt Timing (Input Capture)
Rev. 5.00 Mar 28, 2005 page 603 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
TCFV Flag/TCFU Flag Setting Timing: Figure 11.44 shows the timing for setting of the TCFV
flag in TSR by overflow occurrence, and TCIV interrupt request signal timing.
Figure 11.45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
TCIU interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
H'FFFF
H'0000
Overflow
signal
TCFV flag
TCIV interrupt
Figure 11.44 TCIV Interrupt Setting Timing
φ
TCNT
input clock
TCNT
(underflow)
H'0000
H'FFFF
Underflow signal
TCFU flag
TCIU interrupt
Figure 11.45 TCIU Interrupt Setting Timing
Rev. 5.00 Mar 28, 2005 page 604 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC* or DMAC* is activated, the flag is cleared automatically. Figure 11.46
shows the timing for status flag clearing by the CPU, and figure 11.47 shows the timing for status
flag clearing by the DTC* or DMAC*.
Note: * DMAC and DTC functions are not available in the H8S/2695.
TSR write cycle
T1
T2
φ
Address
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 11.46 Timing for Status Flag Clearing by CPU
DTC*/DMAC*
read cycle
T1
T2
DTC*/DMAC*
write cycle
T1
T2
φ
Address
Source address
Destination
address
Status flag
Interrupt
request
signal
Note: * DMAC and DTC functions are not available in the H8S/2695.
Figure 11.47 Timing for Status Flag Clearing by DTC* or DMAC* Activation
Rev. 5.00 Mar 28, 2005 page 605 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
11.7
Usage Notes
Note that the kinds of operation and contention described below occur during TPU operation.
Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of
single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not
operate properly with a narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.48 shows the input clock
conditions in phase counting mode.
Overlap
Phase
Phase
differdifference Overlap ence
Pulse width
Pulse width
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
: 2.5 states or more
Pulse width
Figure 11.48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in
the final state in which it matches the TGR value (the point at which the count value matched by
TCNT is updated). Consequently, the actual counter frequency is given by the following formula:
f=
φ
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value
Rev. 5.00 Mar 28, 2005 page 606 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 11.49 shows the timing in this case.
TCNT write cycle
T1
T2
φ
TCNT address
Address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 11.49 Contention between TCNT Write and Clear Operations
Rev. 5.00 Mar 28, 2005 page 607 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2
state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 11.50 shows the timing in this case.
TCNT write cycle
T1
T2
φ
TCNT address
Address
Write signal
TCNT input
clock
N
TCNT
M
TCNT write data
Figure 11.50 Contention between TCNT Write and Increment Operations
Rev. 5.00 Mar 28, 2005 page 608 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Compare Match: If a compare match occurs in the T2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 11.51 shows the timing in this case.
TGR write cycle
T1
T2
φ
TGR address
Address
Write signal
Compare
match signal
Inhibited
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 11.51 Contention between TGR Write and Compare Match
Rev. 5.00 Mar 28, 2005 page 609 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
data prior to the write.
Figure 11.52 shows the timing in this case.
TGR write cycle
T1
T2
φ
Buffer register
address
Address
Write signal
Compare
match signal
Buffer register write data
Buffer
register
TGR
N
M
N
Figure 11.52 Contention between Buffer Register Write and Compare Match
Rev. 5.00 Mar 28, 2005 page 610 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 11.53 shows the timing in this case.
TGR read cycle
T1
T2
φ
TGR address
Address
Read signal
Input capture
signal
TGR
Internal
data bus
X
M
M
Figure 11.53 Contention between TGR Read and Input Capture
Rev. 5.00 Mar 28, 2005 page 611 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 11.54 shows the timing in this case.
TGR write cycle
T1
T2
φ
TGR address
Address
Write signal
Input capture
signal
TCNT
M
M
TGR
Figure 11.54 Contention between TGR Write and Input Capture
Rev. 5.00 Mar 28, 2005 page 612 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the
write to the buffer register is not performed.
Figure 11.55 shows the timing in this case.
Buffer register write cycle
T1
T2
φ
Buffer register
address
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
N
M
N
M
Figure 11.55 Contention between Buffer Register Write and Input Capture
Rev. 5.00 Mar 28, 2005 page 613 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and
counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing
takes precedence.
Figure 11.56 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter
clear signal
TGF
Prohibited
TCFV
Figure 11.56 Contention between Overflow and Counter Clearing
Rev. 5.00 Mar 28, 2005 page 614 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write
takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 11.57 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T1
T2
φ
TCNT address
Address
Write signal
TCNT
TCNT write data
H'FFFF
M
Prohibited
TCFV flag
Figure 11.57 Contention between TCNT Write and Overflow
Multiplexing of I/O Pins: In the H8S/2633 Group, the TCLKA input pin is multiplexed with the
TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the
TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is
input, compare match output should not be performed from a multiplexed pin.
Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DMAC* or DTC*
activation source. Interrupts should therefore be disabled before entering module stop mode.
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 615 of 1422
REJ09B0234-0500
Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 5.00 Mar 28, 2005 page 616 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
Section 12 Programmable Pulse Generator (PPG)
(This function is not available in the H8S/2695)
12.1
Overview
The H8S/2633 Group has a built-in programmable pulse generator (PPG) that provides pulse
outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are
divided into 4-bit groups (group 3 and group 2) that can operate both simultaneously and
independently.
12.1.1
Features
PPG features are listed below.
• 8-bit output data
 Maximum 8-bit data can be output, and output can be enabled on a bit-by-bit basis
• Two output groups
 Output trigger signals can be selected in 4-bit groups to provide up to two different 4-bit
outputs
• Selectable output trigger signals
 Output trigger signals can be selected for each group from the compare match signals of
four TPU channels
• Non-overlap mode
 A non-overlap margin can be provided between pulse outputs
• Can operate together with the data transfer controller (DTC) and DMA controller (DMAC)
 The compare match signals selected as output trigger signals can activate the DTC or
DMAC for sequential output of data without CPU intervention
• Settable inverted output
 Inverted data can be output for each group
• Module stop mode can be set
 As the initial setting, PPG operation is halted. Register access is enabled by exiting module
stop mode
Rev. 5.00 Mar 28, 2005 page 617 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the PPG.
Compare match signals
Control logic
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
NDERH
NDERL
PMR
PCR
Pulse output
pins, group 3
PODRH
NDRH
PODRL
NDRL
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
Legend:
PMR:
PCR
NDERH:
NDERL:
NDRH:
NDRL:
PODRH:
PODRL:
PPG output mode register
PPG output control register
Next data enable register H
Next data enable register L
Next data register H
Next data register L
Output data register H
Output data register L
Figure 12.1 Block Diagram of PPG
Rev. 5.00 Mar 28, 2005 page 618 of 1422
REJ09B0234-0500
Internal
data bus
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.1.3
Pin Configuration
Table 12.1 summarizes the PPG pins.
Table 12.1 PPG Pins
Name
Symbol
I/O
Function
Group 2 pulse output
Pulse output 8
PO8
Output
Pulse output 9
PO9
Output
Pulse output 10
PO10
Output
Pulse output 11
PO11
Output
Pulse output 12
PO12
Output
Pulse output 13
PO13
Output
Pulse output 14
PO14
Output
Pulse output 15
PO15
Output
Group 3 pulse output
Rev. 5.00 Mar 28, 2005 page 619 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.1.4
Registers
Table 12.2 summarizes the PPG registers.
Table 12.2 PPG Registers
Abbreviation
R/W
Initial Value
Address*1
PPG output control register
PCR
R/W
H'FF
H'FE26
PPG output mode register
PMR
R/W
H'F0
H'FE27
Next data enable register H
Next data enable register L*4
NDERH
R/W
H'00
H'FE28
NDERL
R/W
H'00
H'FE29
Output data register H
Output data register L*4
PODRH
H'00
H'FE2A
PODRL
R/(W)*2
R/(W)*2
H'00
H'FE2B
Next data register H
NDRH
R/W
H'00
Next data register L*4
NDRL
R/W
H'00
H'FE2C*3
H'FE2E
H'FE2D*3
H'FE2F
Port 1 data direction register
P1DDR
W
H'00
H'FE30
Module stop control register A
MSTPCRA
R/W
H'3F
H'FDE8
Name
Notes: 1. Lower 16 bits of the address.
2. A bit that has been set for pulse output by NDER is read-only.
3. When the same output trigger is selected for pulse output groups 2 and 3 by the PCR
setting, the NDRH address is H'FE2C. When the output triggers are different, the
NDRH address is H'FE2E for group 2 and H'FE2C for group 3.
Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by
the PCR setting, the NDRL address is H'FE2D. When the output triggers are different,
the NDRL address is H'FE2F for group 0 and H'FE2D for group 1.
4. The H8S/2633 Group has no pins corresponding to pulse output groups 0 and 1.
Rev. 5.00 Mar 28, 2005 page 620 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.2
Register Descriptions
12.2.1
Next Data Enable Registers H and L (NDERH, NDERL)
NDERH
Bit
:
7
6
5
4
3
2
1
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9
Initial value :
R/W
0
NDER8
0
0
0
0
0
0
0
0
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
7
6
5
4
3
2
1
0
NDER7
NDER6
NDER5
NDER4
NDER3
NDER2
NDER1
NDER0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NDERL
Bit
Initial value :
R/W
:
NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a
bit-by-bit basis.
If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically
transferred to the corresponding PODR bit when the TPU compare match event specified by PCR
occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from
NDR to PODR and the output value does not change.
NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They
are not initialized in software standby mode.
NDERH Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or
disable pulse output on a bit-by-bit basis.
Bits 7 to 0
NDER15 to NDER8
Description
0
Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not
transferred to POD15 to POD8)
(Initial value)
1
Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred
to POD15 to POD8)
Rev. 5.00 Mar 28, 2005 page 621 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
NDERL Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or
disable pulse output on a bit-by-bit basis. However, the H8S/2633 Group has no output pins
corresponding to NDRL.
Bits 7 to 0
NDER7 to NDER0
Description
0
Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not
transferred to POD7 to POD0)
(Initial value)
1
Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to
POD7 to POD0)
12.2.2
Output Data Registers H and L (PODRH, PODRL)
PODRH
Bit
:
7
6
5
4
3
2
1
0
POD15
POD14
POD13
POD12
POD11
POD10
POD9
POD8
0
0
0
0
0
0
0
0
:
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
:
7
6
5
4
3
2
1
0
POD7
POD6
POD5
POD4
POD3
POD2
POD1
POD0
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Initial value :
R/W
PODRL
Bit
Initial value :
R/W
:
Note: * A bit that has been set for pulse output by NDER is read-only.
PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse
output. However, the H8S/2633 Group has no pins corresponding to PODRL.
Rev. 5.00 Mar 28, 2005 page 622 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.2.3
Next Data Registers H and L (NDRH, NDRL)
NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output.
During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in
PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH
and NDRL addresses differ depending on whether pulse output groups have the same output
trigger or different output triggers. For details see section 12.2.4, Notes on NDR Access.
NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are
not initialized in software standby mode.
12.2.4
Notes on NDR Access
The NDRH and NDRL addresses differ depending on whether pulse output groups have the same
output trigger or different output triggers.
Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the
same compare match event, the NDRH address is H'FE2C. The upper 4 bits belong to group 3
and the lower 4 bits to group 2. Address H'FE2E consists entirely of reserved bits that cannot be
modified and are always read as 1.
Address H'FE2C
Bit
:
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Address H'FE2E
Bit
:
Initial value :
1
1
1
1
1
1
1
1
R/W
—
—
—
—
—
—
—
—
:
If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address
is H'FE2D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FE2F
consists entirely of reserved bits that cannot be modified and are always read as 1. However, the
H8S/2633 Group has no output pins corresponding to pulse output groups 0 and 1.
Rev. 5.00 Mar 28, 2005 page 623 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
Address H'FE2D
Bit
:
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value :
1
1
1
1
1
1
1
1
R/W
—
—
—
—
—
—
—
—
Initial value :
R/W
:
Address H'FE2F
Bit
:
:
Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by
different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FE2C and
the address of the lower 4 bits (group 2) is H'FE2E. Bits 3 to 0 of address H'FE2C and bits 7 to 4
of address H'FE2E are reserved bits that cannot be modified and are always read as 1.
Address H'FE2C
Bit
:
7
6
5
4
3
2
1
0
NDR15
NDR14
NDR13
NDR12
—
—
—
—
0
0
0
0
1
1
1
1
R/W
R/W
R/W
R/W
—
—
—
—
7
6
5
4
3
2
1
0
—
—
—
—
NDR11
NDR10
NDR9
NDR8
Initial value :
1
1
1
1
0
0
0
0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
Initial value :
R/W
:
Address H'FE2E
Bit
:
:
If pulse output groups 0 and 1 are triggered by different compare match event, the address of the
upper 4 bits in NDRL (group 1) is H'FE2D and the address of the lower 4 bits (group 0) is
H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that
cannot be modified and are always read as 1. However, the H8S/2633 Group has no output pins
corresponding to pulse output groups 0 and 1.
Rev. 5.00 Mar 28, 2005 page 624 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
Address H'FE2D
Bit
:
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
—
—
—
—
0
0
0
0
1
1
1
1
R/W
R/W
R/W
R/W
—
—
—
—
7
6
5
4
3
2
1
0
—
—
—
—
NDR3
NDR2
NDR1
NDR0
Initial value :
1
1
1
1
0
0
0
0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
4
3
2
1
0
Initial value :
R/W
:
Address H'FE2F
Bit
12.2.5
Bit
:
:
PPG Output Control Register (PCR)
:
7
6
5
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value :
R/W
:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a
group-by-group basis.
PCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match that triggers pulse output group 3 (pins PO15 to PO12).
Bit 7
Bit 6
Description
G3CMS1
G3CMS0
Output Trigger for Pulse Output Group 3
0
0
Compare match in TPU channel 0
1
Compare match in TPU channel 1
0
Compare match in TPU channel 2
1
Compare match in TPU channel 3
1
(Initial value)
Rev. 5.00 Mar 28, 2005 page 625 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits
select the compare match that triggers pulse output group 2 (pins PO11 to PO8).
Bit 5
Bit 4
Description
G2CMS1
G2CMS0
Output Trigger for Pulse Output Group 2
0
0
Compare match in TPU channel 0
1
Compare match in TPU channel 1
1
0
Compare match in TPU channel 2
1
Compare match in TPU channel 3
(Initial value)
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match that triggers pulse output group 1 (pins PO7 to PO4). However, the
H8S/2633 Group has no output pins corresponding to pulse output group 1.
Bit 3
Bit 2
Description
G1CMS1
G1CMS0
Output Trigger for Pulse Output Group 1
0
0
Compare match in TPU channel 0
1
Compare match in TPU channel 1
0
Compare match in TPU channel 2
1
Compare match in TPU channel 3
1
(Initial value)
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match that triggers pulse output group 0 (pins PO3 to PO0). However, the
H8S/2633 Group has no output pins corresponding to pulse output group 0.
Bit 1
Bit 0
Description
G0CMS1
G0CMS0
Output Trigger for Pulse Output Group 0
0
0
Compare match in TPU channel 0
1
Compare match in TPU channel 1
0
Compare match in TPU channel 2
1
Compare match in TPU channel 3
1
Rev. 5.00 Mar 28, 2005 page 626 of 1422
REJ09B0234-0500
(Initial value)
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.2.6
Bit
PPG Output Mode Register (PMR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
G3INV
G2INV
G1INV
G0INV
G3NOV
G2NOV
G1NOV
G0NOV
1
1
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping
operation for each group.
The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB
and the non-overlap margin is set in TGRA. The output values change at compare match A and B.
For details, see section 12.3.4, Non-Overlapping Pulse Output.
PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output
group 3 (pins PO15 to PO12).
Bit 7
G3INV
Description
0
Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)
1
Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)
(Initial value)
Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output
group 2 (pins PO11 to PO8).
Bit 6
G2INV
Description
0
Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)
1
Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)
(Initial value)
Rev. 5.00 Mar 28, 2005 page 627 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output
group 1 (pins PO7 to PO4). However, the H8S/2633 Group has no pins corresponding to pulse
output group 1.
Bit 5
G1INV
Description
0
Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)
1
Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL)
(Initial value)
Bit 4—Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output
group 0 (pins PO3 to PO0). However, the H8S/2633 Group has no pins corresponding to pulse
output group 0.
Bit 4
G0INV
Description
0
Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL)
1
Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL)
(Initial value)
Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping operation for pulse
output group 3 (pins PO15 to PO12).
Bit 3
G3NOV
Description
0
Normal operation in pulse output group 3 (output values updated at compare match A
in the selected TPU channel)
(Initial value)
1
Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Rev. 5.00 Mar 28, 2005 page 628 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse
output group 2 (pins PO11 to PO8).
Bit 2
G2NOV
Description
0
Normal operation in pulse output group 2 (output values updated at compare match A
in the selected TPU channel)
(Initial value)
1
Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse
output group 1 (pins PO7 to PO4). However, the H8S/2633 Group has no pins corresponding to
pulse output group 1.
Bit 1
G1NOV
Description
0
Normal operation in pulse output group 1 (output values updated at compare match A
in the selected TPU channel)
(Initial value)
1
Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse
output group 0 (pins PO3 to PO0). However, the H8S/2633 Group has no pins corresponding to
pulse output group 0.
Bit 0
G0NOV
Description
0
Normal operation in pulse output group 0 (output values updated at compare match A
in the selected TPU channel)
(Initial value)
1
Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Rev. 5.00 Mar 28, 2005 page 629 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.2.7
Bit
Port 1 Data Direction Register (P1DDR)
:
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
:
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1.
Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must
be set to 1. For further information about P1DDR, see sections 10A.2 and 10B.2, Port 1.
12.2.8
Bit
Module Stop Control Register A (MSTPCRA)
:
7
6
5
4
3
2
1
0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
R/W
:
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPA3 bit in MSTPCRA is set to 1, PPG operation stops at the end of the bus cycle
and a transition is made to module stop mode. Registers cannot be read or written to in module
stop mode. For details, see section 24.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset and in software standby mode.
Bit 3—Module Stop (MSTPA3): Specifies the PPG module stop mode.
Bit 3
MSTPA3
Description
0
PPG module stop mode cleared
1
PPG module stop mode set
Rev. 5.00 Mar 28, 2005 page 630 of 1422
REJ09B0234-0500
(Initial value)
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.3
Operation
12.3.1
Overview
PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In
this state the corresponding PODR contents are output.
When the compare match event specified by PCR occurs, the corresponding NDR bit contents are
transferred to PODR to update the output values.
Figure 12.2 illustrates the PPG output operation and table 12.3 summarizes the PPG operating
conditions.
DDR
NDER
Q
Q
Output trigger signal
C
Q PODR D
Q NDR D
Internal data bus
Pulse output pin
Normal output/inverted output
Figure 12.2 PPG Output Operation
Table 12.3 PPG Operating Conditions
NDER
DDR
Pin Function
0
0
Generic input port
1
Generic output port
0
Generic input port (but the PODR bit is a read-only bit, and when
compare match occurs, the NDR bit value is transferred to the PODR bit)
1
PPG pulse output
1
Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the
next compare match. For details of non-overlapping operation, see section 12.3.4, NonOverlapping Pulse Output.
Rev. 5.00 Mar 28, 2005 page 631 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.3.2
Output Timing
If pulse output is enabled, NDR contents are transferred to PODR and output when the specified
compare match event occurs. Figure 12.3 shows the timing of these operations for the case of
normal output in groups 2 and 3, triggered by compare match A.
φ
N
TCNT
TGRA
N+1
N
Compare match
A signal
n
NDRH
PODRH
m
PO8 to PO15
n
m
n
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example)
Rev. 5.00 Mar 28, 2005 page 632 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.3.3
Normal Pulse Output
Sample Setup Procedure for Normal Pulse Output: Figure 12.4 shows a sample procedure for
setting up normal pulse output.
Normal PPG output
Select TGR functions
[1]
Set TGRA value
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
Enable pulse output
[6]
Select output trigger
[7]
[1] Set TIOR to make TGRA an output
compare register (with output
disabled).
[2] Set the PPG output trigger period.
TPU setup
Port and
PPG setup
TPU setup
Set next pulse
output data
[8]
Start counter
[9]
Compare match?
No
[3] Select the counter clock source
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR1 and CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC or DMAC can also be set
up to transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to 1.
[7] Select the TPU compare match
event to be used as the output
trigger in PCR.
[8] Set the next pulse output values in
NDR.
Yes
Set next pulse
output data
[10]
[9] Set the CST bit in TSTR to 1 to
start the TCNT counter.
[10] At each TGIA interrupt, set the next
output values in NDR.
Figure 12.4 Setup Procedure for Normal Pulse Output (Example)
Rev. 5.00 Mar 28, 2005 page 633 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 12.5 shows
an example in which pulse output is used for cyclic five-phase pulse output.
TCNT value
Compare match
TCNT
TGRA
H'0000
Time
80
NDRH
PODRH
00
C0
80
40
C0
60
40
20
60
30
20
10
30
18
10
08
18
88
08
80
88
C0
80
40
C0
PO15
PO14
PO13
PO12
PO11
Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output)
[1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output
compare register and the counter will be cleared by compare match A. Set the trigger period in
TGRA and set the TGIEA bit in TIER to 1 to enable the compare match A (TGIA) interrupt.
[2] Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Write output data H'80 in NDRH.
[3] The timer counter in the TPU channel starts. When compare match A occurs, the NDRH
contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the
next output data (H'C0) in NDRH.
[4] Five-phase overlapping pulse output (one or two phases active at a time) can be obtained
subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA
interrupts. If the DTC or DMAC is set for activation by this interrupt, pulse output can be
obtained without imposing a load on the CPU.
Rev. 5.00 Mar 28, 2005 page 634 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.3.4
Non-Overlapping Pulse Output
Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 12.6 shows a sample
procedure for setting up non-overlapping pulse output.
[1] Set TIOR to make TGRA and
TGRB an output compare registers
(with output disabled).
Non-overlapping
PPG output
Select TGR functions
[1]
Set TGR values
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
TPU setup
PPG setup
TPU setup
Enable pulse output
[6]
Select output trigger
[7]
Set non-overlapping groups
[8]
Set next pulse
output data
[9]
Start counter
[10]
Compare match?
No
[3] Select the counter clock source
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR1 and CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC or DMAC can also be set
up to transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to
1.
[7] Select the TPU compare match
event to be used as the pulse
output trigger in PCR.
[8] In PMR, select the groups that will
operate in non-overlap mode.
Yes
Set next pulse
output data
[2] Set the pulse output trigger period
in TGRB and the non-overlap
margin in TGRA.
[11]
[9] Set the next pulse output values in
NDR.
[10] Set the CST bit in TSTR to 1 to
start the TCNT counter.
[11] At each TGIA interrupt, set the next
output values in NDR.
Figure 12.6 Setup Procedure for Non-Overlapping Pulse Output (Example)
Rev. 5.00 Mar 28, 2005 page 635 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 12.7 shows an example in which pulse output is used for fourphase complementary non-overlapping pulse output.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRH
Time
95
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
Non-overlap margin
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 12.7 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
Rev. 5.00 Mar 28, 2005 page 636 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
[1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are
output compare registers. Set the trigger period in TGRB and the non-overlap margin in
TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1
to enable the TGIA interrupt.
[2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.
Write output data H'95 in NDRH.
[3] The timer counter in the TPU channel starts. When a compare match with TGRB occurs,
outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0
to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt
handling routine writes the next output data (H'65) in NDRH.
[4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by
writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for
activation by this interrupt, pulse output can be obtained without imposing a load on the CPU.
Rev. 5.00 Mar 28, 2005 page 637 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.3.5
Inverted Pulse Output
If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the
inverse of the PODR contents can be output.
Figure 12.8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the
settings of figure 12.7.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRL
Time
95
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 12.8 Inverted Pulse Output (Example)
Rev. 5.00 Mar 28, 2005 page 638 of 1422
REJ09B0234-0500
65
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
12.3.6
Pulse Output Triggered by Input Capture
Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA
functions as an input capture register in the TPU channel selected by PCR, pulse output will be
triggered by the input capture signal.
Figure 12.9 shows the timing of this output.
φ
TIOC pin
Input capture
signal
NDR
N
PODR
M
PO
M
N
N
Figure 12.9 Pulse Output Triggered by Input Capture (Example)
12.4
Usage Notes
Operation of Pulse Output Pins: Pins PO8 to PO15 are also used for other peripheral functions
such as the TPU. When output by another peripheral function is enabled, the corresponding pins
cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits
takes place, regardless of the usage of the pins.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
Note on Non-Overlapping Output: During non-overlapping operation, the transfer of NDR bit
values to PODR bits takes place as follows.
• NDR bits are always transferred to PODR bits at compare match A.
• At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Rev. 5.00 Mar 28, 2005 page 639 of 1422
REJ09B0234-0500
Section 12 Programmable Pulse Generator (PPG) (This function is not available in the H8S/2695)
Figure 12.10 illustrates the non-overlapping pulse output operation.
DDR
NDER
Q
Compare match A
Compare match B
C
Q PODR D
Pulse
output
pin
Q NDR D
Internal data bus
Normal output/inverted output
Figure 12.10 Non-Overlapping Pulse Output
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. The NDR contents should not be altered during the interval from compare
match B to compare match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next
data must be written before the next compare match B occurs.
Figure 12.11 shows the timing of this operation.
Compare match A
Compare match B
Write to NDR
Write to NDR
NDR
PODR
0 output
0/1 output
Write to NDR
Do not write here
to NDR here
0 output 0/1 output
Write to NDR
Do not write here
to NDR here
Figure 12.11 Non-Overlapping Operation and NDR Write Timing
Rev. 5.00 Mar 28, 2005 page 640 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695)
13.1
Overview
The H8S/2633 Group includes an 8-bit timer module with four channels (TMR0, TMR1, TMR2,
and TMR3). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA
and TCORB) that are constantly compared with the TCNT value to detect compare match events.
The 8-bit timer module can thus be used for a variety of functions, including pulse output with an
arbitrary duty cycle.
13.1.1
Features
The features of the 8-bit timer module are listed below.
• Selection of four clock sources
 The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or
an external clock input (enabling use as an external event counter)
• Selection of three ways to clear the counters
 The counters can be cleared on compare match A or B, or by an external reset signal
• Timer output control by a combination of two compare match signals
 The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to generate output waveforms with an arbitrary
duty cycle or PWM output
• Provision for cascading of two channels
 Operation as a 16-bit timer is possible, using channel 0 (channel 2) for the upper 8 bits and
channel 1 (channel 3) for the lower 8 bits (16-bit count mode)
 Channel 1 (channel 3) can be used to count channel 0 (channel 2) compare matches
(compare match count mode)
• Three independent interrupts
 Compare match A and B and overflow interrupts can be requested independently
• A/D converter conversion start trigger can be generated
 Channel 0 compare match A signal can be used as an A/D converter conversion start
trigger
• Module stop mode can be set
 As the initial setting, 8-bit timer operation is halted. Register access is enabled by exiting
module stop mode
Rev. 5.00 Mar 28, 2005 page 641 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.1.2
Block Diagram
Figure 13.1 shows a block diagram of the 8-bit timer module (TMR0, TMR1).
External clock source
TMCI01
TMCI23
Internal clock sources
φ/8
φ/64
φ/8192
Clock select
Clock 1
Clock 0
TCORA0
Compare match A1
Compare match A0 Comparator A0
Overflow 1
Overflow 0
TMO0
TMRI01
TMRI23
TCNT0
TCORA1
Comparator A1
TCNT1
Clear 1
TMO1
Control logic
Compare match B1
Compare match B0 Comparator B0
A/D
conversion
start request
signal
Comparator B1
TCORB0
TCORB1
TCSR0
TCSR1
TCR0
TCR1
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals
Figure 13.1 Block Diagram of 8-Bit Timer
Rev. 5.00 Mar 28, 2005 page 642 of 1422
REJ09B0234-0500
Internal bus
Clear 0
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.1.3
Pin Configuration
Table 13.1 summarizes the input and output pins of the 8-bit timer.
Table 13.1 Pin Configuration
Channel
Name
Symbol
I/O
Function
0
Timer output pin 0
TMO0
Output
Outputs at compare match
Timer clock input pin 01
TMCI01
Input
Inputs external clock for counter
Timer reset input pin 01
TMRI01
Input
Inputs external reset to counter
Timer output pin 1
TMO1
Output
Outputs at compare match
Timer clock input pin 23
TMCI23
Input
Inputs external clock for counter
Timer reset input pin 23
TMRI23
Input
Inputs external reset to counter
Timer output pin 2
TMO2
Output
Outputs at compare match
Timer clock input pin 23
TMCI23
Input
Inputs external clock for counter
Timer reset input pin 23
TMRI23
Input
Inputs external reset to counter
Timer output pin 3
TMO3
Output
Outputs at compare match
Timer clock input pin 01
TMCI01
Input
Inputs external clock for counter
Timer reset input pin 01
TMRI01
Input
Inputs external reset to counter
1
2
3
Rev. 5.00 Mar 28, 2005 page 643 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.1.4
Register Configuration
Table 13.2 summarizes the registers of the 8-bit timer module.
Table 13.2 8-Bit Timer Registers
Channel
Name
0
1
2
3
All
Address*1
Abbreviation
R/W
Initial value
Timer control register 0
TCR0
H'FF68
TCSR0
R/W
R/(W)*2
H'00
Timer control/status register 0
H'00
H'FF6A
Time constant register A0
TCORA0
R/W
H'FF
H'FF6C
Time constant register B0
TCORB0
R/W
H'FF
H'FF6E
Timer counter 0
TCNT0
R/W
H'00
H'FF70
Timer control register 1
TCR1
R/W
H'00
H'FF69
Timer control/status register 1
TCSR1
R/(W)*2
H'10
H'FF6B
Time constant register A1
TCORA1
R/W
H'FF
H'FF6D
Time constant register B1
TCORB1
R/W
H'FF
H'FF6F
Timer counter 1
TCNT1
R/W
H'00
H'FF71
Timer control register 2
TCR2
R/W
H'00
H'FDC0
Timer control/status register 2
TCSR2
R/(W)*2
H'00
H'FDC2
Time constant register A2
TCORA2
R/W
H'FF
H'FDC4
Time constant register B2
TCORB2
R/W
H'FF
H'FDC6
Timer counter 2
TCNT2
R/W
H'00
H'FDC8
Timer control register 3
TCR3
R/W
H'00
H'FDC1
Timer control/status register 3
TCSR3
R/(W)*2
H'10
H'FDC3
Time constant register A3
TCORA3
R/W
H'FF
H'FDC5
Time constant register B3
TCORB3
R/W
H'FF
H'FDC7
Timer counter 3
TCNT3
R/W
H'00
H'FDC9
Module stop control register A
MSTPCRA
R/W
H'3F
H'FDE8
Notes: 1. Lower 16 bits of the address
2. Only 0 can be written to bits 7 to 5, to clear these flags.
Each pair of registers for channel 0 (channel 2) and channel 1 (channel 3) is a 16-bit register with
the upper 8 bits for channel 0 (channel 2) and the lower 8 bits for channel 1 (channel 3), so they
can be accessed together by word transfer instruction.
Rev. 5.00 Mar 28, 2005 page 644 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.2
Register Descriptions
13.2.1
Timer Counters 0 to 3 (TCNT0 to TCNT3)
TCNT0 (TCNT2)
Bit
:
Initial value:
R/W
:
TCNT1 (TCNT3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT0 to TCNT3 are 8-bit readable/writable up-counters that increment on pulses generated from
an internal or external clock source. This clock source is selected by clock select bits CKS2 to
CKS0 of TCR. The CPU can read or write to TCNT0 to TCNT3 at all times.
TCNT0 and TCNT1 (TCNT2 and TCNT3) comprise a single 16-bit register, so they can be
accessed together by word transfer instruction.
TCNT0 and TCNT1 (TCNT2 and TCNT3) can be cleared by an external reset input or by a
compare match signal. Which signal is to be used for clearing is selected by clock clear bits
CCLR1 and CCLR0 of TCR.
When a timer counter overflows from H'FF to H'00, OVF in TCSR is set to 1.
TCNT0 and TCNT1 are each initialized to H'00 by a reset and in hardware standby mode.
13.2.2
Time Constant Registers A0 to A3 (TCORA0 to TCORA3)
TCORA0 (TCORA2)
Bit
TCORA1 (TCORA3)
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORA0 to TCORA3 are 8-bit readable/writable registers. TCORA0 and TCORA1 (TCORA2
and TCORA3) comprise a single 16-bit register so they can be accessed together by word transfer
instruction.
TCORA is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFA flag of TCSR is set. Note, however, that comparison is disabled during the
T2 state of a TCOR write cycle.
Rev. 5.00 Mar 28, 2005 page 645 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
The timer output can be freely controlled by these compare match signals and the settings of bits
OS1 and OS0 of TCSR.
TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode.
13.2.3
Time Constant Registers B0 to B3 (TCORB0 to TCORB3)
TCORB0 (TCORB2)
Bit
TCORB1 (TCORB3)
:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0 to TCORB3 are 8-bit readable/writable registers. TCORB0 and TCORB1 (TCORB2
and TCORB3) comprise a single 16-bit register so they can be accessed together by word transfer
instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag of TCSR is set. Note, however, that comparison is disabled during the
T2 state of a TCOR write cycle.
The timer output can be freely controlled by these compare match signals and the settings of
output select bits OS3 and OS2 of TCSR.
TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode.
13.2.4
Bit
Timer Control Registers 0 to 3 (TCR0 to TCR3)
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCR0 to TCR3 are 8-bit readable/writable registers that select the input clock source and the time
at which TCNT is cleared, and enable interrupts.
TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode.
For details of this timing, see section 13.3, Operation.
Rev. 5.00 Mar 28, 2005 page 646 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt
requests (CMIB) are enabled or disabled when the CMFB flag of TCSR is set to 1.
Bit 7
CMIEB
Description
0
CMFB interrupt requests (CMIB) are disabled
1
CMFB interrupt requests (CMIB) are enabled
(Initial value)
Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt
requests (CMIA) are enabled or disabled when the CMFA flag of TCSR is set to 1.
Bit 6
CMIEA
Description
0
CMFA interrupt requests (CMIA) are disabled
1
CMFA interrupt requests (CMIA) are enabled
(Initial value)
Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests
(OVI) are enabled or disabled when the OVF flag of TCSR is set to 1.
Bit 5
OVIE
Description
0
OVF interrupt requests (OVI) are disabled
1
OVF interrupt requests (OVI) are enabled
(Initial value)
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by
which TCNT is cleared: by compare match A or B, or by an external reset input.
Bit 4
Bit 3
CCLR1
CCLR0
Description
0
0
Clear is disabled
1
Clear by compare match A
0
Clear by compare match B
1
Clear by rising edge of external reset input
1
(Initial value)
Rev. 5.00 Mar 28, 2005 page 647 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to
TCNT is an internal or external clock.
Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192.
The falling edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channel 0 and channel 1.
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
0
0
1
1
0
Description
0
Clock input disabled
1
Internal clock, counted at falling edge of φ/8
0
Internal clock, counted at falling edge of φ/64
1
Internal clock, counted at falling edge of φ/8192
For channel 0: count at TCNT1 overflow signal*
0
(Initial value)
For channel 1: count at TCNT0 compare match A*
For channel 2: count at TCNT3 overflow signal*
For channel 3: count at TCNT2 compare match A*
1
1
External clock, counted at rising edge
0
External clock, counted at falling edge
1
External clock, counted at both rising and falling edges
Note: * If the count input of channel 0 (channel 2) is the TCNT1 (TCNT3) overflow signal and that of
channel 1 (channel 3) is the TCNT0 (TCNT2) compare match signal, no incrementing clock
is generated. Do not use this setting.
Rev. 5.00 Mar 28, 2005 page 648 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.2.5
Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3)
TCSR0
Bit
:
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ADTE
OS3
OS2
OS1
OS0
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
Initial value:
R/W
:
TCSR1, TCSR3
Bit
:
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
—
OS3
OS2
OS1
OS0
0
0
0
1
0
0
0
0
:
R/(W)*
R/(W)*
R/(W)*
—
R/W
R/W
R/W
R/W
:
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
—
OS3
OS2
OS1
OS0
Initial value :
R/W
TCSR2
Bit
Initial value :
R/W
:
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
TCSR0 to TCSR3 are 8-bit registers that display compare match and timer overflow statuses, and
control compare match output.
TCSR0 and TCSR2 are initialized to H'00, and TCSR1 and TCSR3 to H'10, by a reset and in
hardware standby mode.
Rev. 5.00 Mar 28, 2005 page 649 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and
TCORB match.
Bit 7
CMFB
Description
0
[Clearing conditions]
1
(Initial value)
•
Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0
[Setting condition]
Set when TCNT matches TCORB
Bit 6—Compare Match Flag A (CMFA): Status flag indicating whether the values of TCNT and
TCORA match.
Bit 6
CMFA
Description
0
[Clearing conditions]
1
(Initial value)
•
Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
•
When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0
[Setting condition]
Set when TCNT matches TCORA
Bit 5—Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed
from H'FF to H'00).
Bit 5
OVF
Description
0
[Clearing condition]
(Initial value)
Cleared by reading OVF when OVF = 1, then writing 0 to OVF
1
[Setting condition]
Set when TCNT overflows from H'FF to H'00
Bit 4—A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D
converter start requests by compare-match A.
TCSR1 to TCSR3 are reserved bits. When TCSR1 and TCSR3 are read, always 1 is read off.
Write is disenabled. TCSR2 is readable/writable.
Rev. 5.00 Mar 28, 2005 page 650 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
Bit 4
ADTE
Description
0
A/D converter start requests by compare match A are disabled
1
A/D converter start requests by compare match A are enabled
(Initial value)
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is
to be changed by a compare match of TCOR and TCNT.
Bits OS3 and OS2 select the effect of compare match B on the output level, bits OS1 and OS0
select the effect of compare match A on the output level, and both of them can be controlled
independently.
Note, however, that priorities are set such that: toggle output > 1 output > 0 output. If compare
matches occur simultaneously, the output changes according to the compare match with the higher
priority.
Timer output is disabled when bits OS3 to OS0 are all 0.
After a reset, the timer output is 0 until the first compare match event occurs.
Bit 3
Bit 2
OS3
OS2
Description
0
0
No change when compare match B occurs
1
0 is output when compare match B occurs
0
1 is output when compare match B occurs
1
Output is inverted when compare match B occurs (toggle output)
1
Bit 1
Bit 0
OS1
OS0
Description
0
0
No change when compare match A occurs
1
0 is output when compare match A occurs
0
1 is output when compare match A occurs
1
Output is inverted when compare match A occurs (toggle output)
1
(Initial value)
(Initial value)
Rev. 5.00 Mar 28, 2005 page 651 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.2.6
Bit
Module Stop Control Register A (MSTPCRA)
:
7
6
5
4
3
2
1
0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
R/W
:
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.
When the MSTPA4 and MSTPA0 bits in MSTPCR is set to 1, the 8-bit timer operation stops at
the end of the bus cycle and a transition is made to module stop mode. For details, see section
24.5, Module Stop Mode.
MSTPCRA is initialized to H'3F by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset and in software standby mode.
Bit 4—Module Stop (MSTPA4): Specifies the TMR0 and TMR1 module stop mode.
Bit 4
MSTPA4
Description
0
TMR0, TMR1 module stop mode cleared
1
TMR0, TMR1 module stop mode set
(Initial value)
Bit 0—Module Stop (MSTPA0): Specifies the TMR2 and TMR3 module stop mode.
Bit 0
MSTPA0
Description
0
TMR2, TMR3 module stop mode cleared
1
TMR2, TMR3 module stop mode set
Rev. 5.00 Mar 28, 2005 page 652 of 1422
REJ09B0234-0500
(Initial value)
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.3
Operation
13.3.1
TCNT Incrementation Timing
TCNT is incremented by input clock pulses (either internal or external).
Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the
system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 13.2 shows the
count timing.
φ
Internal clock
Clock input
to TCNT
TCNT
N–1
N
N+1
Figure 13.2 Count Timing for Internal Clock Input
External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in
TCR: at the rising edge, the falling edge, and both rising and falling edges.
Note that the external clock pulse width must be at least 1.5 states for incrementation at a single
edge, and at least 2.5 states for incrementation at both edges. The counter will not increment
correctly if the pulse width is less than these values.
Figure 13.3 shows the timing of incrementation at both edges of an external clock signal.
Rev. 5.00 Mar 28, 2005 page 653 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
φ
External clock
input
Clock input
to TCNT
N–1
TCNT
N
N+1
Figure 13.3 Count Timing for External Clock Input
13.3.2
Compare Match Timing
Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in
TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match.
The compare match signal is generated at the last state in which the match is true, just before the
timer counter is updated.
Therefore, when TCOR and TCNT match, the compare match signal is not generated until the
next incrementation clock input. Figure 13.4 shows this timing.
φ
TCNT
N
TCOR
N
Compare match
signal
CMF
Figure 13.4 Timing of CMF Setting
Rev. 5.00 Mar 28, 2005 page 654 of 1422
REJ09B0234-0500
N+1
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
Timer Output Timing: When compare match A or B occurs, the timer output changes a specified
by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to
0, change to 1, or toggle.
Figure 13.5 shows the timing when the output is set to toggle at compare match A.
φ
Compare match A
signal
Timer output pin
Figure 13.5 Timing of Timer Output
Timing of Compare Match Clear: The timer counter is cleared when compare match A or B
occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.6 shows the
timing of this operation.
φ
Compare match
signal
TCNT
N
H'00
Figure 13.6 Timing of Compare Match Clear
Rev. 5.00 Mar 28, 2005 page 655 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.3.3
Timing of External RESET on TCNT
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 13.7
shows the timing of this operation.
φ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 13.7 Timing of External Reset
13.3.4
Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure
13.8 shows the timing of this operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 13.8 Timing of OVF Setting
Rev. 5.00 Mar 28, 2005 page 656 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.3.5
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer
mode) or compare matches of the 8-bit timer channel 0 (channel 2) could be counted by the timer
of channel 1 (channel 3) (compare match counter mode). In this case, the timer operates as below.
16-Bit Counter Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as
a single 16-bit timer with channel 0 (channel 2) occupying the upper 8 bits and channel 1 (channel
3) occupying the lower 8 bits.
• Setting of compare match flags
 The CMF flag in TCSR0 and TCSR2 is set to 1 when a 16-bit compare match event occurs
 The CMF flag in TCSR1 and TCSR3 is set to 1 when a lower 8-bit compare match event
occurs
• Counter clear specification
 If the CCLR1 and CCLR0 bits in TCR0 (TCR2) have been set for counter clear at compare
match, the 16-bit counter (TCNT0 and TCNT1 (TCNT2 and TCNT3) together) is cleared
when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1
(TCNT2 and TCNT3) together) is cleared even if counter clear by the TMRI01 (TMRI23)
pin has also been set
 The settings of the CCLR1 and CCLR0 bits in TCR1 and TCR3 are ignored. The lower 8
bits cannot be cleared independently
• Pin output
 Control of output from the TMO0 (TMO2) pin by bits OS3 to OS0 in TCSR0 (TCSR2) is
in accordance with the 16-bit compare match conditions
 Control of output from the TMO1 (TMO3) pin by bits OS3 to OS0 in TCSR1 (TCSR3) is
in accordance with the lower 8-bit compare match conditions
Compare Match Counter Mode: When bits CKS2 to CKS0 in TCR1 (TCR3) are B'100, TCNT1
(TCNT3) counts compare match A’s for channel 0 (channel 2).
Channels 0 to 3 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clear are in accordance with the
settings for each channel.
Note on Usage: If the 16-bit counter mode and compare match counter mode are set
simultaneously, the input clock pulses for TCNT0 and TCNT1 (TCNT2 and TCNT3) are not
generated and thus the counters will stop operating. Software should therefore avoid using both
these modes.
Rev. 5.00 Mar 28, 2005 page 657 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.4
Interrupts
13.4.1
Interrupt Sources and DTC Activation
(The H8S/2695 does not have a DTC function or an 8-bit timer)
There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are
shown in table 13.3. Each interrupt source is set as enabled or disabled by the corresponding
interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt
controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts.
Table 13.3 8-Bit Timer Interrupt Sources
Channel
Interrupt Source
Description
DTC Activation
Priority
0
CMIA0
Interrupt by CMFA
Possible
High
CMIB0
Interrupt by CMFB
Possible
OVI0
Interrupt by OVF
Not possible
CMIA1
Interrupt by CMFA
Possible
CMIB1
Interrupt by CMFB
Possible
OVI1
Interrupt by OVF
Not possible
CMIA2
Interrupt by CMFA
Possible
CMIB2
Interrupt by CMFB
Possible
OVI2
Interrupt by OVF
Not possible
CMIA3
Interrupt by CMFA
Possible
CMIB3
Interrupt by CMFB
Possible
OVI3
Interrupt by OVF
Not possible
1
2
3
Low
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
13.4.2
A/D Converter Activation
The A/D converter can be activated only by channel 0 compare match A.
If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel
0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit
timer conversion start trigger has been selected on the A/D converter side at this time, A/D
conversion is started.
Rev. 5.00 Mar 28, 2005 page 658 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.5
Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle,
as shown in figure 13.9. The control bits are set as follows:
[1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that TCNT is cleared by
comparing and matching TCORA.
[2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA
compare match and to 0 at a TCORB compare match.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with
a pulse width determined by TCORB. No software intervention is required.
TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 13.9 Example of Pulse Output
Rev. 5.00 Mar 28, 2005 page 659 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.6
Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit
timer.
13.6.1
Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 13.10 shows this operation.
TCNT write cycle by CPU
T1
T2
φ
TCNT address
Address
Internal write signal
Counter clear signal
N
TCNT
H'00
Figure 13.10 Contention between TCNT Write and Clear
Rev. 5.00 Mar 28, 2005 page 660 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.6.2
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 13.11 shows this operation.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 13.11 Contention between TCNT Write and Increment
Rev. 5.00 Mar 28, 2005 page 661 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.6.3
Contention between TCOR Write and Compare Match
During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is disabled even if a compare match event occurs.
Figure 13.12 shows this operation.
TCOR write cycle by CPU
T1
T2
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data
Compare match signal
Disabled
Figure 13.12 Contention between TCOR Write and Compare Match
Rev. 5.00 Mar 28, 2005 page 662 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
13.6.4
Contention between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 13.4.
Table 13.4 Timer Output Priorities
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
13.6.5
Low
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 13.5 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in
table 13.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge. This increments TCNT.
The erroneous incrementation can also happen when switching between internal and external
clocks.
Rev. 5.00 Mar 28, 2005 page 663 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
Table 13.5 Switching of Internal Clock and TCNT Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
Switching from
low to low*1
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
CKS bit write
2
Switching from
2
low to high*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit write
3
Switching from
high to low*3
Clock before
switchover
Clock after
switchover
*4
TCNT clock
TCNT
N
N+1
CKS bit write
Rev. 5.00 Mar 28, 2005 page 664 of 1422
REJ09B0234-0500
N+2
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
No.
4
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
Switching from high
to high
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit write
Notes: 1.
2.
3.
4.
13.6.6
Includes switching from low to stop, and from stop to low.
Includes switching from stop to high.
Includes switching from high to stop.
Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or DMAC and DTC activation source. Interrupts should therefore
be disabled before entering module stop mode.
Rev. 5.00 Mar 28, 2005 page 665 of 1422
REJ09B0234-0500
Section 13 8-Bit Timers (TMR) (This function is not available in the H8S/2695)
Rev. 5.00 Mar 28, 2005 page 666 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
Section 14 14-Bit PWM D/A
(This function is not available in the H8S/2695)
14.1
Overview
The H8S/2633 Group has an on-chip 14-bit pulse-width modulator (PWM) with four output
channels.
Each channel can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
Both channels share the same counter (DACNT) and control register (DACR).
14.1.1
Features
The features of the 14-bit PWM D/A are listed below.
• The pulse is subdivided into multiple base cycles to reduce ripple.
• Two resolution settings and two base cycle settings are available
The resolution can be set equal to one or two system clock cycles. The base cycle can be set
equal to T × 64 or T × 256, where T is the resolution.
• Four operating rates
The two resolution settings and two base cycle settings combine to give a selection of four
operating rates.
Rev. 5.00 Mar 28, 2005 page 667 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
14.1.2
Block Diagram
Figure 14.1 shows a block diagram of the PWM D/A module.
Internal clock
φ
Internal data bus
φ/2
Clock
Clock selection
Bus interface
Basic cycle
compare-match A
PWM0
Fine-adjustment
pulse addition A
PWM1
Basic cycle
compare-match B
Fine-adjustment
pulse addition B
Comparator
A
DADRA
Comparator
B
DADRB
Control logic
Basic cycle overflow
DACNT
DACR
Module data bus
Legend:
DACR:
DADRA:
DADRB:
DACNT:
PWM D/A control register ( 6 bits)
PWM D/A data register A (15 bits)
PWM D/A data register B (15 bits)
PWM D/A counter (14 bits)
Figure 14.1 PWM D/A Block Diagram
Rev. 5.00 Mar 28, 2005 page 668 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
14.1.3
Pin Configuration
Table 14.1 lists the pins used by the PWM D/A module.
Table 14.1 Input and Output Pins
Name
Abbr.
I/O
Function
PWM output pin 0
PWM0
Output
PWM output, channel 0A
PWM output pin 1
PWM1
Output
PWM output, channel 0B
PWM output pin 2
PWM2
Output
PWM output, channel 1A
PWM output pin 3
PWM3
Output
PWM output, channel 1B
14.1.4
Register Configuration
Table 14.2 lists the registers of the PWM D/A module.
Table 14.2 Register Configuration
Channel
Name
Abbreviation
R/W
Initial value
Address*1
0
PWM D/A control register 0
DACR0
R/W
H'30
PWM D/A data register AH0
DADRAH0
R/W
H'FF
H'FDB8*2
H'FDB8*2
PWM D/A data register AL0
DADRAL0
R/W
H'FF
PWM D/A data register BH0
DADRBH0
R/W
H'FF
PWM D/A data register BL0
DADRBL0
R/W
H'FF
PWM D/A counter H0
DACNTH0
R/W
H'00
PWM D/A counter L0
DACNTL0
R/W
H'03
PWM D/A control register 1
DACR1
R/W
H'30
PWM D/A data register AH1
DADRAH1
R/W
H'FF
PWM D/A data register AL1
DADRAL1
R/W
H'FF
PWM D/A data register BH1
DADRBH1
R/W
H'FF
PWM D/A data register BL1
DADRBL1
R/W
H'FF
PWM D/A counter H1
DACNTH1
R/W
H'00
PWM D/A counter L1
DACNTL1
R/W
H'03
H'FDBE*2
H'FDBF*2
Module stop control register B
MSTPCRB
R/W
H'FF
H'FDE9
1
All
H'FDB9*2
H'FDBA*2
H'FDBB*2
H'FDBA*2
H'FDBB*2
H'FDBC*2
H'FDBC*2
H'FDBD*2
H'FDBE*2
H'FDBF*2
Notes: 1. Lower 16 bits of the address.
2. The same addresses are shared by DADRA and DACR, and by DADRB and DACNT.
Switching is performed by the REGS bit in DACNT or DADRB.
Rev. 5.00 Mar 28, 2005 page 669 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
14.2
Register Descriptions
14.2.1
PWM D/A Counter (DACNT)
DACNTH
Bit (CPU)
DACNTL
: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
8
9
10
11
12
13
—
—
BIT (Counter)
REGS
Initial value
:
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W —
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
R/W
DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse. The
input clock is selected by the clock select bit (CKS) in DACR. The CPU can read and write the
DACNT value, but since DACNT is a 16-bit register, data transfers between it and the CPU are
performed using a temporary register (TEMP). See section 14.3, Bus Master Interface, for details.
DACNT functions as the time base for both PWM D/A channels. When a channel operates with
14-bit precision, it uses all DACNT bits. When a channel operates with 12-bit precision, it uses the
lower 12 (counter) bits and ignores the upper two (counter) bits.
DACNT is initialized to H'0003 by a reset, in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode, and by the PWME bit.
Bit 1 of DACNTL (CPU) is not used, and is always read as 1.
DACNTL Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS
Description
0
DADRA and DADRB can be accessed
1
DACR and DACNT can be accessed
Rev. 5.00 Mar 28, 2005 page 670 of 1422
REJ09B0234-0500
(Initial value)
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
14.2.2
PWM D/A Data Registers A and B (DADRA and DADRB)
DADRH
Bit (CPU)
Bit (Data)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS
DADRA
Initial value : 1
R/W
1
1
1
1
1
1
1
1
1
1
1
1
1
1
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DADRB
—
1
—
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS
Initial value :
R/W
DADRL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
There are two 16-bit readable/writable PWM D/A data registers: DADRA and DADRB. DADRA
corresponds to PWM D/A channel A, and DADRB to PWM D/A channel B. The CPU can read
and write the PWM D/A data register values, but since DADRA and DADRB are 16-bit registers,
data transfers between them and the CPU are performed using a temporary register (TEMP). See
section 14.3, Bus Master Interface, for details.
The least significant (CPU) bit of DADRA is not used and is always read as 1.
DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 15 to 3—PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an
analog value is set in the upper 14 bits of the PWM D/A data register.
In each base cycle, the DACNT value is continually compared with these upper 14 bits to
determine the duty cycle of the output waveform, and to decide whether to output a fineadjustment pulse equal in width to the resolution. To enable this operation, the data register must
be set within a range that depends on the carrier frequency select bit (CFS). If the DADR value is
outside this range, the PWM output is held constant.
A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA0 and
DA1) cleared to 0 and writing the data to be converted in the upper 12 bits. The two lowest data
bits correspond to the two highest counter (DACNT) bits.
Rev. 5.00 Mar 28, 2005 page 671 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
Bit 1—Carrier Frequency Select (CFS)
Bit 1
CFS
Description
0
Base cycle = resolution (T) × 64
DADR range = H'0401 to H'FFFD
1
Base cycle = resolution (T) × 256
DADR range = H'0103 to H'FFFF
(Initial value)
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS
Description
0
DADRA and DADRB can be accessed
1
DACR and DACNT can be accessed
14.2.3
Bit
PWM D/A Control Register (DACR)
:
Initial value :
R/W
(Initial value)
:
7
6
5
4
3
2
1
0
TEST
PWME
—
—
OEB
OEA
OS
CKS
0
0
1
1
0
0
0
0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and
selects the output phase and operating speed.
DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Rev. 5.00 Mar 28, 2005 page 672 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
Bit 7—Test Mode (TEST): Selects test mode, which is used in testing the chip. Normally this bit
should be cleared to 0.
Bit 7
TEST
Description
0
PWM (D/A) in user state: normal operation
1
PWM (D/A) in test state: correct conversion results unobtainable
(Initial value)
Bit 6—PWM Enable (PWME): Starts or stops the PWM D/A counter (DACNT).
Bit 6
PWME
Description
0
DACNT operates as a 14-bit up-counter
1
DACNT halts at H'0003
(Initial value)
Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Output Enable B (OEB): Enables or disables output on PWM D/A channel B.
Bit 3
OEB
Description
0
PWM (D/A) channel B output (at the PWM1/PWM3 pin) is disabled
1
PWM (D/A) channel B output (at the PWM1/PWM3 pin) is enabled
(Initial value)
Bit 2—Output Enable A (OEA): Enables or disables output on PWM D/A channel A.
Bit 2
OEA
Description
0
PWM (D/A) channel A output (at the PWM0/PWM2 pin) is disabled
1
PWM (D/A) channel A output (at the PWM0/PWM2 pin) is enabled
(Initial value)
Rev. 5.00 Mar 28, 2005 page 673 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
Bit 1—Output Select (OS): Selects the phase of the PWM D/A output.
Bit 1
OS
Description
0
Direct PWM output
1
Inverted PWM output
(Initial value)
Bit 0—Clock Select (CKS): Selects the PWM D/A resolution. If the system clock (φ) frequency
is 10 MHz, resolutions of 100 ns and 200 ns can be selected.
Bit 0
CKS
Description
0
Operates at resolution (T) = system clock cycle time (tcyc)
1
Operates at resolution (T) = system clock cycle time (tcyc) × 2
14.2.4
Bit
(Initial value)
Module Stop Control Register B (MSTPCRB)
:
7
6
5
4
3
2
1
0
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
Initial value :
R/W
:
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSTPCRB is an 8-bit readable/writable register, and is used to perform module stop mode
control.
When the MSTPB2 is set to 1, at the end of the bus cycle 14-bit PWM timer 0 operation is halted
and a transition made to module stop mode. When the MSTPB1 is set to 1, at the end of the bus
cycle PWM timer 1 operation is halted and a transition made to module stop mode. See section
24.5, Module Stop Mode, for details.
MSTPCRB is initialized to H'FF by a power-on reset and in hardware standby mode. It is not
initialized in manual reset or software standby mode.
Rev. 5.00 Mar 28, 2005 page 674 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
Bit 2—Module Stop (MSTPB2): Specifies PWM0 module stop mode.
Bit 2
MSTPB2
Description
0
PWM0 module stop mode is cleared
1
PWM0 module stop mode is set
(Initial value)
Bit 1—Module Stop (MSTPB1): Specifies PWM1 module stop mode.
Bit 1
MSTPB1
Description
0
PWM1 module stop mode is cleared
1
PWM1 module stop mode is set
14.3
(Initial value)
Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the
on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these
registers, it therefore uses an 8-bit temporary register (TEMP).
These registers are written and read as follows (taking the example of the CPU interface).
• Write
When the upper byte is written, the upper-byte write data is stored in TEMP. Next, when the
lower byte is written, the lower-byte write data and TEMP value are combined, and the
combined 16-bit value is written in the register.
• Read
When the upper byte is read, the upper-byte value is transferred to the CPU and the lower-byte
value is transferred to TEMP. Next, when the lower byte is read, the lower-byte value in
TEMP is transferred to the CPU.
These registers should always be accessed 16 bits at a time (by word access or two consecutive
byte accesses), and the upper byte should always be accessed before the lower byte. Correct data
will not be transferred if only the upper byte or only the lower byte is accessed.
Figure 14.2 shows the data flow for access to DACNT. The other registers are accessed similarly.
Rev. 5.00 Mar 28, 2005 page 675 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
Example 1: Write to DACNT
MOV.W R0, @DACNT
; Write R0 contents to DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0
; Copy contents of DADRA to R0
Table 14.3 Read and Write Access Methods for 16-Bit Registers
Read
Write
Register Name
Word
Byte
Word
Byte
DADRA and DADRB
Yes
Yes
Yes
×
DACNT
Yes
×
Yes
×
Notes: Yes: Permitted type of access. Word access includes successive byte accesses to the
upper byte (first) and lower byte (second).
×:
This type of access may give incorrect results.
Rev. 5.00 Mar 28, 2005 page 676 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
Upper-Byte Write
CPU
(H'AA)
Upper byte
Module data bus
Bus
interface
TEMP
(H'AA)
DACNTH
(
)
DACNTL
(
)
Lower-Byte Write
CPU
(H'57)
Lower byte
Module data bus
Bus
interface
TEMP
(H'AA)
DACNTH
(H'AA)
DACNTL
(H'57)
Figure 14.2 (a) Access to DACNT (CPU Writes H'AA57 to DACNT)
Rev. 5.00 Mar 28, 2005 page 677 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
Upper-Byte Read
CPU
(H'AA)
Upper byte
Module data bus
Bus
interface
TEMP
(H'57)
DACNTH
(H'AA)
DACNTL
(H'57)
Lower-Byte Read
CPU
(H'57)
Lower byte
Module data bus
Bus
interface
TEMP
(H'57)
DACNTH
(
)
DACNTL
(
)
Figure 14.2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT)
Rev. 5.00 Mar 28, 2005 page 678 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
14.4
Operation
A PWM waveform like the one shown in figure 14.3 is output from the PWMX pin. When OS =
0, the value in DADR corresponds to the total width (TL) of the low (0) pulses output in one
conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output
waveform is inverted and the DADR value corresponds to the total width (TH) of the high (1)
output pulses. Figure 14.4 shows the types of waveform output available.
1 conversion cycle
(T × 214 (= 16384))
tf
Basic cycle
(T × 64 or T × 256)
tL
T: Resolution
m
TL = ∑ tLn (when OS = 0)
n=1
(When CFS = 0, m = 256; when CFS = 1, m = 64)
Figure 14.3 PWM D/A Operation
Table 14.4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution,
base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a
certain minimum value. Table 14.4 indicates the range of DADR settings that give an output
waveform like the one in figure 14.3, and lists the conversion cycle length when low-order DADR
bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.
Rev. 5.00 Mar 28, 2005 page 679 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
Table 14.4 Settings and Operation (Examples when φ = 10 MHz)
Fixed DADR Bits
Resolution
Base
Conversion TL (if OS = 0)
CKS T (µs)
CFS Cycle (µs) Cycle (µs) TH (if OS = 1)
Bit Data
Conversion
Precision
(Bits)
3 2 1 0 Cycle* (µs)
0
14
0.1
0
6.4
1638.4
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
1
25.6
1638.4
1. Always low (or high)
(DADR = H'0003 to
H'00FF)
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
1
0.2
0
12.8
3276.8
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
1
51.2
3276.8
1. Always low (or high)
(DADR = H'0003 to
H'00FF)
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
1638.4
12
0 0 409.6
10
0 0 0 0 102.4
14
1638.4
12
0 0 409.6
10
0 0 0 0 102.4
14
3276.8
12
0 0 819.2
10
0 0 0 0 204.8
14
3276.8
12
0 0 819.2
10
0 0 0 0 204.8
Note: * This column indicates the conversion cycle when specific DADR bits are fixed.
Rev. 5.00 Mar 28, 2005 page 680 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
1. OS = 0 (DADR corresponds to TL)
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
tf1
tL1
tf2
tf255
tL2
tL3
tL255
tf256
tL256
tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64
tL1 + tL2 + tL3 + · · · + tL255 + tL256 = TL
Figure 14.4 (1) Output Waveform
b. CFS = 1 [base cycle = resolution (T) × 256]
1 conversion cycle
tf1
tL1
tf2
tL2
tf63
tL3
tL63
tf64
tL64
tf1 = tf2 = tf3 = · · · = tf63 = tf64 = T × 256
tL1 + tL2 + tL3 + · · · + tL63 + tL64 = TL
Figure 14.4 (2) Output Waveform
Rev. 5.00 Mar 28, 2005 page 681 of 1422
REJ09B0234-0500
Section 14 14-Bit PWM D/A (This function is not available in the H8S/2695)
2. OS = 1 (DADR corresponds to TH)
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
tf1
tH1
tf2
tf255
tH2
tH3
tH255
tf256
tH256
tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64
tH1 + tH2 + tH3 + · · · + tH255 + tH256 = TH
Figure 14.4 (3) Output Waveform
b. CFS = 1 [base cycle = resolution (T) × 256]
1 conversion cycle
tf1
tH1
tf2
tH2
tf63
tH3
tH63
tf1 = tf2 = tf3 = · · · = tf63 = tf64 = T × 256
tH1 + tH2 + tH3 + · · · + tH63 + tH64 = TH
Figure 14.4 (4) Output Waveform
Rev. 5.00 Mar 28, 2005 page 682 of 1422
REJ09B0234-0500
tf64
tH64
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
Section 15 Watchdog Timer
(WDT1 is not available in the H8S/2695)
15.1
Overview
The H8S/2633 Group has a two channel inbuilt watchdog timer, (WDT0/WDT1). The WDT
outputs an overflow signal (
) if a system crash prevents the CPU from writing to the
timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal
reset signal for the H8S/2633 Group.
WDTOVF
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
15.1.1
Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
•
output when in watchdog timer mode
If the counter overflows, the WDT outputs
. It is possible to select whether the LSI
is internally reset or an NMI interrupt is generated at the same time.
This internal reset is effected by either a power-on reset or a manual reset.
• Interrupt generation when in interval timer mode
If the counter overflows, the WDT generates an interval timer interrupt.
• WDT0 and WDT1 respectively allow eight and sixteen types of counter input clock to be
selected
The maximum interval of the WDT is given as a system clock cycle × 131072 × 256.
A subclock may be selected for the input counter of WDT1*.
Where a subclock is selected, the maximum interval is given as a subclock cycle × 256 × 256.
• Selected clock can be output from the BUZZ* output pin (WDT1)*
WDTOVF
WDTOVF
Note: * This function is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 683 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.1.2
Block Diagram
Figure 15.1 (a) and 15.1 (b) show a block diagram of the WDT.
Overflow
WDTOVF
Internal reset signal*1
Clock
Clock
select
Reset
control
RSTCSR
φ/2*2
φ/64*2
φ/128*2
φ/512*2
φ/2048*2
φ/8192*2
φ/32768*2
φ/131072*2
Internal clock
sources
TCNT
TSCR
Module bus
Bus
interface
WDT
Legend:
TCSR:
Timer control/status register
TCNT:
Timer counter
RSTCSR: Reset control/status register
Notes: 1. The type of internal reset signal depends on a register setting.
There are two alternative types of reset, namely power-on reset and manual reset.
2. The φ in the subactive and subsleep mode is φSUB.
Figure 15.1 (a) Block Diagram of WDT0
Rev. 5.00 Mar 28, 2005 page 684 of 1422
REJ09B0234-0500
Internal bus
WOVI 0
(interrupt request
signal)
Interrupt
control
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
Internal NMI
Interrupt request signal
Interrupt
control
Overflow
Clock
select
Clock
Reset
control
Internal reset signal*
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
BUZZ
TCNT
TCSR
Bus
interface
Module bus
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
Internal bus
WOVI1
(Interrupt request signal)
WDT
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
Note: * An internal reset signal can be generated by setting the register.
The reset thus generated is a power-on reset.
This function is not available in the H8S/2695.
Figure 15.1 (b) Block Diagram of WDT1
Rev. 5.00 Mar 28, 2005 page 685 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.1.3
Pin Configuration
Table 15.1 describes the WDT output pin.
Table 15.1 WDT Pin
Name
Symbol
Watchdog timer overflow
WDTOVF
Buzzer output
BUZZ*
I/O
Function
Output
Outputs counter overflow signal in watchdog
timer mode
Output
Outputs clock selected by watchdog timer
(WDT1)
Note: * This function is not available in the H8S/2695.
15.1.4
Register Configuration
Table 15.2 summarizes the WDT register configuration. These registers control clock selection,
WDT mode switching, and the reset signal.
Table 15.2 WDT Registers
Address*1
Channel Name
0
1
All
Abbreviation R/W
Initial Value Write*2 Read
Timer control/status register 0 TCSR0
R/(W)*3 H'18
H'FF74 H'FF74
Timer counter 0
TCNT0
Reset control/status register
RSTCSR
H'FF76 H'FF77
Timer control/status register 1 TCSR1
R/W
H'00
R/(W)*3 H'1F
R/(W)*3 H'00
Timer counter 1
TCNT1
R/W
H'00
H'FFA2 H'FFA3
Pin function control register
PFCR
R/W
H'0D/H'00
H'FDEB
H'FF74 H'FF75
H'FFA2 H'FFA2
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 15.2.5, Notes on Register Access.
3. Only a write of 0 is permitted to bit 7, to clear the flag.
Rev. 5.00 Mar 28, 2005 page 686 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.2
Register Descriptions
15.2.1
Timer Counter (TCNT)
Bit
:
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
:
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), either the watchdog timer overflow signal (
) or an interval timer
interrupt (WOVI) is generated, depending on the mode selected by the WT/ bit in TCSR.
WDTOVF
IT
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see
section 15.2.5, Notes on Register Access.
Rev. 5.00 Mar 28, 2005 page 687 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.2.2
Timer Control/Status Register (TCSR)
TCSR0
Bit
:
7
OVF
Initial value :
R/W
:
0
R/(W)*
6
WT/
IT
5
4
3
2
1
0
TME
—
—
CKS2
CKS1
CKS0
0
0
1
1
0
0
0
R/W
R/W
—
—
R/W
R/W
R/W
5
4
3
2
1
0
TME
PSS
CKS2
CKS1
CKS0
Note: * Only a 0 can be written, for flag clearing.
TCSR1*1
Bit
:
7
OVF
Initial value :
R/W
:
0
R/(W)*2
6
WT/
IT
RST/
NMI
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: 1. In the case of the H8S/2695, only 0 should be written to the TCSR1 register.
2. Only a 0 can be written, for flag clearing.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not
initialized in software standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
section 15.2.5, Notes on Register Access.
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00.
Bit 7
OVF
Description
0
[Clearing conditions]
1
•
Cleared when 0 is written to the TME bit (Only applies to WDT1)
•
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
(Initial value)
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.
Rev. 5.00 Mar 28, 2005 page 688 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
In interval timer mode, to clear OVF flag in WOVI handling routine, reead TCSR when OVF = 1,
then write with 0 to OVF, as stated above.
When WOVI is masked and OVF flag is poling, if contention between OVF flag set and TCSR
read is occurred, OVF = 1 is read but OVF can not be cleared by writing with 0 to OVF.
In this case, reading TCSR when OVF = 1 two times meet the requirements of OVF clear
condition. Please read TCSR when OVF = 1 two times before writing with 0 to OVF.
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. When TCNT overflows, WDT0 generates the
signal when in watchdog
timer mode, or a WOVI interrupt request to the CPU when in interval timer mode. WDT1*
generates a reset or NMI interrupt request when in watchdog timer mode, or a WOVI interrupt
request to the CPU when in interval timer mode.
WDTOVF
Note: * This function is not available in the H8S/2695.
WDT0 Mode Select
WDT0
WT/IT
Description
0
Interval timer mode: WDT0 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows.
1
Watchdog timer mode: WDT0 outputs a
(Initial value)
WDTOVF signal when the TCNT overflows.*
Note: * For details on a TCNT overflow in watchdog timer mode, see section 15.2.3, Reset
Control/Status Register (RSTCSR).
WDT1* Mode Select
WDT1
WT/IT
Description
0
Interval timer mode: WDT1 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows.
1
Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from
the CPU when the TCNT overflows.
Note: * In the case of the H8S/2695, only 0 should be written to the WT/
register.
(Initial value)
IT bit in the TCSR1
Rev. 5.00 Mar 28, 2005 page 689 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME
Description
0
TCNT is initialized to H'00 and halted
1
TCNT counts
(Initial value)
WDT0 TCSR Bit 4—Reserved Bit: This bit is always read as 1 and cannot be modified.
Note: In the case of the H8S/2695, only 0 should be written to the TME bit in the TCSR1
register.
WDT1 TCSR Bit 4—Prescaler Select (PSS): This bit is used to select an input clock source for
the TCNT of WDT1.
See the descriptions of Clock Select 2 to 0 for details.
WDT1 TCSR
Bit 4
PSS
Description
0
The TCNT counts frequency-division clock pulses of the φ based
prescaler (PSM).
1
(Initial value)
The TCNT counts frequency-division clock pulses of the φ SUB-based prescaler
(PSS).
Note: In the case of the H8S/2695, only 0 should be written to the PSS bit in the TCSR1 register.
WDT0 TCSR Bit 3—Reserved Bit: This bit is always read as 1 and cannot be modified.
WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal
reset request and an NMI request when the TCNT overflows during the watchdog timer mode.
Bit 3
RTS/NMI
Description
0
NMI request.
1
Internal reset request.
Rev. 5.00 Mar 28, 2005 page 690 of 1422
REJ09B0234-0500
(Initial value)
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (φ) or subclock (φ SUB), for input to TCNT.
Note: In the case of the H8S/2695, only 0 should be written to the RST/
register.
NMI bit in the TCSR1
WDT0 Input Clock Select
Description
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Clock*2
Overflow Period*1 (where φ = 25 MHz)
0
0
0
φ/2 (Initial value)
20.4 µs
1
φ/64
655.3 µs
0
φ/128
1.3 ms
1
φ/512
5.2 ms
1
1
0
1
0
φ/2048
20.9 ms
1
φ/8192
83.8 ms
0
φ/32768
335.5 ms
1
φ/131072
1.34 s
Notes: 1. An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the occurrence of a TCNT overflow.
2. In the H8S/2633 Group, the φ in the subactive and subsleep mode is φSUB.
Rev. 5.00 Mar 28, 2005 page 691 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
WDT1*1 Input Clock Select
Description
Bit 4
PSS
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Clock
2
Overflow Period* (where φ = 25 MHz)
(where φ SUB = 32.768 kHz)
0
0
0
0
φ/2 (Initial value)
20.4 µs
1
φ/64
655.3 µs
0
φ/128
1.3 ms
1
φ/512
5.2 ms
1
1
0
1
1
0
0
1
1
0
1
0
φ/2048
20.9 ms
1
φ/8192
83.8 ms
0
φ/32768
335.5 ms
1
φ/131072
1.34 s
0
φSUB/2
15.6 ms
1
φSUB/4
31.3 ms
0
φSUB/8
62.5 ms
1
φSUB/16
125 ms
0
φSUB/32
250 ms
1
φSUB/64
500 ms
0
φSUB/128
1s
1
φSUB/256
2s
Notes: 1. WDT1 is not available in the H8S/2695.
2. An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the occurrence of a TCNT overflow.
Rev. 5.00 Mar 28, 2005 page 692 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.2.3
Bit
Reset Control/Status Register (RSTCSR)
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
WOVF
RSTE
RSTS
—
—
—
—
—
0
0
0
1
1
1
1
1
R/(W)*
R/W
R/W
—
—
—
—
—
Note: * Only 0 can be written, for flag clearing.
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the
reset signal caused by overflows.
RES pin, but not by the WDT internal
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
see section 15.2.5, Notes on Register Access.
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF
Description
0
[Clearing condition]
(Initial value)
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
1
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the
H8S/2633 Group if TCNT overflows during watchdog timer operation.
Bit 6
RSTE
Description
0
Reset signal is not generated if TCNT overflows*
1
Reset signal is generated if TCNT overflows
(Initial value)
Note: * The modules within the H8S/2633 Group are not reset, but TCNT and TCSR within the
WDT are reset.
Rev. 5.00 Mar 28, 2005 page 693 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows
during watchdog timer operation.
For details of the types of reset, see section 4, Exception Handling.
Bit 5
RSTS
Description
0
Power-on reset
1
Manual reset
(Initial value)
Bits 4 to 0—Reserved: These bits are always read as 1 and cannot be modified.
15.2.4
Bit
Pin Function Control Register (PFCR)
:
7
CSS07
Initial value :
R/W
:
6
5
4
CSS36 BUZZE* LCASS
3
2
1
0
AE3
AE2
AE1
AE0
0
0
0
0
1/0
1/0
0
1/0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * This function is not available in the H8S/2695.
PFCR is an 8-bit readable/writable register that performs address output control in external
expanded mode.
Only bit 5 is described here. For details of the other bits, see section 7.2.6, Pin Function Control
Register (PFCR).
Bit 5—BUZZ Output Enable (BUZZE): Enables or disables BUZZ output from the PF1 pin.
The WDT1 input clock selected with bits PSS and CKS2 to CKS0 is output as the BUZZ signal.
Bit 5
BUZZE
Description
0
Functions as PF1 I/O pin
1
Functions as BUZZ output pin
Note: In the case of the H8S/2695, only 0 should be written to the BUZZ bit.
Rev. 5.00 Mar 28, 2005 page 694 of 1422
REJ09B0234-0500
(Initial value)
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.2.5
Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction.
They cannot be written to with byte instructions.
Figure 15.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the written word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
TCNT write
15
8 7
H'5A
Address: H'FF74
0
Write data
TCSR write
15
Address: H'FF74
8 7
H'A5
0
Write data
Figure 15.2 Format of Data Written to TCNT and TCSR (WDT0)
Rev. 5.00 Mar 28, 2005 page 695 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address
H'FF76. It cannot be written to with byte instructions.
Figure 15.3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF
bit differs from that for writing to the RSTE and RSTS bits.
To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the
lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write
to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the
write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits,
but has no effect on the WOVF bit.
Writing 0 to WOVF bit
15
8 7
H'A5
Address: H'FF76
0
H'00
Writing to RSTE and RSTS bits
15
Address: H'FF76
8 7
H'5A
0
Write data
Figure 15.3 Format of Data Written to RSTCSR (WDT0)
Reading TCNT, TCSR, and RSTCSR (WDT0): These registers are read in the same way as
other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for
RSTCSR.
Rev. 5.00 Mar 28, 2005 page 696 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.3
Operation
15.3.1
Watchdog Timer Operation
IT
To use the WDT as a watchdog timer, set the WT/ bit in TCSR and TME bit to 1. Software
must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before
overflows occurs. This ensures that TCNT does not overflow while the system is operating
normally. If TCNT overflows without being rewritten because of a system crash or other error, in
the WDT0 the
signal is output. This is shown in figure 15.4 (a). This
signal
signal is output for 132 states when RSTE = 1, and
can be used to reset the system. The
for 130 states when RSTE = 0.
WDTOVF
WDTOVF
WDTOVF
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2633
Group internally is generated at the same time as the
signal. This reset can be selected
as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The
internal reset signal is output for 518 states.
WDTOVF
RES
pin occurs at the same time as a reset caused by a
If a reset caused by a signal input to the
pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
WDT overflow, the
RES
In the case of WDT1, the chip is reset, or an NMI interrupt request is generated, for 516 system
clock periods (516φ) (515 or 516 states when the clock source is φSUB (PSS = 1)). This is
illustrated in figure 15.4 (b).
An NMI request from the watchdog timer and an interrupt request from the NMI pin are both
treated as having the same vector. So, avoid handling an NMI request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
Rev. 5.00 Mar 28, 2005 page 697 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
TCNT count
Overflow
H'FF
Time
H'00
WT/IT=1
TME=1
H'00 written
to TCNT
WT/IT=1
TME=1
WOVF=1
WDTOVF and
internal reset are
generated
H'00 written
to TCNT
WDTOVF signal
132 states*2
Internal reset signal*1
518 states
Legend:
WT/IT: Timer mode select bit
TME: Timer enable bit
Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1.
2. 130 states when the RSTE bit is cleared to 0.
Figure 15.4 (a) WDT0 Watchdog Timer Operation
TCNT value
Overflow
H'FF
Time
H'00
WT/IT= 1
TME= 1
Write H'00
to TCNT
WOVF= 1*
WT/IT= 1 Write H'00
TME= 1 to TCNT
Occurrence
of internal reset
Internal
reset signal
515/516 states
Legend:
WT/IT: Timer Mode Select bit
TME: Timer Enable bit
Note: * The WOVF bit is set to 1 and then cleared to 0 by an internal reset.
Figure 15.4 (b) WDT1 Operation in Watchdog Timer Mode
Rev. 5.00 Mar 28, 2005 page 698 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.3.2
Interval Timer Operation
IT
To use the WDT as an interval timer, clear the WT/ bit in TCSR to 0 and set the TME bit to 1.
An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the
WDT is operating as an interval timer, as shown in figure 15.5. This function can be used to
generate interrupt requests at regular intervals.
TCNT count
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WT/IT=0
TME=1
WOVI
WOVI
WOVI
WOVI
Legend:
WOVI: Interval timer interrupt request generation
Figure 15.5 Interval Timer Operation
15.3.3
Timing of Setting Overflow Flag (OVF)
The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an
interval timer interrupt (WOVI) is requested. This timing is shown in figure 15.6.
With WDT1*, the OVF bit of the TCSR is set to 1 and a simultaneous NMI interrupt is requested
when the TCNT overflows if the NMI request has been chosen in the watchdog timer mode.
Note: * WDT1 is not available in the H8S/2695.
Rev. 5.00 Mar 28, 2005 page 699 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
φ
TCNT
H'FF
H'00
Overflow signal
(internal signal)
OVF
Figure 15.6 Timing of Setting of OVF
15.3.4
Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At
signal goes low. If TCNT overflows while the RSTE bit in RSTCSR
the same time, the
is set to 1, an internal reset signal is generated for the entire H8S/2633 Group chip. Figure 15.7
shows the timing in this case.
WDTOVF
φ
TCNT
H'FF
H'00
Overflow signal
(internal signal)
WOVF
132 states
WDTOVF signal
Internal reset
signal
518 states (WDT0)
515/516 states (WDT1)
Figure 15.7 Timing of Setting of WOVF
Rev. 5.00 Mar 28, 2005 page 700 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.4
Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated
when a TCNT overflow occurs.
15.5
Usage Notes
15.5.1
Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 15.8 shows this operation.
TCNT write cycle
T1
T2
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 15.8 Contention between TCNT Write and Increment
Rev. 5.00 Mar 28, 2005 page 701 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.5.2
Changing Value of PSS and CKS2 to CKS0
If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could
occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0)
before changing the value of bits PSS and CKS2 to CKS0.
15.5.3
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
WDTOVF Signal
If the WDTOVF output signal is input to the RES pin of the H8S/2633 Group, the H8S/2633
Group will not be initialized correctly. Make sure that the WDTOVF signal is not input logically
to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown
15.5.4
System Reset by
in figure 15.9.
H8S/2633 Group
RES
Reset input
Reset signal to entire system
Figure 15.9 Circuit for System Reset by
15.5.5
WDTOVF
WDTOVF Signal (Example)
Internal Reset in Watchdog Timer Mode
The H8S/2633 Group is not reset internally if TCNT overflows while the RSTE bit is cleared to 0
during watchdog timer operation, but TCNT and TCSR of the WDT are reset.
WDTOVF
signal is low. Also note
TCNT, TCSR, and RSTCSR cannot be written to while the
that a read of the WOVF flag is not recognized during this period. To clear the WOVF falg,
signal goes high, then write 0 to the WOVF flag.
therefore, read RSTCSR after the
WDTOVF
Rev. 5.00 Mar 28, 2005 page 702 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
15.5.6
OVF Flag Clearing in Interval Timer Mode
When the OVF Flag setting conflicts with the OVF flag reading in interval timer mode, writing 0
to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there
is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is
polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before
writing 0 to the OVF bit to clear the flag.
Rev. 5.00 Mar 28, 2005 page 703 of 1422
REJ09B0234-0500
Section 15 Watchdog Timer (WDT1 is not available in the H8S/2695)
Rev. 5.00 Mar 28, 2005 page 704 of 1422
REJ09B0234-0500
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function)
Section 16 Serial Communication Interface (SCI, IrDA)
(The H8S/2695 is not equipped with an IrDA function)
16.1
Overview
The H8S/2633 is equipped with 5 independent serial communication interface (SCI) channels. The
SCI can handle both asynchronous and clocked synchronous serial communication. A function is
also provided for serial communication between processors (multiprocessor communication
function).
One of the five SCI channels is capable of sending and receiving IrDA communications
waveforms (based on IrDA Version 1.0).
16.1.1
Features
SCI features are listed below.
• Choice of asynchronous or clocked synchronous serial communication mode
Asynchronous mode
 Serial data communication executed using asynchronous system in which synchronization
is achieved character by character
Serial data communication can be carried out with standard asynchronous communication
chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous
Communication Interface Adapter (ACIA)
 A multiprocessor communication function is provided that enables serial data
communication with a number of processors
 Choice of 12 serial data transfer formats
Data length:
7 or 8 bits
Stop bit length:
1 or 2 bits
Parity:
Even, odd, or none
Multiprocessor bit: 1 or 0
 Receive error detection: Parity, overrun, and framing errors
 Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
Rev. 5.00 Mar 28, 2005 page 705 of 1422
REJ09B0234-0500
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function)
Clocked Synchronous mode
 Serial data communication synchronized with a clock
Serial data communication can be carried out with other chips that have a synchronous
communication function
 One serial data transfer format
Data length: 8 bits
 Receive error detection: Overrun errors detected
• Full-duplex communication capability
 The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
 Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
• Choice of LSB-first or MSB-first transfer
 Can be selected regardless of the communication mode* (except in the case of
asynchronous mode 7-bit data)
Note: * Descriptions in this section refer to LSB-first transfer.
• On-chip baud rate generator allows any bit rate to be selected
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
• Four interrupt sources
 Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive
error — that can issue requests independently
 The transmit-data-empty interrupt and receive data full interrupts can activate the DMA
controller (DMAC) or data transfer controller (DTC) to execute data transfer
• Module stop mode can be set
 As the initial setting, SCI operation is halted. Register access is enabled by exiting module
stop mode
Rev. 5.00 Mar 28, 2005 page 706 of 1422
REJ09B0234-0500
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function)
16.1.2
Block Diagram
Bus interface
Figure 16.1 shows a block diagram of the SCI.
Module data bus
RxD
TxD
RDR
TDR
RSR
TSR
BRR
φ
Baud rate
generator
Transmission/
reception control
Parity generation
Parity check
SCK
Legend
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
SCMR:
BRR:
SCMR
SSR
SCR
SMR
Internal
data bus
φ/4
φ/16
φ/64
Clock
External clock
TEI
TXI
RXI
ERI
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Smart card mode register
Bit rate register
Figure 16.1 Block Diagram of SCI
Rev. 5.00 Mar 28, 2005 page 707 of 1422
REJ09B0234-0500
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function)
16.1.3
Pin Configuration
Table 16.1 shows the serial pins for each SCI channel.
Table 16.1 SCI Pins
Channel
Pin Name
Symbol*
I/O
Function
0
Serial clock pin 0
SCK0
I/O
SCI0 clock input/output
Receive data pin 0
RxD0/IrRxD
Input
SCI0 receive data input (normal/IrDA)
Transmit data pin 0
TxD0/IrTxD
Output
SCI0 transmit data output (normal/IrDA)
Serial clock pin 1
SCK1
I/O
SCI1 clock input/output
Receive data pin 1
RxD1
Input
SCI1 receive data input
Transmit data pin 1
TxD1
Output
SCI1 transmit data output
Serial clock pin 2
SCK2
I/O
SCI2 clock input/output
Receive data pin 2
RxD2
Input
SCI2 receive data input
1
2
3
4
Transmit data pin 2
TxD2
Output
SCI2 transmit data output
Serial clock pin 3
SCK3
I/O
SCI3 clock input/output
Receive data pin 3
RxD3
Input
SCI3 receive data input
Transmit data pin 3
TxD3
Output
SCI3 transmit data output
Serial clock pin 4
SCK4
I/O
SCI4 clock input/output
Receive data pin 4
RxD4
Input
SCI4 receive data input
Transmit data pin 4
TxD4
Output
SCI4 transmit data output
Note: * Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel
designation.
Rev. 5.00 Mar 28, 2005 page 708 of 1422
REJ09B0234-0500
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function)
16.1.4
Register Configuration
The SCI has the internal registers shown in table 16.2. These registers are used to specify
asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control
transmitter/receiver.
Table 16.2 SCI Registers
Channel
Name
Abbreviation
R/W
Initial Value
Address*1
0
Serial mode register 0
SMR0
R/W
H'00
Bit rate register 0
BRR0
R/W
H'FF
H'FF78*3
H'FF79*3
Serial control register 0
SCR0
R/W
H'00
Transmit data register 0
TDR0
R/W
Serial status register 0
SSR0
H'FF
2
*
R/(W)
H'84
H'FF7A*3
H'FF7B*3
Receive data register 0
RDR0
R
H'00
H'FF7C*3
H'FF7D*3
Smart card mode register 0
SCMR0
R/W
H'F2
H'FF7E*3
IrDA control register
IrCR
R/W
H'00
Serial mode register 1
SMR1
R/W
H'00
H'FDB0
H'FF80*3
Bit rate register 1
BRR1
R/W
H'FF
Serial control register 1
SCR1
R/W
H'00
Transmit data register 1
TDR1
R/W
H'FF
Serial status register 1
SSR1
R/(W)*2 H'84
Receive data register 1
RDR1
R
H'00
Smart card mode register 1
SCMR1
R/W
H'F2
H'FF85*3
H'FF86*3
Serial mode register 2
SMR2
R/W
H'00
H'FF88
1
2
H'FF81*3
H'FF82*3
H'FF83*3
H'FF84*3
Bit rate register 2
BRR2
R/W
H'FF
H'FF89
Serial control register 2
SCR2
R/W
H'00
H'FF8A
Transmit data register 2
TDR2
R/W
H'FF
H'FF8B
*2
Serial status register 2
SSR2
R/(W)
H'84
H'FF8C
Receive data register 2
RDR2
R
H'00
H'FF8D
Smart card mode register 2
SCMR2
R/W
H'F2
H'FF8E
Rev. 5.00 Mar 28, 2005 page 709 of 1422
REJ09B0234-0500
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function)
Channel
Name
Abbreviation
R/W
Initial Value
Address*1
3
Serial mode register 3
SMR3
R/W
H'00
H'FDD0
Bit rate register 3
BRR3
R/W
H'FF
H'FDD1
4
All
Serial control register 3
SCR3
R/W
H'00
H'FDD2
Transmit data register 3
TDR3
R/W
H'FF
H'FDD3
Serial status register 3
SSR3
R/(W)*2 H'84
H'FDD4
Receive data register 3
RDR3
R
H'00
H'FDD5
Smart card mode register 3
SCMR3
R/W
H'F2
H'FDD6
Serial mode register 4
SMR4
R/W
H'00
H'FDD8
Bit rate register 4
BRR4
R/W
H'FF
H'FDD9
Serial control register 4
SCR4
R/W
H'00
H'FDDA
Transmit data register 4
TDR4
R/W
H'FDDB
Serial status register 4
SSR4
H'FF
2
*
R/(W)
H'84
Receive data register 4
RDR4
R
H'00
H'FDDD
Smart card mode register 4
SCMR4
R/W
H'F2
H'FDDE
Module stop control register B
MSTPCRB
R/W
H'FF
H'FDE9
Module stop control register C
MSTPCRC
R/W
H'FF
H'FDEA
H'FDDC
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
3. Some of the SCI registers are allocated to the same addresses as other registers. The
IICE bit of the serial timer control register X (SCRX) selects the respective registers.
Rev. 5.00 Mar 28, 2005 page 710 of 1422
REJ09B0234-0500
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function)
16.2
Register Descriptions
16.2.1
Receive Shift Register (RSR)
Bit
:
7
6
5
4
3
2
1
0
R/W
:
—
—
—
—
—
—
—
—
RSR is a register used to receive serial data.
The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to RDR automatically.
RSR cannot be directly read or written to by the CPU.
16.2.2
Bit
Receive Data Register (RDR)
:
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
:
RDR is a register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received serial data from RSR to
RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled.
Since RSR and RDR function as a double buffer in this way, enables continuous receive
operations to be performed.
RDR is a read-only register, and cannot be written to by the CPU.
RDR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, and subsleep
mode or module stop mode.
Rev. 5.00 Mar 28, 2005 page 711 of 1422
REJ09B0234-0500
Section 16 Serial Communication Interface (SCI, IrDA) (The H8S/2695 is not equipped with an IrDA function)
16.2.3
Transmit Shift Register (TSR)
Bit
:
7
6
5
4
3
2
1
0
R/W
:
—
—
—
—
—
—
—
—
TSR is a register used to transmit serial data.
To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then
se