To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
DESCRIPTION
M35062-XXXSP is CATV screen display control IC which can display
40 (horizontal) × 17 (vertical). It has built-in SYRAM which can be
used with character ROM.
It uses a silicon gate CMOS process and M35062-XXXSP housed in
a small 32-pin shrink DIP package. For M35062-001SP that is a standard ROM version of M35062-XXXSP, the character pattern is also
mentioned.
• Screen composition ................................. 40 characters × 17 lines
•
•
•
•
•
•
•
•
•
•
•
•
•
Note: Superimpose coloring is available. (NTSC, PAL, M-PAL)
REV.1.2
1
32
CS
AD1
2
31
SCK
AD2
3
30
TESTA
AD3
4
29
P5
AD4
5
28
P4
AD5
AD6
6
27
P3
26
P2
AD7
8
25
P1
AC
9
24
P0
23
PHIN
22
OSCIN
21
OSCOUT
20
LP2
7
VDD1
10
VSS
11
XXXSP
•
•
•
(at scrolling ............................................. 40 characters × 16 lines)
Number of characters displayed ................................... 680 (Max.)
Character composition ..................................... 12 × 13 dot matrix
Characters available character ROM ................ 128 characters
SYRAM ................................ 7 characters
Character sizes available horizontal ..................... 2 (once, twice)
vertical ......................... 2 (once, twice)
setting by every line
Display locations available
Horizontal direction ................................................ 486 locations
Vertical direction .................................................... 235 locations
Blinking ................................................................... character units
Cycle .... approximately 1 second, or approximately 0.5 seconds
(per screen)
Duty ................................................................ 25%, 50% or 75%
(per screen)
Data input ............................................................. 8-bit parallel × 3
Coloring Character coloring .......... 8 colors choices per character
(Note)
Background coloring ...... 8 colors choices per character
(Note)
Raster coloring .................. 8 colors choices per screen
Blanking
Character size blanking
Border size blanking
Matrix-outline
Halftone blanking
Can be set by every line
General-purpose output ports
Combined port output ............ 6
(switching to RGB output)
RAM erase ............................. Display RAM erasing by every line
SYRAM erasing separately
Scrolling ............ Bit by bit smooth scroll implemented by software
Composite synchronizating signal generation .................... Built-in
(PAL, NTSC, M-PAL)
Display oscillation circuit .................................................... Built-in
Synchronous separation circuit .......................................... Built-in
Synchronous correction circuit ........................................... Built-in
AD0
M35062
FEATURES
PIN CONFIGURATION (TOP VIEW)
CVIDEO
12
LECHA
13
LEBK
14
19
V DD2
CVIN
15
18
LP1
HOR
16
17
VREF
Outline
32P4B
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
PIN DESCRIPTION
Symbol
AD0 to AD7
Pin name
Parallel data input
Input/Output
Input
__
AC
Auto-clear input
Input
VDD1
VSS
CVIDEO
Power pin
Earthing pin
Composite video
signal output
—
—
Output
LECHA
LEBK
CVIN
VREF
Character level input
Black level input
Composite video
signal input
Synchronous signal
input
Slice level input
LP1
VDD2
LP2
Filter output 1
Power pin
Filter output 2
Output
—
Output
OSCOUT
fsc I/O pin for
synchronous signal
generating
Output
PHASE control input
Port output
Port output
Port output
Port output
Port output
Port output
Test input
Clock input for data
input
Chip select input
Input
Output
Output
Output
Output
Output
Output
Input
Input
HOR
OSCIN
PHIN
P0
P1
P2
P3
P4
P5
TESTA
SCK
CS
Input
Input
Input
Input
Input
Input
Input
Function
These input pins determine address and data of display control register and display
data memory by 8-bit parallel. Hysteresis input is required.
When this input pin transitions from “H” to “L”, the device is reset. Built-in a pull-up
resistor. Hysteresis input is required.
Digital power supply pin. This pin must be connected to +5 V.
Ground pin. This pin must be connected to 0 V.
This pin outputs the composite video signal. The output signal is 2 VP-P. In superimpose mode, this pin’s signal consists of the OSD signal combined with the input
composite signal CVIN.
This input pin is used for controlling the “white” character color level of the OSD signal.
This input pin is used for controlling the “black” character color level of the OSD signal.
This pin inputs the external composite video signal. In superimpose mode, this pin’s
signal consists of the OSD signal combined with the external composite video signal.
This pin inputs the external composite video signal. This pin inputs the clamped
external video signal, sync-sep internal.
This input pin is used to determine the slice voltage for extracting the sync signals from
the video composite signal.
This is filter output pin 1.
Analog power supply pin. This pin must be connected to +5 V.
This is filter output pin 2.
These are the sub-carrier oscillation (fsc) input pins for synchronous signal generating.
NTSC (3.580 MHz), PAL (4.434 MHz), M-PAL (3.576 MHz) (Note).
Control the phase changing by scanning line by PAL, M-PAL method.
This output pin can be configured to port P0 or YM output.
This output pin can be configured to port P1 or BLNK output.
This output pin can be configured to port P2 or B output.
This output pin can be configured to port P3 or G output.
This output pin can be configured to port P4 or R output.
This output pin can be configured to port P5 or CSYN output.
Factory test pin. The pin must be connected to GND.
This pin is enabled when the CS pin is “L”. Data input to pins AD0 to AD7 is latched at
the rising edge of this signal. This pin is hysteresis input.
This is chip selection input pin. When this pin is “L”, transmission is enabled. This pin is
hysteresis input.
Note: fsc signal input ……refer to “note on when fsc signal input”.
2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
8
7
6
5
4
3
2
1
Write access
control
Display
position
detection
19
VDD2
10
VDD1
VSS
11
9
AC
Shift circuit
Blinking
SYRAM
Display RAM
Display control
Display control register
25
26
27
P0 P1 P2 P3
/YM /BLNK /B /G
24
P4
/R
28
Port output circuit
Sync
generation
Timing
generator
30
32
Read access
control
TESTA
CS
Character
Pattern ROM
Input control circuit
31
SCK
BLOCK DIAGRAM
29
P5
/CSYN
17
Video signal
output
NTSC, PAL,
M-PAL
Quadruple
frequency circuit
Synchronous
correction circuit
VSYNC
separation
Sync
separation
16
HOR VREF
LECHA
CVIDEO
12
LEBK
14
13
CVIN
PHIN
23
15
LP2
20
OSCIN
OSCOUT
21
22
LP1
18
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
3
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
MEMORY CONSTRUCTION
The internal circuit is reset and all display control registers (address
2A816 to 2B016) are set to “0”. The memory constitution of display
RAM and register is shown in Figure 1 and the memory constitution
of SYRAM is shown in Figure 2.
Address 00016 to 2A716 are assigned to the display RAM, 2A816 to
2B016 are assigned to the display control registers and 30016 to
36C16 are assigned to SYRAM.
Table 1 The memory constitution of display RAM and register
addDA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 DAF
ress
~
00016 SB
SG
SR
SY color setting
0
0
0
0
0
0
0
0
2A716 SB
SG
2A816
TEST TEST TEST
3
2
1
BLINK
–
–
3
TEST
–
–
12
TEST
TEST
–
26
25
–
SR
0
DAE
DAD
DAC
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
SYC2 SYC1 SYC0 BB
BG
BR BLINK CB
CG
CR
0
C6
C5
C4
C3
C2
C1
C0
Raster color setting BLINK Character color setting
0
C1
C0
SYRAM setting
SYC2 SYC1 SYC0 BB
TEST TEST TEST
10
0
11
BLINK BLINK BLINK
0
2
1
TEST
HIDE
EQP
20
PHASE PHASE PHASE
2
1
0
LINE
LINE
LINE
–
– LBLACK
B
G
R
TEST TEST SERS –
–
–
0
23
22
BG
BR BLINK CB
–
CG
CR
0
Character setting
C6
C5
C4
C3
C2
HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0
HSZ HSZ HSZ
14
13
12
VSZ
VSZ
VSZ
2AA16 –
14
13
12
DSP0
DSP0
DSP0
2AB16 –
14
13
12
DSP1
DSP1
DSP1
2AC16 –
14
13
12
ERS
ERS
ERS
2AD16 –
14
13
12
SEND
SST
SST
–
–
2AE16 –
–
–
0
4
3
SRAND
SRAND
SRAND
2AF16 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 ALL24
2
1
0
__
TEST TEST TEST TEST LEVEL LEVEL LEVEL INT ___
PAL
MPAL PALH
2B016 –
19
18
17
24
0
NON NTSC
2
1
2A916
DAB
HSZ
16
VSZ
16
DSP0
16
DSP1
16
ERS
16
SEND SEND SEND
2
4
3
HSZ
15
VSZ
15
DSP0
15
DSP1
15
ERS
15
SEND
1
HSZ
11
VSZ
11
DSP0
11
DSP1
11
ERS
11
SST
2
PTD
5
TEST
16
HSZ
10
VSZ
10
DSP0
10
DSP1
10
ERS
10
SST
1
PTD
4
TEST
15
HSZ
9
VSZ
9
DSP0
09
DSP1
09
ERS
9
SST
0
PTD
3
HSZ
8
VSZ
8
DSP0
08
DSP1
08
ERS
8
SLIN
4
PTD
2
HSZ
7
VSZ
7
DSP0
07
DSP1
07
ERS
7
SLIN
3
PTD
1
SEPV1 SEPV0 BLK
HSZ
6
VSZ
6
DSP0
06
DSP1
06
ERS
6
SLIN
2
PTD
0
–
HSZ
5
VSZ
5
DSP0
05
DSP1
05
ERS
5
SLIN
1
PTC
5
DSP
ONV
HSZ
4
VSZ
4
DSP0
04
DSP1
04
ERS
4
SLIN
0
PTC
4
DSP
ON
HSZ
3
VSZ
3
DSP0
03
DSP1
03
ERS
3
SBIT
3
PTC
3
–
HSZ
2
VSZ
2
DSP0
02
DSP1
02
ERS
2
SBIT
2
PTC
2
SEL
COR
HSZ
1
VSZ
1
DSP0
01
DSP1
01
ERS
1
SBIT
1
PTC
1
SCOR EX
TESTn (n = number) is MITSUBISHI test memory. Set 0 to all bits.
…~
4
DA0
SYEX
S00B
S00A
S009
S008
S007
S006
S005
S004
S003
S002
S001
S000
…
…
…
…
…
…
…
…
…
…
…
…
SYEX
SYEX
S00B
S01B
S00A
S01A
S009
S019
S008
S018
S007
S017
S006
S016
S005
S015
S004
S014
S003
S013
S002
S012
S001
S011
S000
S010
…
…
…
…
…
SYEX
S01B
S01A
S019
S018
S017
SYEX
S05B
S05A
S059
S058
S057
S056
…
…
…
…
…
…
…
…
…
…
…
…
SYEX
SYEX
S05B
S06B
S05A
S06A
S059
S069
S058
S068
S057
S067
S056
S066
S055
S065
S054
S064
S053
S063
S052
S062
S051
S061
S050
S060
…
…
…
…
…
…
…
…
…
…
…
SYEX
S06B
S06A
S069
S068
S067
S066
S065
S064
S063
S062
S061
S060
S016
S015
S014
S013
S012
S011
S010
S055
S054
S053
S052
S051
S050
~
: Name or value changes by definite ratio.
: The same name or value continues.
SYRAM code
0016
0116
~
…
DA1
…
DA2
…
DA3
…
DA4
…
DA5
…
DA6
…
DA7
…
0
DA8
…
36C16
DA9
…
~
35C16
36016
DAA
…
…
0
DAB
…
~
~
~
~
35016
DAC
…
Table 2 The memory constitution of SYRAM
addDA17 to DAD
ress
30016
0
30C16
31016
0
31C16
0516
0616
HSZ
0
VSZ
0
DSP0
00
DSP1
00
ERS
0
SBIT
0
PTC
0
The hexadecimal numbers in the boxes show the display RAM address
Line 16 280 281 282 283 284 285 286 287 288 289 28A 28B 28C 28D 28E 28F 290 291 292 293 294 295 296 297 298 299 29A 29B 29C 29D 29E 29F 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
Line 15 258 259 25A 25B 25C 25D 25E 25F 260 261 262 263 264 265 266 267 268 269 26A 26B 26C 26D 26E 26F 270 271 272 273 274 275 276 277 278 279 27A 27B 27C 27D 27E 27F
230 231 232 233 234 235 236 237 238 239 23A 23B 23C 23D 23E 23F 240 241 242 243 244 245 246 247 248 249 24A 24B 24C 24D 24E 24F 250 251 252 253 254 255 256 257
208 209 20A 20B 20C 20D 20E 20F 210 211 212 213 214 215 216 217 218 219 21A 21B 21C 21D 21E 21F 220 221 222 223 224 225 226 227 228 229 22A 22B 22C 22D 22E 22F
1E0 1E1 1E2 1E3 1E4 1E5 1E6 1E7 1E8 1E9 1EA 1EB 1EC 1ED 1EE 1EF 1F0 1F1 1F2 1F3 1F4 1F5 1F6 1F7 1F8 1F9 1FA 1FB 1FC 1FD 1FE 1FF 200 201 202 203 204 205 206 207
1B8 1B9 1BA 1BB 1BC 1BD 1BE 1BF 1C0 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 1C9 1CA 1CB 1CC 1CD 1CE 1CF 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1DA 1DB 1DC 1DD 1DE 1DF
190 191 192 193 194 195 196 197 198 199 19A 19B 19C 19D 19E 19F 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1AA 1AB 1AC 1AD 1AE 1AF 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
168 169 16A 16B 16C 16D 16E 16F 170 171 172 173 174 175 176 177 178 179 17A 17B 17C 17D 17E 17F 180 181 182 183 184 185 186 187 188 189 18A 18B 18C 18D 18E 18F
140 141 142 143 144 145 146 147 148 149 14A 14B 14C 14D 14E 14F 150 151 152 153 154 155 156 157 158 159 15A 15B 15C 15D 15E 15F 160 161 162 163 164 165 166 167
118 119 11A 11B 11C 11D 11E 11F 120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F
0F0 0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 0F9 0FA 0FB 0FC 0FD 0FE 0FF 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117
0C8 0C9 0CA 0CB 0CC 0CD 0CE 0CF 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0DA 0DB 0DC 0DD 0DE 0DF 0E0 0E1 0E2 0E3 0E4 0E5 0E6 0E7 0E8 0E9 0EA 0EB 0EC 0ED 0EE 0EF
0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF 0C0 0C1 0C2 0C3 0C4 0C5 0C6 0C7
078 079 07A 07B 07C 07D 07E 07F 080 081 082 083 084 085 086 087 088 089 08A 08B 08C 08D 08E 08F 090 091 092 093 094 095 096 097 098 099 09A 09B 09C 09D 09E 09F
050 051 052 053 054 055 056 057 058 059 05A 05B 05C 05D 05E 05F 060 061 062 063 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070 071 072 073 074 075 076 077
Line 1 028 029 02A 02B 02C 02D 02E 02F 030 031 032 033 034 035 036 037 038 039 03A 03B 03C 03D 03E 03F 040 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 04E 04F
Line 0 000 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 017 018 019 01A 01B 01C 01D 01E 01F 020 021 022 023 024 025 026 027
Row
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
SCREEN CONSTITUTION
The screen lines and rows are determined from each address of the display RAM.
The screen constitution is shown in Figure 1.
Fig. 1 Screen constitution
5
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
REGISTERS DESCRIPTION
(1) Address 2A816
Register
0
VP0
1
VP1
2
VP2
3
VP3
4
VP4
5
VP5
6
VP6
7
VP7
8
HP0
9
HP1
A
B
HP3
C
HP4
D
HP5
E
HP6
F
HP7
10
HP8
11
TEST10
12
TEST11
13
TEST0
14
TEST1
15
TEST2
16
TEST3
17
—
Note: The mark
6
HP2
Status
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Contents
Function
Remarks
The vertical start location is
specified using the 8 bits from
VP7 to VP0.
VP7 to VP0 < 1416 are not
available.
If VS is the vertical display start location,
7
VS = H × ( Σ 2n VPn )
n=0
H: Cycle with the horizontal synchronizing pulse
If HS is the horizontal display start location,
8
HS = T × ( Σ 2 HPn + 9 )
n
n=0
T: Cycle with the display clock
HOR
TV screen
VS
HS
VERT
DA
Character
displaying area
1 bit weights 1 clock.
Test mode (Must be cleared to 0.)
Must be cleared to 0.
__
around the status value means the reset status by the “L” level is input to AC pin.
The horizontal start location is
specified using the 9 bits from
HP8 to HP0.
HP8 to HP0 < 1916 are not
available.
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(2) Address 2A916
DA
Register
0
HSZ0
1
HSZ1
2
HSZ2
3
HSZ3
4
HSZ4
5
HSZ5
6
HSZ6
7
HSZ7
8
HSZ8
9
HSZ9
A
HSZ10
B
HSZ11
C
HSZ12
D
HSZ13
E
HSZ14
F
HSZ15
10
HSZ16
11
BLINK0
12
BLINK1
13
BLINK2
14
BLINK3
15
—
16
—
17
—
Contents
Function
Status
Remarks
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Cycle approximately 1 second.
Cycle approximately 0.5 second.
Normal blinking
1
Normal character, reversed character alternation display.
0
1
0
1
0
1
Must be cleared to 0.
HSZx
Horizontal direction character size
0
1T/dot
1
2T/dot
Set to line 0 of display RAM
Set to line 1 of display RAM
Set to line 2 of display RAM
T: Display clock
Set to line 3 of display RAM
Set to line 4 of display RAM
Set to line 5 of display RAM
Set to line 6 of display RAM
Set to line 7 of display RAM
Set to line 8 of display RAM
Set to line 9 of display RAM
Set to line 10 of display RAM
Set to line 11 of display RAM
Set to line 12 of display RAM
Set to line 13 of display RAM
Set to line 14 of display RAM
Set to line 15 of display RAM
Set to line 16 of display RAM
BLINK0
BLINK1
0
1
0
Blinking OFF
Duty 50%
1
Duty 25%
Duty 75%
Blinking duty ratio can be altered.
Blinking cycle can be altered.
Character is in flashing state.
Character is always displayed
(normal character, reversed character).
7
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(3) Address 2AA16
8
DA
Register
0
VSZ0
1
VSZ1
2
VSZ2
3
VSZ3
4
VSZ4
5
VSZ5
6
VSZ6
7
VSZ7
8
VSZ8
9
VSZ9
A
VSZ10
B
VSZ11
C
VSZ12
D
VSZ13
E
VSZ14
F
VSZ15
10
VSZ16
11
HIDE
12
TEST20
13
EQP
14
TEST12
15
—
16
—
17
—
Status
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Contents
Function
VSZx
Vertical direction character size
0
1H/dot
1
2H/dot
H: Horizontal synchronous pulse
Remarks
Set to line 0 of display RAM
Set to line 1 of display RAM
Set to line 2 of display RAM
Set to line 3 of display RAM
Set to line 4 of display RAM
Set to line 5 of display RAM
Set to line 6 of display RAM
Set to line 7 of display RAM
Set to line 8 of display RAM
Set to line 9 of display RAM
Set to line 10 of display RAM
Set to line 11 of display RAM
Set to line 12 of display RAM
Set to line 13 of display RAM
Set to line 14 of display RAM
Set to line 15 of display RAM
Set to line 16 of display RAM
SYRAM writting over
SYRAM writting over or character erasing
Test mode (Must be cleared to 0.)
It does not include equivalent pulse.
It includes equivalent pulse.
Test mode (Must be cleared to 0.)
Must be cleared to 0.
Decided by register LINER, G and
B or DAC bit (SYEX) of SYRAM.
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(4) Address 2AB16
DA
Register
0
DSP0 00
1
DSP0 01
2
DSP0 02
3
DSP0 03
4
DSP0 04
5
DSP0 05
6
DSP0 06
7
DSP0 07
8
DSP0 08
9
DSP0 09
A
DSP0 10
B
DSP0 11
C
DSP0 12
D
DSP0 13
E
DSP0 14
F
DSP0 15
10
DSP0 16
11
PHASE 0
Status
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
12
PHASE 1
1
0
13
PHASE 2
1
14
TEST25
15
TEST26
16
—
17
—
0
1
0
1
0
1
0
1
Contents
Function
DSP0XX
Remarks
0
1
0
Character
Border
1
Matrix-outline
Set to line 0 of display RAM
DSP1XX
Halftone
(Note)
Set by combination of DSP0XX (address 2AB16) and DSP1XX
(address 2AC16).
At internal synchronous mode (EX = 1), display monitor signal
area is all blanking signal (BLNK output) area.
Set to line 1 of display RAM
Set to line 2 of display RAM
Set to line 3 of display RAM
Set to line 4 of display RAM
Set to line 5 of display RAM
Note: For half-tone display, it is necessary to input the external
Set to line 6 of display RAM
composite video signal to the CVIN pin, and externally
connect a 100 to 200 resistor in series. However, the
half-tone display is possible only with superimposed Set to line 7 of display RAM
displays.
Set to line 8 of display RAM
Set to line 9 of display RAM
Set to line 10 of display RAM
Set to line 11 of display RAM
Set to line 12 of display RAM
Set to line 13 of display RAM
Set to line 14 of display RAM
Set to line 15 of display RAM
Set to line 16 of display RAM
PHASE PHASE PHASE
2
1
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Color
SELCOR=0
Black
Red
Green
Yellow
Blue
Gray
Cyan
White
Raster color setting.
At PHASE 2 through 0 =101,
video signal output is gray, and
RGB output is magenta.
Refer Fig 3 about phase angle.
Test mode (Must be cleared to 0.)
Must be cleared to 0.
9
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(5) Address 2AC16
DA
Register
0
DSP1 00
1
DSP1 01
2
DSP1 02
3
DSP1 03
4
DSP1 04
5
DSP1 05
6
DSP1 06
7
DSP1 07
8
DSP1 08
9
DSP1 09
A
DSP1 10
B
DSP1 11
C
DSP1 12
D
DSP1 13
E
DSP1 14
F
DSP1 15
10
DSP1 16
11
LINER
Status
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
12
LINEG
1
0
13
LINEB
1
10
14
LBLACK
15
—
16
—
17
—
0
1
0
1
0
1
0
1
Contents
Function
DSP0XX
Remarks
0
1
0
Character
Border
1
Matrix-outline
Set to line 0 of display RAM
DSP1XX
Halftone
(Note)
Set by combination of DSP0XX (address 2AB16) and DSP1XX
(address 2AC16).
At internal synchronous mode (EX = 1), display monitor signal
area is all blanking signal (BLNK output) area.
Set to line 1 of display RAM
Set to line 2 of display RAM
Set to line 3 of display RAM
Set to line 4 of display RAM
Set to line 5 of display RAM
Note: For half-tone display, it is necessary to input the external
composite video signal to the CVIN pin, and externally Set to line 6 of display RAM
connect a 100 to 200 resistor in series. However, the
half-tone display is possible only with superimposed
Set to line 7 of display RAM
displays.
Set to line 8 of display RAM
Set to line 9 of display RAM
Set to line 10 of display RAM
Set to line 11 of display RAM
Set to line 12 of display RAM
Set to line 13 of display RAM
Set to line 14 of display RAM
Set to line 15 of display RAM
Set to line 16 of display RAM
LINE
B
0
0
0
0
1
1
1
1
LINE
G
0
0
1
1
0
0
1
1
LINE
R
0
1
0
1
0
1
0
1
Set black level to 2.3V
Set black level to 2.1V
Must be cleared to 0.
Color
SELCOR=0
Black
Red
Green
Yellow
Blue
Gray
Cyan
White
SYRAM color setting.
Color is decided by DAC bit
(SYEX) of SYRAM or HIDE
register.
At LINE BGR = 101, video signal
output is gray, and RGB output is
magenta.
Refer Fig. 3 about phase angle.
Set black level of video signal.
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(6) Address 2AD16
DA
Register
0
ERS0
1
ERS1
2
ERS2
3
ERS3
4
ERS4
5
ERS5
6
ERS6
7
ERS7
8
ERS8
9
ERS9
A
ERS10
B
ERS11
C
ERS12
D
ERS13
E
ERS14
F
ERS15
10
ERS16
11
–
12
–
13
–
14
SERS0
15
TEST22
16
TEST23
17
—
Status
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Contents
Function
Erase display RAM
ERSx
0
1
Remarks
Set to line 0 of display RAM
RAM erase
do not erase
do erase
Do not set “1” more than 2 bits at the same time.
The setting is not retained even if the bit is set to “1”.
Therefore, it is not necessary to cancel it.
Set to line 1 of display RAM
Set to line 2 of display RAM
Set to line 3 of display RAM
Set to line 4 of display RAM
Set to line 5 of display RAM
Set to line 6 of display RAM
Set to line 7 of display RAM
Set to line 8 of display RAM
Set to line 9 of display RAM
Set to line 10 of display RAM
Set to line 11 of display RAM
Set to line 12 of display RAM
Set to line 13 of display RAM
Set to line 14 of display RAM
Set to line 15 of display RAM
Set to line 16 of display RAM
Must be cleared to 0.
do not erase SYRAM
erase SYRAM
Set to SYRAM code 0016 to 0616
(Note)
Test mode (Must be cleared to 0.)
Must be cleared to 0.
Note: The setting is not retained even if the bit is set to “1”. Therefore, it is not necessary to cancel it.
11
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(7) Address 2AE16
DA
Register
0
SBIT0
1
SBIT1
2
SBIT2
3
SBIT3
4
SLIN0
5
SLIN1
6
SLIN2
7
SLIN3
8
SLIN4
9
SST0
A
SST1
B
SST2
C
SST3
D
SST4
E
SEND0
F
SEND1
10
SEND2
11
SEND3
12
SEND4
13
—
14
—
15
—
16
—
17
—
Status
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Contents
Function
Set display start bit of scroll block:
3
SA = Σ 2 (SBITn)
n
n=0
Set display start line of scroll block:
4
SB = Σ 2n (SLINn)
n=0
Set start line of scroll block
(last line number of the fixed block 1):
4
SC = Σ 2n (SSTn)
Setting valid
SA = 0 to 12
invalid
SA = 13 to15
Setting valid
SB = 0 to 16
invalid
SB = 17 to 31
Setting valid
SC = 0 to 15
invalid
SC = 16 to 31
n=0
Set start line of fixed block 2
(last line number of the scroll block):
4
SD = Σ 2n (SENDn)
n=0
When the scrolling on
setting valid SD = 2 to 17
invalid
SD = 18 to 31
When the scrolling off
set SD = 0
SD > SC + 2
Must be cleared to 0.
Note: When the scrolling on, set the ratio which will be SC < SB < SD.
12
Remarks
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(8) Address 2AF16
DA
Register
0
PTC0
1
PTC1
2
PTC2
3
PTC3
4
PTC4
5
PTC5
6
PTD0
7
PTD1
8
PTD2
9
PTD3
A
PTD4
B
PTD5
C
SRAND0
D
SRAND1
E
SRAND2
Status
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
F
ALL24
1
Contents
Function
Port P0 output
YM output
Port P1 output
BLNK output
Port P2 output
B output
Port P3 output
G output
Port P4 output
R output
Port P5 output
CSYN output
When port output: 0 output, when YM output: negative polarity.
When port output: 1 output, when YM output: polarity.
When port output: 0 output, when BLNK output: negative polarity.
When port output: 1 output, when BLNK output: polarity.
When port output: 0 output, when B output: negative polarity.
When port output: 1 output, when B output: polarity.
When port output: 0 output, when G output: negative polarity.
When port output: 1 output, when G output: polarity.
When port output: 0 output, when R output: negative polarity.
When port output: 1 output, when R output: polarity.
When port output: 0 output, when CSYN output: negative polarity.
When port output: 1 output, when CSYN output: polarity.
SRAND2
SRAND SRAND
0
1
1
0
Complete border = 1 dot Right and dot border = 1 dot
0
0
Complete border = 2 dot Right and dot border = 2 dot
0
1
Complete border = 3 dot Right and dot border = 3 dot
1
0
Complete border = 4 dot Right and dot border = 4 dot
1
1
Vertical direction is 1 dot only.
Blanking with all 40 characters in matrix-outline mode
Horizontal display period fully blanked with all characters in
matrix-outline size.
Remarks
Select P0 pin
Select P1 pin
Select P2 pin
Select P3 pin
Select P4 pin
Select P5 pin
Select data of P0 pin
Select data of P1 pin
Select data of P2 pin
Select data of P3 pin
Select data of P4 pin
Select data of P5 pin
Condition of border display is
changeable.
Horizontal display range can be
altered when all characters are in
matrix-outline size.
At external synchronous, set to 0.
Operation of character code FF16
becomes ineffective.
PC7 to PC0 < 3616,
PC7 to PC0 > C616 is not
available.
0
Display frequency fT control
1
7
0
n
11
PC1
fT = fH × { Σ (2 PCn) + 512 }
1
n=0
0
12
PC2
1
0
13
PC3
1
0
14
PC4
1
0
15
PC5
1
0
16
PC6
1
0
17
PC7
1
Note: At EX (address 2B016) = “0” (external synchronous), setting “1” of ALL24 register is not available.
Refer Fig. 2 about PTC0 to 5, PTD0 to 5.
10
PC0
13
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(9) Address 2B016
DA
Register
0
EX
1
SCOR
2
SELCOR
3
—
4
DSPON
5
DSPONV
6
—
7
BLK
8
SEPV0
Status
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Contents
Function
External synchronization
Internal synchronization
Superimpose black and white display
Superimpose coloring display
Normal
Can not be used.
Must be cleared to 0.
0
9
SEPV1
1
A
TEST15
B
TEST16
C
PALH
D
MPAL
E
PAL/NTSC
____
___
F
INT/NON
0
1
0
1
0
1
0
1
0
1
0
1
(Note 1)
Valid at only register “EX”=0 (at external synchronous) (Note 2, 3 and 4)
Refer to Table 3 and 6.
Digital output display OFF
Digital output display ON
Composite video output display OFF
Composite video output display ON
Must be cleared to 0.
Matrix outline
Matrix outline + border (border color is black)
Only at register “DSP1XX”
= 1 (XX = 00 ~ 16) is valid.
Method of sync separation from composite video.
0
1
Remarks
SEPV1 SEPV0
Composite Sync Spearation Function
0
0 Separation is performed during 1 in vertical blanking period
0
1 Separation is performed during 2 in vertical blanking period
1
0 Separation is performed during 3 in vertical blanking period
1
1 Setting disabled
2
1
3
Case 1 condition: vertical sync must repeat 2X
within 2 or 3; indicates this area.
Test mode (Must be cleared to 0.)
Interlace/noninterlace normal mode
Interlace/noninterlace expansion mode
PAL/NTSC
0
0
1
1
MPAL
0
1
0
1
Valid at only PAL and MPAL
mode.
Format
NTSC
M-PAL
PAL
Setting disabled
Interlace
Noninterlace
Notes 1: For internal synchronization, shut out (mute) the external video signal input, outside the IC. This avoids external video signal leaks
inside the IC.
2: For superimposed color displays, input an fsc signal which is synchronized with the color burst of the composite video signal (input to
the CVIN pin) to the OSCIN pin.
3: When EX (address 2B016) = “1” (internal synchronization), set the SCOR register to “0”.
4: When using a crystal oscillator (for the fsc input) between the OSCIN and OSCOUT pin, set the SCOR register to “0”.
14
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(9) Address 2B016 (cont.)
DA
Register
10
LEVEL0
11
LEVEL1
12
LEVEL2
13
TEST24
14
TEST17
15
TEST18
16
TEST19
17
—
Status
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Contents
Function
Composite video generation is off.
Composite video generation is on.
Display clock is on (oscillating).
Display clock is off (not oscillating).
Sync separation is disabled.
Sync separation is enabled.
Test mode (Must be cleared to 0.)
Remarks
Refer to Table 4 and 5.
Must be cleared to 0.
15
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
REGISTER CONSTRUCTION COMPOSITION
Table 3 Color and phase of NTSC, PAL (SELCOR = 0)
Table 4 Setting condition at LEVEL 0, 1 and 2
Color
Black
Red
Green
Yellow
Blue
Gray
Cyan
White
±
±
R (G, B, YM, BLNK, CSYN)
Phase (rad)
NTSC
PAL
—
—
7π/16
± 7π/16
27π/16
5π/16
π/16
± π/16
17π/16
15π/16
—
—
23π/16
9π/16
—
—
±
PHASE2 PHASE1 PHASE0
/
/
/
LINEB LINEG LINER
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PTD
PTC
1
LEVEL1
DSPON
DSPONV
CS pin
At display clock operates
0
1
1
L
At display clock stops
1
0
0
H
No character display at display clock
Table 5 Setting condition at LEVEL 0, 1 and 2 (at operation)
LEVEL0
LEVEL1
LEVEL2
Operation state
1
0
1
Stop state
0
1
0
1
0
0
Polarity
Select
PTD
Fig. 2 Switching port output with R, G and B output
Table 6 Video signal level (SELCOR = 0)
±
±
Sync
Pedestal
Color Burst
Black
Red
Green
Yellow
Blue
Gray
Cyan
White
Phase (rad)
NTSC
PAL
—
—
—
—
0
±4π/16
—
—
7π/16 ± 2π/16
± 7π/16 ± 2π/16
27π/16 ± 2π/16
5π/16 ± 2π/16
π/16 ± 2π/16
± π/16 ± 2π/16
17π/16 ± 2π/16
15π/16 ± 2π/16
—
—
23π/16 ± 2π/16
9π/16 ± 2π/16
—
—
±
Color name
Luminance level (V) (Note1)
Min.
Typ.
Max.
1.40
1.50
1.60
2.00
2.10
2.20
2.00
2.10
2.20
2.00
2.10
2.20
2.00
2.25
2.35
2.15
2.45
2.55
2.35
2.75
2.85
2.65
2.15
2.75
—
2.55
—
2.40
2.50
2.60
2.85
2.95
3.05
Notes 1: The luminance level and the chroma amplitude of this video signal are ruled only for PAL method.
2: The chroma amplitude is ruled by each color’s chroma and color burst’s chroma.
16
Chroma amplitude (Notes 1 and 2)
Min.
Typ.
Max.
—
—
—
—
—
—
—
1.00
—
—
—
—
1.23
1.46
1.69
1.11
1.31
1.51
0.85
1.00
1.15
0.91
1.08
1.25
—
—
—
1.37
1.62
1.86
—
—
—
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
Table 7 Display forms
DISPLAY FORMS
1. Blanking mode
Display forms are shown in Table 7, display forms at each display
mode are shown in Fig. 3.
12 dots
12 dots
c
c
Display mode
Character
Border
Matrix-outline
Halftone
DSP1 XX
DSP0 XX
(Address 2AC16) (Address 2AB16)
0
0
0
1
1
0
1
1
14 dots
BLNK output
Character size
Border size
All blanking
Blanking OFF
14 dots
Scanning
13
dots
BLNK
R,G,B
b c
b c b
b
YM L
L
CVIDEO
(Internal sync)
b c
b
b c
b
a
a
a
a
b c
b
b c b
(External sync)
(1)Character size
(2)Border size
a
(3)Matrix-outline size
a
(4)Halftone size
a: External display
signal
b: Background color
c: Character color
Fig. 3 Display forms at each display mode
17
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
For matrix and halftone, a character’s number of dots in the horizontal direction increases to 14.
Figure 4 shows a display example for a case where adjacent characters have different background colors and for character code FF16.
13 dots
12 dots
13 dots
11 dots
11 dots
14 dots
11 dots
40 characters
Character code FF16
Fig. 4 Number of dots in the horizontal direction at matrix-outline or halftone
2. Border mode
In border mode, characters are displayed with borders. (Refer to
Table 7.) In matrix and halftone modes also, characters are displayed
with borders if the BLK register (address 2B016) is set to 1.
Table 8 lists the types of borders.
Table 8
Bordering
SRAND1, 0
SRAND2
(Address 2AF16)
00
01
10
11
1dot in horizontal
direction
2 dots in horizontal
direction
3 dots in horizontal
direction
4 dots in horizontal
direction
1 dot in horizontal
direction
2 dots in horizontal
direction
3 dots in horizontal
direction
4 dots in horizontal
direction
The zero ¤
dot
0
1
Horizontal direction bordering is only 1 dot. When the character extends to the top line of the matrix, no border is left at the top, and when the
character extends to the bottom (12th) line of the matrix, no border is left at the bottom.
18
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
3. Setting matrix outline
The ALL24 register (address 2AF16) allows you to set a matrix outline. A matrix outline can be set for each line by using the DSP1XX
register (address 2AC16) .
However, this setting is inhibited if the EX register (address 2B016)
is 0 (external sync). An example of how you set a matrix outline is
shown in Figure 5.
Setting example of register
DSP1xx
DSP1 00
“0”
ALL24 “0”
to characters all matrix-outline
ALL24 “1”
Horizontal display area all
matrix-outline
40 characters
DSP1 08
DSP1 09
DSP1 10
“0”
“1”
“0”
DSP1 16
“0”
BR, BG, BB
OSD display area
Line 9
TV Screen
PHASE0, PHASE1, PHASE2
Note : It is not available to set when external synchronous. ( register EX = “0” )
Fig. 5 Setting example all matrix-outline area
4. Blinking mode
Two patterns blinking by register BLINK3 (address 2A916) or BLINK
bit of display RAM.
Blinking mode is shown in Table 9 (SYRAM do not blink).
Use registers BLINK0, 1, and 2 (address 2A916) to set the duty ratio
and period that determines the blinking time. Tables 12 and 13 list the
relationship between the register settings and the duty ratio and period.
Table 9 Blinking mode
Table 10 Setting of duty ratio
Blinking mode
BLINK3
at blinking OFF
Blinking
Normal
Normal character, reversed
character alternation display
Reverse
0
1
BLINK0
BLINK1
0
1
0
1
Blink OFF
Duty 50%
Duty 25%
Duty 75%
Table 11 Setting of cycle
BLINK2
0
1
Cycle
Approximately 1 second (Vertical sync
divided into 1/64)
Approximately 0.5 second (Vertical sync
divided into 1/32)
19
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
5. Scroll display mode
The scroll display mode is entered by setting registers SBIT0 to 3
(SA), SLIN0 to 4 (SB), SST0 to 4 (SC), and SEND0 to 4 (SD) (all at
address 2AE16). (Scroll is turned off when SD = 0.)
The screen is scrolled in the range from the (SC)’th line to the
(SD-1)’th line, and sections above and below this range are fixed.
The beginning line and beginning dot of scroll are the (SA)’th dot on
Setting example 1
SA = 0
SB = 2
SC = 2
SD = 14
Setting example 2
SA = 3
SB = 5
SC = 2
SD = 14
the (SB)’th line.
The screen can be scrolled up or down by successively incrementing
or decrementing SA and SB.
Figure 6 shows examples of how the display is scrolled. The scroll
range in these examples contains 12 lines (second to the 13th lines).
However, the screen can display only 11 lines at a time, and the remaining one line is handled as a dummy line and not displayed.
Line number when
on screen display
0
1
Zero line
1st line
<fixed block>
2
3
4
5
6
7
8
9
10
11
12
2nd line (0 dot to 12 dots)
3rd
4th line
5th line
6th line
<Scrolling
7th line
8th line
9th line
10th line
11th line
12th line (0 dot to 12 dots)
13
14
15
14th line
15th line
16th line
block>
Dummy line
13th line (0 dot to 12
dots)
<fixed block>
Line number when
on screen display
0
1
Zero line
1st line
<fixed block>
5th line (3 dots to 12 dots)
2
3
4
5
6
7
8
9
10
11
12
6th line
7th line
8th line
9th line
10th line
11th line
12th line
13th line
2nd line
3rd line
<Scrolling block>
4th line (0 dot to 2 dots)
13
14
15
14th line
15th line
16th line
Dummy line
5th line (0 dot to 2 dots)
or
4th line (3 dots to 12
dots)
<fixed block>
When displayed in order of SA = 0, 1, 2, and so on, the screen scrolls up. When displayed in order of SA = 12, 11, 10, and so on, the
screen scrolls down.
(1) To scroll the screen up, write the dummy line after you set the 0th dot in SA but before setting the 1st dot.
(2) To scroll the screen down, write the dummy line after you set the 0th dot in SA but before setting the 12th dot of the preceding line.
Fig. 6 Scrolling example
20
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
6. Character font
(1) Character ROM
Images are composed on a 12 × 13 dot matrix, and characters
can be linked vertically and horizontally with other characters to
allow the display the continuous symbols.
Character code FF16 is fixed as blank, without a background.
13 dots
12 dots
Fig. 7 Character construction
13 dots
12 dots
Fig. 8 Example for displaying a continuous pattern
21
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(2) SYRAM
You can set characters for 7 letters per screen (SYRAM code
0016 to 0616). Figure 9 shows an example of how to set.
Use display RAM’s SYC2 to 0 (0016 to 0616) to specify SYRAM.
Note that SYRAM code 0716 is fixed to a blank, so you cannot set
a character font to this code.
If you do not put SYRAM and a character together, use code
0716.
(ex) SYRAM code 0016 .................. Set character by setting data to address 30016 to 30C16
13 dots
Address
12 dots
30016
30116
30216
30316
30416
30516
30616
30716
30816
30916
30A16
30B16
30C16
17
0
0
0
0
0
0
0
0
0
0
0
0
0
…
…
…
…
…
…
…
…
…
…
…
…
…
…
Color expansion bit SYEX (set for each dot line)
The HIDE register (address 2AA16) becomes valid for
only the dot line where✽ = 1.
For details, refer to the next section, “(3) Compounding character ROM and SYRAM.”
Fig. 9 Setting example of SYRAM
22
D
0
0
0
0
0
0
0
0
0
0
0
0
0
C
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
B
0
0
0
0
0
0
0
0
0
0
0
0
1
A
0
0
0
0
0
0
0
0
0
0
0
1
1
DA
9
0
0
0
0
0
0
0
0
0
0
1
1
1
8
0
0
0
0
0
0
0
0
0
1
1
1
1
7
0
0
0
0
0
0
0
0
1
1
1
1
1
6
0
0
0
0
0
0
0
1
1
1
1
1
1
5
0
0
0
0
0
0
1
1
1
1
1
1
1
4
0
0
0
0
0
1
1
1
1
1
1
1
1
12 dots
1 bit: 1 dot of character
3
0
0
0
0
1
1
1
1
1
1
1
1
1
2
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
13 dots
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
(3) Compounding character ROM and SYRAM
You can compound characters in character ROM with SYRAM.
The compounding method is determined by the SYEX color expansion bit and the HIDE register (address 2AA16).
For dot lines where SYEX = 0, the SYRAM color is set by the display RAM’s SR, SG, and SB irrespective of the HIDE register’s
content.
If the HIDE register’s content is 0, the SYRAM color for dot lines
where SYEX = 1 is set by the LINER, LINEG, and LINEB registers (address 2AC16).
If the HIDE register’s content is 1, the character ROM part of the
dot lines where SYEX = 1 is overwritten in HIDE mode with colors
set by the LINER, LINEG, and LINEB registers irrespective of the
ROM’s content and color. The color of the SYRAM part is set by
the display RAM’s SR, SG, and SB as in the case of dot lines
where SYEX = 0.
Figure 10 shows an example for each instance of compounding.
SYRAM
Character ROM
Compounding
Contents of
register HIDE
Ex. 1
Ex. 2
0 (normal mode)
SYEX
0
0
0
0
0
0
0
0
0
0
0
0
0
SYEX
1
1
1
1
1
0
0
0
0
0
0
0
0
1 (HIDE mode)
SR,
SG,
SB
LINER,
LINEG,
LINEB
SR,
SG,
SB
SYEX
0
0
0
0
0
0
0
0
0
0
0
0
0
SYEX
1
1
1
1
1
0
0
0
0
0
0
0
0
SR,
SG,
SB
LINER,
LINEG,
LINEB
SR,
SG,
SB
When HIDE = 1, the character ROM’s contents for dot lines where SYEX = 1 become invisible.
Fig. 10 Compounding example
23
4
3
2
1
96
95
94
93
~
Data (00116)
Data (2A716)
Data (2A816)
Data (2A916)
Data (2AA16)
Data (2AB16)
Data (2AC16)
Data (2AD16)
Data (2AE16)
Data (2AF16)
Data (2B016)
774
775
776
777
778
779
780
781
782
0
0
0
0
0
0
16
0
0
0
0
0
0
15
Display ON
Set registers
address
2A816 to 2AF16
0
0
0
0
0
0
0
0
0
0
0
PC7 PC6 PC5
0
0
0
0
0
0
0
0
0
0
1
0
10
0
0
0
0
0
0
F
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C6 C5 C4 C3 C2 C1 C0
0
1
1
0
0
0
HSZ
12
VSZ
12
DSP
012
DSP
112
ERS
12
SST
3
SRAND
0
0
HSZ
11
VSZ
11
DSP
011
DSP
111
ERS
11
SST
2
PTD
5
HSZ HSZ
9
8
VSZ VSZ
9
8
DSP DSP
009 008
DSP DSP
109 108
ERS ERS
9
8
SST SLIN
0
4
PTD PTD
3
2
SEPV
SEPV
0
1
0
HSZ
10
VSZ
10
DSP
010
DSP
110
ERS
10
SST
1
PTD
4
BLK
HSZ
7
VSZ
7
DSP
007
DSP
107
ERS
7
SLIN
3
PTD
1
0
HSZ
6
VSZ
6
DSP
006
DSP
106
ERS
6
SLIN
2
PTD
0
1
HSZ
5
VSZ
5
DSP
005
DSP
105
ERS
5
SLIN
1
PTC
5
1
HSZ
4
VSZ
4
DSP
004
DSP
104
ERS
4
SLIN
0
PTC
4
0
HSZ
3
VSZ
3
DSP
003
DSP
103
ERS
3
SBIT
3
PTC
3
0
HSZ
2
VSZ
2
DSP
002
DSP
102
ERS
2
SBIT
2
PTC
2
0
HSZ
1
VSZ
1
DSP
001
DSP
101
ERS
1
SBIT
1
PTC
1
EX
HSZ
0
VSZ
0
DSP
000
DSP
100
ERS
0
SBIT
0
PTC
0
0 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0
SYC SYC SYC
BB BG BR BLINK CB CG CR
1
0
2
0
C6 C5 C4 C3 C2 C1 C0
0
0
0
C6 C5 C4 C3 C2 C1 C0
0
0
0
0 SYEX S3EB S3EA S3E9 S3E8 S3E7 S3E6 S3E5 S3E4 S3E3 S3E2 S3E1 S3E0
0
0
2
3
0 SYEX S01B S01A S019 S018 S017 S016 S015 S014 S013 S012 S011 S010
4
0
5
0 SYEX S00B S00A S009 S008 S007 S006 S005 S004 S003 S002 S001 S000
6
0
7
0
8
0
9
0
A
B
0
C
D
E
SYC SYC SYC
BB BG BR BLINK CB CG CR
2
1
0
SYC SYC SYC
BB BG BR BLINK CB CG CR
2
1
0
0
0
0
0
0
0
11
BLINK BLINK BLINK BLINK HSZ HSZ HSZ HSZ
3
0 16 15 14 13
2
1
0 EQP 0 HIDE VSZ VSZ VSZ VSZ
16 15 14 13
DSP
DSP DSP DSP
PHASE
PHASE
PHASE
0
0 016 015 014 013
2
1
1 LINE LINE LINE DSP DSP DSP DSP
B G R 116 115 114 113
SERS
ERS ERS ERS ERS
0
0
0
0
16 15 14 13
SEND
SEND
SEND SEND SST
SEND
0
0
3
2
1
0
4
4
SRAND
SRAND
PC4 PC3 PC2 PC1 PC0 ALL24
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
12
13
0
0
0
0
0
0
0
0
0
14
SB SG SR
Set registers SB SG SR
address
display RAM SB SG SR
00016 to 2A716
0
Address (00016)
Data (00016)
0
0
0
0
0
17
DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA
Data (36C16)
Set address
Set addresses
SYRAM
30016 to 36C16
Data (30016)
Data (30116)
Display OFF
Address setting
Address (2B016)
Data (2B016)
Remarks
Contents
Address/data
773
~
~
~
~
~
~
~
~
24
~
No.
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
EXAMPLE FOR DATA INPUT
Use an 8-bit parallel × 3 serial input to set data in the display RAM,
display control register, and SYRAM. Table 12 lists an example of
how data is set.
Table 12 Data setting
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
SERIAL DATA INPUT TIMING
(1) The address consists of 8 bits × 3.
(2) The data consists of 8 bits × 3.
__
(3) The 8 bits × 3 in the SCK after the CS signal has fallen are the
address, and for succeeding input data, the address is
incremented every 24 bits (8 bits × 3). Refer to Fig.12 about detail for address increment.
CS
SCK
DA7 to DA0
(MSB) (LSB)
LSB
MSB
Address (8 bits✕3)
LSB
MSB
Data N (8 bits✕3)
LSB
MSB
Data N+1 (8 bits✕3)
N=1, 2, 3
Fig. 11 Serial input timing
25
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
Address
00016
display RAM
2A716
2A816
register
Jump to address 000 16
automatically
2B016
2B116
unused address area
2FF16
30016
Jump to address 310 16
automatically
30D16
SYRAM code 00 16
unused address area
31016
SYRAM code 01 16
ƒJump to address 320 16
automatically
31D16
unused address area
32016
ƒJump to address 360 16
automatically
35D16
unused address area
36016
SYRAM code 06 16
36D16
Address setting and data input disable area
FFF16
Following FFF 16 is disabled
When entering data, note that although addresses are incremented every data entry (8 bits × 3), if an address value falls in the unused
address area, it is automatically converted to the address value indicated by the arrow. When entering SYRAM data, for example, you
can set this data simply by setting address 30016 first and then entering data 30016 to 30C16 (SYRAM code 0016) and next data 31016 to
31C16 (SYRAM code 0116). The same applies for SYRAM code 0216 to 0616.However, set CS to H after setting SYRAM code 0616 (36016
to 36C16).
Fig. 12 Address construction
26
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
Notes on others
1. At system start-up
6. When no external composite video signal
is input
__
At system start-up, always set the AC pin to low level before setting
registers.
2. Power supply noise
When power supply noise is generated, the internal oscillator circuit
does not stabilize, whereby causing horizontal jitters across the picture display. Therefore, connect a bypass capacitor between the
power supply and GND.
3. At power on
When power to the M35062-XXXSP is activated, characters are
sometimes output without defining the internal display RAM, composite RAM and register. Also, immediately after power is turned on,
up until the oscillator circuit stabilizes, data is sometimes not set correctly in the register. Therefore, use the following start-up procedure.
__
(a) Activate power. (AC pin = “L”)
__
(b) Engage auto clear. (AC pin = “H”)
(c) Disable data input for a 200 m sec (time enough to allow the
internal oscillator circuit to stabilize).
(d) Set register LEVEL n.
_
_
_
_
_
_
_
_
_
_
_
_
_
_
(e) Set register PAL/NTSC.
(f) Set register PC n.
(g) Disable data input for a 20 m sec (time enough to allow the
internal oscillator circuit to stabilize).
(h) Set other registers.
(i) Set the SYRAM.
(j) Set the internal display RAM.
(k) Turn registers DSPON and DSPONV on.
Without a signal, characters cannot be displayed by external synchronization. Therefore, switch to internal synchronization.
7. When signal level of the external composite video signal is extremely poor
With a weak electric field, character display is uncontrollable by external synchronization. Therefore, switch to internal synchronization.
8. When a crystal oscillator is used as the IC's
fsc input
It is possible to connect a crystal oscillator between OSCIN and
OSCOUT to input the subcarrier frequency (fsc) signal to the OSCIN
pin. Talk with the manufacturer of the crystal oscillator you want to
use about matching it to this IC.
However, when using a crystal oscillator, it is not possible to superimpose colors. Therefore, set the SCOR register (address 2B016 in
DAI register) to “0”.
Crystal oscillator frequency
NTSC system: 3.580 MHz
PAL system: 4.434 MHz
M-PAL system: 3.576 MHz
4. When resuming internal oscillation from
the off state
The internal oscillator circuit stops oscillating when register LEVEL 1
__
= 1, DSPON = 0, DSPONV = 0 and CS pin = “H”.
When resuming internal oscillation from the off state, up until the oscillator circuit stabilizes, data is sometimes not set correctly in the
register. Therefore, start oscillation as follows.
__
(a) CS pin = “H” (Oscillation off)
__
(b) CS pin =“L” (Oscillation start)
(c) Wait for a 20 m sec (time enough to allow the internal oscillator circuit to stabilize).
(d) Set register LEVEL 1 = 0.
(e) Set other registers, SYRAM and internal display RAM.
(f) Turn registers DSPON and DSPONV on.
5. Other notes on oscillation
Make note of the fact that the internal oscillator circuit cannot stabilize in the below situations.
(a) When the external composite video signal is discontinuous
(when changing channels, etc.)
(b) When register PC n setting is changed
(c) When register LEVEL n setting is changed
Before changing settings, turn registers DSPON and DSPONV off.
Also, disable data input for 20 m sec after making settings.
27
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
9. Notes on superimposed colors
(1) Register setting
The below table gives register settings for superimposed colors.
Broadcasting method
Register
____
PAL/NTSC
MPAL
EX
SCOR
0
0
0
1
Connect to GND
PAL
1
0
0
1
Input control signal. Refer to (2)
M-PAL
0
1
0
1
Input control signal. Refer to (2)
NTSC
(2) Signal input to PHIN (23-pin) pin
It is necessary to input a control signal for alternating color burst
phase (CB1/CB2) every other scanning line. The signal is input into
the PHIN (23-pin) pin.
The below figure shows timing for the signal input to the PHIN (23pin) pin.
PHIN pin
R-Y
CB1
B-Y
CB2
Fig. 13 Bector phase of PAL, M-PAL method
CB1
CB2
CB1
C. Video signal
PHIN pin
Fig. 14 Signal input timing for PHIN (23-pin) pin
28
PHIN input
sellect
H
CB1
L
CB2
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
10. Notes on fsc signal input
(1) This IC amplifies the subcarrier frequency (fsc) signal (NTSC system: 3.580 MHz, PAL system: 4.434 MHz, M-PAL system: 3.576
MHz) input to the OSCIN pin and generates the composite video
signal internally.
The amplified fsc signal can be destabilized in the following cases.
(a) When the fsc signal is outside of recommended operating
conditions
(b) When the waveform of the fsc signal is distorted
(c) When DC level in the fsc waveform fluctuates
When the amplified signal is unstable, the composite video signal
generated inside the IC is also unstable in terms of synchronization with the subcarrier and phase.
Consequently, this results in color flicker and lost synchronization
when the composite video signal is generated. Make note of the
fact that this may prevent a stable blue background from being
formed.
(2) When switching to internal synchronization from external synchronization (fsc signal is OFF), start fsc signal input 20 m sec or
more before the internal oscillator circuit stabilizes.
(2) To switch from external sync to internal sync when the oscillator
is already stable
(a) Set the registers DIPON and DISPONV = low. (The display is
turned off.)
(b) Disable data input during a 20 ms wait state (internal oscillator
stabilization period).
(c) Set the registers EX and PAL/NTSC = high and INT/NON =
low. (The display is temporarily placed in the interlaced mode.)
(d) Disable data input during a 30 ms wait state (internal oscillator
stabilization period).
(e) Set the registers INT/NON and PALH = high (for 628 scanning
lines). (The scanning fields are fixed to the first field.)
(f) Set up other registers, SYRAM, and display RAM.
(g) Set the registers DIPON and DISPONV = high. (The display is
turned on.)
11. Procedure for fixing to the first field in PAL
system
The M35062-XXXSP allows to fix the scanning fields to the first field
during PAL system noninterlaced display (internally synchronized).
In this case, the display must be placed in the interlaced mode temporarily before entering the noninterlaced mode in order to ensure
that the scanning fields are fixed. Follow the setup procedure described below.
(1) When powering on
(a) Turn on the power (AC pin = low).
(b) Deactivate auto clear (AC pin = high).
(c) Disable data input during a 200 ms wait state (internal stabilization period).
(d) Set the registers LEVEL 0 and 2 = high and LEVEL 1 = low.
(e) Disable data input during a 20 ms wait state (internal oscillator stabilization period).
(f) Set the registers EX and PAL /NTSC = high and INT/NON =
low. (The display is temporarily placed in the interlaced
mode.)
(g) Disable data input during a 30 ms wait state (internal oscillator stabilization period).
(h) Set the registers INT/NON and PALH = high (for 628 scanning
lines). (The scanning fields are fixed to the first field.)
(i) Set up the register PCn.
(j) Disable data input during a 20 ms wait state (internal oscillator stabilization period).
(k) Set up other registers.
(l) Set up SYRAM.
(m) Set up the display RAM.
(n) Set the registers DIPON and DISPONV = high.(The display is
turned on.)
29
30
Fig.15 M35062-XXXSP example of peripheral circuit
470
150
120
+7.0V
Note 2 Set basic electric potential in
consideration of dynamic range
of the transistor.
220
2.2k
1.50V
Note 1
10k
+5.0V
47 ˚
+
Note 1 Clamp sync chip to 1.50 V.
75
220 ˚
+
Composite video
signal output
47 ˚
+
Note 2
+7.0V
From microcomputer
External composite video
signal input
@+
11
10
9
8
7
470p
680
HOR
CVIN
LEBK
LECHA
CVIDEO
VSS
VDD1
AC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Note 6
16
15
14
13
100 ˚ 1 ˚ 0.01 ˚
12
@+
1 ˚
+
Note 5
6
5
4
3
2
1
VREF
LP1
VDD2
LP2
OSCOUT
OSCIN
PHIN
P0
P1
P2
P3
P4
P5
TESTA
SCK
CS
1.75V
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note 4
1 ˚
1k
fsc input
470p
Note 3
+
47p
0.01 ˚
+5.0V
Note 3
100 ˚1 ˚
+
0.01 ˚
1k
Delay circuit
Note 7
NTSC : 3.580MHz
PAL
: 4.434MHz
M-PAL : 3.576MHz
Note 8 For internal synchronization,
shut out (mute) the external
video signal input, outside the
IC. This avoids external video
signal leaks inside the IC.
Note 7 at fsc signal input
0.3 VP-P < Vin< 4.0 VP-P Noise
component of fsc- IN is less
than 30 mV.
Note 6 This is provisional value of
sync separation noise eliminate filter.
Note 5 Construct _integral
circuit by
_______
built-in 30 kΩ of AC pin and
an external condenser.
Attention to supply voltage
rise time about this CR constant.
Note 4 Set electric potential of VREF
to (Sync chip electric potential
+0.25) V= 1.75 V.
Note 3 External loop filter constant is
provisional value.
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
M35062-XXXSP PERIPHERAL CIRCUIT (For external fsc input)
470
150
120
Note 2 Set basic electric potential in
consideration of dynamic range
of the transistor.
220
2.2k
1.50V
Note 1
10k
+5.0V
47 ˚
+
Note 1 Clamp sync chip to 1.50 V.
75
220 ˚
+
+7.0V
+7.0V
Composite video
signal output
47 ˚
+
Note 2
From microcomputer
External composite video
signal input
@+
11
10
9
8
470p
680
HOR
CVIN
LEBK
LECHA
CVIDEO
VSS
VDD1
AC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Note 6
16
15
14
13
100 ˚ 1 ˚ 0.01 ˚
12
@+
1 ˚
+
Note 5
7
6
5
4
3
2
1
VREF
LP1
VDD2
LP2
OSCOUT
OSCIN
PHIN
P0
P1
P2
P3
P4
P5
TESTA
SCK
CS
1.75V
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note 4
1 ˚
1k
Note 7
470p
Note 3
+
100 ˚1 ˚
+
0.01 ˚
1k
47p
0.01 ˚
+5.0V
Note 3
NTSC : 3.580MHz
PAL
: 4.434MHz
M-PAL : 3.576MHz
Note 8 For internal synchronization,
shut out (mute) the external
video signal input, outside the
IC. This avoids external video
signal leaks inside the IC.
Note 7 Connect a crystal oscillator at
this mode. Coloring is disabled
at superimpose.
Note 6 This is provisional value of
sync separation noise eliminate filter.
Note 5 Construct
integral circuit by
_________
built-in 30 kΩ of AC pin and
an external condenser.
Attention to supply voltage
rise time about this CR constant.
Note 4 Set electric potential of VREF
to (Sync chip electric potential
+0.25) V= 1.75 V.
Note 3 External loop filter constant is
provisional value.
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
M35062-XXXSP PERIPHERAL CIRCUIT (When using a crystal oscillator)
Fig.16 M35062-XXXSP example of peripheral circuit
31
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
TIMING REQUIREMENTS (Ta = – 20°C to + 70°C, VDD = 5.00 ± 0.25V unless otherwise noted)
DATA INPUT
Symbol
tW (SCK)
tsu (CS)
th (CS)
tsu (AD)
th (AD)
th (SCK)
Paramenter
Limits
Typ.
—
—
—
—
—
—
Min.
200
200
2
200
200
2
SCK width
CS setup time
CS hold time
AD setup time
AD hold time
1 word hold time
Unit
Max.
—
—
—
—
—
—
ns
ns
µs
ns
ns
µs
tw(CS)
2µs
(min.)
CS
tsu(CS)
tw(SCK)
tw(SCK)
th(CS)
SCK
tsu(AD)
th(AD)
AD0 to 7
CS
th(SCK)
2µs
or more
th(SCK)
2µs
or more
SCK
1
Fig. 17 Serial input timing requirements
32
2
3
1
2
3
1
2
3
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
ABSOLUTE MAXIMUM RATINGS (VDD = 5.00V, Ta = – 20°C to +70°C unless otherwise noted)
Symbol
VDD
VI
VO
Pd
Topr
Tstg
Conditions
With respect to VSS.
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Ta = 25°C
Ratings
– 0.3 to 6.0
VSS – 0.3 < VI < VDD + 0.3
VSS < VO < VDD
300
– 20 to 70
– 40 to 125
Unit
V
V
V
mW
°C
°C
RECOMMENDED OPERATIONAL CONDITIONS (VDD = 5.00 V, Ta = – 20°C to +70°C unless otherwise noted)
Symbol
VDD
VIH
VIL
VCVIN
VOSCIN
fOSCIN
Parameter
Min.
4.75
0.8 × VDD
0
—
Supply voltage
“H” level input voltage AC, CS, SCK, AD0 to AD7
“L” level input voltage AC, CS, SCK, AD0 to AD7
Composite video input voltage CVIN
Input voltage OSCIN
Oscillation frequency for synchronous signal
(Duty 40 to 60%)
0.3 VP-P
—
Limits
Typ.
5.00
VDD
0
2 VP-P
—
3.580
4.434
3.576
Max.
5.25
VDD
0.2 × VDD
Unit
4.0 VP-P
V
V
V
V
V
—
MHz
—
ELECTRICAL CHARACTERISTICS
Symbol
VDD
IDD
VOH
VOL
RI
Parameter
Supply voltage
Supply current
“H” level output voltage P0 to P5
“L” level output voltage P0 to P5
Pull-up resistance AC
Test conditions
Ta = – 20°C to +70°C
VDD = 5.00 V
VDD = 4.75, IOH = – 0.2 mA
VDD = 4.75, IOL = 0.2 mA
VDD = 5.00 V
Min.
4.75
—
3.75
—
10
Limits
Typ.
5.00
25
—
—
30
Max.
5.25
50
—
0.4
100
Min.
Limits
Typ.
Max.
—
1.5
—
Unit
V
mA
V
V
kΩ
VIDEO SIGNAL INPUT CONDITIONS (VDD = 5.00 V, Ta = – 20°C to +70°C)
Symbol
VIN-CU
Parameter
Composite video signal input clamp voltage
Test conditions
Sync-chip voltage
Unit
V
33
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
NOTE FOR SUPPLYING
POWER
__
(1) Timing of power supplying to AC pin
The internal circuit of M35062-XXXSP
is reset when the level of
__
the auto clear input pin AC is “L”.
This pin is hysteresis input
with the pull-up resistor. The timing
__
about power supplying of AC pin is shown in Figure 18.
After supplying the power (VDD and VSS) to M35062-XXXSP, the
tW time must be reserved for 1 ms or more.
Before starting input from the microcomputer, the waiting time (t__
S)
must be reserved for 200 ms after the supply voltage to the AC
pin becomes 0.8 × VDD or more.
(2) Timing of power supplying to VDD1 pin and VDD2 pin
The power need to supply to VDD1 and VDD2 at a time, though it
is separated perfectly between the VDD1 as the digital line and
the VDD2 as the analog line.
Voltage [V]
Data input is not available
VDD
Supply voltage
VAC
(AC pin input voltage)
0.8 ✕ VDD
0.2 ✕ VDD
tw
200ms
Time t [s]
__
Fig. 18 Timing of power supplying to AC pin
PRECAUTION FOR USE
Notes on noise and latch-up
In order to avoid noise and latch-up, connect a bypass capacitor (≈
0.1 ˚F) directly between the VDD1 pin and VSS pin, and the VDD2 pin
and VSS pin using a heavy wire.
34
DATA REQUIRED FOR MASK ROM ORDERING
Please send the following data for mask orders.
(1) M35062-XXXSP mask ROM order confirmation form
(2) 32P4B mask specification form
(3) ROM data (EPROM 3 sets)
(4) Floppy disks containing the character font generating program
+character data
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
STANDARD ROM TYPE : M35062-XXXSP
M35062-001SP is a standard ROM type of M35062-XXXSP.
Character patterns are fixed to the contents of Figures 19 and 20.
35
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
0016
0116
0216
0316
0416
0516
0616
0716
0816
0916
0A16
0B16
0C16
0D16
0E16
0F16
1016
1116
1216
1316
1416
1516
1616
1716
1816
1916
1A16
1B16
1C16
1D16
1E16
1F16
2016
2116
2216
2316
2416
2516
2616
2716
2816
2916
2A16
2B16
2C16
2D16
2E16
2F16
3016
3116
3216
3316
3416
3516
3616
3716
3816
3916
3A16
3B16
3C16
3D16
3E16
3F16
Fig. 19 M35062-001SP character patterns (1)
36
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
4016
4116
4216
4316
4416
4516
4616
4716
4816
4916
4A16
4B16
4C16
4D16
4E16
4F16
5016
5116
5216
5316
5416
5516
5616
5716
5816
5916
5A16
5B516
5C16
5D16
5E16
5F16
6016
6116
6216
6316
6416
6516
6616
6716
6816
6916
6A16
6B16
6C16
6D16
6E16
6F16
7016
7116
7216
7316
7416
7516
7616
7716
7816
7916
7A16
7B16
7C16
7D16
7E16
7F16
Fig. 20 M35062-001SP character patterns (2)
37
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
PACKAGE OUTLINE
32P4B
38
MITSUBISHI MICROCOMPUTERS
M35062-XXXSP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
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distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
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When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
•
© 2000 MITSUBISHI ELECTRIC CORP.
New publication, effective August. 2000.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
M35062-XXXSP DATA SHEET
Revision Description
Rev.
date
1.0
First Edition
980402
1.1
• Deletes some Japanese font and create pdf file (some pages)
• P41 and P42 MARK SPECIFICATION FORM and PACKAGE OUTLINE are added
000725
1.2
Delete Mask ROM ORDER CONFIRMATION FORM and MASK SPECIFICATION FORM
000829
(1/1)