To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and “Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. “Standard”: 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. “High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. “Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. 3804 Group (Spec.L) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3804 group (Spec.L) is the 8-bit microcomputer based on the 740 family core technology. The 3804 group (Spec.L) is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the A/D converter and D/A converters. FEATURES • Basic machine-language instructions ................................. 71 • Minimum instruction execution time .......................... 0.24 μs (at 16.8 MHz oscillation frequency) • Memory size ROM (Flash memory) ............................................ 60 K bytes RAM ...................................................................... 2048 bytes • Programmable input/output ports ....................................... 56 • Software pull-up resistors ............................................ Built-in • Interrupts 21 sources, 16 vectors............................................................... (external 8, internal 12, software 1) • Timers ...................................................................... 16-bit × 1 8-bit × 4 (with 8-bit prescaler) • Serial interface ......... 8-bit × 2 (UART or Clock-synchronized) 8-bit × 1 (Clock-synchronized) • PWM ....................................... 8-bit × 1 (with 8-bit prescaler) • A/D converter ........................................ 10-bit × 16 channels (8-bit reading enabled) • D/A converter ............................................ 8-bit × 2 channels • Watchdog timer ....................................................... 16-bit × 1 • Multi-master I2C-BUS interface.............................. 1 channel • LED direct drive port............................................................. 8 • Clock generating circuit ............................. Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 1 of 128 REJ03B0266-0100 Rev.1.00 Oct 27, 2008 • Power source voltage [In high-speed mode] At 16.8 MHz oscillation frequency .................... 4.5 to 5.5 V At 12.5 MHz oscillation frequency .................... 4.0 to 5.5 V At 8.4 MHz oscillation frequency ...................... 2.7 to 5.5 V [In middle-speed mode] At 16.8 MHz oscillation frequency .................... 4.5 to 5.5 V At 12.5 MHz oscillation frequency .................... 2.7 to 5.5 V [In low-speed mode] At 32 kHz oscillation frequency......................... 2.7 to 5.5 V • Power dissipation In high-speed mode ........................................ 27.5 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ........................................ 1200 μW (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) • Operating temperature range ............................. −20 to 85 °C • Packages SP...............PRDP0064BA-A (64P4B) (64-pin 750 mil SDIP) HP ......PLQP0064KB-A (64P6Q-A) (64-pin 10 × 10 mm LQFP) KP ......PLQP0064GA-A (64P6U-A) (64-pin 14 × 14 mm LQFP) WG ........PTLG0064JA-A (64F0G) (64-pin 6 × 6 mm FLGA) <Flash memory mode> • Power source voltage ................................ VCC = 2.7 to 5.5 V • Program/Erase voltage ............................. VCC = 2.7 to 5.5 V • Programming method ............... Programming in unit of byte • Erasing method ................................................. Block erasing • Program/Erase control by software command • Number of times for programming/erasing ...................... 100 APPLICATION Camera, Household appliance, Consumer electronics, etc. P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 3804 Group (Spec.L) P37/SRDY3 49 32 P20(LED0) P36/SCLK3 50 31 P21(LED1) P35/TXD3 51 30 P22(LED2) P34/RXD3 52 29 P23(LED3) P33/SCL 53 28 P24(LED4) P32/SDA 54 27 P25(LED5) P31/DA2 55 26 P26(LED6) P30/DA1 56 25 P27(LED7) VCC 57 24 VSS VREF 58 23 XOUT AVSS 59 22 XIN P67/AN7 60 21 P40/INT40/XCOUT P66/AN6 61 20 P41/INT00/XCIN P65/AN5 62 19 RESET P64/AN4 63 18 CNVSS P63/AN3 64 17 P42/INT1 8 9 10 11 12 13 14 15 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 16 7 P54/CNTR0 P43/INT2 6 4 P57/INT3 P55/CNTR1 3 P60/AN0 5 2 P61/AN1 P56/PWM 1 P62/AN2 M38049FFLHP/KP Package code : PLQP0064KB-A (64P6Q-A)/PLQP0064GA-A (64P6U-A) Fig. 1 Pin configuration (Top view) PLQP0064KB-A (64P6Q-A)/PLQP0064GA-A (64P6U-A) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M38049FFLSP VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN XOUT VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) Package code : PRDP0064BA-A (64P4B) Fig. 2 Pin configuration (Top view) (PRDP0064BA-A (64P4B)) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 2 of 128 3804 Group (Spec.L) PIN CONFIGURATION (TOP VIEW) A 8 7 6 5 4 3 2 1 B C D E F G H 50 46 44 41 40 32 31 30 P36/SCLK3 P02/AN10 P04/AN12 P07/AN15 P10/INT41 P20(LED0) P21(LED1) P22(LED2) 51 47 45 42 39 27 29 28 P35/TXD3 P01/AN9 P03/AN11 P06/AN14 P11/INT01 P25(LED5) P23(LED3) P24(LED4) 53 52 48 43 38 37 26 25 P33/SCL P34/RXD3 P00/AN8 P05/AN13 P12 P13 P26(LED6) P27(LED7) 56 55 54 49 33 36 35 34 P30/DA1 P31/DA2 P32/SDA P37/SRDY3 P17 P14 P15 P16 1 64 58 59 57 24 22 23 P62/AN2 P63/AN3 VREF AVSS VCC VSS XIN XOUT 60 61 4 7 P67/AN7 P66/AN6 P57/INT3 P54/CNTR0 12 62 63 5 8 10 13 17 19 P65/AN5 P64/AN4 P56/PWM P53/SRDY2 P51/SOUT2 P46/SCLK1 P42/INT1 RESET 2 3 6 9 11 15 16 18 P61/AN1 P60/AN0 P55/CNTR1 P52/SCLK2 P50/SIN2 P44/RXD1 P43/INT2 CNVSS A B C D E F G H P47/SRDY1/CNTR2 14 P45/TXD1 21 P40/INT40/XCOUT 20 M38049 FFLWG Package (TOP VIEW) Fig. 3 Pin configuration (Top view) (PTLG0064JA-A (64F0G)) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 3 of 128 7 6 5 4 3 P41/INT00/XCIN Package code : PTLG0064JA-A (64F0G) Note : The numbers in circles corresponds with the number on the packages HP/KP. 8 2 1 3804 Group (Spec.L) Table 1 Performance overview Parameter Function Number of basic instructions 71 Minimum instruction execution time 0.24 μs (Oscillation frequency 16.8 MHz) Oscillation frequency Oscillation frequency 16.8 MHz (Maximum) Memory sizes ROM 60 Kbytes RAM 2048 bytes I/O port P0-P6 56 pins Software pull-up resistors Built-in Interrupt 21 sources, 16 vectors (8 external, 12 internal, 1 software) Timer 8-bit × 4 (with 8-bit prescaler), 16-bit × 1 Serial interface 8-bit × 2 (UART or Clock-synchronized) 8-bit × 1 (Clock-synchronized) PWM 8-bit × 1 (with 8-bit prescaler) A/D converter 10-bit × 16 channels (8-bit reading enabled) D/A converter 8-bit × 2 channels Watchdog timer 16-bit × 1 Multi-master I2C-BUS interface 1 channel LED direct drive port 8 (average current: 15 mA, peak current: 30 mA, total current: 90 mA) Clock generating circuits Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode In middle-speed mode At 16.8 MHz 4.5 to 5.5 V At 12.5 MHz 4.0 to 5.5 V At 8.4 MHz 2.7 to 5.5 V At 16.8 MHz 4.5 to 5.5 V At 12.5 MHz In low-speed mode At 32 MHz Power dissipation 2.7 to 5.5 V 2.7 to 5.5 V In high-speed mode Typ. 27.5 mW (Vcc = 5.0 V, f(XIN) = 16.8 MHz, Ta = 25 °C) In low-speed mode Typ. 1200 μW (Vcc = 3.0 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25 °C) Operating temperature range -20 to 85 °C Device structure CMOS silicon gate Package 64-pin plastic molded SDIP/LQFP/FLGA Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 4 of 128 Fig. 4 Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Functional block diagram Page 5 of 128 VREF AVSS 3 A/D converter (10) 2 31 28 29 I/O port P5 12 13 14 15 16 17 18 19 4 5 6 7 8 9 10 11 I/O port P6 P5 (8) INT3 RAM P6 (8) PWM (8) Main clock Sub-clock Sub-clock output output input XOUT XCIN XCOUT Clock generating circuit 30 Main clock input XIN SI/O2 (8) ROM P4 (8) I/O port P4 PS PCL S Y X A INT00 INT1 INT2 INT40 D/A converter 2 (8) C P U 20 21 22 23 24 25 28 29 SI/O1 (8) 0 PCH 1 32 Data bus VCC VSS D/A converter 1 (8) FUNCTIONAL BLOCK DIAGRAM (Package: PRDP0064BA-A (64P4B)) I/O port P3 57 58 59 60 61 62 63 64 P3 (8) SI/O3 (8) 27 Reset input RESET I/O port P2 (LED drive) I/O port P0 49 50 51 52 53 54 55 56 41 42 43 44 45 46 47 48 I/O port P1 P0 (8) INT01 INT41 P1 (8) I2C Timer Y (8) Timer X (8) Timer 2 (8) Timer 1 (8) Timer Z (16) Prescaler Y (8) Prescaler X (8) Prescaler 12 (8) 33 34 35 36 37 38 39 40 P2 (8) CNTR2 CNTR1 CNTR0 26 CNVSS 3804 Group (Spec.L) 3804 Group (Spec.L) PIN DESCRIPTION Table 2 Pin description Pin Name Functions Function except a port function VCC, VSS Power source • Apply voltage of 2.7 V − 5.5 V to VCC, and 0 V to VSS. CNVSS CNVSS input • This pin controls the operation mode of the chip. • Normally connected to VSS. VREF Reference voltage • Reference voltage input pin for A/D and D/A converters. AVSS Analog power source • Analog power source input pin for A/D and D/A converters. • Connect to VSS. RESET Reset input • Reset input pin for active “L”. XIN Main clock input • Input and output pins for the clock generating circuit. • Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. Main clock • When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin output open. XOUT P00/AN8− P07/AN15 I/O port P0 P10/INT41 P11/INT01 I/O port P1 P12−P17 • 8-bit CMOS I/O port. • I/O direction register allows each pin to be individually programmed as either input or output. • CMOS compatible input level. • CMOS 3-state output structure. • Pull-up control is enabled in a bit unit. • P20 − P27 (8 bits) are enabled to output large current for LED drive. • A/D converter input pin • Interrupt input pin P20(LED0)P27(LED7) I/O port P2 P30/DA1 P31/DA2 I/O port P3 • D/A converter input pin • 8-bit CMOS I/O port. • I/O direction register allows each pin to be individually programmed as either input or output. • I2C-BUS interface function pins • CMOS compatible input level. • P32 to P33 can be switched between CMOS compatible • Serial I/O3 function pin input level or SMBUS input level in the I2C-BUS interface function. • P30, P31, P34 − P37 are CMOS 3-state output structure. • P32, P33 are N-channel open-drain output structure. • Pull-up control of P30, P31, P34 − P37 is enabled in a bit unit. I/O port P4 • 8-bit CMOS I/O port. • I/O direction register allows each pin to be individually programmed as either input or output. • CMOS compatible input level. • CMOS 3-state output structure. • Pull-up control is enabled in a bit unit. P32/SDA P33/SCL P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P40/INT40/XCOUT P41/INT00/XCIN P42/INT1 P43/INT2 P44/RXD1 P45/TXD1 P46/SCLK1 • Interrupt input pin • Serial I/O1 function pin • Serial I/O1, timer Z function pin P47/SRDY1/CNTR2 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 • Interrupt input pin • Sub-clock generating I/O pin (resonator connected) I/O port P5 • Serial I/O2 function pin P54/CNTR0 • Timer X function pin P55/CNTR1 • Timer Y function pin P56/PWM • PWM output pin P57/INT3 • Interrupt input pin P60/AN0− P67/AN7 I/O port P6 Rev.1.00 Oct 27, 2008 REJ03B0266-0100 • A/D converter input pin Page 6 of 128 3804 Group (Spec.L) PART NUMBERING Product name M3804 9 F F L SP Package code SP : PRDP0064BA-A (64P4B) HP : PLQP0064KB-A (64P6Q-A) KP : PLQP0064GA-A (64P6U-A) WG : PTLG0064JA-A (64F0G) -: standard L: Minner spec. change product ROM/PROM size 1: 4096 bytes 2: 8192 bytes 3: 12288 bytes 4: 16384 bytes 5: 20480 bytes 6: 24576 bytes 7: 28672 bytes 8: 32768 bytes 9: 36864 bytes A: 40960 bytes B: 45056 bytes C: 49152 bytes D: 53248 bytes E: 57344 bytes F: 61440 bytes Memory type F: Flash memory version RAM size 0: 192 bytes 1: 256 bytes 2: 384 bytes 3: 512 bytes 4: 640 bytes Fig. 5 Part numbering Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 7 of 128 5: 768 bytes 6: 896 bytes 7: 1024 bytes 8: 1536 bytes 9: 2048 bytes 3804 Group (Spec.L) GROUP EXPANSION Renesas plans to expand the 3804 group (Spec.L) as follows. Memory Size • Flash memory size .....................................................60 Kbytes • RAM size ................................................................. 2048 bytes Packages • PRDP0064BA-A (64P4B) ........................................... 64-pin shrink plastic-molded SDIP • PLQP0064KB-A (64P6Q-A) ...........................................0.5 mm-pitch plastic molded LQFP • PLQP0064GA-A (64P6U-A) ...........................................0.8 mm-pitch plastic molded LQFP • PTLG0064JA-A (64F0G) ........................................0.65 mm-pitch plastic molded FLGA Memory Expansion Plan ROM size (bytes) M38049FFL 60 K 48 K 32 K 28 K 24 K 20 K 16 K 12 K 8K 384 512 640 768 896 1024 1152 1280 1408 1536 2048 3072 4032 RAM size (bytes) Fig. 6 Table 3 Memory expansion plan Support products Part No. ROM size (bytes) RAM size (bytes) Package M38049FFLSP PRDP0064BA-A (64P4B) M38049FFLHP PLQP0064KB-A (64P6Q-A) M38049FFLKP 57344+4096 (NOTE) M38049FFLWG PLQP0064GA-A (64P6U-A) PTLG0064JA-A (64F0G) NOTE: 1. ROM size includes the ID code area. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 2048 Page 8 of 128 Remarks VCC = 2.7 to 5.5 V 3804 Group (Spec.L) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3804 group (Spec.L) uses the standard 740 Family instruction set. Refer to the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc. are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b7 [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0”, the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 8. Store registers other than those described in Figure 7 with program when the user needs them during interrupts or subroutine calls (see Table 4). [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b0 A b7 Accumulator b0 X b7 Index Register X b0 Y b7 Index Register Y b0 S b15 b7 b0 PCL PCH Stack Pointer Program Counter b7 b0 N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig. 7 740 Family CPU register structure Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 9 of 128 3804 Group (Spec.L) On-going Routine Interrupt request(1) M(S)←(PCH) Push Return Address on Stack (S)←(S) − 1 Execute JSR M(S)←(PCL) Push Return Address on Stack M(S)←(PCH) (S)←(S) − 1 (S)←(S) − 1 M(S)←(PS) M(S)←(PCL) Push Contents of Processor Status Register on Stack (S)←(S) − 1 (S)←(S) − 1 Interrupt Service Routine ..... Subroutine ..... Execute RTI I Flag is Set from “0” to “1” Fetch the Jump Vector Execute RTS (S)←(S) + 1 POP Return Address from Stack (S)←(S) + 1 (PS)←M(S) POP Contents of Processor Status Register from Stack (PCL)←M(S) (S)←(S) + 1 (S)←(S) + 1 (PCL)←M(S) (PCH)←M(S) POP Return Address from Stack (S)←(S) + 1 (PCH)←M(S) Note 1 : Condition for acceptance of an interrupt → Interrupt enable flag is “1” Interrupt disable flag is “0” Fig. 8 Table 4 Register push and pop at interrupt generation and subroutine call Push and pop instructions of accumulator or processor status register Push instruction to stack PHA PHP Accumulator Processor status register Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 10 of 128 Pop instruction from stack PLA PLP 3804 Group (Spec.L) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to − 128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can execute decimal arithmetic. Table 5 Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Z flag − − Page 11 of 128 I flag SEI CLI D flag SED CLD B flag − − T flag SET CLT V flag − CLV N flag − − 3804 Group (Spec.L) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, the internal system clock control bits, etc. The CPU mode register is allocated at address 003B16. b7 b0 1 CPU mode register (CPUM: address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to “1”. Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig. 9 Structure of CPU mode register Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 12 of 128 3804 Group (Spec.L) MISRG (1) Bit 0 of address 001016: Oscillation stabilizing time set after STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt source, usually, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = 01 1 6 , Prescaler 12 = FF 1 6 ) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by setting “1” to bit 0 of MISRG (address 001016). However, by setting this bit to “1”, the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Figure 10 shows the structure of MISRG. • Middle-speed mode automatic switch by program The middle-speed mode can also be automatically switched by program while operating in low-speed mode. By setting the middle-speed automatic switch start bit (bit 3) of MISRG (address 001016) to “1” in the condition that the middle-speed mode automatic switch set bit is “1” while operating in lowspeed mode, the MCU will automatically switch to middle-speed mode. In this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of MISRG (address 001016). (2) Bits 1, 2, 3 of address 001016: Middle-speed Mode Automatic Switch Function In order to switch the clock mode of an MCU which has a subclock, the following procedure is necessary: set CPU mode register (003B16) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). However, the 3804 group (Spec.L) has the built-in function which automatically switches from low to middle-speed mode by program. b7 b0 MISRG (MISRG: address 001016) Oscillation stabilizing time set after STP instruction released bit 0 : Automatically set “0116” to Timer 1, “FF16” to Prescaler 12 1 : Automatically set disabled Middle-speed mode automatic switch set bit 0 : Not set automatically 1 : Automatic switching enabled (1) Middle-speed mode automatic switch wait time set bit 0 : 4.5 to 5.5 machine cycles 1 : 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0 : Invalid 1 : Automatic switch start(1) Not used (return “0” when read) (Do not write “1” to this bit) Note 1 : When automatic switch to middle-speed mode from low-speed mode occurs, the values of CPU mode register (3B 16) change. Fig. 10 Structure of MISRG Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 13 of 128 3804 Group (Spec.L) MEMORY • Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. • RAM The RAM is used for data storage and for stack area of subroutine calls and interrupts. • ROM The ROM area can program/erase. • Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. • Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. <Note> Since the contents of RAM are undefined at reset, be sure to set an initial value before use. • Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 Address XXXX 16 0 0 0 0 16 00FF 16 013F 16 01BF 16 023F 16 02BF 16 033F 16 03BF 16 043F 16 063F 16 083F 16 0 0 4 0 16 RAM SFR area Zero page 0 10 0 16 XXXX16 Not used 0FF0 16 0FFF 16 SFR area Not used ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY 16 F000 16 E00016 D000 16 C000 16 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Fig. 11 Memory map diagram Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 14 of 128 YYYY16 ROM FF00 16 FFD4 16 FFDB 16 FFDC16 FFFE 16 FFFF 16 Reserved ROM area (ID code) Reserved ROM area (ROM code Protect) Interrupt vector area Reserved ROM area Special page 3804 Group (Spec.L) 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 002016 Prescaler 12 (PRE12) 002116 Timer 1 (T1) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 002216 Timer 2 (T2) 002316 Timer XY mode register (TM) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 002416 Prescaler X (PREX) 002516 Timer X (TX) 000616 Port P3 (P3) 000716 Port P3 direction register (P3D) 002616 Prescaler Y (PREY) 002716 Timer Y (TY) 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 002816 Timer Z low-order (TZL) 002916 Timer Z high-order (TZH) 002A16 Timer Z mode register (TZM) 002B16 PWM control register (PWMCON) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Timer 12, X count source selection register (T12XCSS) 002C16 PWM prescaler (PREPWM) 002D16 PWM register (PWM) 002E16 000F16 Timer Y, Z count source selection register (TYZCSS) 001016 MISRG 002F16 Baud rate generator 3 (BRG3) 003016 Transmit/Receive buffer register 3 (TB3/RB3) 001116 I2C data shift register (S0) 001216 I2C special mode status register (S3) 003116 Serial I/O3 status register (SIO3STS) 003216 Serial I/O3 control register (SIO3CON) 001316 I C status register (S1) 001416 I2C control register (S1D) 003316 UART3 control register (UART3CON) 003416 AD/DA control register (ADCON) 001516 I2C clock control register (S2) 001616 I2C START/STOP condition control register (S2D) 003516 AD conversion register 1 (AD1) 003616 DA1 conversion register (DA1) 001716 I C special mode control register (S3D) 001816 Transmit/Receive buffer register 1 (TB1/RB1) 003716 DA2 conversion register (DA2) 003816 AD conversion register 2 (AD2) 001916 Serial I/O1 status register (SIO1STS) 001A16 Serial I/O1 control register (SIO1CON) 003916 Interrupt source selection register (INTSEL) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART1 control register (UART1CON) 001C16 Baud rate generator (BRG1) 003B16 CPU mode register (CPUM) 2 2 001D16 Serial I/O2 control register (SIO2CON) 001E16 Watchdog timer control register (WDTCON) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 Interrupt control register 1 (ICON1) 001F16 Serial I/O2 register (SIO2) 003F16 Interrupt control register 2 (ICON2) 0FE016 Flash memory control register 0 (FMCR0) 0FE116 Flash memory control register 1 (FMCR1) 0FF016 Port P0 pull-up control register (PULL0) 0FF116 Port P1 pull-up control register (PULL1) 0FE216 Flash memory control register 2 (FMCR2) 0FE316 Reserved (1) 0FF216 Port P2 pull-up control register (PULL2) 0FF316 Port P3 pull-up control register (PULL3) 0FE416 Reserved (1) 0FE516 Reserved (1) 0FF416 Port P4 pull-up control register (PULL4) 0FF516 Port P5 pull-up control register (PULL5) Reserved (1) 0FF616 Port P6 pull-up control register (PULL6) 0FE716 Reserved (1) 0FE816 Reserved (1) 0FF716 I2C slave address register 0 (S0D0) 0FF816 I2C slave address register 1 (S0D1) 0FE916 Reserved (1) 0FF916 I2C slave address register 2 (S0D2) 0FEA16 Reserved (1) 0FE616 0FEB16 Reserved (1) 0FEC16 Reserved (1) Note 1: Do not write any data to these addresses, because these are reserved area. 0FED16 Reserved (1) 0FEE16 Reserved (1) 0FEF16 Reserved (1) Fig. 12 Memory map of special function register (SFR) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 15 of 128 3804 Group (Spec.L) I/O PORTS The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to Table 6 input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. By setting the port P0 pull-up control register (address 0FF016) to the port P6 pull-up control register (address 0FF616) ports can control pull-up with a program. However, the contents of these registers do not affect ports programmed as the output ports. I/O port function Pin P00/AN8−P07/AN15 P10/INT41 P11/INT01 P12−P17 P20(LED0)− P27(LED7) P30/DA1 P31/DA2 P32/SDA P33/SCL Name Input/ I/O Structure Output Port P0 Input/output, CMOS compatible input level CMOS 3-state output Port P1 individual bits Port P3 CMOS compatible input level N-channel open-drain output CMOS/SMBUS input level (when selecting I2C-BUS interface function) CMOS compatible input level CMOS 3-state output Port P4 D/A converter output AD/DA control register (4) I2C-BUS interface function I/O I2C control register (5) Serial I/O3 function I/O Serial I/O3 control register UART3 control register Interrupt edge selection (10) register (11) CPU mode register Interrupt edge selection (2) register Serial I/O1 function I/O Serial I/O1 control register (6) UART1 control register (7) (8) Serial I/O1 function I/O Serial I/O1 control register (12) Timer Z function I/O Timer Z mode register Serial I/O2 function I/O Serial I/O2 control register (13) (14) (15) (16) Port P5 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 Port P6 Timer X, Y function I/O Timer XY mode register (17) PWM output PWM control register External interrupt input Interrupt edge selection register A/D converter input AD/DA control register (18) (2) NOTES: 1. Refer to the applicable sections how to use double-function ports as function I/O ports. 2. Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 (6) (7) (8) (9) External interrupt input Sub-clock generating circuit External interrupt input P47/SRDY1/CNTR2 P60/AN0−P67/AN7 A/D converter input AD/DA control register External interrupt input Interrupt edge selection register Ref. No. (1) (2) (3) P42/INT1 P43/INT2 P44/RXD1 P45/TXD1 P46/SCLK1 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 Related SFRs Port P2 P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P40/INT40/XCOUT P41/INT00/XCIN Non-Port Function Page 16 of 128 (1) 3804 Group (Spec.L) (1) Ports P0, P6 (2) Ports P10, P11, P42, P43, P57 Pull-up control bit Pull-up control bit Direction register Direction register Port latch Data bus Port latch Data bus A/D converter input Interrupt input Analog input pin selection bit (3) Ports P12 to P17, P2 (4) Ports P30, P31 Pull-up control bit Pull-up control bit Direction register Direction register Port latch Data bus Port latch Data bus D/A converter output DA1 output enable bit (P30) DA2 output enable bit (P31) (5) Ports P32, P33 (6) Ports P34, P44 Pull-up control bit Serial I/O enable bit Receive enable bit I2C-BUS interface enable bit Direction register Data bus Direction register Port latch Data bus SDA output SCL output Port latch SDA input SCL input (7) Ports P35, P45 Serial I/O input (8) Ports P36, P46 Pull-up control bit Serial I/O enable bit Transmit enable bit P-channel output disable bit Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Pull-up control bit Serial I/O enable bit Direction register Data bus Direction register Data bus Port latch Serial I/O output Port latch Serial I/O clock output Serial I/O external clock input Fig. 13 Port block diagram (1) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 17 of 128 3804 Group (Spec.L) (9) Port P37 (10) Port P40 Pull-up control bit Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit SRDY3 output enable bit Port XC switch bit Direction register Direction register Data bus Data bus Port latch Port latch INT40 Interrupt input Serial I/O3 ready output Port XC switch bit (11) Port P41 (12) Port P47 Pull-up control bit Timer Z operating mode bits Bit 2 Bit 1 Bit 0 Port XC switch bit Direction register Data bus Pull-up control bit Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Port latch Direction register INT00 Interrupt input Data bus Port latch Port XC switch bit Sub-clock generating circuit input Timer output Serial I/O1 ready output CNTR2 interrupt input (13) Port P50 (14) Port P51 Pull-up control bit Pull-up control bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register Direction register Data bus Port latch Data bus Port latch Serial I/O2 input Serial I/O2 output Fig. 14 Port block diagram (2) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 18 of 128 P-channel output disable bit 3804 Group (Spec.L) (15) Port P52 (16) Port P53 Pull-up control bit Pull-up control bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit SRDY2 output enable bit Direction register Direction register Data bus Data bus Port latch Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P54, P55 (18) Port P56 Pull-up control bit Pull-up control bit PWM function enable bit Direction register Data bus Direction register Port latch Data bus Port latch Pulse output mode Timer output PWM output CNTR Interrupt input Fig. 15 Port block diagram (3) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 19 of 128 3804 Group (Spec.L) b7 b0 Port P0 pull-up control register (PULL0: address 0FF016) P00 pull-up control bit 0: No pull-up 1: Pull-up P01 pull-up control bit 0: No pull-up 1: Pull-up P02 pull-up control bit 0: No pull-up 1: Pull-up P03 pull-up control bit 0: No pull-up 1: Pull-up P04 pull-up control bit 0: No pull-up 1: Pull-up P05 pull-up control bit 0: No pull-up 1: Pull-up P06 pull-up control bit 0: No pull-up 1: Pull-up P07 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P1 pull-up control register (PULL1: address 0FF116) P10 pull-up control bit 0: No pull-up 1: Pull-up P11 pull-up control bit 0: No pull-up 1: Pull-up P12 pull-up control bit 0: No pull-up 1: Pull-up P13 pull-up control bit 0: No pull-up 1: Pull-up P14 pull-up control bit 0: No pull-up 1: Pull-up P15 pull-up control bit 0: No pull-up 1: Pull-up P16 pull-up control bit 0: No pull-up 1: Pull-up P17 pull-up control bit 0: No pull-up 1: Pull-up Fig. 16 Structure of port pull-up control register (1) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 20 of 128 3804 Group (Spec.L) b7 b0 Port P2 pull-up control register (PULL2: address 0FF216) P20 pull-up control bit 0: No pull-up 1: Pull-up P21 pull-up control bit 0: No pull-up 1: Pull-up P22 pull-up control bit 0: No pull-up 1: Pull-up P23 pull-up control bit 0: No pull-up 1: Pull-up P24 pull-up control bit 0: No pull-up 1: Pull-up P25 pull-up control bit 0: No pull-up 1: Pull-up P26 pull-up control bit 0: No pull-up 1: Pull-up P27 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P3 pull-up control register (PULL3: address 0FF316) P30 pull-up control bit 0: No pull-up 1: Pull-up P31 pull-up control bit 0: No pull-up 1: Pull-up Not used (return “0” when read) P34 pull-up control bit 0: No pull-up 1: Pull-up P35 pull-up control bit 0: No pull-up 1: Pull-up P36 pull-up control bit 0: No pull-up 1: Pull-up P37 pull-up control bit 0: No pull-up 1: Pull-up Fig. 17 Structure of port pull-up control register (2) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 21 of 128 3804 Group (Spec.L) b7 b0 Port P4 pull-up control register (PULL4: address 0FF416) P40 pull-up control bit 0: No pull-up 1: Pull-up P41 pull-up control bit 0: No pull-up 1: Pull-up P42 pull-up control bit 0: No pull-up 1: Pull-up P43 pull-up control bit 0: No pull-up 1: Pull-up P44 pull-up control bit 0: No pull-up 1: Pull-up P45 pull-up control bit 0: No pull-up 1: Pull-up P46 pull-up control bit 0: No pull-up 1: Pull-up P47 pull-up control bit 0: No pull-up 1: Pull-up b7 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b0 Port P5 pull-up control register (PULL5: address 0FF516) P50 pull-up control bit 0: No pull-up 1: Pull-up P51 pull-up control bit 0: No pull-up 1: Pull-up P52 pull-up control bit 0: No pull-up 1: Pull-up P53 pull-up control bit 0: No pull-up 1: Pull-up P54 pull-up control bit 0: No pull-up 1: Pull-up P55 pull-up control bit 0: No pull-up 1: Pull-up P56 pull-up control bit 0: No pull-up 1: Pull-up P57 pull-up control bit 0: No pull-up 1: Pull-up Fig. 18 Structure of port pull-up control register (3) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 22 of 128 3804 Group (Spec.L) b7 b0 Port P6 pull-up control register (PULL6: address 0FF616) P60 pull-up control bit 0: No pull-up 1: Pull-up P61 pull-up control bit 0: No pull-up 1: Pull-up P62 pull-up control bit 0: No pull-up 1: Pull-up P63 pull-up control bit 0: No pull-up 1: Pull-up P64 pull-up control bit 0: No pull-up 1: Pull-up P65 pull-up control bit 0: No pull-up 1: Pull-up P66 pull-up control bit 0: No pull-up 1: Pull-up P67 pull-up control bit 0: No pull-up 1: Pull-up Fig. 19 Structure of port pull-up control register (4) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 23 of 128 Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. 3804 Group (Spec.L) Termination of unused pins • Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. In addition, it is recommended that related registers be overwritten periodically to prevent malfunctions, etc. Output ports: Open. Input ports: If the input level become unstable, through current flow to an input circuit, and the power supply current may increase. Table 7 Especially, when expecting low consumption current (at STP or WIT instruction execution etc.), pull-up or pull-down input ports to prevent through current (built-in resistor can be used). We recommend processing unused pins through a resistor which can secure IOH(avg) or IOL(avg). Because, when an I/O port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc. Termination of unused pins Pins P0, P1, P2, P3, P4, P5, P6 VREF AVSS XOUT Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Termination • Set to the input mode and connect each to VCC or VSS through a resistor of 1 kΩ to 10 kΩ. • Set to the output mode and open at “L” or “H” output state. Connect to VCC or VSS (GND). Connect to VCC or VSS (GND). Open (only when using external clock) Page 24 of 128 3804 Group (Spec.L) INTERRUPTS The 3804 group (Spec.L) interrupts are vector interrupts with a fixed priority scheme, and generated by 16 sources among 24 sources: 10 external, 13 internal, and 1 software. The interrupt sources, vector addresses(1), and interrupt priority are shown in Table 8. Each interrupt except the BRK instruction interrupt has the interrupt request bit and the interrupt enable bit. These bits and the interrupt disable flag (I flag) control the acceptance of interrupt requests. Figure 20 shows an interrupt control diagram. Table 8 An interrupt requests is accepted when all of the following conditions are satisfied: • Interrupt disable flag.................................“0” • Interrupt request bit...................................“1” • Interrupt enable bit....................................“1” Though the interrupt priority is determined by hardware, priority processing can be performed by software using the above bits and flag. Interrupt vector addresses and priority 1 Vector Interrupt Request Generating Addresses(1) Conditions High Low FFFD16 FFFC16 At reset 2 FFFB16 FFFA16 Timer Z INT1 3 FFF916 FFF816 Serial I/O1 reception 4 FFF716 FFF616 Serial I/O1 transmission 5 FFF516 FFF416 Interrupt Source Reset(2) INT0 Priority SCL, SDA 6 7 8 9 10 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFF216 FFF016 FFEE16 FFEC16 FFEA16 11 FFE916 FFE816 Serial I/O2 12 FFE716 FFE616 Timer Z INT2 13 FFE516 FFE416 I2C INT3 14 FFE316 FFE216 INT4 15 FFE116 FFE016 16 FFDF16 FFDE16 Timer X Timer Y Timer 1 Timer 2 CNTR0 SCL, SDA CNTR1 Serial I/O3 reception CNTR2 A/D conversion Serial I/O3 transmission At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At detection of either rising or falling edge of SCL or SDA At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of SCL or SDA At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception At completion of serial I/O2 data transmission or reception At timer Z underflow At detection of either rising or falling edge of INT2 input At completion of data transfer At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input At completion of A/D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty At BRK instruction execution BRK instruction 17 FFDD16 FFDC16 NOTES: 1. Vector addresses contain interrupt jump destination addresses. 2. Reset function in the same way as an interrupt with the highest priority. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 25 of 128 Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected External interrupt (active edge selectable) STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Non-maskable software interrupt 3804 Group (Spec.L) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig. 20 Interrupt control diagram • Interrupt Disable Flag The interrupt disable flag is assigned to bit 2 of the processor status register. This flag controls the acceptance of all interrupt requests except for the BRK instruction. When this flag is set to “1”, the acceptance of interrupt requests is disabled. When it is set to “0”, acceptance of interrupt requests is enabled. This flag is set to “1” with the SET instruction and set to “0” with the CLI instruction. When an interrupt request is accepted, the contents of the processor status register are pushed onto the stack while the interrupt disable flag remains set to “0”. Subsequently, this flag is automatically set to “1” and multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI instruction within the interrupt processing routine. The contents of the processor status register are popped off the stack with the RTI instruction. • Interrupt Request Bits Once an interrupt request is generated, the corresponding interrupt request bit is set to “1” and remains “1” until the request is accepted . Wh en the request is accepted, th is bit is automatically set to “0”. Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software. • Interrupt Enable Bits The interrupt enable bits control the acceptance of the corresponding interrupt requests. When an interrupt enable bit is set to “0”, the acceptance of the corresponding interrupt request is disabled. If an interrupt request occurs in this condition, the corresponding interrupt request bit is set to “1”, but the interrupt request is not accepted. When an interrupt enable bit is set to “1”, acceptance of the corresponding interrupt request is enabled. Each interrupt enable bit can be set to “0” or “1” by software. The interrupt enable bit for an unused interrupt should be set to “0”. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 26 of 128 • Interrupt Source Selection Any of the following combinations can be selected by the interrupt source selection register (003916). 1. INT0 or timer Z 2. Serial I/O1 transmission or SCL, SDA 3. CNTR0 or SCL, SDA 4. CNTR1 or Serial I/O3 reception 5. Serial I/O2 or timer Z 6. INT2 or I2C 7. INT4 or CNTR2 8. A/D conversion or serial I/O3 transmission • External Interrupt Pin Selection For external interrupts INT0 and INT4, the INT0, INT4 interrupt switch bit in the interrupt edge selection register (bit 6 of address 003A 16 ) can be used to select INT00 and INT40 pin input or INT01 and INT41 pin input. 3804 Group (Spec.L) b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit Not used (returns “0” when read) INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit INT0, INT4 interrupt switch bit 0 : INT00, INT40 interrupt 1 : INT01, INT41 interrupt Not used (returns “0” when read) b7 b0 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active Interrupt request register 1 (IREQ1 : address 003C16) b7 b0 INT0/Timer Z interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit/SCL,SDA interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit CNTR0/SCL,SDA interrupt request bit CNTR1/Serial I/O3 receive interrupt request bit Serial I/O2/Timer Z interrupt request bit INT2/I2C interrupt request bit INT3 interrupt request bit INT4/CNTR2 interrupt request bit AD converter/Serial I/O3 transmit interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0/Timer Z interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit/SCL,SDA interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0/SCL,SDA interrupt enable bit CNTR1/Serial I/O3 receive interrupt enable bit Serial I/O2/Timer Z interrupt enable bit INT2/I2C interrupt enable bit INT3 interrupt enable bit INT4/CNTR2 interrupt enable bit AD converter/Serial I/O3 transmit interrupt enable bit Not used (returns “0” when read) (Do not write “1”.) 0 : Interrupts disabled 1 : Interrupts enabled Interrupt source selection register (INTSEL : address 003916) INT0/Timer Z interrupt source selection bit 0 : INT0 interrupt 1 : Timer Z interrupt (Do not write “1” to these bits simultaneously.) Serial I/O2/Timer Z interrupt source selection bit 0 : Serial I/O2 interrupt 1 : Timer Z interrupt Serial I/O1 transmit/SCL, SDA interrupt source selection bit 0 : Serial I/O1 transmit interrupt 1 : SCL, SDA interrupt (Do not write “1” to these bits simultaneously.) CNTR0/SCL, SDA interrupt source selection bit 0 : CNTR0 interrupt 1 : SCL, SDA interrupt INT4/CNTR2 interrupt source selection bit 0 : INT4 interrupt 1 : CNTR2 interrupt INT2/I2C interrupt source selection bit 0 : INT2 interrupt 1 : I2C interrupt CNTR1/Serial I/O3 receive interrupt source selection bit 0 : CNTR1 interrupt 1 : Serial I/O3 receive interrupt AD converter/Serial I/O3 transmit interrupt source selection bit 0 : A/D converter interrupt 1 : Serial I/O3 transmit interrupt Fig. 21 Structure of interrupt-related registers Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 27 of 128 3804 Group (Spec.L) • Interrupt Request Generation, Acceptance, and Handling Interrupts have the following three phases. (i) Interrupt Request Generation An interrupt request is generated by an interrupt source (external interrupt signal input, timer underflow, etc.) and the corresponding request bit is set to “1”. (ii) Interrupt Request Acceptance Based on the interrupt acceptance timing in each instruction cycle, the interrupt control circuit determines acceptance conditions (interrupt request bit, interrupt enable bit, and interrupt disable flag) and interrupt priority levels for accepting interrupt requests. When two or more interrupt requests are generated simultaneously, the highest priority interrupt is accepted. The value of interrupt request bit for an unaccepted interrupt remains the same and acceptance is determined at the next interrupt acceptance timing point. (iii) Handling of Accepted Interrupt Request The accepted interrupt request is processed. Figure 22 shows the time up to execution in the interrupt processing routine, and Figure 23 shows the interrupt sequence. Figure 24 shows the timing of interrupt request generation, interrupt request bit, and interrupt request acceptance. • Interrupt Handling Execution When interrupt handling is executed, the following operations are performed automatically. (1) Once the currently executing instruction is completed, an interrupt request is accepted. (2) The contents of the program counters and the processor status register at this point are pushed onto the stack area in order from 1 to 3. 1. High-order bits of program counter (PCH) 2. Low-order bits of program counter (PCL) 3. Processor status register (PS) (3) Concurrently with the push operation, the jump address of the corresponding interrupt (the start address of the interrupt processing routine) is transferred from the interrupt vector to the program counter. (4) The interrupt request bit for the corresponding interrupt is set to “0”. Also, the interrupt disable flag is set to “1” and multiple interrupts are disabled. (5) The interrupt routine is executed. (6) When the RTI instruction is executed, the contents of the registers pushed onto the stack area are popped off in the order from 3 to 1. Then, the routine that was before running interrupt processing resumes. As described above, it is necessary to set the stack pointer and the jump address in the vector area corresponding to each interrupt to execute the interrupt processing routine. <Notes> The interrupt request bit may be set to “1” in the following cases. • When setting the external interrupt active edge Related registers: Interrupt edge selection register (address 003A16) Timer XY mode register (address 002316) Timer Z mode register (address 002A16) I2C START/STOP condition control register (address 001616) • When switching the interrupt sources of an interrupt vector address where two or more interrupt sources are assigned Related registers: Interrupt source selection register (address 003916) If it is not necessary to generate an interrupt synchronized with these settings, take the following sequence. (1) Set the corresponding enable bit to “0” (disabled). (2) Set the interrupt edge selection bit (the active edge switch bit) or the interrupt source bit. (3) Set the corresponding interrupt request bit to “0” after one or more instructions have been executed. (4) Set the corresponding interrupt enable bit to “1” (enabled). Interrupt request generated Interrupt request acceptance Interrupt routine starts Interrupt sequence Stack push and Vector fetch Main routine * 0 to 16 cycles 7 cycles 7 to 23 cycles * When executing DIV instruction Fig. 22 Time up to execution in interrupt routine Push onto stack Vector fetch Page 28 of 128 Execute interrupt routine φ SYNC RD WR Address bus Data bus PC Not used S,SPS S-1,SPS S-2,SPS PCH PCL PS BL BH AL AL,AH AH SYNC : CPU operation code fetch cycle (This is an internal signal that cannot be observed from the external unit.) BL, BH: Vector address of each interrupt AL, AH: Jump destination address of each interrupt SPS : “0016” or “0116” ([SPS] is a page selected by the stack page selection bit of CPU mode register.) Fig. 23 Interrupt sequence Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Interrupt handling routine 3804 Group (Spec.L) Push onto stack Vector fetch Instruction cycle Instruction cycle Internal clock φ SYNC 1 2 IR1 T2 T1 IR2 T3 T1 T2 T3 : Interrupt acceptance timing points IR1 IR2 : Timings points at which the interrupt request bit is set to “1”. Note : Period 2 indicates the last φ cycle during one instruction cycle. (1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1. (2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2. The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2 separately. Fig. 24 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 29 of 128 3804 Group (Spec.L) TIMERS • 8-bit Timers The 3804 group (Spec.L) has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use each prescaler. Those are 8-bit prescalers. Each of the timers and prescalers has a timer latch or a prescaler latch. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are down-counters. When the timer reaches “0016”, an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to “1”. • Timer divider The divider count source is switched by the main clock division ratio selection bits of CPU mode register (bits 7 and 6 at address 003B16). When these bits are “00” (high-speed mode) or “01” (middle-speed mode), XIN is selected. When these bits are “10” (low-speed mode), XCIN is selected. • Prescaler 12 The prescaler 12 counts the output of the timer divider. The count source is selected by the timer 12, X count source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(XIN) or f(XCIN). • Timer 1 and Timer 2 The timer 1 and timer 2 counts the output of prescaler 12 and periodically set the interrupt request bit. • Prescaler X and prescaler Y The prescaler X and prescaler Y count the output of the timer divider or f(XCIN). The count source is selected by the timer 12, X count source selection register (address 000E16) and the timer Y, Z count source selection register (address 000F16) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN) or f(XCIN); and f(XCIN). • Timer X and Timer Y The timer X and timer Y can each select one of four operating modes by setting the timer XY mode register (address 002316). (1) Timer mode • Mode selection This mode can be selected by setting “00” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). • Explanation of operation The timer count operation is started by setting “0” to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). When the timer reaches “0016”, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) Pulse Output Mode • Mode selection This mode can be selected by setting “01” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). • Explanation of operation The operation is the same as the timer mode’s. Moreover the pulse which is inverted each time the timer underflows is output from CNTR0/CNTR1 pin. Regardless of the timer counting or not the output of CNTR0/CNTR1 pin is initialized to the level of specified by their active edge switch bits when writing to the timer. When the CNTR0 active edge switch bit (bit 2) and the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is “0”, the output starts with “H” level. When it is “1”, the output starts with “L” level. Switching the CNTR 0 or CNTR 1 active edge switch bit will reverse the output level of the corresponding CNTR0 or CNTR1 pin. • Precautions Set the double-function port of CNTR0 /CNTR 1 pin and port P54/P55 to output in this mode. (3) Event Counter Mode • Mode selection This mode can be selected by setting “10” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). • Explanation of operation The operation is the same as the timer mode’s except that the timer counts signals input from the CNTR0 or CNTR1 pin. The valid edge for the count operation depends on the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316). When it is “0”, the rising edge is valid. When it is “1”, the falling edge is valid. • Precautions Set the double-function port of CNTR0 /CNTR 1 pin and port P54/P55 to input in this mode. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 30 of 128 3804 Group (Spec.L) (4) Pulse Width Measurement Mode • Mode selection This mode can be selected by setting “11” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). • Explanation of operation When the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is “1”, the timer counts during the term of one falling edge of CNTR0/CNTR1 pin input until the next rising edge of input (“L” term). When it is “0”, the timer counts during the term of one rising edge input until the next falling edge input (“H” term). • Precautions Set the double-function port of CNTR0 /CNTR 1 pin and port P54/P55 to input in this mode. The count operation can be stopped by setting “1” to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). The interrupt request bit is set to “1” each time the timer underflows. • Precautions when switching count source When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 31 of 128 3804 Group (Spec.L) XIN “00” “01” (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Divider Count source selection bit Clock for timer X Clock for timer Y Main clock division ratio selection bits Clock for timer 12 XCIN “10” Data bus Prescaler X latch (8) f(XCIN) Prescaler X (8) CNTR0 active edge switch bit “0” P54/CNTR0 Timer X latch (8) Pulse width Timer mode measurement Pulse output mode mode Event counter mode Timer X (8) To timer X interrupt request bit Timer X count stop bit To CNTR0 interrupt request bit “1” CNTR0 active edge switch bit Q “0” Port P54 latch Port P54 direction register “1” Toggle flip-flop T Q R Timer X latch write pulse Pulse output mode Pulse output mode Data bus Count source selection bit Clock for timer Y Prescaler Y latch (8) f(XCIN) Prescaler Y (8) CNTR1 active edge switch bit “0” P55/CNTR1 Timer Y latch (8) Pulse width Timer mode measurement Pulse output mode mode Event counter mode Timer Y (8) To timer Y interrupt request bit Timer Y count stop bit To CNTR1 interrupt request bit “1” CNTR1 active edge switch bit “1” Q Toggle flip-flop T Q “0” Port P55 latch Port P55 direction register R Timer Y latch write pulse Pulse output mode Pulse output mode Data bus Prescaler 12 latch (8) Clock for timer 12 Prescaler 12 (8) Timer 1 latch (8) Timer 2 latch (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig. 25 Block diagram of timer X, timer Y, timer 1, and timer 2 Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 32 of 128 3804 Group (Spec.L) b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bits b1 b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bits b5 b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop Fig. 26 Structure of timer XY mode register Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 33 of 128 3804 Group (Spec.L) b7 b0 Timer 12, X count source selection register (T12XCSS : address 000E16) Timer 12 count source selection bits b3 b2 b1 b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 Timer X count source selection bits b7 b6 b5 b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) b7 1010: 1011: 1100: 1101: 1110: 1111: Not used 1011: 1100: 1101: 1110: 1111: Not used 1011: 1100: 1101: 1110: 1111: Not used 1011: 1100: 1101: 1110: 1111: Not used b0 Timer Y, Z count source selection register (TYZCSS : address 000F16) Timer Y count source selection bits b3 b2 b1 b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Timer Z count source selection bits b7 b6 b5 b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Fig. 27 Structure of timer 12, X and timer Y, Z count source selection registers Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 34 of 128 3804 Group (Spec.L) • 16-bit Timer The timer Z is a 16-bit timer. When the timer reaches “000016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to the timer Z is set to “1”. When reading/writing to the timer Z, perform reading/writing to both the high-order byte and the low-order byte. When reading the timer Z, read from the high-order byte first, followed by the low-order byte. Do not perform the writing to the timer Z between read operation of the high-order byte and read operation of the low-order byte. When writing to the timer Z, write to the low-order byte first, followed by the high-order byte. Do not perform the reading to the timer Z between write operation of the low-order byte and write operation of the high-order byte. The timer Z can select the count source by the timer Z count source selection bits of timer Y, Z count source selection register (bits 7 to 4 at address 000F16). Timer Z can select one of seven operating modes by setting the timer Z mode register (address 002A16). (1) Timer mode • Mode selection This mode can be selected by setting “000” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN ); or f(XCIN) can be selected as the count source. • Interrupt When an underflow occurs, the INT0/timer Z interrupt request bit (bit 0) of the interrupt request register 1 (address 003C16) is set to “1”. • Explanation of operation During timer stop, usually write data to a latch and a timer at the same time to set the timer value. The timer count operation is started by setting “0” to the timer Z count stop bit (bit 6) of the timer Z mode register (address 002A16). When the timer reaches “000016”, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. When writing data to the timer during operation, the data is written only into the latch. Then the new latch value is reloaded into the timer at the next underflow. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 35 of 128 (2) Event counter mode • Mode selection This mode can be selected by setting “000” to the timer Z operating mode bits (bits 2 to 0) and setting “1” to the timer/event counter mode switch bit (bit 7) of the timer Z mode register (address 002A16). The valid edge for the count operation depends on the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16). When it is “0”, the rising edge is valid. When it is “1”, the falling edge is valid. • Interrupt The interrupt at an underflow is the same as the timer mode’s. • Explanation of operation The operation is the same as the timer mode’s. Set the double-function port of CNTR2 pin and port P47 to input in this mode. Figure 30 shows the timing chart of the timer/event counter mode. (3) Pulse output mode • Mode selection This mode can be selected by setting “001” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN ); or f(XCIN) can be selected as the count source. • Interrupt The interrupt at an underflow is the same as the timer mode’s. • Explanation of operation The operation is the same as the timer mode’s. Moreover the pulse which is inverted each time the timer underflows is output from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is “0”, the output starts with “H” level. When it is “1”, the output starts with “L” level. • Precautions The double-function port of CNTR 2 pin and port P4 7 is automatically set to the timer pulse output port in this mode. The output from CNTR2 pin is initialized to the level depending on CNTR2 active edge switch bit by writing to the timer. When the value of the CNTR2 active edge switch bit is changed, the output level of CNTR2 pin is inverted. Figure 31 shows the timing chart of the pulse output mode. 3804 Group (Spec.L) (4) Pulse period measurement mode • Mode selection This mode can be selected by setting “010” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). (5) Pulse width measurement mode • Mode selection This mode can be selected by setting “011” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN ); or f(XCIN) can be selected as the count source. • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN ); or f(XCIN) can be selected as the count source. • Interrupt The interrupt at an underflow is the same as the timer mode’s. When the pulse period measurement is completed, the INT4/CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to “1”. • Interrupt The interrupt at an underflow is the same as the timer mode’s. When the pulse widths measurement is completed, the INT4/CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to “1”. • Explanation of operation The cycle of the pulse which is input from the CNTR 2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is “0”, the timer counts during the term from one falling edge of CNTR2 pin input to the next falling edge. When it is “1”, the timer counts during the term from one rising edge input to the next rising edge input. When the valid edge of measurement completion/start is detected, the 1’s complement of the timer value is written to the timer latch and “FFFF16” is set to the timer. Furthermore when the timer underflows, the timer Z interrupt request occurs and “FFFF16” is set to the timer. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. • Explanation of operation The pulse width which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is “0”, the timer counts during the term from one rising edge input to the next falling edge input (“H” term). When it is “1”, the timer counts during the term from one falling edge of CNTR2 pin input to the next rising edge of input (“L” term). When the valid edge of measurement completion is detected, the 1’s complement of the timer value is written to the timer latch. When the valid edge of measurement completion/start is detected, “FFFF16” is set to the timer. When the timer Z underflows, the timer Z interrupt occurs and “FFFF16” is set to the timer Z. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. • Precautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period m e a s u r em e n t d e p e n d s o n t h e t i m e r v a l u e j u s t b ef o r e measurement start. Figure 32 shows the timing chart of the pulse period measurement mode. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 36 of 128 • Precautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width m e a s u r em e n t d ep e n d s o n t h e t i m e r v a l u e j u s t b ef o r e measurement start. Figure 33 shows the timing chart of the pulse width measurement mode. 3804 Group (Spec.L) (6) Programmable waveform generating mode • Mode selection This mode can be selected by setting “100” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN ); or f(XCIN) can be selected as the count source. • Interrupt The interrupt at an underflow is the same as the timer mode’s. • Explanation of operation The operation is the same as the timer mode’s. Moreover the timer outputs the data set in the output level latch (bit 4) of the timer Z mode register (address 002A16) from the CNTR2 pin each time the timer underflows. Changing the value of the output level latch and the timer latch after an underflow makes it possible to output an optional waveform from the CNTR2 pin. • Precautions The double-function port of CNTR 2 pin and port P4 7 is automatically set to the programmable waveform generating port in this mode. Figure 34 shows the timing chart of the programmable waveform generating mode. (7) Programmable one-shot generating mode • Mode selection This mode can be selected by setting “101” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. • Interrupt The interrupt at an underflow is the same as the timer mode’s. The trigger to generate one-shot pulse can be selected by the INT1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003A16). When it is “0”, the falling edge active is selected; when it is “1”, the rising edge active is selected. When the valid edge of the INT 1 pin is detected, the INT 1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003C16) is set to “1”. • Explanation of operation 1. “H” one-shot pulse; Bit 5 of timer Z mode register = “0” The output level of the CNTR2 pin is initialized to “L” at mode selection. When trigger generation (input signal to INT1 pin) is detected, “H” is output from the CNTR2 pin. When an underflow occurs, “L” is output. The “H” one-shot pulse width is set by the setting value to the timer Z register low-order and high-order. When trigger generating is detected during timer count stop, although “H” is output from the CNTR2 pin, “H” output state continues because an underflow does not occur. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 37 of 128 2. “L” one-shot pulse; Bit 5 of timer Z mode register = “1” The output level of the CNTR2 pin is initialized to “H” at mode selection. When trigger generation (input signal to INT1 pin) is detected, “L” is output from the CNTR2 pin. When an underflow occurs, “H” is output. The “L” one-shot pulse width is set by the setting value to the timer Z loworder and high-order. When trigger generating is detected during timer count stop, although “L” is output from the CNTR2 pin, “L” output state continues because an underflow does not occur. • Precautions Set the double-function port of INT1 pin and port P42 to input in this mode. The double-function port of CNTR 2 pin and port P4 7 is automatically set to the programmable one-shot generating port in this mode. This mode cannot be used in low-speed mode. If the value of the CNTR2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. Figure 35 shows the timing chart of the programmable one-shot generating mode. 3804 Group (Spec.L) <Notes regarding all modes> • Timer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. • Switch of interrupt active edge of CNTR2 and INT1 Each interrupt active edge depends on setting of the CNTR2 active edge switch bit and the INT1 active edge selection bit. • Switch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. • Usage of CNTR2 pin as normal I/O port P47 To use the CNTR 2 pin as normal I/O port P4 7 , set timer Z operating mode bits (b2, b1, b0) of timer Z mode register (address 002A16) to “000”. • Timer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. CNTR2 active edge Data bus switch bit Programmable one-shot “1” generating mode P42/INT1 Programmable one-shot generating circuit Programmable one-shot generating mode “0” Programmable waveform generating mode D Output level latch To INT1 interrupt request bit Q T Pulse output mode S Q T Q “001” CNTR2 active edge switch bit “0” “1” Pulse output mode “100” “101” Timer Z operating mode bits Port P47 latch Timer Z low-order latch Timer Z high-order latch Timer Z low-order Timer Z high-order To timer Z interrupt request bit Port P47 direction register Pulse period measurement mode Pulse width measurement mode Edge detection circuit “1” “0” CNTR2 active edge switch bit XIN XCIN Clock for timer z P47/SRDY2/ CNTR2 “1” “0” Timer Z count stop bit Timer/Event counter mode switch bit Count source Divider selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Fig. 28 Block diagram of timer Z Rev.1.00 Oct 27, 2008 REJ03B0266-0100 f(XCIN) Page 38 of 128 To CNTR2 interrupt request bit 3804 Group (Spec.L) b7 b0 Timer Z mode register (TZM : address 002A16) Timer Z operating mode bits b2 b1 b0 0 0 0 : Timer/Event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : Not available 1 1 1 : Not available Timer Z write control bit 0 : Writing data to both latch and timer simultaneously 1 : Writing data only to latch Output level latch 0 : “L” output 1 : “H” output CNTR2 active edge switch bit 0 : •Event counter mode: Count at rising edge •Pulse output mode: Start outputting “H” •Pulse period measurement mode: Measurement between two falling edges •Pulse width measurement mode: Measurement of “H” term •Programmable one-shot generating mode: After start outputting “L”, “H” one-shot pulse generated •Interrupt at falling edge 1 : •Event counter mode: Count at falling edge •Pulse output mode: Start outputting “L” •Pulse period measurement mode: Measurement between two rising edges •Pulse width measurement mode: Measurement of “L” term •Programmable one-shot generating mode: After start outputting “H”, “L” one-shot pulse generated •Interrupt at rising edge Timer Z count stop bit 0 : Count start 1 : Count stop Timer/Event counter mode switch bit (1) 0 : Timer mode 1 : Event counter mode Note 1: When selecting the modes except the timer/event counter mode, set “0” to this bit. Fig. 29 Structure of timer Z mode register Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 39 of 128 3804 Group (Spec.L) FFFF16 TL 000016 TR TR TR TL : Value set to timer latch TR : Timer interrupt request Fig. 30 Timing chart of timer/event counter mode FFFF16 TL 000016 TR Waveform output from CNTR2 pin CNTR2 TR TR TR CNTR2 TL : Value set to timer latch TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig. 31 Timing chart of pulse output mode Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 40 of 128 3804 Group (Spec.L) 000016 T3 T2 T1 FFFF16 TR FFFF16 + T1 TR T2 T3 FFFF16 Signal input from CNTR2 pin CNTR2 CNTR2 CNTR2 CNTR2 CNTR2 of rising edge active TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 32 Timing chart of pulse period measurement mode (Measuring term between two rising edges) 000016 T3 T2 T1 FFFF16 TR Signal input from CNTR2 pin FFFF16 + T2 T3 CNTR2 T1 CNTR2 CNTR2 CNTR2 interrupt of rising edge active; Measurement of “L” width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig. 33 Timing chart of pulse width measurement mode (Measuring “L” term) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 41 of 128 3804 Group (Spec.L) FFFF16 T3 L T2 T1 000016 Signal output from CNTR2 pin L T3 T1 TR TR CNTR2 T2 TR TR CNTR2 L : Timer initial value TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig. 34 Timing chart of programmable waveform generating mode FFFF16 L TR Signal input from INT1 pin Signal output from CNTR2 pin TR L L L CNTR2 TR CNTR2 L : One-shot pulse width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig. 35 Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 42 of 128 3804 Group (Spec.L) SERIAL INTERFACE • Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O1 control register Address 001816 Receive buffer register 1 Receive buffer full flag (RBF) Receive shift register 1 P44/RXD1 Address 001A16 Receive interrupt request (RI) Shift clock Clock control circuit P46/SCLK1 BRG count source selection bit f(XIN) Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 1/4 (f(XCIN) in low-speed mode) Address 001C16 1/4 P47/SRDY1 F/F Falling-edge detector Clock control circuit Shift clock P45/TXD1 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 1 Transmit buffer register 1 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001816 Address 001916 Data bus Fig. 36 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD1 D0 D1 D2 D3 D4 D5 D6 D7 Serial input RXD1 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register 1 (address 001816) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”. Fig. 37 Operation of clock synchronous serial I/O1 Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 43 of 128 3804 Group (Spec.L) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 Receive buffer register 1 OE Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Character length selection bit P44/RXD1 ST detector 7 bits Receive shift register 1 1/16 8 bits PE FE UART1 control register SP detector Address 001B16 Clock control circuit Serial I/O1 synchronous clock selection bit P46/SCLK1 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P45/TXD1 Transmit shift register 1 Transmit interrupt source selection bit Transmit interrupt request (TI) Character length selection bit Transmit buffer empty flag (TBE) Transmit buffer register 1 Serial I/O1 status register Address 001816 Address 001916 Data bus Fig. 38 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD1 TBE=0 TBE=1 ST D0 D1 SP TSC=1* ST D0 D1 SP Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Receive buffer read signal RBF=0 RBF=1 Serial input RXD1 ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1”. 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 39 Operation of UART serial I/O1 Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 44 of 128 3804 Group (Spec.L) [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 001816 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 Control Register (UART1CON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P45/TXD1 pin. [Baud Rate Generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 45 of 128 3804 Group (Spec.L) b7 b0 Serial I/O1 status register (SIO1STS : address 001916) b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 UART1 control register (UART1CON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 40 Structure of serial I/O1 control registers Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 46 of 128 b0 Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as normal I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 to P47 operate as normal I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O1 pins) 3804 Group (Spec.L) <Notes concerning serial I/O1> 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation • Note Clear the serial I/O1 enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation • Note Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to “0”. • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 1 , RX D 1 , S CLK1 , and S RDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD1 pin and an operation failure occurs. • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 1 , RX D 1 , S CLK1 , and S RDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD1 pin and an operation failure occurs. 1.2 Stop of receive operation • Note Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0” (serial I/O disabled). 2.2 Stop of receive operation • Note Clear the receive enable bit to “0” (receive disabled). 1.3 Stop of transmit/receive operation • Note Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) • Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to “0” (serial I/O disabled) (refer to 1.1). Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 47 of 128 2.3 Stop of transmit/receive operation • Note 1 (only transmission operation is stopped) Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to “0”. • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 1 , RX D 1 , S CLK1 , and S RDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD1 pin and an operation failure occurs. • Note 2 (only receive operation is stopped) Clear the receive enable bit to “0” (receive disabled). 3804 Group (Spec.L) 3. SRDY1 output of reception side • Note When signals are output from the SRDY1 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/O1 control register again • Note Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0”. Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time 5.Data transmission control with referring to transmit shift register completion flag • Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected • Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the SCLK1 input level. Also, write data to the transmit buffer register at “H” of the SCLK1 input level. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 48 of 128 7. Transmit interrupt request when transmit enable bit is set • Note When using the transmit interrupt, take the following sequence. 1. Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). 2. Set the transmit enable bit to “1”. 3. Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instruction has executed. 4. Set the serial I/O1 transmit interrupt enable bit to “1” (enabled). • Reason When the transmit enable bit is set to “1”, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. 3804 Group (Spec.L) • Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register (address 001F16). b7 b0 Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2, SCLK2 signal output SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P51/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains eight bits which control various serial I/O2 functions. Fig. 41 Structure of Serial I/O2 control register Internal synchronous clock selection bits 1/8 Divider 1/16 f(XIN) (f(XCIN) in low-speed mode) P53 latch 1/128 1/256 Synchronization circuit SCLK2 SRDY2 “1” SRDY2 output enable bit 1/64 Serial I/O2 synchronous clock selection bit “1” “0” P53/SRDY2 Data bus 1/32 “0” External clock P52 latch “0” P52/SCLK2 “1” Serial I/O2 port selection bit P51 latch Serial I/O counter 2 (3) “0” P51/SOUT2 “1” Serial I/O2 port selection bit Serial I/O2 register (8) P50/SIN2 Address 001F16 Fig. 42 Block diagram of serial I/O2 Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 49 of 128 Serial I/O2 interrupt request 3804 Group (Spec.L) Transfer clock (1) Serial I/O2 register write signal (2) Serial I/O2 output SOUT2 D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or (f(XCIN) in low-speed mode, can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Fig. 43 Timing of serial I/O2 Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 50 of 128 3804 Group (Spec.L) • Serial I/O3 Serial I/O3 can be used as either clock synchronous or asynchronous (UART) serial I/O3. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O3 mode can be selected by setting the serial I/O3 mode selection bit of the serial I/O3 control register (bit 6 of address 003216) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O3 control register Address 003016 Receive buffer register 3 Receive buffer full flag (RBF) Receive shift register 3 P34/RXD3 Address 003216 Receive interrupt request (RI) Shift clock Clock control circuit P36/SCLK3 BRG count source selection bit f(XIN) Serial I/O3 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 3 1/4 (f(XCIN) in low-speed mode) Address 002F16 1/4 P37/SRDY3 F/F Falling-edge detector Clock control circuit Shift clock P35/TXD3 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 3 Transmit buffer register 3 Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003016 Address 003116 Data bus Fig. 44 Block diagram of clock synchronous serial I/O3 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD3 D0 D1 D2 D3 D4 D5 D6 D7 Serial input RXD3 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY3 Write pulse to receive/transmit buffer register (address 003016) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”. Fig. 45 Operation of clock synchronous serial I/O3 Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 51 of 128 3804 Group (Spec.L) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit (b6) of the serial I/O3 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 003016 Receive buffer register 3 OE Serial I/O3 control register Address 003216 Receive buffer full flag (RBF) Receive interrupt request (RI) Character length selection bit P34/RXD3 ST detector 7 bits Receive shift register 3 1/16 8 bits PE FE UART3 control register SP detector Address 003316 Clock control circuit Serial I/O3 synchronous clock selection bit P36/SCLK3 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Frequency division ratio 1/(n+1) Baud rate generator 3 Address 002F16 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P35/TXD3 Transmit shift register 3 Transmit interrupt source selection bit Transmit interrupt request (TI) Character length selection bit Transmit buffer empty flag (TBE) Transmit buffer register 3 Serial I/O3 status register Address 003016 Address 003116 Data bus Fig. 46 Block diagram of UART serial I/O3 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD3 TBE=0 TBE=1 ST D0 D1 SP TSC=1* ST D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP * Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 Serial input RXD3 ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1”. 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig. 47 Operation of UART serial I/O3 Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 52 of 128 3804 Group (Spec.L) [Transmit Buffer Register 3/Receive Buffer Register 3 (TB3/RB3)] 003016 The transmit buffer register 3 and the receive buffer register 3 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O3 Status Register (SIO3STS)] 003116 The read-only serial I/O3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O3 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O3 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O3 enable bit SIOE (bit 7 of the serial I/O3 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O3 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O3 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O3 Control Register (SIO3CON)] 003216 The serial I/O3 control register consists of eight control bits for the serial I/O3 function. [UART3 Control Register (UART3CON)] 003316 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P35/TXD3 pin. [Baud Rate Generator 3 (BRG3)] 002F16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 53 of 128 3804 Group (Spec.L) b7 b0 Serial I/O3 status register (SIO3STS : address 003116) b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 UART3 control register (UART3CON : address 003316) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P35/TXD3 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 48 Structure of serial I/O3 control registers Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 54 of 128 b0 Serial I/O3 control register (SIO3CON : address 003216) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O3 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O3 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O3 is selected, external clock input divided by 16 when UART is selected. SRDY3 output enable bit (SRDY) 0: P37 pin operates as normal I/O pin 1: P37 pin operates as SRDY3 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O3 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O3 enable bit (SIOE) 0: Serial I/O3 disabled (pins P34 to P37 operate as normal I/O pins) 1: Serial I/O3 enabled (pins P34 to P37 operate as serial I/O3 pins) 3804 Group (Spec.L) <Notes concerning serial I/O3> 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation • Note Clear the serial I/O3 enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation • Note Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to “0”. • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 3 , RX D 3 , S CLK3 , and S RDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD3 pin and an operation failure occurs. • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 3 , RX D 3 , S CLK3 , and S RDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD3 pin and an operation failure occurs. 1.2 Stop of receive operation • Note Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O3 enable bit to “0” (serial I/O disabled). 2.2 Stop of receive operation • Note Clear the receive enable bit to “0” (receive disabled). 1.3 Stop of transmit/receive operation • Note Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) • Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O3 enable bit to “0” (serial I/O disabled) (refer to 1.1). Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 55 of 128 2.3 Stop of transmit/receive operation • Note 1 (only transmission operation is stopped) Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to “0”. • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 3 , RX D 3 , S CLK3 , and S RDY3 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD3 pin and an operation failure occurs. • Note 2 (only receive operation is stopped) Clear the receive enable bit to “0” (receive disabled). 3804 Group (Spec.L) 3. SRDY3 output of reception side • Note When signals are output from the SRDY3 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY3 output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/O3 control register again • Note Set the serial I/O3 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0”. Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/O3 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time 5.Data transmission control with referring to transmit shift register completion flag • Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected • Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the SCLK3 input level. Also, write data to the transmit buffer register at “H” of the SCLK input level. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 56 of 128 7. Transmit interrupt request when transmit enable bit is set • Note When using the transmit interrupt, take the following sequence. 1. Set the serial I/O3 transmit interrupt enable bit to “0” (disabled). 2. Set the transmit enable bit to “1”. 3. Set the serial I/O3 transmit interrupt request bit to “0” after 1 or more instruction has executed. 4. Set the serial I/O3 transmit interrupt enable bit to “1” (enabled). • Reason When the transmit enable bit is set to “1”, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. 3804 Group (Spec.L) PWM (PWM: Pulse Width Modulation) The 3804 group (Spec.L) has PWM functions with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2 or the clock input XCIN or that clock input divided by 2 in low-speed mode. • Data Setting The PWM output pin also functions as port P56. Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255): PWM period = 255 × (n+1) / f(XIN) = 31.875 × (n+1) μs (when f(XIN) = 8 MHz, count source selection bit = “0”) Output pulse “H” term = PWM period × m / 255 = 0.125 × (n+1) × m μs (when f(XIN) = 8 MHz, count source selection bit = “0”) • PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. 31.875 × m × (n+1) 255 μs PWM output T = [31.875 × (n+1)] μs m : Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz, count source selection bit = “0”) Fig. 49 Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch PWM register latch PWM prescaler PWM register Count source selection bit XIN (XCIN at lowspeed mode) “0” 1/2 Port P56 “1” Port P56 latch PWM function enable bit Fig. 50 Block diagram of PWM function Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 57 of 128 3804 Group (Spec.L) b7 b0 PWM control register (PWMCON: address 002B16) PWM function enable bit 0 : PWM disabled 1 : PWM enabled Count source selection bit 0 : f(XIN) (f(XCIN) at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Not used (return “0” when read) Fig. 51 Structure of PWM control register A B C B C T = T2 PWM output T PWM register write signal T T2 (Changes “H” term from “A” to “ B”.) PWM prescaler write signal (Changes PWM period from “T” to “T2”.) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 52 PWM output timing when PWM register or PWM prescaler is changed <Notes> The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin. The length of this “L” level output is as follows: n+1 ---------------------sec 2 × f ( X IN ) n + 1--------------sec f ( X IN ) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 (Count source selection bit = 0, where n is the value set in the prescaler) (Count source selection bit = 1, where n is the value set in the prescaler) Page 58 of 128 3804 Group (Spec.L) A/D CONVERTER (successive approximation type) [AD Conversion Register 1, 2 (AD1, AD2)] 0035 16 , 003816 The AD conversion register is a read-only register that stores the result of an A/D conversion. When reading this register during an A/D conversion, the previous conversion result is read. Bit 7 of the AD conversion register 2 is the conversion mode selection bit. When this bit is set to “0”, the A/D converter becomes the 10-bit A/D mode. When this bit is set to “1”, that becomes the 8-bit A/D mode. The conversion result of the 8-bit A/D mode is stored in the AD conversion register 1. As for 10-bit A/D mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the AD conversion registers 1, 2 after A/D conversion is completed (in Figure 54). As for 10-bit A/D mode, the 8-bit reading inclined to MSB is performed when reading the AD converter register 1 after A/D conversion is started; and when the AD converter register 1 is read after reading the AD converter register 2, the 8-bit reading inclined to LSB is performed. • Channel Selector The channel selector selects one of ports P67/AN7 to P60/AN0 or P07/AN15 to P00/AN8, and inputs the voltage to the comparator. • Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the AD conversion registers 1, 2. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(X IN ) to 500 kHz or more during an A/D conversion. b7 b0 AD/DA control register (ADCON : address 003416) Analog input pin selection bits 1 b2 b1 b0 0 0 0 0 1 1 1 1 [AD/DA Control Register (ADCON)] 003416 The AD/DA control register controls the A/D conversion process. Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals the completion of an A/D conversion. The value of this bit remains at “0” during an A/D conversion, and changes to “1” when an A/D conversion ends. Writing “0” to this bit starts the A/D conversion. =0 (n = 0) P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 or or or or or or or or P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 Analog input pin selection bit 2 0: AN0 to AN7 side 1: AN8 to AN15 side Not used (returns “0” when read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled • 10-bit A/D mode (10-bit reading) V REF Vref = ------------- × n (n = 0 − 1023) 1024 • 8-bit A/D mode V REF Vref = ------------- × (n − 0.5) (n = 1 − 255) 256 0: 1: 0: 1: 0: 1: 0: 1: AD conversion completion bit 0: Conversion in progress 1: Conversion completed • Comparison Voltage Generator The comparison voltage generator divides the voltage between AV SS and V REF into 1024, and that outputs the comparison voltage in the 10-bit A/D mode (256 division in 8-bit A/D mode). The A/D converter successively compares the comparison voltage Vref in each mode, dividing the V REF voltage (see below), with the input voltage. • 10-bit A/D mode (8-bit reading) V REF Vref = ------------- × n (n = 0 − 255) 256 0 0 1 1 0 0 1 1 DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled Fig. 53 Structure of AD/DA control register 10-bit reading (Read address 003816 before 003516) AD conversion register 2 (AD2: address 003816) b7 0 b0 b9 b8 AD conversion register 1 (AD1: address 003516) b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 Note : Bits 2 to 6 of address 003816 become “0” at reading. 8-bit reading (Read only address 003516) AD conversion register 1 (AD1: address 003516) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 Fig. 54 Structure of 10-bit A/D mode reading Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 59 of 128 3804 Group (Spec.L) Data bus AD/DA control register b7 (Address 003416) b0 4 A/D converter interrupt request A/D control circuit Comparator Channel selector P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 10 Resistor ladder VREF AVSS Fig. 55 Block diagram of A/D converter Rev.1.00 Oct 27, 2008 REJ03B0266-0100 AD conversion register 2 AD conversion register 1 Page 60 of 128 (Address 003816) (Address 003516) 3804 Group (Spec.L) D/A CONVERTER The 3804 group (Spec.L) has two internal D/A converters (DA1 and DA2) with 8-bit resolution. The D/A conversion is performed by setting the value in each DA conversion register. The result of D/A conversion is output from the DA1 or DA2 pin by setting the DA output enable bit to “1”. When using the D/A converter, the corresponding port direction register bit (P30 /DA 1 or P3 1 /DA 2 ) must be set to “0” (input status). The output analog voltage V is determined by the value n (decimal notation) in the DA conversion register as follows: DA1 conversion register (8) DA1 output enable bit Data bus R-2R resistor ladder V = VREF × n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the DA conversion registers are cleared to “0016”, and the DA output enable bits are cleared to “0”, and the P30/DA1 and P31/DA2 pins become high impedance. The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load. P30/DA1 DA2 conversion register (8) DA2 output enable bit R-2R resistor ladder P31/DA2 Fig. 56 Block diagram of D/A converter “0” DA1 output enable bit R R R R R R R 2R P30/DA1 “1” 2R 2R 2R MSB DA1 conversion register “0” 2R 2R 2R 2R LSB “1” AVSS VREF Fig. 57 Equivalent connection circuit of D/A converter (DA1) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 2R Page 61 of 128 3804 Group (Spec.L) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. • Watchdog Timer Initial Value Watchdog timer L is set to “FF16” and watchdog timer H is set to “FF16” by writing to the watchdog timer control register (address 001E16) or at a reset. Any write instruction that causes a write signal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog timer control register. Regardless of the value written to bits 0 to 5, the abovementioned value will be set to each timer. Bit 6 can be written only once after releasing reset. After rewriting it is disable to write any data to this bit. • Watchdog Timer Operations The watchdog timer stops at reset and starts to count down by writing to the watchdog timer control register (address 001E16). An internal reset occurs at an underflow of the watchdog timer H. The reset is released after waiting for a reset release time and the program is processed from the reset vector address. Accordingly, programming is usually performed so that writing to the watchdog timer control register may be started before an underflow. If writing to the watchdog timer control register is not performed once, the watchdog timer does not function. • Bit 6 of Watchdog Timer Control Register • When bit 6 of the watchdog timer control register is “0”, the MCU enters the stop mode by execution of STP instruction. Just after releasing the stop mode, the watchdog timer restarts counting (Note.) . When executing the WIT instruction, the watchdog timer does not stop. • When bit 6 is “1”, execution of STP instruction causes an internal reset. When this bit is set to “1” once, it cannot be rewritten to “0” by program. Bit 6 is “0” at reset. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is “0”: when XCIN = 32.768 kHz; 32 s when XIN = 16 MHz; 65.536 ms Bit 7 of the watchdog timer control register is “1”: when XCIN = 32.768 kHz; 125 ms when XIN = 16 MHz; 256 μs Note. The watchdog timer continues to count even during the wait time set by timer 1 and timer 2 to release the stop state and in the wait mode. Accordingly, write to the watchdog timer control register to not underflow the watchdog timer in this time. “FF16” is set when watchdog timer control register is written to. XCIN “10” Main clock division ratio selection bits(1) Data bus Watchdog timer L (8) 1/16 XIN “0” “1” “00” “01” “FF16” is set when watchdog timer control register is written to. Watchdog timer H (8) Watchdog timer H count source selection bit STP instruction function selection bit STP instruction Reset circuit RESET Internal reset Note 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig. 58 Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 001E16) Watchdog timer H (for read-out of high-order 6 bit) STP instruction function selection bit 0: Entering stop mode by execution of STP instruction 1: Internal reset by execution of STP instruction Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig. 59 Structure of Watchdog timer control register Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 62 of 128 3804 Group (Spec.L) MULTI-MASTER I2C-BUS INTERFACE The 3804 group (Spec. L) has the multi-master I 2 C-BUS interface. The multi-master I 2 C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multimaster serial communications. Figure 60 shows a block diagram of the multi-master I2C-BUS interface and Table 9 lists the multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C slave address registers 0 to 2, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register, the I2C START/STOP condition control register, the I2C special mode control register, the I2C special mode status register, and other control circuits. When using the multi-master I2C-BUS interface, set 1 MHz or more to the internal clock φ. Multi-master I2C-BUS interface functions Table 9 Item Function Format In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode Communication mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception SCL clock frequency 16.1 kHz to 400 kHz (at φ = 4 MHz) System clock φ = f(XIN)/2 (high-speed mode) φ = f(XIN)/8 (middle-speed mode) NOTE: 1. We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bit 6 of the I2C control register at address 002E16) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, and SDA2). Interrupt generating circuit Interrupt request signal (SCL, SDA, IRQ) b7 I2C slave address registers 0 to 2 b0 Interrupt generating circuit SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW S0D0-2 Interrupt request signal (I2CIRQ) Address comparator Noise elimination circuit Serial data (SDA) Data control circuit b0 b7 I2C data shift register b7 S0 b0 AL AAS AD0 LRB MST TRX BB PIN SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 AL circuit I2C status register S1 S2D I2C START/STOP condition control register Internal data bus BB circuit Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE b7 b0 SPCF PIN2 AAS2 AAS1 AAS0 S2 I2C clock control register Clock division System clock (φ) S3 I 2C special mode status register b7 b7 TISS b0 TSEL 10BIT SAD ALS SPCFL PIN2 HD b0 PIN2 IN HSLAD ACKI CON ES0 BC2 BC1 BC0 S3D I 2C special mode control register S1D I2C control register Bit counter Fig. 60 Block diagram of multi-master I2C-BUS interface *: Purchase of Renesas Technology Corporation’s I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 63 of 128 3804 Group (Spec.L) [I2C Data Shift Register (S0)] 001116 The I2C data shift register (S0: address 001116) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL, and each time one-bit data is output, the data of this register are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL, and each time one-bit data is input, the data of this register are shifted by one bit to the left. The minimum 2 cycles of the internal clock φ are required from the rising of the SCL until input to this register. The I2C data shift register is in a write enable status only when the I2C-BUS interface enable bit (ES0 bit) of the I2C control register (S1D: address 001416) is “1”. The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (S1: address 001316) are “1”, the SCL is output by a write instruction to the I 2 C data shift register. Reading data from the I2 C data shift register is always enabled regardless of the ES0 bit value. [I2C Slave Address Registers 0 to 2 (S0D0 to S0D2)] 0FF716 to 0FF916 The I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF716 to 0FF916) consists of a 7-bit slave address and a read/ write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition is detected. • Bit 0: Read/write bit (RWB) This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, set RWB to “0” because the first address data to be received is compared with the contents (SAD6 to SAD0 + RWB) of the I2C slave address registers 0 to 2. When 2-byte address data match slave address, a 7-bit slave address which is received after restart condition has detected and R/W data can be matched by setting “1” to RWB with software. The RWB is cleared to “0” automatically when the stop condition is detected. • Bits 1 to 7: Slave address (SAD0-SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with these bits’ contents. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 64 of 128 b7 b0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB I2C slave address register 0 (S0D0: address 0FF716) I2C slave address register 1 (S0D1: address 0FF816) I2C slave address register 2 (S0D2: address 0FF916) Read/write bit Slave address Fig. 61 Structure of I2C slave address registers 0 to 2 3804 Group (Spec.L) [I2C Clock Control Register (S2)] 001516 The I2C clock control register (S2: address 001516) is used to set ACK control, SCL mode and SCL frequency. b7 ACK b0 ACK BIT FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE • Bits 0 to 4: SCL frequency control bits (CCR0-CCR4) These bits control the SCL frequency. Refer to Table 10. SCL frequency control bits Refer to Table 10. • Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0”, the standard clock mode is selected. When the bit is set to “1”, the high-speed clock mode is selected. When connecting the bus of the high-speed mode I 2 C bus standard (maximum 400 kbits/s), use 8 MHz or more oscillation frequency f(XIN) in the high-speed mode (2 division clock). • Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock* is generated. When this bit is set to “0”, the ACK return mode is selected and SDA goes to “L” at the occurrence of an ACK clock. When the bit is set to “1”, the ACK non-return mode is selected. The SDA is held in the “H” status at the occurrence of an ACK clock. However, when the slave address agree with the address data in the reception of address data at ACK BIT = “0”, the SDA is automatically made “L” (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is automatically made “H” (ACK is not returned). * ACK clock: Clock for acknowledgment • Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which is an acknowledgment response of data transfer. When this bit is set to “0”, the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to “1”, the ACK clock mode is selected and the master generates an ACK clock each completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA “H”) and receives the ACK bit generated by the data receiving device. Note. Do not write data into the I2C clock control register during transfer. If data is written during transfer, the I2C clock generator is reset, so that data cannot be transferred normally. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 65 of 128 I2C clock control register (S2: address 001516) SCL mode specification bit 0: Standard clock mode 1: High-speed clock mode ACK bit 0: ACK is returned 1: ACK is not returned ACK clock bit 0: No ACK clock 1: ACK clock Fig. 62 Structure of I2C clock control register Table 10 Set values of I2C clock control register and SCL frequency Setting value of CCR4-CCR0 SCL frequency (at φ = 4 MKz, unit: kHz) (Note 1) Standard clock High-speed CCR4 CCR3 CCR2 CCR1 CCR0 mode clock mode 0 0 0 0 0 Setting disabled Setting disabled 0 0 0 0 1 Setting disabled Setting disabled 0 0 0 1 0 Setting disabled Setting disabled 0 0 0 1 1 0 0 1 0 0 0 0 : : 1 1 1 0 0 : : 1 1 1 1 1 : : 1 1 1 0 1 : : 0 1 1 1 0 : : 1 0 1 − (Note 2) − (Note 2) 333 250 100 400 (Note 3) 83.3 166 500/CCR value 1000/CCR value (Note 3) (Note 3) 17.2 34.5 16.6 33.3 16.1 32.3 NOTES: 1. Duty of SCL output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates from -4 to +2 machine cycles in the standard clock mode, and fluctuates from -2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H” duration reduction. These are values when SCL synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2. Each value of SCL frequency exceeds the limit at φ = 4 MHz or more. When using these setting value, use φ of 4 MHz or less. 3. The data formula of SCL frequency is described below: φ/(8 × CCR value) Standard clock mode φ/(4 × CCR value) High-speed clock mode (CCR value ≠ 5) φ/(2 × CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of φ frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0. 3804 Group (Spec.L) [I2C Control Register (S1D)] 001416 The I2C control register (S1D: address 001416) controls data communication format. b7 TISS • Bits 0 to 2: Bit counter (BC0-BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I2C interrupt request signal occurs immediately after the number of count specified with these bits (ACK clock is added to the number of count when ACK clock is selected by ACK clock bit (bit 7 of S2, address 0015 1 6 ) have been transferred, and BC0 to BC2 are returned to “0002”. Also when a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits. • Bit 3: I2C interface enable bit (ES0) This bit enables to use the multi-master I2 C-BUS interface. When this bit is set to “0”, the use disable status is provided, so that the SDA and the SCL become high-impedance. When the bit is set to “1”, use of the interface is enabled. When ES0 = “0”, the following is performed. • PIN = “1”, BB = “0” and AL = “0” are set (which are bits of the I2C status register, S1, at address 001316 ). • Writing data to the I2C data shift register (S0: address 001116) is disabled. • Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0”, the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “I2C Status Register”, bit 1) is received, transfer processing can be performed. When this bit is set to “1”, the free data format is selected, so that slave addresses are not recognized. • Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0”, the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C slave address registers 0 to 2 are compared with address data. When this bit is set to “1”, the 10-bit addressing format is selected, and all the bits of the I2C slave address registers 0 to 2 are compared with address data. • Bit 7: I2C-BUS interface pin input level selection bit (TISS) This bit selects the input level of the SCL and SDA pins of the multi-master I2C-BUS interface. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 66 of 128 b0 10BIT ALS ES0 BC2 BC1 BC0 SAD I2C control register (S1D: address 001416) Bit counter (Number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 I2C-BUS interface enable bit 0: Disabled 1: Enabled Data format selection bit 0: Addressing format 1: Free data format Addressing format selection bit 0: 7-bit addressing format 1: 10-bit addressing format Not used (return “0” when read) I2C-BUS interface pin input level selection bit 0: SMBUS input 1: CMOS input Fig. 63 Structure of I2C clock control register 3804 Group (Spec.L) [I2C Status Register (S1)] 001316 The I2C status register (S1: address 001316) controls the I2CBUS interface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. Set “00002” to the low-order 4 bits, because these bits become the reserved bits at writing. • Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0”. If ACK is not returned, this bit is set to “1”. Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (S0: address 001116). • Bit 1: General call detecting flag (AD0) When the ALS bit is “0”, this bit is set to “1” when a general call* whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition, or reset. * General call: The master transmits the general call address “0016” to all slaves. • Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data when the ALS bit is “0”. (1) In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions: • The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I2C slave address register. • A general call is received. (2) In the slave receive mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition: • When the address data is compared with the I2C slave address register (8 bits consisting of slave address and RWB bit), the first bytes agree. (3) This bit is set to”0” by executing a write instruction to the I2C data shift register (S0: address 001116) when ES0 is set to “1” or reset. • Bit 3: Arbitration lost* detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1”. At the same time, the TRX bit is set to “0”, so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0”. The arbitration lost can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to detect the agreement of its own slave address and address data transmitted by another master device. The AL bit is set to “0” in one of the following conditions: • Executing a write instruction to the I2C data shift register (S0: address 001116) • When the ES0 bit is “0” • At reset * Arbitration lost: The status in which communication as a master is disabled. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 67 of 128 • Bit 4: SCL pin low hold bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the PIN bit changes from “1” to “0”. At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to “0” in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is “0”, the SCL is kept in the “0” state and clock generation is disabled. Figure 65 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in one of the following conditions: • Executing a write instruction to the I2C data shift register (S0: address 0011 16 ). (This is the only condition which the prohibition of the internal clock is released and data can be communicated except for the start condition detection.) • When the ES0 bit is “0” • At reset • When writing “1” to the PIN bit by software The PIN bit is set to “0” in one of the following conditions: • Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) • Immediately after completion of 1-byte data reception • In the slave reception mode, with ALS = “0” and immediately after completion of slave address agreement or general call address reception • In the slave reception mode, with ALS = “1” and immediately after completion of address data reception • Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0”, this bus system is not busy and a START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of master/slave. This flag is set to “1” by detecting the START condition, and is set to “0” by detecting the STOP condition. The condition of these detecting is set by the START/STOP condition setting bits (SSC4-SSC0) of the I2C START/STOP condition control register (S2D: address 001616). When the ES0 bit of the I2C control register (bit 3 of S1D, address 001416) is “0” or reset, the BB flag is set to “0”. For the writing function to the BB flag, refer to the sections “START Condition Generating Method” and “STOP Condition Generating Method” described later. 3804 Group (Spec.L) • Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0”, the reception mode is selected and the data of a transmitting device is received. When the bit is “1”, the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. This bit is set/reset by software and hardware. About set/reset by hardware is described below. This bit is set to “1” by hardware when all the following conditions are satisfied: • When ALS is “0” • In the slave reception mode or the slave transmission mode • When the R/W bit reception is “1” • This bit is set to “0” in one of the following conditions: • When arbitration lost is detected. • When a STOP condition is detected. • When writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note). • With MST = “0” and when a START condition is detected. • With MST = “0” and when ACK non-return is detected. • At reset • Bit 7: Communication mode specification bit (master/ slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0”, the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1”, the master is specified and a START condition and a STOP condition are generated. Additionally, the clocks required for data communication are generated on the SCL. This bit is set to “0” in one of the following conditions. • Immediately after completion of the byte which has lost arbitration when arbitration lost is detected • When a STOP condition is detected. • Writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note). • At reset b7 b0 MST TRX BB PIN AL AAS AD0 LRB I2C status register (S1: address 001316) Last receive bit (Note) 0: Last bit = “0” 1: Last bit = “1” General call detecting flag (Note) 0: No general call detected 1: General call detected Slave address comparison flag (Note) 0: Address disagreement 1: Address agreement Arbitration lost detecting flag (Note) 0: Not detected 1: Detected SCL pin low hold bit 0: SCL pin low hold 1: SCL pin low release Bus busy flag 0: Bus free 1: Bus busy Communication mode specification bits 0 0 : Slave receive mode 0 1 : Slave transmit mode 1 0 : Master receive mode 1 1 : Master transmit mode Note: These bits and flags can be read out, but cannot be written. Write “0” to these bits at writing. Fig. 64 Structure of I2C status register SCL PIN Note. START condition duplication preventing function The MST, TRX, and BB bits is set to “1” at the same time after confirming that the BB flag is “0” in the procedure of a START condition occurrence. However, when a START condition by another master device occurs and the BB flag is set to “1” immediately after the contents of the BB flag is confirmed, the START condition duplication preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the rising of the BB flag to reception completion of slave address. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 68 of 128 I2CIRQ Fig. 65 Interrupt request signal generating timing 3804 Group (Spec.L) START Condition Generating Method STOP Condition Generating Method I2C When writing “1” to the MST, TRX, and BB bits of the status register (S1: address 001316) at the same time after writing the slave address to the I 2 C data shift register (S0: address 001116 ) with the condition in which the ES0 bit of the I 2 C control register (S1D: address 001416) is “1” and the BB flag is “0”, a START condition occurs. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 66, the START condition generating timing diagram, and Table 11, the START condition generating timing table. When the ES0 bit of the I2 C control register (S1D: address 001416) is “1”, write “1” to the MST and TRX bits, and write “0” to the BB bit of the I2 C status register (S1: address 0013 16 ) simultaneously. Then a STOP condition occurs. The STOP condition generating timing is different in the standard clock mode and the high-speed clock mode. Refer to Figure 67, the STOP condition generating timing diagram, and Table 12, the STOP condition generating timing table. I2C status register write signal SCL I2C status register write signal SCL Setup time Hold time SDA Setup time Hold time Fig. 67 STOP condition generating timing diagram SDA Table 12 STOP condition generating timing table Fig. 66 START condition generating timing diagram Table 11 START condition generating timing table Item Setup time Hold time Standard clock mode 5.0 μs (20 cycles) 5.0 μs (20 cycles) High-speed clock mode 2.5 μs (10 cycles) 2.5 μs (10 cycles) NOTE: 1. Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 69 of 128 Item Setup time Hold time NOTE: Standard clock mode 5.0 μs (20 cycles) 4.5 μs (18 cycles) High-speed clock mode 3.0 μs (12 cycles) 2.5 μs (10 cycles) 1. Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. 3804 Group (Spec.L) START/STOP Condition Detecting Operation The START/STOP condition detection operations are shown in Figures 68, 69, and Table 13. The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy three conditions: SCL release time, setup time, and hold time (see Table 13). The BB flag is set to “1” by detecting the START condition and is reset to “0” by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table 13, the BB flag set/reset time. SCL release time SCL SDA Setup time Hold time BB flag reset time BB flag Fig. 68 START/STOP condition detecting timing diagram Note. When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “I2CIRQ” occurs to the CPU. SCL release time Table 13 START condition/STOP condition detecting conditions Standard clock mode High-speed clock mode SCL release time SSC value + 1 cycle (6.25 μs) 4 cycle (1.0 μs) Setup time SSC value + 1 cycle < 4 μs (3.125 μs) 2 2 cycle (0.5 μs) Hold time SSC value + 1 cycle < 4 μs (3.125 μs) 2 2 cycle (0.5 μs) BB flag set/ reset time SSC value −1 + 2 cycles (3.375 μs) 2 3.5 cycle (0.875 μs) Setup time Hold time SDA BB flag reset time BB flag NOTE: 1. Unit : Cycle number of system clock φ SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC value. The value in parentheses is an example when the I2C START/STOP condition control register is set to “1816” at φ = 4 MHz. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 SCL Page 70 of 128 Fig. 69 STOP condition detecting timing diagram 3804 Group (Spec.L) [I2C START/STOP Condition Control Register (S2D)] 001616 The I2C START/STOP condition control register (S2D: address 001616) controls START/STOP condition detection. • Bits 0 to 4: START/STOP condition set bits (SSC4-SSC0) SCL release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(XIN ) because these time are measured by the internal system clock. Accordingly, set the proper value to the START/STOP condition set bits (SSC4 to SSC0) in considered of the system clock frequency. Refer to Table 13. Do not set “00000 2 ” or an odd number to the START/STOP condition set bits (SSC4 to SSC0). Refer to Table 14, the recommended set value to START/STOP condition set bits (SSC4-SSC0) for each oscillation frequency. • Bit 6: SCL/SDA interrupt pin selection bit (SIS) This bit selects the pin of which interrupt becomes valid between the SCL pin and the SDA pin. Note. When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2CBUS interface enable bit ES0, the SCL/SDA interrupt request bit may be set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt. • Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP) An interrupt can occur when detecting the falling or rising edge of the SCL or SDA pin. This bit selects the polarity of the SCL or SDA pin interrupt pin. b7 b0 SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0 I2C START/STOP condition control register (S2D: address 001616) START/STOP condition set bits SCL/SDA interrupt pin polarity selection bit 0: Falling edge active 1: Rising edge active SCL/SDA interrupt pin selection bit 0: SDA valid 1: SCL valid Not used (Fix this bit to “0”.) Fig. 70 Structure of I2C START/STOP condition control register Table 14 Recommended set value to START/STOP condition set bits (SSC4-SSC0) for each oscillation frequency Oscillation frequency f(XIN)(MHz) Main clock divide ratio Internal clock φ (MHz) 8 2 4 8 8 1 4 2 2 2 2 1 START/STOP condition control register SCL release time (μs) XXX11010 XXX11000 Setup time (μs) Hold time (μs) 6.75 μs (27 cycles) 3.5 μs (14 cycles) 3.25 μs (13 cycles) 6.25 μs (25 cycles) 3.25 μs (13 cycles) 3.0 μs (12 cycles) XXX00100 5.0 μs (5 cycles) 3.0 μs (3 cycles) 2.0 μs (2 cycles) XXX01100 6.5 μs (13 cycles) 3.5 μs (7 cycles) 3.0 μs (6 cycles) XXX01010 5.5 μs (11 cycles) 3.0 μs (6 cycles) 2.5 μs (5 cycles) XXX00100 5.0 μs (5 cycles) 3.0 μs (3 cycles) 2.0 μs (2 cycles) NOTE: 1. Do not set an odd number to the START/STOP condition set bits (SSC4 to SSC0) and “000002”. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 71 of 128 3804 Group (Spec.L) [I2C Special Mode Status Register (S3)] 001216 The I 2 C special mode status register (S3: address 0012 16 ) consists of the flags indicating I 2C operating state in the I2C special mode, which is set by the I2 C special mode control register (S3D: address 001716). The stop condition flag is valid in all operating modes. • Bit 0: Slave address 0 comparison flag (AAS0) Bit 1: Slave address 1 comparison flag (AAS1) Bit 2: Slave address 2 comparison flag (AAS2) These flags indicate a comparison result of address data. These flags are valid only when the slave address control bit (MSLAD) is “1”. In the 7-bit addressing format of the slave reception mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the I2C slave address registers 0 to 2 are set to “1” when an address data immediately after an occurrence of a START condition agrees with the high-order 7-bit slave address stored in the I2C slave address registers 0 to 2 (addresses 0FF716 to 0FF916). In the 10-bit addressing format of the slave mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the I2C slave address registers are set to “1” when an address data is compared with the 8 bits consisting of the slave address stored in the I2C slave address registers 0 to 2 and the RWB bit, and the first byte agrees. These flags are initialized to “0” at reset, when the slave address control bit (MSLAD) is “0”, or when writing data to the I2C data shift register (S0: address 001116). b7 SPCF • Bit 5: SCL pin low hold 2 flag (PIN2) When the ACK interrupt control bit (ACKICON) and the ACK clock bit (ACK) are “1”, this flag is set to “0” in synchronization with the falling of the data’s last SCL clock, just before the ACK clock. The SCL pin is simultaneously held low, and the I2 C interrupt request occurs. This flag is initialized to “1” at reset, when the ACK interrupt control bit (ACKICON) is “0”, or when writing “1” to the SCL pin low hold 2 flag set bit (PIN2IN). The SCL pin is held low when either the SCL pin low hold bit (PIN) or the SCL pin low hold 2 flag (PIN2) becomes “0”. The low hold state of the SCL pin is released when both the SCL pin low hold bit (PIN) and the SCL pin low hold 2 flag (PIN2) are “1”. • Bit 7: Stop condition flag (SPCF) This flag is set to “1” when a STOP condition occurs. This flag is initialized to “0” at reset, when the I 2 C-BUS interface enable bit (ES0) is “0”, or when writing “1” to the STOP condition flag clear bit (SPFCL). b0 PIN2 AAS2 AAS1 AAS0 I2C special mode status register (S3: address 001216) Slave address 0 comparison flag 0: Address disagreement 1: Address agreement Slave address 1 comparison flag 0: Address disagreement 1: Address agreement Slave address 2 comparison flag 0: Address disagreement 1: Address agreement Not used (return “0” when read) Not used (undefined when read) SCL pin low hold 2 flag 0: SCL pin low hold 1: SCL pin low release (Note) Not used (return “0” when read) STOP condition flag 0: No detection 1: Detection Note: In order that the low hold state of the SCL pin may release, it is necessary that the SCL pin low hold 2 flag and the SCL pin low hold bit (PIN) are “1” simultaneously. Fig. 71 Structure of I2C special mode status register Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 72 of 128 3804 Group (Spec.L) [I2C Special Mode Control Register (S3D)] 001716 The I2C special mode control register (S3D: address 001716 ) controls special functions such as occurrence timing of reception interrupt request and extending slave address comparison to 3 bytes. • Bit 1: ACK interrupt control bit (ACKICON) This bit controls the timing of I2C interrupt request occurrence at completion of data receiving due to master reception or slave reception. When this bit is “0”, the SCL pin low hold bit (PIN) is set to “0” in synchronization with the falling of the last SCL clock, including the ACK clock. The SCL pin is simultaneously held low, and the I2C interrupt request occurs. When this bit is “1” and the ACK clock bit (ACK) is “1”, the SCL pin low hold 2 flag (PIN2) is set to “0” in synchronization with the falling of the data’s last SCL clock, just before the ACK clock. The SCL pin is simultaneously held low, and the I2 C interrupt request occurs again. The ACK bit can be changed after the contents of data are confirmed by using this function. • Bit 2: I2C slave address control bit (MSLAD) This bit controls a slave address. When this bit is “0”, only the I2C slave address register 0 (address 0FF716) becomes valid as a slave address and a read/write bit. When this bit is “1”, all of the I2C slave address registers 0 to 2 (addresses 0FF716 to 0FF916) become valid as a slave address and a read/write bit. In this case, when an address data agrees with any one of the I2C slave address registers 0 to 2, the slave address comparison flag (AAS) is set to “1” and the I2C slave address comparison flag corresponding to the agreed I2C slave address registers 0 to 2 is also set to “1”. • Bit 5: SCL pin low hold 2 flag set bit (PIN2IN) Writing “1” to this bit initializes the SCL pin low hold 2 flag (PIN2) to “1”. When writing “0”, nothing is generated. • Bit 6: SCL pin low hold set bit (PIN2HD) When the SCL pin low hold bit (PIN) becomes “0”, the SCL pin is held low. However, the SCL pin low hold bit (PIN) cannot be set to “0” by software. The SCL pin low hold set bit (PIN2HD) is used to, hold the SCL pin in the low state by software. When writing “1” to this bit, the SCL pin low hold 2 flag (PIN2) becomes “0”, and the SCL pin is held low. When writing “0”, nothing occurs. • Bit 7: STOP condition flag clear bit (SPFCL) Writing “1” to this bit initializes the STOP condition flag (SPCF) to “0”. When writing “0”, nothing is generated. b7 b0 SPFCL PIN2HD PIN2IN ACKI MSLAD CON I2C special mode control register (S3D: address 001716) Not used (Fix this bit to “0”.) ACK interrupt control bit 0: At communication completion 1: At falling of ACK clock and communication completion Slave address control bit 0: One-byte slave address compare mode 1: Three-byte slave address compare mode Not used (return “0” when read) Not used (Fix this bit to “0”.) SCL pin low hold 2 flag set bit (Notes 1, 2) Writing “1” to this bit initializes the SCL pin low hold 2 flag to “1”. SCL pin low hold set bit (Notes 1, 2) When writing “1” to this bit, the SCL pin low hold 2 flag becomes “0” and the SCL pin is held low. STOP condition flag clear bit (Note 2) Writing “1” to this bit initializes the STOP condition flag to “0”. Notes 1: Do not write “1” to these bits simultaneously. 2: return “0” when read Fig. 72 Structure of I2C special mode control register Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 73 of 128 3804 Group (Spec.L) Address Data Communication There are two address data communication formats, namely, 7bit addressing format and 10-bit addressing format. The respective address communication formats are described below. • 7-bit addressing format To adapt the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (S1D: address 001416) to “0”. The first 7bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C slave address register. At the time of this comparison, address comparison of the RWB bit of the I2C slave address register is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 73, (1) and (2). • 10-bit addressing format To adapt the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (S1D: address 001416) to “1”. An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I2C slave address register. At the time of this comparison, an address comparison between the RWB bit of the I 2 C slave address register and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RWB bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I2C status register (S1: address 001316) is set to “1”. After the second-byte address data is stored into the I2C data shift register (S0: address 0011 1 6 ), perform an address comparison between the second-byte data and the slave address by software. When the address data of the 2 bytes agree with the slave address, set the RWB bit of the I2C slave address register to “1” by software. This processing can make the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of the I2C slave address register. For the data transmission format when the 10bit addressing format is selected, refer to Figure 73, (3) and (4) . (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W 7 bits A “0” Data A 1 to 8 bits Data A/A P A P 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter S Slave address R/W 7 bits “1” A Data A 1 to 8 bits Data 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address Slave address Data Data R/W A A A A/A S 2nd bytes 1st 7 bits “0” 7 bits 8 bits 1 to 8 bits 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address Slave address Slave address Slave address S R/W A A Sr 1st 7 bits R/W 1st 7 bits 2nd bytes 7 bits 8 bits 7 bits “1” “0” S: START condition A: ACK bit Sr: Restart condition P: STOP condition R/W: Read/Write bit Fig. 73 Address data communication format Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 74 of 128 P A : Master to slave : Slave to master Data 1 to 8 bits A Data 1 to 8 bits A P 3804 Group (Spec.L) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. (1) Set a slave address in the high-order 7 bits of the I2C slave address register and “0” into the RWB bit. (2) Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (S2: address 001516). (3) Set “0016” in the I2C status register (S1: address 001316) so that transmission/reception mode can become initializing condition. (4) Set a communication enable status by setting “0816” in the I2C control register (S1D: address 001416). (5) Confirm the bus free condition by the BB flag of the I2C status register (S1: address 001316). (6) Set the address data of the destination of transmission in the high-order 7 bits of the I2C data shift register (S0: address 001116) and set “0” in the least significant bit. (7) Set “F016” in the I2C status register (S1: address 001316) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occur. (8) Set transmit data in the I2C data shift register (S0: address 0 011 1 6 ) . A t t hi s ti me, a n SCL and an ACK clock automatically occur. (9) When transmitting control data of more than 1 byte, repeat step (8). (10) Set “D016” in the I2C status register (S1: address 001316) to generate a STOP condition if ACK is not returned from slave reception side or transmission ends. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 75 of 128 Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. (1) Set a slave address in the high-order 7 bits of the I2C slave address register and “0” in the RWB bit. (2) Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (S2: address 001516). (3) Set “0016” in the I2C status register (S1: address 001316) so that transmission/reception mode can become initializing condition. (4) Set a communication enable status by setting “0816” in the I2C control register (S1D: address 001416). (5) When a START condition is received, an address comparison is performed. (6) • When all transmitted addresses are “0” (general call): AD0 of the I2C status register (S1: address 001316) is set to “1” and an interrupt request signal occurs. • When the transmitted addresses agree with the address set in (1): AAS of the I2C status register (S1: address 001316) is set to “1” and an interrupt request signal occurs. • In the cases other than the above AD0 and AAS of the I2C status register (S1: address 001316) are set to “0” and no interrupt request signal occurs. (7) Set dummy data in the I2C data shift register (S0: address 001116). (8) When receiving control data of more than 1 byte, repeat step (7). (9) When a STOP condition is detected, the communication ends. 3804 Group (Spec.L) Precautions when using multi-master I2C BUS interface (1) Read-modify-write instruction The precautions when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below. • I2C data shift register (S0: address 001116) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. • I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF716 to0FF916) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not intended. It is because H/W changes the read/write bit (RWB) at the above timing. • I2C status register (S1: address 001316) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by H/W. • I2C control register (S1D: address 001416) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because H/W changes the bit counter (BC0-BC2) at the above timing. • I2C clock control register (S2: address 001516) The read-modify-write instruction can be executed for this register. • I2C START/STOP condition control register (S2D: address 001616) The read-modify-write instruction can be executed for this register. (2) START condition generating procedure using multi-master 1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 5. : LDA − (Taking out of slave address value) SEI (Interrupt disabled) BBS 5, S1, BUSBUSY (BB flag confirming and branch process) BUSFREE: STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of START condition generating) CLI (Interrupt enabled) : BUSBUSY: CLI (Interrupt enabled) : 2. Use “Branch on Bit Set” of “BBS 5, S1, -” for the BB flag confirming and branch process. 3. Use “STA $12, STX $12” or “STY $12” of the zero page addressing instruction for writing the slave address value to the I2C data shift register. 4. Execute the branch instruction of above 2 and the store instruction of above 3 continuously shown the above procedure example. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 76 of 128 5. Disable interrupts during the following three process steps: • BB flag confirming • Writing of slave address value • Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately. (3) RESTART condition generating procedure 1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 4.) Execute the following procedure when the PIN bit is “0” : LDM #$00, S1 (Select slave receive mode) LDA − (Taking out of slave address value) SEI (Interrupt disabled) STA S0 (Writing of slave address value) LDM #$F0, S1 (Trigger of RESTART condition generating) CLI (Interrupt enabled) : 2. Select the slave receive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. 3. The SCL pin is released by writing the slave address value to the I2C data shift register. 4. Disable interrupts during the following two process steps: • Writing of slave address value • Trigger of RESTART condition generating (4) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. It is because it may become the same as above. (5) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers does not have the problem. 3804 Group (Spec.L) RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of X IN . Then the RESET pin is returned to an “H” level (the power source voltage should be between 2.7 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Input to the RESET pin in the following procedure. • When power source is stabilized (1) Input “L” level to RESET pin. (2) Input “L” level for 16 cycles or more to XIN pin. (3) Input “H” level to RESET pin. • At power-on (1) Input “L” level to RESET pin. (2) Increase the power source voltage to 2.7 V. (3) Wait for td(P-R) until internal power source has stabilized. (4) Input “L” level for 16 cycles or more to XIN pin. (5) Input “H” level to RESET pin. VCC RESET VCC 2.7 V 0V RESET 0.2VCC or less 0V td(P-R)+XIN16 cycles or more 5V VCC RESET VCC Power source voltage detection circuit 2.7 V 0V 5V RESET 0V td(P-R)+XIN16 cycles or more Example at VCC = 5 V Fig. 74 Reset circuit example XIN φ RESET Internal reset ? Address ? ? ? FFFC FFFD ADH,L Reset address from the vector table. ? Data ? ? ? ADL ADH SYNC XIN : 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 75 Reset sequence Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 77 of 128 3804 Group (Spec.L) Address Register contents Address Register contents (1) Port P0 (P0) 000016 0016 (41) Timer Z (low-order) (TZL) 002816 FF16 (2) Port P0 direction register (P0D) 000116 0016 (42) Timer Z (high-order) (TZH) 002916 FF16 (3) Port P1 (P1) 000216 0016 (43) Timer Z mode register (TZM) 002A16 0016 (4) Port P1 direction register (P1D) 000316 0016 (44) PWM control register (PWMCON) 002B16 0016 (5) Port P2 (P2) 000416 0016 (45) PWM prescaler (PREPWM) 002C16 X X X X X X X X (6) Port P2 direction register (P2D) 000516 0016 (46) PWM register (PWM) 002D16 X X X X X X X X (7) Port P3 (P3) 000616 0016 (47) Baud rate generator 3 (BRG3) 002F16 X X X X X X X X (8) Port P3 direction register (P3D) 000716 0016 (48) Transmit/Receive buffer register 3 (TB3/RB3) 003016 X X X X X X X X (9) Port P4 (P4) 000816 0016 (49) Serial I/O3 status register (SIO3STS) 003116 1 0 0 0 0 0 0 0 (10) Port P4 direction register (P4D) 000916 0016 (50) Serial I/O3 control register (SIO3CON) 003216 (11) Port P5 (P5) 000A16 0016 (51) UART3 control register (UART3CON) 003316 1 1 1 0 0 0 0 0 (12) Port P5 direction register (P5D) 000B16 0016 (52) AD/DA control register (ADCON) 003416 0 0 0 0 1 0 0 0 000C16 0016 (53) AD conversion register 1 (AD1) 003516 X X X X X X X X 000D16 0016 (13) Port P6 (P6) 0016 (54) DA1 conversion register (DA1) 003616 0016 (15) Timer 12, X count source selection register (T12XCSS) 000E16 0 0 1 1 0 0 1 1 (55) DA2 conversion register (DA2) 003716 0016 (16) Timer Y, Z count source selection register (TYZCSS) 000F16 0 0 1 1 0 0 1 1 (56) AD conversion register 2 (AD2) 003816 0 0 0 0 0 0 X X (17) MISRG 001016 (57) Interrupt source selection register (INTSEL) 003916 (18) I2C data shift register (S0) 001116 X X X X X X X X (58) Interrupt edge selection register (INTEDGE) 003A16 0016 (19) I2C special mode status register (S3) 001216 0 0 1 0 0 0 0 0 (59) CPU mode register (CPUM) 003B16 0 1 0 0 1 0 0 0 (20) I2C status register (S1) 001316 0 0 0 1 0 0 0 X (60) Interrupt request register 1 (IREQ1) 003C16 0016 (21) I2C control register (S1D) 001416 0016 (61) Interrupt request register 2 (IREQ2) 003D16 0016 (22) I2C clock control register (S2) 001516 0016 (62) Interrupt control register 1 (ICON1) 003E16 0016 (23) I2C START/STOP condition control register (S2D) 001616 0 0 0 1 1 0 1 0 (63) Interrupt control register 2 (ICON2) 003F16 0016 (24) I2C special mode control register (S3D) (64) Flash memory control register 0 (FMCR0) 0FE016 0 0 0 0 0 0 0 1 (25) Transmit/Receive buffer register 1 (TB1/RB1) 001816 X X X X X X X X (65) Flash memory control register 1 (FMCR1) 0FE116 0 1 0 0 0 0 0 0 (26) Serial I/O1 status register (SIO1STS) 001916 1 0 0 0 0 0 0 0 (66) Flash memory control register 2 (FMCR2) 0FE216 0 1 0 0 0 1 0 1 (27) Serial I/O1 control register (SIO1CON) 001A16 (67) Port P0 pull-up control register (PULL0) 0FF016 (28) UART1 control register (UART1CON) 001B16 1 1 1 0 0 0 0 0 (68) Port P1 pull-up control register (PULL1) 0FF116 0016 (29) Baud rate generator 1 (BRG1) 001C16 X X X X X X X X (69) Port P2 pull-up control register (PULL2) 0FF216 0016 (30) Serial I/O2 control register (SIO2CON) 001D16 (70) Port P3 pull-up control register (PULL3) 0FF316 0016 (31) Watchdog timer control register (WDTCON) 001E16 0 0 1 1 1 1 1 1 (71) Port P4 pull-up control register (PULL4) 0FF416 0016 (32) Serial I/O2 register (SIO2) 001F16 X X X X X X X X (72) Port P5 pull-up control register (PULL5) 0FF516 0016 (33) Prescaler 12 (PRE12) 002016 FF16 (73) Port P6 pull-up control register (PULL6) 0FF616 0016 (34) Timer 1 (T1) 002116 0116 (74) I2C slave address register 0 (S0D0) 0FF716 0016 (35) Timer 2 (T2) 002216 FF16 (75) I2C slave address register 1 (S0D1) 0FF816 0016 (36) Timer XY mode register (TM) 002316 0016 (76) I2C slave address register 2 (S0D2) 0FF916 0016 (37) Prescaler X (PREX) 002416 FF16 (77) Processor status register (PS) X X X X X 1 X X (38) Timer X (TX) 002516 FF16 (78) Program counter (PCH) FFFD16 contents (39) Prescaler Y (PREY) 002616 FF16 (PCL) FFFC16 contents (40) Timer Y (TY) 002716 FF16 (14) Port P6 direction register (P6D) 001716 0016 0016 0016 0016 Note : X: Not fixed. Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 76 Internal status at reset Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 78 of 128 0016 0016 3804 Group (Spec.L) CLOCK GENERATING CIRCUIT The 3804 group (Spec.L) has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub clock XCINXCOUT oscillation circuit. An oscillation circuit can be formed by connecting a resonator between X IN and X OUT (X CIN and X COUT ). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between X IN and X OUT since a feed-back resistor exists on-chip.(An external feed-back resistor may be needed depending on conditions.) However, an external feedback resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. • Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset is released, this mode is selected. (2) High-speed mode The internal clock φ is half the frequency of XIN. (3) Low-speed mode The internal clock φ is half the frequency of XCIN. (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and X IN and X CIN oscillators stop. When the oscillation stabilizing time set after STP instruction released bit (bit 0 of address 001016) is “0”, the prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the oscillation stabilizing time set after STP instruction released bit is “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. After STP instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the STP instruction, and the output of the prescaler 12 is connected to timer 1. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the oscillation is stable since a wait time will not be generated. In the flash memory L version, the built-in power source circuit is switched to the low power dissipation mode at executing the STP instruction to reduce consumption current. At returning from the STP instruction, the built-in power source circuit is switched to the normal mode, but a specified time is required from when the power supply to the flash memory is started until the flash memory operation is enabled. In this version, set a wait time of 100 μs or more with the oscillation stabilizing time set after STP instruction released function by using timer 1. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction. When releasing the STP state, the input of the prescaler 12 and timer 1 is connected to the count source which had set at executing the STP instruction and the prescaler 12 and timer 1 will start counting. Set the timer 1 interrupt enable bit to “0” before executing the STP instruction. <Notes> • If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(X IN ) > 3×f(XCIN). • When using the quartz-crystal oscillator of high frequency, such as 16 MHz etc., it may be necessary to select a specific oscillator with the specification demanded. • When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 79 of 128 3804 Group (Spec.L) XCIN XCOUT XIN XOUT Rd Rf Rd CCOUT CCIN CIN COUT Note 1 : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer’s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. Fig. 77 Ceramic resonator circuit X IN X COUT X CIN Rf C CIN X OUT Open Rd External oscillation circuit C COUT V CC V CC V SS V SS Fig. 78 External clock input circuit Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 80 of 128 3804 Group (Spec.L) XCOUT XCIN “0” “1” Port XC switch bit XIN XOUT (4) Main clock division ratio selection bits(1) Divider Low-speed mode 1/2 Timer 1 Prescaler 12 1/4 High-speed or middle-speed mode (3) Reset or STP instruction(2) Main clock division ratio selection bits(1) Middle-speed mode Timing φ (internal clock) High-speed or low-speed mode Main clock stop bit Q S S R STP instruction WIT instruction R Q Reset Q S R STP instruction Reset Interrupt disable flag l Interrupt request Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port XC switch bit (b4) to “1”. 2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the STP instruction is supplied as the count source at executing STP instruction. 3: When bit 0 of MISRG is “0”, timer 1 is set “0116” and prescaler 12 is set “FF16” automatically. When bit 0 of MISRG is “1” , set the appropriate value to them in accordance with oscillation stabilizing time required by the using oscillator because nothing is automatically set into timer 1 and prescaler 12. 4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig. 79 System clock generating circuit block diagram (Single-chip mode) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 81 of 128 3804 Group (Spec.L) Reset ”0 ” → C M ”← 0” “1 M 6 →” C ”← “1 Middle-speed mode (f(φ) = 1 MHz) CM7=0 CM6=1 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) C “0 M 4 C M ”← “1 6 → ” 1” ”← → ”0 ” CM6 “1”←→”0” C “0 M7 C M ”← → “1 6 ”1 ”← ” → ”0 ” High-speed mode (f(φ) = 4 MHz) CM7=0 CM6=0 CM5=0 (8 MHz oscillating) CM4=0 (32 kHz stopped) CM4 “1”←→”0” 4 CM6 “1”←→”0” High-speed mode (f(φ) = 4 MHz) CM7=0 CM6=0 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) CM7 “1”←→”0” CM4 “1”←→”0” Middle-speed mode (f(φ) = 1 MHz) CM7=0 CM6=1 CM5=0 (8 MHz oscillating) CM4=0 (32 kHz stopped) CM5 “1”←→”0” Low-speed mode (f(φ) = 16 kHz) CM7=1 CM6=0 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) Low-speed mode (f(φ) = 16 kHz) CM7=1 CM6=0 CM5=1 (8 MHz stopped) CM4=1 (32 kHz oscillating) b7 b4 CPU mode register (CPUM : address 003B 16) CM4 : Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN-XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : φ = f(XIN)/2 (High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not available Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer operates in the wait mode. 4: When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/highspeed mode. 5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode. 6: Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/ high-speed mode. 7: The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal clock. Fig. 80 State transitions of system clock Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 82 of 128 3804 Group (Spec.L) FLASH MEMORY MODE The 3804 group (Spec.L)’s flash memory version has the flash memory that can be rewritten with a single power source. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). This flash memory version has some blocks on the flash memory as shown in Figure 81 and each block can be erased. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This Boot ROM area can be rewritten in only parallel I/O mode. Summary Table 15 lists the summary of the 3804 group (Spec.L) flash memory version. Table 15 Summary of 3804 group (Spec.L)’s flash memory version Item Power source voltage (VCC) Program/Erase VPP voltage (VPP) Flash memory mode Erase block division Specifications User ROM area/Data ROM area Boot ROM area (1) Program method Erase method Program/Erase control method Number of commands Number of program/Erase times ROM code protection NOTE: VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V 3 modes; Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode Refer to Figure 81. Not divided (4 Kbytes) In units of bytes Block erase Program/Erase control by software command 5 commands 100(Max.) Available in parallel I/O mode and standard serial I/O mode 1. The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be erased and written in only parallel I/O mode. Table 16 Electrical characteristics of flash memory (program ROM) Symbol − − Parameter Byte programming time (Block 1) (Block 2) Block erase time (Block 3) (Block A, B) NOTES: Test conditions VCC = 5.0 V, Topr = 25 °C VCC = 5.0 V, Topr = 25 °C Min. − − − − − Limits Typ. 60 0.5 0.9 1.3 0.3 Max. 400 9 9 9 9 Unit μs s s s s 1. VCC = AVCC = 2.7 V to 5.5 V, Topr = 0 °C to 60 °C, unless otherwise noted. 2. Definition of programming/erase count The programming/erase count refers to the number of erase operations per block. For example, if block A is a 2 K-byte block and 2,048 1-byte writes are performed, all to different addresses, after which block A is erased, the programming/erase count is 1. Note that for each erase operation it is not possible to perform more than one programming (write) operation to the same address (overwrites prohibited). 3. This is the number of times for which all electrical characteristics are guaranteed after a programming or erase operation. (The guarantee covers the range from 1 to maximum value.) 4. On systems where reprogramming is performed a large number of times, it is possible to reduce the effective number of overwrites by sequentially shifting the write address, so that as much of the available area of the block is used up through successive programming (write) operations before an erase operation is performed. For example, if each programming operation uses 16 bytes of space, a maximum of 128 programming operations may be performed before it becomes necessary to erase the block in order to continue. In this way the effective number of overwrites can be kept low. The effective overwrite count can be further reduced by evenly dividing operations between block A and block B. It is recommended that data be retained on the number of times each block has been erased and a limit count set. 5. If a block erase error occurs, execute the clear status register command followed by the block erase command a minimum of three times and until the erase error is no longer generated. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 83 of 128 3804 Group (Spec.L) Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 81 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset and the CNVSS pin high after pulling the P45/TxD1 pin and CNVSS pin high, the CPU starts operating (start address of program is stored into addresses FFFC 16 and FFFD 16 ) using the control program in the Boot ROM area. This mode is called the “Boot mode”. Also, User ROM area can be rewritten using the control program in the Boot ROM area. CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 81 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area before it can be executed. Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. 000016 User ROM area SFR area 100016 004016 Internal RAM area (2 Kbytes) RAM 180016 Data block B: 2 Kbytes Data block A: 2 Kbytes 200016 083F16 Block 3: 24 Kbytes 0FE016 SFR area 800016 0FFF16 100016 Block 2: 16 Kbytes C00016 Internal flash memory area (60 Kbytes) Notes 1: The boot ROM area can be rewritten in a parallel I/O mode. (Access to except boot ROM area is disabled.) 2: To specify a block, use the maximum address in the block. Block 1: 8 Kbytes F00016 E00016 Boot ROM area 4 Kbytes Block 0: 8 Kbytes FFFF16 FFFF16 Fig. 81 Block diagram of built-in flash memory Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 84 of 128 FFFF16 3804 Group (Spec.L) Outline Performance CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM area before it can be executed. The MCU enters CPU rewrite mode by setting “1” to the CPU rewrite mode select bit (bit 1 of address 0FE016). Then, software commands can be accepted. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 82 shows the flash memory control register 0. Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0” (busy). Otherwise, it is “1” (ready). Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. When this bit is set to “1”, the MCU enters CPU rewrite mode. And then, software commands can be accepted. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in the internal RAM for write to bit 1. To set this bit 1 to “1”, it is necessary to write “0” and then write “1” in succession to bit 1. The bit can be set to “0” by only writing “0”. Bit 2 of the flash memory control register 0 is the 8 KB user block E/W enable bit. By setting combination of bit 4 of the flash memory control register 2 and this bit as shown in Table 17, E/W is disabled to user block in the CPU rewriting mode. Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when flash memory access has failed. When the CPU rewrite mode select bit is “1”, setting “1” for this bit resets the control circuit. To release the reset, it is necessary to set this bit to “0”. Bit 5 of the flash memory control register 0 is the User ROM area select bit and is valid only in the boot mode. Setting this bit to “1” in the boot mode switches an accessible area from the boot ROM area to the user ROM area. To use the CPU rewrite mode in the boot mode, set this bit to “1”. To rewrite bit 5, execute the user original reprogramming control software transferred to the internal RAM in advance. Bit 6 of the flash memory control register 0 is the program status flag. This bit is set to “1” when writing to flash memory is failed. When program error occurs, the block cannot be used. Bit 7 of the flash memory control register 0 is the erase status flag. This bit is set to “1” when erasing flash memory is failed. When erase error occurs, the block cannot be used. Figure 83 shows the flash memory control register 1. Bit 0 of the flash memory control register 1 is the Erase suspend enable bit. By setting this bit to “1”, the erase suspend mode to suspend erase processing temporary when block erase command is executed can be used. In order to set this bit to “1”, writing “0” and “1” in succession to bit 0. In order to set this bit to “0”, write “0” only to bit 0. Bit 1 of the flash memory control register 1 is the erase suspend request bit. By setting this bit to “1” when erase suspend enable bit is “1”, the erase processing is suspended. Bit 6 of the flash memory control register 1 is the erase suspend flag. This bit is cleared to “0” at the flash erasing. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 85 of 128 b7 b0 Flash memory control register 0 (FMCR0: address : 0FE016: initial value: 0116) RY/BY status flag 0 : Busy (being written or erased) 1 : Ready CPU rewrite mode select bit(1) 0 : CPU rewrite mode invalid 1 : CPU rewrite mode valid 8 KB user block E/W enable bit(1, 2) 0 : E/W disabled 1 : E/W enabled Flash memory reset bit(3, 4) 0 : Normal operation 1 : reset Not used (do not write “1” to this bit.) User ROM area select bit(5) 0 : Boot ROM area is accessed 1 : User ROM area is accessed Program status flag 0: Pass 1: Error Erase status flag 0: Pass 1: Error Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: This bit can be written only when CPU rewrite mode select bit is “1”. 3: Effective only when the CPU rewrite mode select bit = “1”. Fix this bit to “0” when the CPU rewrite mode select bit is “0”. 4: When setting this bit to “1” (when the control circuit of flash memory is reset), the flash memory cannot be accessed for 10 μs. 5: Write to this bit in program on RAM Fig. 82 Structure of flash memory control register 0 b7 b0 Flash memory control register 1 (FMCR1: address : 0FE116: initial value: 4016) Erase Suspend enable bit(1) 0 : Suspend invalid 1 : Suspend valid Erase Suspend request bit(2) 0 : Erase restart 1 : Suspend request Not used (do not write “1” to this bit.) Erase Suspend flag 0 : Erase active 1 : Erase inactive (Erase Suspend mode) Not used (do not write “1” to this bit.) Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: Effective only when the suspend enable bit = “1”. Fig. 83 Structure of flash memory control register 1 3804 Group (Spec.L) b7 b0 Flash memory control register 2 (FMCR2: address : 0FE216: initial value: 4516) Not used Not used (do not write “1” to this bit.) Not used All user block E/W enable bit(1, 2) 0 : E/W disabled 1 : E/W enabled Not used Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: Effective only when the CPU rewrite mode select bit = “1”. Fig. 84 Structure of flash memory control register 2 Table 17 State of E/W inhibition function All user block E/W enable bit 8 KB user block E/W enable bit 8 KB × 2 block Addresses C00016 to FFFF16 16 KB + 24 KB block Addresses 200016 to BFFF16 Data block Addresses 100016 to 1FFF16 0 0 E/W disabled E/W disabled E/W enabled 0 1 E/W disabled E/W disabled E/W enabled 1 0 E/W disabled E/W enabled E/W enabled 1 1 E/W enabled E/W enabled E/W enabled Figure 85 shows a flowchart for setting/releasing CPU rewrite mode. Start Single-chip mode or Boot mode Set CPU mode register(1) Transfer CPU rewrite mode control program to internal RAM Jump to control program transferred to internal RAM (Subsequent operations are executed by control program in this RAM) Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession) Set all user block E/W enable bit to “1” (by writing “0” and then “1” in succession) Set 8 KB user block E/W enable bit (At E/W disabled; writing “0” , at E/W enabled; writing “0” and then “1” in succession Using software command executes erase, program, or other operation Execute read array command(2) Set all user block E/W enable bit to “0” Set 8 KB user block E/W enable bit to “0” Write “0” to CPU rewrite mode select bit End Notes 1: Set the main clock as follows depending on the clock division ratio selection bits of CPU mode register (bits 6, 7 of address 003B16). 2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command. Fig. 85 CPU rewrite mode set/release flowchart be sure to execute Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 86 of 128 3804 Group (Spec.L) <Notes on CPU Rewrite Mode> Take the notes described below when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the system clock φ to 4.0 MHz or less using the clock division ratio selection bits (bits 6 and 7 of address 003B16). (2) Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode. (3) Interrupts The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. (4) Watchdog timer If the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase. (5) Reset Reset is always valid. The MCU is activated using the boot mode at release of reset in the condition of CNVSS = “H”, so that the program will begin at the address which is stored in addresses FFFC16 and FFFD16 of the boot ROM area. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 87 of 128 3804 Group (Spec.L) Software Commands Table 18 lists the software commands. After setting the CPU rewrite mode select bit to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. The RY/BY status flag of the flash memory control register is “0” during write operation and “1” when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. • Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7). The read array mode is retained until another command is written. • Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the contents of the status register are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section. Start Write “4016” Write Read status register • Clear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. • Program Command (4016) Program operation starts when the command code “4016 ” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by read status register or the RY/BY status flag. When the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (D0 to D7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode remains active until the read array command (FF16) is written. Write address Write data SR7 = “1”? or RY/BY = “1”? NO YES NO Program error SR4 = “0”? YES Program completed Fig. 86 Program flowchart Table 18 List of software commands (CPU rewrite mode) First bus cycle Second bus cycle cycle number Mode Address Data (D0 to D7) Read array 1 Write X(4) FF16 Read status register 2 Write X 7016 Clear status register 1 Write X 5016 Program 2 Write X 4016 Command Block erase 2 Write X 2016 NOTES: 1. 2. 3. 4. SRD = Status Register Data WA = Write Address, WD = Write Data BA = Block Address to be erased (Input the maximum address of each block.) X denotes a given address in the User ROM area. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 88 of 128 Mode Address Data (D0 to D7) Read X SRD(1) Write WA(2) WD(2) Write BA(3) D016 3804 Group (Spec.L) • Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed by read status register or the RY/BY status flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. The RY/BY status flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status register bit 7. After the block erase ends, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. Start Write “2016” Write “D016” Blockaddress Read status register SR7 = “1”? or RY/BY = “1”? NO YES SR5 = “0”? YES Erase completed (write read command “FF16”) Fig. 87 Erase flowchart Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 89 of 128 NO Erase error 3804 Group (Spec.L) • Status Register The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to “8016”. Table 19 shows the status register. Each bit in this register is explained below. • Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to “0” (busy) during write or erase operation and is set to “1” when these operations ends. After power-on, the sequencer status is set to “1” (ready). • Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is reset to “0”. • Program status (SR4) The program status indicates the operating status of write operation. When a write error occurs, it is set to “1”. The program status is reset to “0” when it is cleared. If “1” is written for any of the SR5 and SR4 bits, the read array, program, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to “1”. Table 19 Definition of each bit in status register Each bit of SRD bits Status name SR7 (bit 7) SR6 (bit 6) SR5 (bit 5) SR4 (bit 4) SR3 (bit 3) SR2 (bit 2) SR1 (bit 1) SR0 (bit 0) Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 90 of 128 Definition “1” Ready − Terminated in error Terminated in error − − − − “0” Busy − Terminated normally Terminated normally − − − − 3804 Group (Spec.L) Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 88 shows a full status check flowchart and the action to be taken when each error occurs. Read status register SR4 = “1” YES and SR5 = “1”? Command sequence error Execute the clear status register command (50 16) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. NO SR5 = “0”? NO Erase error Should an erase error occur, the block in error cannot be used. YES SR4 = “0”? NO Program error Should a program error occur, the block in error cannot be used. YES End (block erase, program) Note: When one of SR5 and SR4 is set to “1”, none of the read array, program, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 88 Full status check flowchart and remedial procedure for errors Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 91 of 128 3804 Group (Spec.L) Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. • ROM Code Protect Function The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control address (address FFDB 16 ) in parallel I/O mode. Figure 89 shows the ROM code protect control address (address FFDB16). (This address exists in the User ROM area.) b7 If one or both of the pair of ROM code protect bits is set to “0”, the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to “00”, the ROM code protect is turned off, so that the contents of internal flash memory can be readout or modified. Once the ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM code protect reset bits. Rewriting of only the ROM code protect control address (address FFDB16) cannot be performed. When rewriting the ROM code protect reset bit, rewrite the whole user ROM area (block 0) containing the ROM code protect control address. b0 1 1 ROM code protect control address (address FFDB16) ROMCP (FF16 when shipped) Reserved bits (“1” at read/write) ROM code protect level 2 set bits (ROMCP2)(1, 2) b3 b2 0 0 : Protect enabled 0 1 : Protect enabled 1 0 : Protect enabled 1 1 : Protect disabled ROM code protect reset bits (ROMCR)(3) b5 b4 0 0 : Protect removed 0 1 : Protect set bits effective 1 0 : Protect set bits effective 1 1 : Protect set bits effective ROM code protect level 1 set bits (ROMCP1)(1) b7 b6 0 0 : Protect enabled 0 1 : Protect enabled 1 0 : Protect enabled 1 1 : Protect disabled Notes 1: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite mode. Fig. 89 Structure of ROM code protect control address Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 92 of 128 3804 Group (Spec.L) • ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFD416 to FFDA16. Write a program which has had the ID code preset at these addresses to the flash memory. Address FFD416 ID1 FFD516 ID2 FFD616 ID3 FFD716 ID4 FFD816 ID5 FFD916 ID6 FFDA16 ID7 FFDB16 ROM code protect control Interrupt vector area Fig. 90 ID code store addresses Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 93 of 128 3804 Group (Spec.L) Parallel I/O Mode The parallel I/O mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. Use the external device (writer) only for 3804 group (Spec.L) flash memory version. For details, refer to the user’s manual of each writer manufacturer. • User ROM and Boot ROM Areas In parallel I/O mode, the User ROM and Boot ROM areas shown in Figure 81 can be rewritten. Both areas of flash memory can be operated on in the same way. The Boot ROM area is 4 Kbytes in size and located at addresses F00016 through FFFF 16 . Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. Therefore, using the MCU in standard serial I/O mode, do not rewrite to the Boot ROM area. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 94 of 128 3804 Group (Spec.L) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H” to the CNVSS pin and “H” to the P45 (BOOTENT) pin, and releasing the reset operation. (In the ordinary microcomputer mode, set CNVSS pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Renesas. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. The standard serial I/ O mode has standard serial I/O mode 1 of the clock synchronous serial and standard serial I/O mode 2 of the clock asynchronous serial. Table 20 and 21 show description of pin function (standard serial I/O mode). Figures 91 to 96 show the pin connections for the standard serial I/O mode. Figures 97 and 98 show the operating waveform for standard serial I/O mode 1 and the operating waveform for standard serial I/O mode 1, respectively. Figures 99 and 100 show the connection examples in standard serial I/O mode. In standard serial I/O mode, only the User ROM area shown in Figure 81 can be rewritten. The Boot ROM area cannot be written. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, this function determines whether the ID code sent from the peripheral unit (programmer) and those written in the flash memory match. The commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 95 of 128 3804 Group (Spec.L) Table 20 Description of pin function (Flash Memory Serial I/O Mode 1) Pin name VCC,VSS CNVSS RESET XIN XOUT AVSS VREF P00−P07, P10−P17, P20−P27, P30−P37, P40−P43, P50−P57, P60−P67 P44 P45 P46 P47 Signal name Power supply CNVSS Reset input I/O I I I Function Apply 2.7 to 5.5 V to the VCC pin and 0 V to the VSS pin. After input of port is set, input “H” level. Clock input Clock output Analog power supply input Reference voltage input I/O port I O Reset input pin. To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of XIN. Connect an oscillation circuit between the XIN and XOUT pins. As for the connection method, refer to the “clock generating circuit”. I I/O Connect AVSS to VSS. Apply reference voltage of A/D to this pin. Input “L” or “H” level, or keep open. RxD input TxD output SCLK input BUSY output I O I O Serial data input pin. Serial data output pin. Serial clock input pin. BUSY signal output pin. Table 21 Description of pin function (Flash Memory Serial I/O Mode 2) Pin name VCC,VSS CNVSS RESET XIN XOUT AVSS VREF P00−P07, P10−P17, P20−P27, P30−P37, P40−P43, P50−P57, P60−P67 P44 P45 P46 P47 Signal name Power supply CNVSS Reset input I/O I I I Clock input Clock output Analog power supply input Reference voltage input I/O port I O Reset input pin. To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of XIN. Connect an oscillation circuit between the XIN and XOUT pins. As for the connection method, refer to the “clock generating circuit”. I I/O Connect AVSS to VSS. Apply reference voltage of A/D to this pin. Input “L” or “H” level, or keep open. RxD input TxD output SCLK input BUSY output I O I O Serial data input pin. Serial data output pin. Input “L” level. BUSY signal output pin. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 96 of 128 Function Apply 2.7 to 5.5 V to the VCC pin and 0 V to the VSS pin. After input of port is set, input “H” level. P14 P15 P16 P17 38 36 35 34 33 37 P11/INT01 P12 P13 39 P07/AN15 42 P10/INT41 P06/AN14 43 40 P05/AN13 44 41 P03/AN11 P04/AN12 45 P01/AN9 P02/AN10 46 P00/AN8 47 P37/SRDY3 49 32 P20(LED0) P36/SCLK3 50 31 P21(LED1) P35/TXD3 51 30 P22(LED2) P34/RXD3 52 29 P23(LED3) P33/SCL 53 28 P24(LED4) P32/SDA 54 27 P25(LED5) P31/DA2 55 26 P26(LED6) P30/DA1 56 25 P27(LED7) VCC 57 24 VSS VREF 58 23 XOUT M38049FFLHP/KP VSS * 9 10 11 12 13 14 15 16 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 P52/SCLK2 17 8 64 P53/SRDY2 CNVSS P63/AN3 7 CNVSS 6 18 P54/CNTR0 RESET 63 P55/CNTR1 RESET P64/AN4 5 P41/INT00/XCIN 19 4 20 62 P57/INT3 61 P65/AN5 P56/PWM P66/AN6 3 P40/INT40/XCOUT P60/AN0 XIN 21 2 22 60 1 59 P61/AN1 AVSS P67/AN7 P62/AN2 VCC 48 3804 Group (Spec.L) *Connect oscillation circuit. RxD indicates flash memory pin. TxD SCLK BUSY Package code: PLQP0064KB-A (64P6Q-A) / PLQP0064GA-A (64P6U-A) Fig. 91 Connection for standard serial I/O mode 1 (M38049FFLHP/KP) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 97 of 128 P14 P15 P16 P17 38 36 35 34 33 37 P11/INT01 P12 P13 39 P07/AN15 42 P10/INT41 P06/AN14 43 40 P05/AN13 44 41 P03/AN11 P04/AN12 45 P01/AN9 P02/AN10 46 P00/AN8 47 P37/SRDY3 49 32 P20(LED0) P36/SCLK3 50 31 P21(LED1) P35/TXD3 51 30 P22(LED2) P34/RXD3 52 29 P23(LED3) P33/SCL 53 28 P24(LED4) P32/SDA 54 27 P25(LED5) P31/DA2 55 26 P26(LED6) P30/DA1 56 25 P27(LED7) VCC 57 24 VSS VREF 58 23 XOUT M38049FFLHP/KP VSS * 9 10 11 12 13 14 15 16 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 P52/SCLK2 17 8 64 P53/SRDY2 CNVSS P63/AN3 7 CNVSS 6 18 P54/CNTR0 RESET 63 P55/CNTR1 RESET P64/AN4 5 P41/INT00/XCIN 19 4 20 62 P57/INT3 61 P65/AN5 P56/PWM P66/AN6 3 P40/INT40/XCOUT P60/AN0 XIN 21 2 22 60 1 59 P61/AN1 AVSS P67/AN7 P62/AN2 VCC 48 3804 Group (Spec.L) *Connect oscillation circuit. RxD indicates flash memory pin. TxD “L” input BUSY Package code: PLQP0064KB-A (64P6Q-A) / PLQP0064GA-A (64P6U-A) Fig. 92 Connection for standard serial I/O mode 2 (M38049FFLHP/KP) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 98 of 128 3804 Group (Spec.L) VCC BUSY SCLK TXD RXD CNVSS RESET VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M38049FFLSP VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN * XOUT VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Package code: PRDP0064BA-A (64P4B) *Connect oscillation circuit. indicates flash memory pin. Fig. 93 Connection for standard serial I/O mode 1 (M38049FFLSP) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 99 of 128 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) 3804 Group (Spec.L) VCC BUSY “L” input TXD RXD CNVSS RESET VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M38049FFLSP VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN * XOUT VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Package code: PRDP0064BA-A (64P4B) *Connect oscillation circuit. indicates flash memory pin. Fig. 94 Connection for standard serial I/O mode 2 (M38049FFLSP) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 100 of 128 P30/DA1 P31/DA2 P32/SDA P33/SCL P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) 3804 Group (Spec.L) PIN CONFIGURATION (TOP VIEW) 8 7 6 A B C D E F G H 50 46 44 41 40 32 31 30 P36/SCLK3 P02/AN10 P04/AN12 P07/AN15 P10/INT41 P20(LED0) P21(LED1) P22(LED2) 51 47 45 42 39 27 29 28 P35/TXD3 P01/AN9 P03/AN11 P06/AN14 P11/INT01 P25(LED5) P23(LED3) P24(LED4) 53 52 48 43 38 37 26 25 P33/SCL P34/RXD3 P00/AN8 P05/AN13 P12 P13 P26(LED6) P27(LED7) 8 7 6 VSS 5 56 55 54 49 33 36 35 34 P30/DA1 P31/DA2 P32/SDA P37/SRDY3 P17 P14 P15 P16 5 * 4 1 64 58 59 57 24 22 23 P62/AN2 P63/AN3 VREF AVSS VCC VSS XIN XOUT 4 BUSY VCC 3 60 61 4 7 P67/AN7 P66/AN6 P57/INT3 P54/CNTR0 12 62 63 5 8 10 13 17 19 P65/AN5 P64/AN4 P56/PWM P53/SRDY2 P51/SOUT2 P46/SCLK1 P42/INT1 RESET 2 3 6 9 11 15 16 18 P61/AN1 P60/AN0 P55/CNTR1 P52/SCLK2 P50/SIN2 P44/RXD1 P43/INT2 CNVSS A B C D E F G H P47/SRDY1/CNTR2 14 P45/TXD1 21 P40/INT40/XCOUT 20 3 P41/INT00/XCIN TXD 2 RESET 2 SCLK 1 RXD * Connect oscillation circuit. Package code: PTLG0064JA-A (64F0G) indicates flash memory pin. Fig. 95 Connection for standard serial I/O mode 1 (M38049FFLWG) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 101 of 128 CNVSS 1 3804 Group (Spec.L) PIN CONFIGURATION (TOP VIEW) 8 7 6 A B C D E F G H 50 46 44 41 40 32 31 30 P36/SCLK3 P02/AN10 P04/AN12 P07/AN15 P10/INT41 P20(LED0) P21(LED1) P22(LED2) 51 47 45 42 39 27 29 28 P35/TXD3 P01/AN9 P03/AN11 P06/AN14 P11/INT01 P25(LED5) P23(LED3) P24(LED4) 53 52 48 43 38 37 26 25 P33/SCL P34/RXD3 P00/AN8 P05/AN13 P12 P13 P26(LED6) P27(LED7) 8 7 6 VSS 5 56 55 54 49 33 36 35 34 P30/DA1 P31/DA2 P32/SDA P37/SRDY3 P17 P14 P15 P16 5 * 4 1 64 58 59 57 24 22 23 P62/AN2 P63/AN3 VREF AVSS VCC VSS XIN XOUT 4 BUSY VCC 3 60 61 4 7 P67/AN7 P66/AN6 P57/INT3 P54/CNTR0 12 62 63 5 8 10 13 17 19 P65/AN5 P64/AN4 P56/PWM P53/SRDY2 P51/SOUT2 P46/SCLK1 P42/INT1 RESET 2 3 6 9 11 15 16 18 P61/AN1 P60/AN0 P55/CNTR1 P52/SCLK2 P50/SIN2 P44/RXD1 P43/INT2 CNVSS A B C D E F G H P47/SRDY1/CNTR2 14 P45/TXD1 21 P40/INT40/XCOUT 20 3 P41/INT00/XCIN TXD 2 RESET 2 “L”input 1 RXD Package code: PTLG0064JA-A (64F0G) * Connect oscillation circuit. indicates flash memory pin. Fig. 96 Connection for standard serial I/O mode 2 (M38049FFLWG) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 102 of 128 CNVSS 1 3804 Group (Spec.L) td(CNVSS-RESET) td(P45-RESET) Power source RESET CNVSS P45(TXD) P46(SCLK) P47(BUSY) P44(RXD) Symbol Limits Min. Typ. Max. td(CNVSS-RESET) 0 − − td(P45-RESET) 0 Unit ms Notes: In the standard serial I/O mode 1, input “H” to the P46 pin. Be sure to set the CNVSS pin to “H” before rising RESET. Be sure to set the P45 pin to “H” before rising RESET. ms Fig. 97 Operating waveform for standard serial I/O mode 1 td(CNVSS-RESET) td(P45-RESET) Power source RESET CNVSS P45(TXD) P46(SCLK) P47(BUSY) P44(RXD) Symbol Limits Min. Typ. Max. td(CNVSS-RESET) 0 − − td(P45-RESET) 0 Unit ms Notes: In the standard serial I/O mode 2, input “H” to the P46 pin. Be sure to set the CNVSS pin to “H” before rising RESET. Be sure to set the P45 pin to “H” before rising RESET. ms Fig. 98 Operating waveform for standard serial I/O mode 2 Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 103 of 128 3804 Group (Spec.L) 3804 Group (Spec. L) T_VDD VCC T_VPP N.C. 4.7kΩ T_RXD P45 (TXD) T_TXD P44 (RXD) T_SCLK P46 (SCLK) T_PGM/OE/MD CNVSS 4.7kΩ T_BUSY P47 (BUSY) RESET circuit RESET T_RESET GND VSS AVSS XIN XOUT Set the same termination as the single-chip mode. Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. Fig. 99 When using programmer (in standard serial I/O mode 1) of Suisei Electronics System Co., LTD, connection example Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 104 of 128 3804 Group (Spec.L) 3804 Group (Spec. L) VCC VCC CNVSS 4.7 kΩ 4.7 kΩ 4.7 kΩ P45 (TXD) P44 (RXD) P46 (SCLK) P47 (BUSY) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESET circuit *1 RESET VSS AVSS XIN XOUT Set the same termination as the single-chip mode. *1 : Open-collector buffer Note : For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. Fig. 100 When using E8 programmer (in standard serial I/O mode 1), connection example Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 105 of 128 3804 Group (Spec.L) NOTES NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. <Reason> After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “1”. Set D flag to “1” ADC or SBC instruction NOP instruction SEC, CLC, or CLD instruction Reset Fig. 103 Execution of decimal calculations Initializing of flags Main program Fig. 101 Initialization of processor status register (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. (S) (S) + 1 Stored PS Fig. 102 Stack memory contents after PHP instruction execution 2. Decimal calculations (1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. (2) Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized to “1” before each calculation. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 106 of 128 3. JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 4. Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. 5. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The instruction with the addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. 6. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock φ by the number of cycles mentioned in the 740 Family Software Manual. The frequency of the internal clock φ is the twice the XIN cycle in high-speed mode, 8 times the XIN cycle in middle-speed mode, and the twice the XCIN in low-speed mode. 3804 Group (Spec.L) Countermeasures against noise (1) Shortest wiring length 1. Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). <Reason> The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit VSS N.G. Reset circuit VSS XIN XOUT VSS N.G. XIN XOUT VSS O.K. Fig. 105 Wiring for clock I/O pins RESET VSS Noise RESET (2) Connection of bypass capacitor across VSS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 μF bypass capacitor across the VSS line and the VCC line as follows: • Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. • Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for VSS line and VCC line. • Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. VSS O.K. VCC VCC VSS VSS Fig. 104 Wiring for the RESET pin 2. Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other VSS patterns. <Reason> If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 107 of 128 N.G. O.K. Fig. 106 Bypass capacitor across the VSS line and the VCC line 3804 Group (Spec.L) (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful especially when range of voltage and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. 1. Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. <Reason> In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. 2. Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. <Reason> Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. (4) Analog input The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory size When memory size differ in one group, actual values such as an electrical characteristics, A/D conversion accuracy, and the amount of proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evaluation for each product of every after confirming product specification. (6) Wiring to CNVSS pin The CNVSS pin determines the flash memory mode. Connect the CNVSS pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 kΩ. resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the V S S pin of the microcomputer. Note. When the boot mode or the standard serial I/O mode is used, a switch of the input level to the CNVSS pin is required. (Note) 1. Keeping oscillator away from large current signal lines The shortest CNVSS Approx. 5kΩ Microcomputer Mutual inductance M VSS (Note) XIN XOUT VSS Large current Note: Shows the microcomputer’s pin. GND 2. Installing oscillator away from signal lines where potential levels change frequently Do not cross CNTR XIN XOUT VSS N.G. Fig. 107 Wiring for a large current signal line/Wiring of signal lines where potential levels change frequently Rev.1.00 Oct 27, 2008 REJ03B0266-0100 The shortest Page 108 of 128 Fig. 108 Wiring for the CNVSS 3804 Group (Spec.L) NOTES ON PERIPHERAL FUNCTIONS Notes on Input and Output Ports 1. Notes in standby state In standby state*1 for low-power dissipation, do not make input levels of an I/O port “undefined”. Even when an I/O port of Nchannel open-drain is set as output mode, if output data is “1”, the aforementioned notes are necessary. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: • External circuit • Variation of output levels during the ordinary operation When using built-in pull-up resistor, note on varied current values: • When setting as an input port : Fix its input level • When setting as an output port : Prevent current from flowing out to external <Reason> Exclusive input ports are always in a high-impedance state. An output transistor becomes an OFF state when an I/O port is set as input mode by the direction register, so that the port enter a highimpedance state. At this time, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels are “undefined”. This may cause power source current. Even when an I/O port of N-channel open-drain is set as output mode by the direction register, if the contents of the port latch is “1”, the same phenomenon as that of an input port will occur. *1 Standby state : stop mode by executing STP instruction wait mode by executing WIT instruction 2. Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*1, the value of the unspecified bit may be changed. <Reason> I/O ports are set to input or output mode in bit units. Reading from a port register or writing to it involves the following operations. • Port in input mode Read: Read the pin level. Write: Write to the port latch. • Port in output mode Read: Read the port latch or read the output from the peripheral function (specifications differ depending on the port). Write: Write to the port latch. (The port latch value is output from the pin.) Since bit managing instructions *1 are read-modify-write instructions,*2 using such an instruction on a port register causes a read and write to be performed simultaneously on the bits other than the one specified by the instruction. When an unspecified bit is in input mode, its pin level is read and that value is written to the port latch. If the previous value of the port latch differs from the pin level, the port latch value is changed. If an unspecified bit is in output mode, the port latch is generally read. However, for some ports the peripheral function output is read, and the value is written to the port latch. In this case, if the previous value of the port latch differs from the peripheral function output, the port latch value is changed. *1 Bit managing instructions: SEB and CLB instructions *2 Read-modify-write instructions: Instructions that read memory in byte units, modify the value, and then write the result to the same location in memory in byte units Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 109 of 128 Termination of Unused Pins 1. Terminate unused pins (1) Output ports : Open (2) I/O ports : • Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 kΩ to 10 kΩ. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/O ports for the output mode and open them at “L” or “H”. • When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. • Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (3) The AVSS pin when not using the A/D converter : • When not using the A/D converter, handle a power source pin for the A/D converter, AVSS pin as follows: AVSS: Connect to the VSS pin. 2. Termination remarks (1) I/O ports : Do not open in the input mode. <Reason> • The power source current may increase depending on the firststage circuit. • An effect due to noise may be easily produced as compared with proper termination (2) in 1 and shown on the above. (2) I/O ports : When setting for the input mode, do not connect to VCC or VSS directly. <Reason> If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS). (3) I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. <Reason> If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. • At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. 3804 Group (Spec.L) Notes on Interrupts 1. Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. • Interrupt edge selection register (address 003A16) • Timer XY mode register (address 002316) • Timer Z mode register (address 002A16) Set the above listed registers or bits as the following sequence. 2. Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to “0”, execute one or more instructions before executing the BBC or BBS instruction. Clear the interrupt request bit to “0” (no interrupt issued) NOP (one or more instructions) Set the corresponding interrupt enable bit to “0” (disabled). Set the interrupt edge select bit (active edge switch bit) or the interrupt (source) select bit to “1”. NOP (one or more instructions) Set the corresponding interrupt request bit to “0” (no interrupt request issued). Set the corresponding interrupt enable bit to “1” (enabled). Fig. 109 Sequence of changing relevant register <Reason> When setting the followings, the interrupt request bit may be set to “1”. • When setting external interrupt active edge Concerned register: Interrupt edge selection register (address 003A16) Timer XY mode register (address 002316) Timer Z mode register (address 002A16) • When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated. Concerned register: Interrupt source selection register (address 003916) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 110 of 128 Execute the BBC or BBS instruction Fig. 110 Sequence of check of interrupt request bit <Reason> If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0” is read. 3804 Group (Spec.L) Notes on 8-bit Timer (timer 1, 2, X, Y) • If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). • When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. • Set the double-function port of the CNTR0/CNTR1 pin and port P54/P55 to output in the pulse output mode. • Set the double-function port of CNTR0/CNTR1 pin and port P54/P55 to input in the event counter mode and the pulse width measurement mode. Notes on 16-bit Timer (timer Z) 1. Pulse output mode • Set the double-function port of the CNTR2 pin and port P47 to output. 2. Pulse period measurement mode • Set the double-function port of the CNTR2 pin and port P47 to input. • A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). • Since the timer latch in this mode is specialized for the readout of measured values, do not perform any write operation during measurement. • “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. 3. Pulse width measurement mode • Set the double-function port of the CNTR2 pin and port P47 to input. • A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). • Since the timer latch in this mode is specialized for the readout of measured values, do not perform any write operation during measurement. • “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. 4. Programmable waveform generating mode • Set the double-function port of the CNTR2 pin and port P47 to output. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 111 of 128 5. Programmable one-shot generating mode • Set the double-function port of CNTR2 pin and port P47 to output, and of INT1 pin and port P42 to input in this mode. • This mode cannot be used in low-speed mode. • If the value of the CNTR2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. 6. All modes • Timer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. • Timer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. • Switch of interrupt active edge of CNTR2 and INT1 Each interrupt active edge depends on setting of the CNTR2 active edge switch bit and the INT1 active edge selection bit. • Switch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. 3804 Group (Spec.L) Notes on Serial Interface 1. Notes when selecting clock synchronous serial I/O (1) Stop of transmission operation As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the serial I/Oi enable bit and the transmit enable bit to “0” (serial I/Oi and transmit disabled). <Reason> Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled), the internal transmission is running (in this case, since pins TxDi, RxDi, SCLKi, and SRDYi function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/Oi enable bit is set to “1” at this time, the data during internally shifting is output to the TxDi pin and an operation failure occurs. (2) Stop of receive operation As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/Oi enable bit to “0” (serial I/Oi disabled). (3) Stop of transmit/receive operation As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) <Reason> In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/Oi enable bit to “0” (serial I/Oi disabled) (refer to (1) in 1.). 2. Notes when selecting clock asynchronous serial I/O (1) Stop of transmission operation Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/Oi enable bit (i = 1, 3) to “0”. <Reason> This is the same as (1) in 1. (2) Stop of receive operation Clear the receive enable bit to “0” (receive disabled). (3) Stop of transmit/receive operation Only transmission operation is stopped. Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/Oi enable bit (i = 1, 3) to “0”. <Reason> This is the same as (1) in 1. Only receive operation is stopped. Clear the receive enable bit to “0” (receive disabled). Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 112 of 128 3. SRDYi (i = 1, 3) output of reception side When signals are output from the SRDYi pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDYi output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/Oi (i = 1, 3) control register again Set the serial I/Oi control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0”. Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/Oi control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time Fig. 111 Sequence of setting serial I/Oi (i = 1, 3) control register again 5. Data transmission control with referring to transmit shift register completion flag After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the SCLKi (i = 1, 3) input level. Also, write the transmit data to the transmit buffer register at “H” of the SCLKi input level. 7. Transmit interrupt request when transmit enable bit is set When using the transmit interrupt, take the following sequence. (1) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “0” (disabled). (2) Set the transmit enable bit to “1”. (3) Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to “0” after 1 or more instruction has executed. (4) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “1” (enabled). <Reason> When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. 8. Writing to baud rate generator i (BRGi) (i = 1, 3) Write data to the baud rate generator i (BRGi) (i = 1, 3) while the transmission/reception operation is stopped. 3804 Group (Spec.L) Notes on PWM The PWM starts from “H” level after the PWM enable bit is set to enable and “L” level is temporarily output from the PWM pin. The length of this “L” level output is as follows: n+1 2 × f(XIN) (s) (Count source selection bit = “0”, where n is the value set in the prescaler) n+1 f(XIN) (s) (Count source selection bit = “1”, where n is the value set in the prescaler) Notes on A/D Converter 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 μF to 1 μF. Further, be sure to verify the operation of application products on the user side. <Reason> An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion precision to be worse. Notes on Watchdog Timer • Make sure that the watchdog timer H does not underflow while waiting Stop release, because the watchdog timer keeps counting during that term. • When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program. Notes on RESET Pin Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : • Make the length of the wiring which is connected to a capacitor as short as possible. • Be sure to verify the operation of application products on the user side. <Reason> If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. Notes on Low-speed Operation Mode 2. A/D converter power source pin The AVSS pin is A/D converter power source pins. Regardless of using the A/D conversion function or not, connect it as following : • AVSS : Connect to the VSS line <Reason> If the AVSS pin is opened, the microcomputer may have a failure because of noise or others. 3. Clock frequency during A/D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A/D conversion. • f(XIN) is 500 kHz or more • Do not execute the STP instruction 4. Difference between at 8-bit reading in 10-bit A/D mode and at 8-bit A/D mode At 8-bit reading in the 10-bit A/D mode, “–1/2 LSB” correction is not performed to the A/D conversion result. In the 8-bit A/D mode, the A/D conversion characteristics is the same as 3802 group’s characteristics because “–1/2 LSB” correction is performed. Notes on D/A Converter 1. VCC when using D/A converter The D/A converter accuracy when VCC is 4.0 V or less differs from that of when VCC is 4.0 V or more. When using the D/A converter, we recommend using a VCC of 4.0 V or more. 2. DAi conversion register when not using D/A converter When a D/A converter is not used, set all values of the DAi conversion registers (i = 1, 2) to “0016”. The initial value after reset is “0016”. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 113 of 128 1. Using sub-clock To use a sub-clock, fix bit 3 of the CPU mode register to “1” or control the Rd (refer to Figure 112) resistance value to a certain level to stabilize an oscillation. For resistance value of Rd, consult the oscillator manufacturer. XCIN XCOUT Rf Rd CCIN CCOUT Fig. 112 Ceramic resonator circuit <Reason> When bit 3 of the CPU mode register is set to “0”, the sub-clock oscillation may stop. 2. Switch between middle/high-speed mode and lowspeed mode If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and lowspeed, set the frequency on condition that f(XIN) > 3 × f(XCIN). Quartz-Crystal Oscillator When using the quartz-crystal oscillator of high frequency, such as 16 MHz etc., it may be necessary to select a specific oscillator with the specification demanded. 3804 Group (Spec.L) Notes on Restarting Oscillation • Restarting oscillation Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = “0116 ”, Prescaler 12 = “FF 16 ”) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by writing “1” to bit 0 of MISRG (address 001016). However, by setting this bit to “1”, the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. <Reason> Oscillation will restart when an external interrupt is received. However, internal clock φ is supplied to the CPU only when Timer 1 starts to underflow. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. Notes on Using Stop Mode • Register setting Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP instruction released bit is “0”) • Clock restoration After restoration from the stop mode to the normal mode by an interrupt request, the contents of the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both main clock and sub clock were oscillating before execution of the STP instruction, the oscillation of both clocks is resumed at restoration. In the above case, when the main clock side is set as a system clock, the oscillation stabilizing time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode. At this time, note that the oscillation on the sub clock side may not be stabilized even after the lapse of the oscillation stabilizing time of the main clock side. Notes on Wait Mode • Clock restoration If the wait mode is released by a reset when XCIN is set as the system clock and XIN oscillation is stopped during execution of the WIT instruction, XCIN oscillation stops, XIN oscillations starts, and XIN is set as the system clock. In the above case, the RESET pin should be held at “L” until the oscillation is stabilized. Notes on CPU rewrite mode of flash memory version 1. Operation speed During CPU rewrite mode, set the system clock φ 4.0 MHz or less using the main clock division ratio selection bits (bits 6 and 7 of address 003B16). 2. Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during the CPU rewrite mode. 3. Interrupts inhibited against use The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data of the flash memory. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 114 of 128 4. Watchdog timer In case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. 5. Reset Reset is always valid. In case of CNVSS = “H” when reset is released, boot mode is active. So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area. Notes on flash memory version The CNVSS pin determines the flash memory mode. Connect the CNVSS pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 kΩ. resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the V S S pin of the microcomputer. Note. When the boot mode or the standard serial I/O mode is used, a switch of the input level to the CNVSS pin is required. (Note) The shortest CNVSS Approx. 5kΩ VSS (Note) The shortest Note: Shows the microcomputer’s pin. Fig. 113 Wiring for the CNVSS Notes on Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 μF–0.1 μF is recommended. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. 3804 Group (Spec.L) ELECTRICAL CHARACTERISTICS Absolute maximum ratings Table 22 Absolute maximum ratings Symbol VCC VI VI VI Parameter Power source voltages Input voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67, VREF Input voltage P32, P33 Input voltage RESET, XIN VI VO Input voltage Output voltage VO Pd Output voltage Power dissipation Topr Tstg Operating temperature Storage temperature CNVSS P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67, XOUT P32, P33 Ta=25 °C NOTE: 1. This value is 300 mW except SP package. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Conditions All voltages are based on VSS. When an input voltage is measured, output transistors are cut off. Page 115 of 128 Ratings −0.3 to 6.5 −0.3 to VCC + 0.3 Unit V V −0.3 to 5.8 −0.3 to VCC + 0.3 V V −0.3 to VCC + 0.3 −0.3 to VCC + 0.3 V V −0.3 to 5.8 V mW 1000(1) −20 to 85 −65 to 125 °C °C 3804 Group (Spec.L) Recommended operating conditions Table 23 Symbol VCC VSS VIH VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL VIL f(XIN) Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Parameter Conditions Power source voltage(1) When start oscillating(2) f(XIN) ≤ 8.4 MHz High-speed mode f(φ) = f(XIN)/2 f(XIN) ≤ 12.5 MHz f(XIN) ≤ 16.8 MHz Middle-speed mode f(XIN) ≤ 12.5 MHz f(φ) = f(XIN)/8 f(XIN) ≤ 16.8 MHz Power source voltage “H” input voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 “H” input voltage P32, P33 “H” input voltage (when I2C-BUS input level is selected) SDA, SCL “H” input voltage (when SMBUS input level is selected) SDA, SCL “H” input voltage RESET, XIN, CNVSS “H” input voltage XCIN “L” input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 “L” input voltage (when I2C-BUS input level is selected) SDA, SCL “L” input voltage (when SMBUS input level is selected) SDA, SCL “L” input voltage RESET, CNVSS “L” input voltage XIN “L” input voltage XCIN Main clock input High-speed mode f(φ) = f(XIN)/2 oscillation frequency(3) Middle-speed mode f(φ) = f(XIN)/8 Limits Min. 2.7 Typ. 5.0 Max. 5.5 2.7 4.0 4.5 2.7 4.5 5.0 5.0 5.0 5.0 5.0 0 5.5 5.5 5.5 5.5 5.5 Sub-clock input oscillation frequency(3, 4) V V V 0.8 VCC VCC V V 0.8 VCC 5.5 V 0.7 VCC 5.5 V 1.4 5.5 V 0.8 VCC VCC V 2 VCC V 0 0.2 VCC V 0 0.3 VCC V 0 0.6 V 0 0.2 VCC V 0.16 VCC V 0.4 V 2.7 ≤ VCC < 4.0 V ( 9 × V CC – 0.3 ) × 1.05 ---------------------------------------------------------3 MHz 4.0 ≤ VCC < 4.5 V ( 24 × V CC – 60 ) × 1.05 ----------------------------------------------------------3 MHz 4.5 ≤ VCC ≤ 5.5 V 2.7 ≤ VCC < 4.5 V 16.8 MHz MHz 4.5 ≤ VCC ≤ 5.5 V f(XCIN) Unit 32.768 ( 15 × V C C + 39 ) × 1.1 -------------------------------------------------------7 16.8 50 MHz kHz NOTES: 1. When using A/D converter, see A/D converter recommended operating conditions. 2. The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation. 3. When the oscillation frequency has a duty cycle of 50%. 4. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 116 of 128 3804 Group (Spec.L) Table 24 Recommended operating conditions (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter Limits Typ. Unit ΣIOH(peak) “H” total peak output current(1) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37 Max. −80 ΣIOH(peak) “H” total peak output current(1) P40-P47, P50-P57, P60-P67 −80 mA ΣIOL(peak) “L” total peak output current(1) P00-P07, P10-P17, P30-P37 80 mA ΣIOL(peak) “L” total peak output current(1) P20-P27 80 mA ΣIOL(peak) “L” total peak output current(1) P40-P47, P50-P57, P60-P67 80 mA ΣIOH(avg) “H” total average output current(1) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37 −40 mA ΣIOH(avg) “H” total average output current(1) P40-P47, P50-P57, P60-P67 −40 mA ΣIOL(avg) “L” total average output current(1) P00-P07, P10-P17, P30-P37 40 mA ΣIOL(avg) “L” total average output current(1) P20-P27 40 mA ΣIOL(avg) “L” total average output current(1) P40-P47, P50-P57, P60-P67 40 mA IOH(peak) “H” peak output current(2) −10 mA IOL(peak) “L” peak output current(2) 10 mA IOL(peak) “L” peak output current(2) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P30-P37, P40-P47, P50-P57, P60-P67 P20-P27 20 mA P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P30-P37, P40-P47, P50-P57, P60-P67 P20-P27 −5 mA 5 mA 10 mA IOH(avg) “H” average output IOL(avg) “L” average output current(3) IOL(avg) “L” average output current(3) current(3) Min. mA NOTES: 1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2. The peak output current is the peak current flowing in each port. 3. The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 117 of 128 3804 Group (Spec.L) Electrical characteristics Table 25 Electrical characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VOH VOL VOL VT+ − VT− VT+ − VT− VT+ − VT− IIH IIH IIH IIL IIL IIL IIL VRAM Parameter “H” output voltage(1) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 “L” output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 “L” output voltage P20-P27 Hysteresis CNTR0, CNTR1, CNTR2, INT0-INT4 Hysteresis RxD1, SCLK1, SIN2, SCLK2, RxD3, SCLK3 Hysteresis RESET “H” input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 “H” input current RESET, CNVSS “H” input current XIN “L” input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 “L” input current RESET, CNVSS “L” input current XIN “L” input current (at Pull-up) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 RAM hold voltage Test conditions IOH = −10 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 2.7 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 2.7 to 5.5 V IOL = 20 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 2.7 to 5.5 V Min. VCC − 2.0 Limits Typ. Unit V VCC − 1.0 2.0 V 1.0 2.0 V 0.4 0.4 V 0.5 V 0.5 V VI = VCC (Pin floating, Pull-up transistor “off”) VI = VCC VI = VCC 5.0 μA 5.0 μA μA 4.0 VI = VSS (Pin floating, Pull-up transistor “off”) VI = VSS −5.0 μA −5.0 μA −4.0 VI = VSS VI = VSS VCC = 5.0 V VI = VSS VCC = 3.0 V When clock stopped Max. μA −80 −210 −420 −30 −70 −140 1.8 VCC μA V NOTE: 1. P35 is measured when the P35/TXD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”. P45 is measured when the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 118 of 128 3804 Group (Spec.L) Table 26 Electrical characteristics (2) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, f(XCIN)=32.768 kHz (Stopped in middle-speed mode), Output transistors “off”, AD converter not operated) Symbol ICC Parameter Test conditions Power source High-speed current mode VCC = 5.0 V VCC = 3.0 V Middle-speed mode VCC = 5.0 V VCC = 3.0 V Low-speed mode VCC = 5.0 V VCC = 3.0 V In STP state (All oscillation stopped) Increment when A/D conversion is executed Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 119 of 128 f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 2.1 MHz f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 6.3 MHz f(XIN) = stopped In WIT state f(XIN) = stopped In WIT state Ta = 25 °C Ta = 85 °C f(XIN) = 16.8 MHz, VCC = 5.0 V In Middle-, high-speed mode Min. Limits Typ. 5.5 4.5 3.5 2.2 2.2 2.7 1.8 1.1 3.0 2.4 2.0 2.1 1.7 1.5 1.3 410 4.5 400 3.7 0.55 0.75 1000 Max. 8.3 6.8 5.3 3.3 3.3 4.1 2.7 1.7 4.5 3.6 3.0 3.2 2.6 2.3 2.0 630 6.8 600 5.6 3.0 Unit mA mA mA mA μA μA μA μA 3804 Group (Spec.L) A/D converter characteristics Table 27 A/D converter recommended operating conditions (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter Power source voltage (When A/D converter is used) VCC VREF AVSS VIA f(XIN) Limits Conditions 8-bit A/D mode(1) 10-bit A/D Analog convert reference voltage Analog power source voltage Analog input voltage AN0-AN15 Main clock input oscillation frequency (When A/D converter is used) Min. 2.7 Typ. 5.0 Max. 5.5 2.7 5.0 5.5 mode(2) 2.0 Unit V VCC V V V MHz 0 2.7 ≤ VCC = VREF < 4.0 V 0 0.5 VCC 4.0 ≤ VCC = VREF < 4.5 V 0.5 ( 24.6 × V CC – 62.7 ) × 1.05 --------------------------------------------------------------------3 4.5 ≤ VCC = VREF ≤ 5.5 V 0.5 16.8 ( 9 × V CC – 0.3 ) × 1.05 ---------------------------------------------------------3 NOTES: 1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”. 2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”. Table 28 A/D converter characteristics (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol − Parameter Test conditions Resolution − Absolute accuracy (excluding quantization error) tCONV 8-bit A/D mode(1) 10-bit A/D mode(2) 10 10-bit A/D Conversion time Limits Typ. Max. 8 8-bit A/D mode(1) 8-bit A/D mode(2) Min. II(AD) bit 2.7 ≤ VREF ≤ 5.5 V ±2 LSB 2.7 ≤ VREF ≤ 5.5 V ±4 LSB 50 2tc(XIN) mode(1) 61 10-bit A/D mode(2) RLADDER IVREF Unit Ladder resistor Reference power at A/D converter operated VREF = 5.0 V source input current at A/D converter stopped VREF = 5.0 V A/D port input current 12 50 35 150 kΩ μA μA μA 100 200 5.0 5.0 NOTES: 1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”. 2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”. D/A converter characteristics Table 29 D/A converter characteristics (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol − − tsu RO IVREF Parameter Resolution Absolute accuracy Min. Limits Typ. 4.0 ≤ VREF ≤ 5.5 V 2.7 ≤ VREF < 4.0 V Setting time Output resistor 2 3.5 Reference power source input current(1) Unit Max. 8 1.0 2.5 3 5 3.2 bit % μs kΩ mA NOTE: 1. Using one D/A converter, with the value in the DA conversion register of the other D/A converter being “0016”. Power source circuit timing characteristics Table 30 Power source circuit timing characteristics (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol td(P−R) Parameter Internal power source stable time at power-on Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 120 of 128 Test conditions 2.7 ≤ VCC < 5.5 V Min. Limits Typ. Max. 2 Unit ms 3804 Group (Spec.L) Timing requirements and switching characteristics Table 31 Timing requirements (1) (VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) Limits Min. td(P-R)ms + 16 Parameter Reset input “L” pulse width Main clock XIN input cycle time tWH(XIN) Main clock XIN input “H” pulse width tWL(XIN) Main clock XIN input “L” pulse width tC(XCIN) tWH(XCIN) tWL(XCIN) tC(CNTR) Sub-clock XCIN input cycle time Sub-clock XCIN input “H” pulse width Sub-clock XCIN input “L” pulse width CNTR0−CNTR2 input cycle time tWH(CNTR) CNTR0−CNTR2 input “H” pulse width tWL(CNTR) CNTR0−CNTR2 input “L” pulse width tWH(INT) INT00, INT01, INT1, INT2, INT3, INT40, INT41 input “H” pulse width tWL(INT) INT00, INT01, INT1, INT2, INT3, INT40, INT41 input “L” pulse width Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 121 of 128 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 59.5 10000/(86 VCC − 219) 2.7 ≤ VCC < 4.0 V 26 × 103/(82 VCC − 3) 25 4000/(86 VCC − 219) 10000/(82 VCC − 3) 25 4000/(86 VCC − 219) 10000/(82 VCC − 3) 20 5 5 120 160 250 48 64 115 48 64 115 48 64 115 48 64 115 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V Typ. Max. Unit XIN cycle ns ns ns μs μs μs ns ns ns ns ns 3804 Group (Spec.L) Table 32 Timing requirements (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) Symbol Parameter tC(SCLK1) tC(SCLK3) Serial I/O1, serial I/O3 clock input cycle time(1) tWH(SCLK1) tWH(SCLK3) Serial I/O1, serial I/O3 clock input “H” pulse width(1) tWL(SCLK1) tWL(SCLK3) Serial I/O1, serial I/O3 clock input “L” pulse width(1) tsu(RxD1-SCLK1) tsu(RxD3-SCLK3) Serial I/O1, serial I/O3 clock input setup time th(SCLK1-RxD1) th(SCLK3-RxD3) Serial I/O1, serial I/O3 clock input hold time tC(SCLK2) Serial I/O2 clock input cycle time tWH(SCLK2) Serial I/O2 clock input “H” pulse width tWL(SCLK2) Serial I/O2 clock input “L” pulse width tsu(SIN2-SCLK2) Serial I/O2 clock input setup time th(SCLK2-SIN2) Serial I/O2 clock input hold time 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V Min. 250 320 500 120 150 240 120 150 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 240 70 90 100 32 40 50 500 650 1000 200 260 400 200 260 400 100 130 200 100 130 150 NOTE: 1. When bit 6 of address 001A16 and bit 6 of address 003216 are “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are “0” (UART). Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 122 of 128 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns 3804 Group (Spec.L) Table 33 Switching characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) Symbol Parameter tWH(SCLK1) tWH(SCLK3) Serial I/O1, serial I/O3 clock output “H” pulse width tWL(SCLK1) tWL(SCLK3) Serial I/O1, serial I/O3 clock output “L” pulse width td(SCLK1-TxD1) td(SCLK3-TxD3) Serial I/O1, serial I/O3 output delay time(1) tV(SCLK1-TxD1) tV(SCLK3-TxD3) Serial I/O1, serial I/O3 output valid time(1) tr(SCLK1) tr(SCLK3) Serial I/O1, serial I/O3 rise time of clock output tf(SCLK1) tf(SCLK3) Serial I/O1, serial I/O3 fall time of clock output tWH(SCLK2) Serial I/O2 clock output “H” pulse width tWL(SCLK2) Serial I/O2 clock output “L” pulse width td(SCLK2-SOUT2) Serial I/O2 output delay time tV(SCLK2-SOUT2) Serial I/O2 output valid time tf(SCLK2) Serial I/O2 fall time of clock output tr(CMOS) CMOS rise time of output(2) tf(CMOS) CMOS fall time of output(2) 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V Test conditions Limits Min. tC(SCLK1)/2-30, tC(SCLK3)/2-30 tC(SCLK1)/2-35, tC(SCLK3)/2-35 tC(SCLK1)/2-40, tC(SCLK3)/2-40 tC(SCLK1)/2-30, tC(SCLK3)/2-30 tC(SCLK1)/2-35, tC(SCLK3)/2-35 tC(SCLK1)/2-40, tC(SCLK3)/2-40 Typ. ns 140 200 350 −30 −30 −30 tC(SCLK2)/2-160 tC(SCLK2)/2-200 tC(SCLK2)/2-240 tC(SCLK2)/2-160 tC(SCLK2)/2-200 tC(SCLK2)/2-240 ns ns ns ns 200 250 300 0 0 0 10 12 15 10 12 15 1. When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. 2. When the P35/TXD3 P4-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”. Page 123 of 128 ns ns 30 35 40 30 35 40 Fig.114 Unit ns NOTES: Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Max. ns ns 30 35 40 30 35 40 30 35 40 ns ns ns 3804 Group (Spec.L) Measurement output pin 1kΩ 100 pF Measurement output pin 100 pF CMOS output N-channel open-drain output Fig. 114 Circuit for measuring output switching characteristics (1) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 124 of 128 Fig. 115 Circuit for measuring output switching characteristics (2) 3804 Group (Spec.L) Single-chip mode timing diagram tC(CNTR) tWL(CNTR) tWH(CNTR) CNTR0, CNTR1 CNTR2 0.8VCC INT1, INT2, INT3 INT00, INT40 INT01, INT41 0.2VCC tWH(INT) tWL(INT) 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN 0.2VCC tC(XCIN) tWL(XCIN) tWH(XCIN) 0.8VCC XCIN 0.2VCC tC(SCLK1), tC(SCLK2), tC(SCLK3) SCLK1 SCLK2 SCLK3 tf tWL(SCLK1), tWL(SCLK2), tWL(SCLK3) tr tWH(SCLK1), tWH(SCLK2), tWH(SCLK3) 0.8VCC 0.2VCC tsu(RXD1-SCLK1), tsu(SIN2-SCLK2), tsu(RXD3-SCLK3) R XD 1 R XD 3 SIN2 th(SCLK1-RXD1), th(SCLK2-SIN2), th(SCLK3-RXD3) 0.8VCC 0.2VCC td(SCLK1-TXD1), td(SCLK2-SOUT2), td(SCLK3-TXD3) T XD 1 T XD 3 SOUT2 Fig. 116 Timing diagram (in single-chip mode) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 125 of 128 tv(SCLK1-TXD1), tv(SCLK2-SOUT2), tv(SCLK3-TXD3) 3804 Group (Spec.L) Table 34 Multi-master I2C-BUS bus line characteristics Symbol Standard clock mode Parameter Min. 4.7 4.0 4.7 tBUF tHD;STA tLOW tR Bus free time Hold time for START condition Hold time for SCL clock = ”0” Rising time of both SCL and SDA signals tHD;DAT tHIGH tF Data hold time Hold time for SCL clock = “1” Falling time of both SCL and SDA signals 0 4.0 tSU;DAT tSU;STA tSU;STO Data setup time Setup time for repeated START condition Setup time for STOP condition 250 4.7 4.0 High-speed clock mode Max. 1000 300 Unit Min. 1.3 0.6 1.3 Max. 20+0.1Cb(1) 0 0.6 300 ns 0.9 μs μs 20+0.1Cb(1) 100 0.6 0.6 300 μs μs μs ns ns μs μs NOTE: 1. Cb = total capacitance of 1 bus line SDA tHD:STA tBUF tLOW SCL P tR tF P Sr S tHD:STA tsu:STO tHD:DTA tHIGH tsu:DAT tsu:STA S : START condition Sr: RESTART condition P : STOP condition Fig. 117 Timing diagram of multi-master I2C-BUS Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 126 of 128 3804 Group (Spec.L) PACKAGE OUTLINE Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. RENESAS Code PRDP0064BA-A Previous Code 64P4B MASS[Typ.] 7.9g 33 1 32 *1 E 64 e1 JEITA Package Code P-SDIP64-17x56.4-1.78 c D A A2 *2 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. A1 L Reference Symbol SEATING PLANE *3 e bp b3 *3 e1 D E A A1 A2 bp b2 b3 c b2 e L JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV Dimension in Millimeters Min 18.75 56.2 16.85 Nom 19.05 56.4 17.0 Max 19.35 56.6 17.15 5.08 0.38 0.4 0.65 0.9 0.2 0° 1.528 2.8 3.8 0.5 0.6 0.75 1.05 1.0 1.3 0.25 0.32 15° 1.778 2.028 MASS[Typ.] 0.3g HD *1 D 48 33 49 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 32 bp 64 1 c1 Terminal cross section ZE 17 Reference Symbol c E *2 HE b1 16 Index mark ZD c A *3 A1 y e A2 F bp L x L1 Detail F Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 127 of 128 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Dimension in Millimeters Min Nom Max 9.9 10.0 10.1 9.9 10.0 10.1 1.4 11.8 12.0 12.2 11.8 12.0 12.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 8° 0° 0.5 0.08 0.08 1.25 1.25 0.35 0.5 0.65 1.0 3804 Group (Spec.L) JEITA Package Code P-LQFP64-14x14-0.80 RENESAS Code PLQP0064GA-A Previous Code 64P6U-A MASS[Typ.] 0.7g HD *1 D 33 48 49 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 32 bp c HE Reference Symbol *2 E c1 b1 Terminal cross section ZE D E A2 HD HE A A1 bp b1 c c1 64 17 A2 16 Index mark c ZD A 1 A1 F L L1 y *3 e JEITA Package Code P-TFLGA64-6x6-0.65 RENESAS Code PTLG0064JA-A e x y ZD ZE L L1 Detail F bp x Previous Code 64F0G w S B Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 8° 0° 0.8 0.20 0.10 1.0 1.0 0.3 0.5 0.7 1.0 MASS[Typ.] 0.07g b1 S AB b D Dimension in Millimeters S w S A AB e A e H G F E E D C B A y S x4 v Index mark (Laser mark) Rev.1.00 Oct 27, 2008 REJ03B0266-0100 Page 128 of 128 1 2 3 Index mark 4 5 6 7 8 Reference Dimension in Millimeters Symbol Min D E v w A e b b1 x y Nom Max 6.0 6.0 0.15 0.20 1.05 0.65 0.31 0.35 0.39 0.39 0.43 0.47 0.08 0.10 REVISION HISTORY Rev. Date 1.00 Oct. 27, 2008 3804 Group (Spec.L) Data Sheet Description Page - Summary First edition issued All trademarks and registered trademarks are the property of their respective owners. (1/1)