Cypress CY7C344 32-macrocell max epld Datasheet

44B
CY7C344
32-Macrocell MAX® EPLD
Features
tional I/O pins communicate to one logic array block. In the
CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two
expanders are used to create an input path. Even if all of the
I/O pins are driven by macrocell registers, there are still 16
“buried” registers available. All inputs, macrocells, and I/O pins
are interconnected within the LAB.
• High-performance, high-density replacement for TTL,
74HC, and custom logic
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• 0.8-micron double-metal CMOS EPROM technology
• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
package
The speed and density of the CY7C344 makes it a natural for
all types of applications. With just this one device, the designer
can implement complex state machines, registered logic, and
combinatorial “glue” logic, without using multiple chips. This
architectural flexibility allows the CY7C344 to replace multichip TTL solutions, whether they are synchronous, asynchronous, combinatorial, or all three.
Functional Description
Available in a 28-pin, 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344 represents the densest EPLD of this size. Eight dedicated inputs and 16 bidirec-
Logic Block Diagram [1]
Pin Configurations
HLCC
Top View
INPUT
15(23)
INPUT
INPUT/CLK 2(9)
27(6)
INPUT
INPUT
13(20)
28(7)
INPUT
INPUT
14(21)
MACROCELL 8
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 20
MACROCELL 22
I/O
3(10)
I/O
4(11)
MACROCELL 5
I/O
5(12)
L
O
I
MACROCELL 7
O
I/O
6(13)
B
A
MACROCELL 11
MACROCELL 3
G
I/O
9(16)
C
O
I/O
10(17)
I/O
11(18)
N
T
I/O
12(19)
I/O
17(24)
R
I/O
18(25)
O
L
I/O
19(26)
I/O
20(27)
MACROCELL 9
MACROCELL 13
L
MACROCELL 16
MACROCELL 18
I/O
I/O
I/O
VCC
GND
I/O
I/O
MACROCELL 1
MACROCELL 4
MACROCELL 6
4 3 2 1 28 27 26
MACROCELL 15
B
MACROCELL 17
U
S
MACROCELL 19
MACROCELL 21
MACROCELL 24
MACROCELL 23
MACROCELL 26
MACROCELL 25
I/O
23(2)
MACROCELL 28
MACROCELL 27
I/O
24(3)
MACROCELL 30
MACROCELL 29
I/O
25(4)
MACROCELL 32
MACROCELL 31
I/O
26(5)
64 EXPANDER PRODUCT TERM ARRAY
I/O
INPUT
INPUT
INPUT
INPUT/CLK
I/O
I/O
12 13 14 1516 1718
25
24
23
22
21
20
19
I/O
I/O
INPUT
INPUT
INPUT
INPUT
I/O
C344–2
CerDIP
Top View
INPUT
INPUT/CLK
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
C344–1
32
5
6
7
8
9
10
11
I/O
I/O
MACROCELL 2
1(8)
I/O
INPUT
VCC
GND
I/O
I/O
15(22)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT
INPUT
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
C344–3
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current
(mA)
Maximum Standby Current
(mA)
Commercial
7C344-15
7C344-20
7C344-25
15
20
25
200
200
200
Military
220
220
Industrial
220
220
220
Commercial
150
150
150
170
170
170
170
Military
Industrial
170
Note:
1. Numbers in () refer to J-leaded packages.
Cypress Semiconductor Corporation
Document #: 38-03006 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised July 18, 2000
CY7C344
Maximum Ratings
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2001V
(Above which the useful life may be impaired. For user guidelines, not tested.)
DC Output Current, per Pin ......................–25 mA to +25 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied...................................................0°C to +70°C
Maximum Junction Temperature (Under Bias)............. 150°C
DC Input Voltage[2] .........................................–3.0V to +7.0V
DC Program Voltage .................................................. +13.0V
Operating Range
Supply Voltage to Ground Potential ............... –2.0V to +7.0V
Ambient
Temperature
Range
Maximum Power Dissipation...................................1500 mW
Commercial
DC VCC or GND Current ............................................500 mA
Industrial
Military
VCC
0°C to +70°C
5V ±5%
–40°C to +85°C
5V ±10%
–55°C to +125°C (Case)
5V ±10%
Electrical Characteristics Over the Operating Range[3]
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8 mA
VIH
Input HIGH Level
VIL
Input LOW Level
IIX
Input Current
GND ≤ VIN ≤ VCC
IOZ
Output Leakage Current
VO = VCC or GND
[4, 5]
Output Short Circuit Current
VCC = Max., VOUT = 0.5V
ICC1
Power Supply
Current (Standby)
VI = VCC or GND (No Load)
Power Supply Current
VI = VCC or GND (No Load)
f = 1.0 MHz[4,6]
Max.
Unit
2.4
V
2.2
IOS
ICC2
Min.
0.45
V
VCC+0.3
V
–0.3
0.8
V
–10
+10
µA
–40
+40
µA
–30
–90
mA
Commercial
150
mA
Military/Industrial
170
mA
Commercial
200
mA
Military/Industrial
220
mA
tR
Recommended Input Rise Time
100
ns
tF
Recommended Input Fall Time
100
ns
Capacitance
Max.
Unit
CIN
Parameter
Input Capacitance
Description
VIN = 2V, f = 1.0 MHz
Test Conditions
10
pF
COUT
Output Capacitance
VOUT = 2.0V, f = 1.0 MHz
10
pF
AC Test Loads and Waveforms[7]
R1 464Ω
5V
R1 464Ω
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
250Ω
50 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
3.0V
R2
250Ω
5 pF
GND
10%
≤ 6 ns
tR
(a)
(b)
C344–4
90%
10%
90%
tf
≤ 6 ns
tF
C344–5
THÉVENIN EQUIVALENT (commercial/military)
163Ω
OUTPUT
1.75V
C344–6
Notes:
2. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.
3. Typical values are for TA = 25°C and VCC = 5V.
4. Guaranteed by design but not 100% tested.
5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid
test problems caused by tester ground degradation.
6. Measured with device programmed as a 16-bit counter.
7. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing
parameters are measured referenced to external pins of the device.
Document #: 38-03006 Rev. **
Page 2 of 15
CY7C344
Timing Delays
Timing delays within the CY7C344 may be easily determined
using Warp™, Warp Professional™, or Warp Enterprise™
software. The CY7C344 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this
data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device
reliability. The CY7C344 contains circuitry to protect device
pins from high-static voltages or electric fields; however, normal
precautions should be taken to avoid applying any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be constrained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused inputs
must always be tied to an appropriate logic level (either VCC or GND).
Each set of VCC and GND pins must be connected together directly
at the device. Power supply decoupling capacitors of at least 0.2 µF
must be connected between VCC and GND. For the most effective
decoupling, each VCC pin should be separately decoupled.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum expander delay tEXP to the overall delay.
When calculating synchronous frequencies, use tS1 if all inputs
are on the input pins. tS2 should be used if data is applied at an I/O
pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency
in the data-path mode unless 1/(tWH + tWL) is less than 1/tS2.
When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of
1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The
lowest of these frequencies is the maximum data-path frequency for
the synchronous configuration.
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on dedicated input pins. If any data is applied to
an I/O pin, tAS2 must be used as the required set-up time. If (tAS2 +
tAH) is greater than tACO1, 1/(tAS2 + tAH) becomes the limiting frequency in the data-path mode unless 1/(tAWH + tAWL) is less than
1/(tAS2 + tAH).
When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which
of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency.
The lowest of these frequencies is the maximum data-path frequency
for the asynchronous configuration.
The parameter tOH indicates the system compatibility of this device
when driving other synchronous logic with positive input hold times,
which is controlled by the same synchronous clock. If tOH is greater
than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case environmental
and supply voltage conditions.
The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C344. In general, if tAOH
is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchronous), then the devices are
guaranteed to function properly under worst-case environmental and
supply voltage conditions, provided the clock signal source is the
same. This also applies if expander logic is used in the clock signal
path of the driving device, but not for the driven device. This is due to
the expander logic in the second device’s clock signal path adding an
additional delay (tEXP), causing the output data from the preceding
device to change prior to the arrival of the clock signal at the following
device’s register.
EXPANDER
DELAY
t EXP
REGISTER
LOGIC ARRAY
CONTROLDELAY tCLR
tLAC
tPRE
INPUT
INPUT
DELAY
tIN
LOGIC ARRAY tRSU
DELAY
tRH
tLAD
OUTPUT
DELAY
OUTPUT
tOD
tXZ
tZX
tRD
tCOMB
tLATCH
SYSTEM CLOCK DELAYtICS
I/O
I/O
I/O DELAY
tIO
CLOCK
DELAY
tIC
FEEDBACK
DELAY
tFD
C344–7
Figure 1. CY7C344 Timing Model.
Document #: 38-03006 Rev. **
Page 3 of 15
CY7C344
External Synchronous Switching Characteristics[7] Over Operating Range
7C344-15
Parameter
tPD1
tPD2
Description
Min.
Dedicated Input to Combinatorial Output Delay
[8]
I/O Input to Combinatorial Output Delay[9]
Max.
7C344-20
Min.
Max.
7C344-25
Min.
Max.
Unit
ns
Com’l/Ind
15
20
25
Mil
15
20
25
Com’l/Ind
15
20
25
Mil
15
20
25
tPD3
Dedicated Input to Combinatorial Output Delay
with Expander Delay[10]
Com’l/Ind
30
30
40
Mil
30
30
40
tPD4
I/O Input to Combinatorial Output Delay with
Expander Delay[4, 11]
Com’l/Ind
30
30
40
Mil
30
30
40
tEA
tER
[4]
Input to Output Enable Delay
Input to Output Disable Delay[4]
Com’l/Ind
20
20
25
Mil
20
20
25
Com’l/Ind
20
20
25
Mil
20
20
25
Com’l/Ind
10
12
15
tCO1
Synchronous Clock Input to Output Delay
Mil
10
12
15
tCO2
Synchronous Clock to Local Feedback to Combinatorial Output[4, 12]
Com’l/Ind
20
22
29
Mil
20
22
29
Dedicated Input or Feedback Set-Up Time to
Synchronous Clock Input
Com’l/Ind
10
12
15
Mil
10
12
15
tS
tH
Input Hold Time from Synchronous Clock Input[7] Com’l/Ind
tWH
Synchronous Clock Input HIGH Time[4]
tWL
Synchronous Clock Input LOW Time[4]
tRW
tRR
Asynchronous Clear Width
[4]
Asynchronous Clear Recovery Time[4]
0
0
0
Mil
0
0
0
Com’l/Ind
6
7
8
Mil
6
7
8
Com’l/Ind
6
7
8
Mil
6
7
8
Com’l/Ind
20
20
25
Mil
20
20
25
Com’l/Ind
20
20
25
Mil
20
20
25
tRO
Asynchronous Clear to Registered Output
Delay[4]
Com’l/Ind
tPW
Asynchronous Preset Width[4]
Com’l /Ind
20
20
25
Mil
20
20
25
Com’l /Ind
20
20
25
Mil
20
20
25
tPR
tPO
Asynchronous Preset Recovery Time
[4]
Asynchronous Preset to Registered Output
Delay[4]
15
Mil
15
ns
25
ns
ns
25
20
25
4
4
7
4
ns
ns
20
Mil
ns
ns
15
External Synchronous Clock Period (1/fMAX3)[4]
ns
ns
15
tP
ns
ns
Mil
Synchronous Clock to Local Feedback Input[4, 13] Com’l /Ind
ns
ns
25
20
ns
ns
Com’l /Ind
tCF
Document #: 38-03006 Rev. **
20
ns
4
ns
ns
7
Com’l/Ind
13
14
16
Mil
13
14
16
ns
Page 4 of 15
CY7C344
External Synchronous Switching Characteristics[7] Over Operating Range (continued)
7C344-15
Parameter
Description
Min.
[4, 14]
Max.
7C344-20
Min.
Max.
7C344-25
Min.
fMAX1
External Maximum Frequency(1/(tCO1 + tS))
fMAX2
Maximum Frequency with Internal Only
Feedback (1/(tCF + tS))[4, 15]
Data Path Maximum Frequency, least of
1/(tWL + tWH), 1/(tS + tH), or (1/tCO1)[4, 16]
Com’l/Ind
83.3
71.4
62.5
Mil
83.3
71.4
62.5
Maximum Register Toggle Frequency
1/(tWL + tWH)[4, 17]
Com’l/Ind
83.3
71.4
62.5
Mil
83.3
71.4
62.5
Output Data Stable Time from Synchronous
Clock Input[4, 18]
Com’l/Ind
3
3
3
Mil
3
3
3
fMAX3
fMAX4
tOH
Com’l/Ind
50.0
41.6
33.3
Mil
50.0
41.6
33.3
Com’l/Ind
71.4
62.5
45.4
Mil
71.4
62.5
45.4
Max.
Unit
MHz
MHz
MHz
MHz
ns
Notes:
8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander
terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used
to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output
for which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the
register is synchronously clocked. This parameter is tested periodically by sampling production material.
13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, tS, is the minimum
internal period for an internal state machine configuration. This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate.
15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states
must also control external points, this frequency can still be observed as long as it is less than 1/tCO1. This specification assumes no expander logic is used. This
parameter is tested periodically by sampling production material.
16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that
no expander logic is used.
17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a
clock signal applied to either a dedicated input pin or an I/O pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
Document #: 38-03006 Rev. **
Page 5 of 15
CY7C344
External Asynchronous Switching Characteristics Over Operating Range[7]
7C344-15
Parameter
tACO1
tACO2
tAS
tAH
tAWH
tAWL
tACF
tAP
fMAXA1
fMAXA2
fMAXA3
fMAXA4
tAOH
Description
7C344-20
7C344-25
Min. Max. Min. Max. Min. Max.
Asynchronous Clock Input to Output Delay
Com’l/Ind
15
20
25
Mil
15
20
25
Asynchronous Clock Input to Local Feedback to
Combinatorial Output[19]
Com’l/Ind
30
30
37
Mil
30
30
37
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input
Com’l/Ind
7
9
12
Mil
7
9
12
Input Hold Time from Asynchronous Clock Input
Com’l/Ind
7
9
12
Mil
7
9
12
Com’l/Ind
6
7
9
Mil
6
7
9
Com’l/Ind
7
9
11
Mil
7
9
11
[4, 20]
Asynchronous Clock Input HIGH Time
Asynchronous Clock Input LOW Time[4]
[4, 21]
Asynchronous Clock to Local Feedback Input
External Asynchronous Clock Period (1/fMAX4)[4]
ns
ns
18
18
21
18
18
21
16
20
Mil
13
16
20
External Maximum Frequency in Asynchronous
Mode 1/(tACO1 + tAS)[4, 22]
Com’l/Ind
45.4
34.4
27
Mil
45.4
34.4
27
Maximum Internal Asynchronous Frequency
1/(tACF + tAS) or 1/(tAWH + tAWL)[4, 23]
Com’l/Ind
40
37
30.3
Mil
40
37
30.3
Data Path Maximum Frequency in Asynchronous
Mode[4, 24]
Com’l/Ind
66.6
50
40
Mil
66.6
50
40
Maximum Asynchronous Register Toggle
Frequency 1/(tAWH + tAWL)[4, 25]
Com’l/Ind
76.9
62.5
50
Mil
76.9
62.5
50
Output Data Stable Time from Asynchronous Clock
Input[4, 26]
Com’l/Ind
15
15
15
Mil
15
15
15
ns
ns
Mil
13
ns
ns
Com’l/Ind
Com’l/Ind
Unit
ns
ns
MHz
MHz
MHz
MHz
ns
Notes:
19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the registered output signal to a combinatorial
output for which the registered output signal is used as an input. Assumes no expanders are used in logic of combinatorial output or the asynchronous clock
input. This parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge-triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped.
If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL.
21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronously clocked register. This delay plus the
asynchronous register set-up time, tAS, is the minimum internal period for an asynchronously clocked state machine configuration. This delay assumes no expander logic
in the asynchronous clock path. This parameter is tested periodically by sampling production material.
22. This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
operate. It is assumed that no expander logic is employed in the clock signal path or data path.
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.
If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. This specification
assumes no expander logic is utilized. This parameter is tested periodically by sampling production material.
24. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked
mode. This frequency is least of 1/(tAWH + tAWL), 1/(tAS + tAH), or 1/tACO1. It also indicates the maximum frequency at which the device may operate in the asynchronously
clocked data-path mode. Assumes no expander logic is used.
25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked
mode by a clock signal applied to an external dedicated input or an I/O pin.
26. This parameter indicates the minimum time that the previous register output data is maintained on the output pin after an asynchronous register clock input
to an external dedicated input or I/O pin.
Document #: 38-03006 Rev. **
Page 6 of 15
CY7C344
Typical Internal Switching Characteristics Over Operating Range[7]
7C344-15
Parameter
Description
tIN
Dedicated Input Pad and Buffer Delay
tIO
I/O Input Pad and Buffer Delay
tEXP
Expander Array Delay
tLAD
Logic Array Data Delay
tLAC
tOD
tZX
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay[27]
Min.
Max.
7C344-20
Min.
Max.
7C344-25
Min.
Max.
Unit
ns
Com’l/Ind
4
5
7
Mil
4
5
7
Com’l/Ind
4
5
7
Mil
4
5
7
Com’l/Ind
8
10
15
Mil
8
10
15
Com’l/Ind
7
9
10
Mil
7
9
10
Com’l/Ind
5
7
7
Mil
5
7
7
Com’l/Ind
4
5
5
Mil
4
5
5
Com’l/Ind
7
8
11
Mil
7
8
11
7
8
11
tXZ
Output Buffer Disable Delay
Com’l/Ind
tRSU
Register Set-Up Time Relative to Clock Signal
at Register
Com’l/Ind
Mil
5
5
8
tRH
Register Hold Time Relative to Clock Signal at
Register
Com’l/Ind
7
9
12
Mil
7
tLATCH
Flow-Through Latch Delay
Com’l/Ind
1
1
3
Mil
1
1
3
Mil
tRD
tCOMB
tCH
Register Delay
Transparent Mode Delay[28]
Clock HIGH Time
7
5
8
5
Com’l/Ind
1
1
1
Mil
1
1
1
Com’l/Ind
1
1
3
Mil
1
1
3
Com’l/Ind
6
7
8
Mil
6
7
8
Com’l/Ind
6
7
8
Mil
6
Com’l/Ind
7
8
10
Mil
7
8
10
tICS
Synchronous Clock Delay
Com’l/Ind
1
2
3
Mil
1
2
3
tFD
Feedback Delay
Com’l/Ind
1
1
1
Mil
1
1
1
tPCW
Asynchronous Preset and Clear Pulse Width
Document #: 38-03006 Rev. **
ns
ns
7
ns
ns
ns
ns
Asynchronous Clock Logic Delay
Asynchronous Register Clear Time
ns
12
tIC
tCLR
ns
ns
Clock LOW Time
Asynchronous Register Preset Time
ns
ns
tCL
tPRE
ns
11
8
9
ns
ns
8
Com’l/Ind
5
6
9
Mil
5
6
9
Com’l/Ind
5
6
9
Mil
5
6
9
Com’l/Ind
5
5
7
Mil
5
5
7
ns
ns
ns
ns
ns
ns
Page 7 of 15
CY7C344
Typical Internal Switching Characteristics Over Operating Range[7] (continued)
7C344-15
Parameter
tPCR
Min.
Max.
7C344-25
Description
Min.
Asynchronous Preset and Clear Recovery Time Com’l/Ind
5
5
7
5
5
7
Mil
Max.
7C344-20
Min.
Max.
Unit
ns
Notes:
27. Sample tested only for an output change of 500 mV.
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
Document #: 38-03006 Rev. **
Page 8 of 15
CY7C344
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
tPD1/tPD2
COMBINATORIAL
OUTPUT
tER
COMBINATORIAL OR
REGISTERED OUTPUT
HIGH-IMPEDANCE
THREE-STATE
tEA
HIGH-IMPEDANCE
THREE-STATE
VALID OUTPUT
C344–8
External Synchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
tS
tH
tWH
tWL
SYNCHRONOUS
CLOCK
tCO1
ASYNCHRONOUS
CLEAR/PRESET
tRW/tPW
tRR/tPR
tOH
tRO/tPO
REGISTERED
OUTPUTS
tCO2
COMBINATORIAL OUTPUT FROM
REGISTERED FEEDBACK [12]
C344–9
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
tAS
ASYNCHRONOUS
CLOCK INPUT
ASYNCHRONOUS
CLEAR/PRESET
tAH
tACO1
tAWH
tRW/tPW
tAWL
tRR/tPR
tAOH
tRO/tPO
ASYNCHRONOUS REGISTERED
OUTPUTS
tACO2
COMBINATORIAL OUTPUT FROM
ASYNCH. REGISTERED
FEEDBACK [19]
C344–10
Document #: 38-03006 Rev. **
Page 9 of 15
CY7C344
Switching Waveforms (continued)
Internal Combinatorial
tIN
INPUT PIN
tPIA
tIO
I/O PIN
tEXP
EXPANDER
ARRAY DELAY
tLAC, tLAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
C344–11
Internal Asynchronous
tAWH
tIOtR
tAWL
tF
CLOCK PIN
tIN
CLOCK INTO
LOGIC ARRAY
tIC
CLOCK FROM
LOGIC ARRAY
tRSU
tRH
DATA FROM
LOGIC ARRAY
tRD,tLATCH
tFD
tCLR,tPRE
tFD
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
tPIA
REGISTER OUTPUT
TO ANOTHER LAB
C344–12
Internal Synchronous (Input Path)
tCH
tCL
SYSTEM CLOCK PIN
tIN
tICS
tRSU
tRH
SYSTEM CLOCK
AT REGISTER
DATA FROM
LOGIC ARRAY
C344–13
Document #: 38-03006 Rev. **
Page 10 of 15
CY7C344
Switching Waveforms (continued)
Internal Synchronous (Output Path)
CLOCK FROM
LOGIC ARRAY
tRD
tOD
DATA FROM
LOGIC ARRAY
tXZ
tZX
HIGH Z
OUTPUT PIN
C344–14
Ordering Information
Speed
(ns)
15
20
25
Ordering Code
Package
Name
Operating
Range
Package Type
CY7C344-15HC/HI
H64
28-Lead Windowed Leaded Chip Carrier
CY7C344-15JC/JI
J64
28-Lead Plastic Leaded Chip Carrier
CY7C344-15PC/PI
P21
28-Lead (300-Mil) Molded DIP
CY7C344-15WC/WI
W22
28-Lead Windowed CerDIP
CY7C344-20HC/HI
H64
28-Lead Windowed Leaded Chip Carrier
CY7C344-20JC/JI
J64
28-Lead Plastic Leaded Chip Carrier
CY7C344-20PC/PI
P21
28-Lead (300-Mil) Molded DIP
CY7C344-20WC/WI
W22
28-Lead Windowed CerDIP
CY7C344-20HMB
H64
28-Lead Windowed Leaded Chip Carrier
CY7C344-20WMB
W22
28-Lead Windowed CerDIP
CY7C344-25HC/HI
H64
28-Lead Windowed Leaded Chip Carrier
CY7C344-25JC/JI
J64
28-Lead Plastic Leaded Chip Carrier
CY7C344-25PC/PI
P21
28-Lead (300-Mil) Molded DIP
CY7C344-25WC/WI
W22
28-Lead Windowed CerDIP
CY7C344-25HMB
H64
28-Lead Windowed Leaded Chip Carrier
CY7C344-25WMB
W22
28-Lead Windowed CerDIP
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
Commercial/Industrial
Commercial/Industrial
Military
Commercial/Industrial
Military
Switching Characteristics
Parameter
Subgroups
tPD1
7, 8, 9, 10, 11
tPD2
7, 8, 9, 10, 11
tPD3
7, 8, 9, 10, 11
VOH
1, 2, 3
tCO1
7, 8, 9, 10, 11
VOL
1, 2, 3
tS
7, 8, 9, 10, 11
VIH
1, 2, 3
tH
7, 8, 9, 10, 11
VIL
1, 2, 3
tACO1
7, 8, 9, 10, 11
IIX
1, 2, 3
tACO1
7, 8, 9, 10, 11
IOZ
1, 2, 3
tAS
7, 8, 9, 10, 11
ICC1
1, 2, 3
tAH
7, 8, 9, 10, 11
MAX is a registered trademark of Altera Corporation.
Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor.
Document #: 38-03006 Rev. **
Page 11 of 15
CY7C344
Package Diagrams
28-Pin Windowed Leaded Chip Carrier H64
51-80077
Document #: 38-03006 Rev. **
Page 12 of 15
CY7C344
Package Diagrams (continued)
28-Lead Plastic Leaded Chip Carrier J64
51-85001-A
28-Lead (300-Mil) Molded DIP P21
51-85014-B
Document #: 38-03006 Rev. **
Page 13 of 15
CY7C344
Package Diagrams (continued)
28-Lead (300-Mil) Windowed CerDIP W22
MIL-STD-1835 D-15 Config. A
51-80087
Document #: 38-03006 Rev. **
Page 14 of 15
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C344
Document Title: CY7C344 32-Macrocell MAX® EPLD
Document Number: 38-03006
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
**
106271
04/19/01
SZV
Change from Spec number: 38-00127 to 38-03006
Document #: 38-03006 Rev. **
Page 15 of 15