ON CS5111YDWFR24 Switching regulator Datasheet

CS5111
1.4 A Switching Regulator
with 5.0 V, 100 mA Linear
Regulator with Watchdog,
RESET and ENABLE
The CS5111 is a dual output power supply integrated circuit. It
contains a 5.0 V ± 2%, 100 mA linear regulator, a watchdog timer, a
linear output voltage monitor to provide a Power On Reset (POR) and
a 1.4 A current mode PWM switching regulator.
The 5.0 V linear regulator is comprised of an error amplifier, reference,
and supervisory functions. It has low internal supply current consumption
and provides 1.2 V (typical) dropout voltage at maximum load current.
The watchdog timer circuitry monitors an input signal (WDI) from
the microprocessor. It responds to the falling edge of this watchdog
signal. If a correct watchdog signal is not received within the
externally programmable time, a reset signal is issued.
The externally programmable active reset circuit operates correctly
for an output voltage (VLIN) as low as 1.0 V. During power up, or if the
output voltage shifts below the regulation limit, RESET toggles low
and remains low for the duration of the delay after proper output
voltage regulation is restored. Additionally a reset pulse is issued if the
correct watchdog is not received within the programmed time. Reset
pulses continue until the correct watchdog signal is received. The reset
pulse width and frequency, as well as the Power On Reset delay, are set
by one external RC network.
The current mode PWM switching regulator is comprised of an
error amplifier with selectable feedback inputs, a current sense
amplifier, an adjustable oscillator, and a 1.4 A output power switch
with anti–saturation control. The switching regulator can be
configured in a variety of topologies.
The CS5111 is load dump capable and has protection circuitry
which includes overvoltage shutdown, current limit on the linear and
switcher outputs, and an overtemperature limiter.
Features
• Linear Regulator
– 5.0 V ± 2% @ 100 mA
• Switching Regulator
– 1.4 A Peak Internal Switch
– 120 kHz Maximum Switching Frequency
– 5.0 V to 26 V Operating Supply Range
• Smart Functions
– Watchdog
– RESET
– ENABLE
• Protection
– Overvoltage
– Overtemperature
– Current Limit
• 54 V Peak Transient Capability
• Internally Fused Leads in SO–24L Package
 Semiconductor Components Industries, LLC, 2001
January, 2001 – Rev. 9
1
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SO–24L
DWF SUFFIX
CASE 751E
24
1
MARKING
DIAGRAM
24
CS5111
AWLYYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
VIN
NC
NC
VSW
GND
GND
GND
GND
VFB1
VFB2
SELECT
COMP
1
24
ENABLE
VREG
VLIN
IBIAS
GND
GND
GND
GND
RESET
CDelay
WDI
COSC
ORDERING INFORMATION
Device
Package
Shipping
CS5111YDWF24
SO–24L
31 Units/Rail
CS5111YDWFR24
SO–24L
1000 Tape & Reel
Publication Order Number:
CS5111/D
CS5111
VIN
Switcher Error Amplifier
VFB1
VFB2
SELECT
Multiplexer
–
+
VSW
COMP
Base
Drive
Logic
COMP
Current Sense Amplifier
IBIAS
1.4 A
+
–
GND
Oscillator
COSC
+
–
Switcher Shutdown
ENABLE
VREG
Overvoltage
+
–
Linear
Error Amplifier
VLIN
Current
Limit
Bandgap
Reference
Over
Temperature
1.25 V
RESET
RESET &
Watchdog Timer
CDELAY
WDI
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Logic Inputs/Outputs (ENABLE, SELECT, WDI, RESET)
VLIN
VIN, VREG:
Value
Unit
–0.3 to VLIN
V
–0.3 to 10
DC Input Voltage
Peak Transient Voltage (40 V Load Dump @ 14 V VIN)
–0.3 to 26
–0.3 to 54
V
V
54
V
–0.3 to VLIM
V
Power Dissipation
Internally Limited
–
VLIN Output Current
Internally Limited
–
VSW Output Current
Internally Limited
–
RESET Output Sink Current
5.0
mA
ESD Susceptibility (Human Body Model)
2.0
kV
ESD Susceptibility (Machine Model)
200
V
–65 to 150
°C
230 peak
°C
VSW Peak Transient Voltage
COSC, CDelay, COMP, VFB1, VFB2
Storage Temperature
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1.)
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
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CS5111
ELECTRICAL CHARACTERISTICS (5.0 V ≤ VIN ≤ 26 V and –40°C ≤ TJ ≤ 150°C, COUT = 100 µF (ESR ≤ 8.0 Ω),
CDelay = 0.1 µF, RBIAS = 64.9 kΩ, COSC = 390 pF, CCOMP = 0.1 µF; unless otherwise specified.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
General
IIN Off Current
6.6 V ≤ VIN ≤ 26 V, ISW = 0 A
–
–
2.0
mA
IIN On Current
6.6 V ≤ VIN ≤ 26 V, ISW = 1.4 A
–
30
70
mA
IREG Current
ILIN = 100 mA, 6.6 V ≤ VIN ≤ 26 V
–
–
6.0
mA
Thermal Limit
Guaranteed by Design
160
–
210
°C
VLIN Output Voltage
6.6 V ≤ VREG ≤ 26 V,
1.0 mA ≤ ILIN ≤ 100 mA
4.9
5.0
5.1
V
Dropout Voltage
(VREG – VLIN) @ ILIN = 100 mA
–
1.2
1.5
V
30
34
38
V
5.0 V Regulator Section
Overvoltage Shutdown
–
Line Regulation
6.6 V ≤ VREG ≤ 26 V, ILIN = 5.0 mA
–
5.0
25
mV
Load Regulation
VREG = 19 V, 1.0 mA ≤ ILIN ≤ 100 mA
–
5.0
25
mV
Current Limit
6.6 V ≤ VREG ≤ 26 V
120
–
–
mA
DC Ripple Rejection
14 V ≤ VREG ≤ 24 V
60
75
–
dB
RESET Section
Low Threshold (VRTL)
VLIN Decreasing
4.05
4.25
4.45
V
High Threshold (VRTH)
VLIN Increasing
4.2
4.45
4.7
V
Hysteresis
VRTH – VRTL
140
190
240
mV
Active High
VLIN > VRTH, IRESET = –25 µA
VLIN – 0.5
–
–
V
Active Low
VLIN = 1.0 V, 10 kΩ Pull–Up from
RESET to VLIN
VLIN = 4.0 V, IRESET = 1.0 mA
–
–
0.4
V
–
–
0.7
V
Delay
Invalid WDI
6.25
8.78
11
ms
Power On Delay
VLIN Crossing VRTH
6.25
–
–
ms
–
–
2.0
V
0.8
–
–
V
Watchdog Input (WDI)
VIH
Peak WDI Needed to Activate RESET
VIL
–
Hysteresis
Note 2.
25
50
–
mV
Pull–Up Resistor
WDI = 0 V
20
50
100
kΩ
Low Threshold
–
6.25
8.78
11
ms
Floating Input Voltage
–
3.5
–
–
V
WDI Pulse Width
–
–
–
5.0
µs
–
–
–
5.0
V
Switcher Section
Minimum Operating Input
Voltage
Switching Frequency
Refer to Figure 5
80
95
110
kHz
Switch Saturation Voltage
ISW = 1.4 A
0.7
1.1
1.6
V
1.4
–
2.5
A
120
–
–
kHz
Output Current Limit
Max Switching Frequency
–
VSW = 7.5 V with 50 Ω Load, Refer to
Figure 5
2. Guaranteed by design, not 100% tested in productions.
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CS5111
ELECTRICAL CHARACTERISTICS (continued) (5.0 V ≤ VIN ≤ 26 V and –40°C ≤ TJ ≤ 150°C, COUT = 100 µF (ESR ≤ 8.0 Ω),
CDelay = 0.1 µF, RBIAS = 64.9 kΩ, COSC = 390 pF, CCOMP = 0.1 µF; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
VFB1 Regulation Voltage
–
1.206
1.25
1.294
V
VFB2 Regulation Voltage
–
1.206
1.25
1.294
V
Switcher Section (continued)
VFB1, VFB2 Input Current
VFB1 = VFB2 = 5.0 V
–
–
1.0
µA
Oscillator Charge Current
COSC = 0 V
35
40
45
µA
Oscillator Discharge Current
COSC = V40
270
320
370
µA
CDelay Charge Current
CDelay = 0 V
35
40
45
µA
Switcher Max Duty Cycle
VSW = 5.0 V with 50 Ω Load,
VFB1 = VFB2 = 1.0 V
72
85
95
%
Current Sense Amp Gain
ISW = 2.3 A
–
7.0
–
V/V
Error Amp DC Gain
–
–
67
–
dB
Error Amp Transconductance
–
–
2700
–
µA/V
VIL
–
0.8
1.24
–
V
VIH
–
–
1.3
2.0
V
Hysteresis
–
–
60
–
mV
Input Impedance
–
10
20
40
kΩ
ENABLE Input
Select Input
VIL (Selects VFB1)
4.9 ≤ VLIN ≤ 5.1
0.8
1.25
–
V
VIH (Selects VFB2)
4.9 ≤ VLIN ≤ 5.1
–
1.25
2.0
V
SELECT Pull–Up
SELECT = 0 V
10
24
50
kΩ
3.5
4.5
–
V
Floating Input Voltage
–
PIN FUNCTION DESCRIPTION
PACKAGE PIN #
SO–24L
PIN SYMBOL
1
VIN
Supply voltage.
2, 3
NC
No connection.
4
VSW
Collector of NPN power switch for switching regulator section.
5, 6, 7, 8, 17, 18, 19, 20
GND
Connected to the heat removing leads.
9
VFB1
Feedback input voltage 1 (referenced to 1.25 V).
10
VFB2
Feedback input voltage 2 (referenced to 1.25 V).
11
SELECT
12
COMP
Output of the transconductance error amplifier.
13
COSC
A capacitor connected to GND sets the switching frequency. Refer to Figure 5.
14
WDI
Watchdog input. Active on falling edge.
15
CDelay
A capacitor connected to GND sets the Power On Reset and Watchdog time.
16
RESET
RESET output. Active low if VLIN is below the regulation limit. If watchdog timeout
is reached, a reset pulse train is issued.
FUNCTION
Logic level input that selects either VFB1 or VFB2. An open selects VFB2. Connect
to GND to select VFB1.
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CS5111
PIN FUNCTION DESCRIPTION (continued)
PACKAGE PIN #
SO–24L
PIN SYMBOL
21
IBIAS
A resistor connected to GND sets internal bias currents as well as the COSC and
CDelay charge currents.
22
VLIN
Regulated 5.0 V output from the linear regulator section.
23
VREG
Input voltage to the linear regulator and the internal supply circuitry.
24
ENABLE
FUNCTION
Logic level input to shut down the switching regulator.
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
IIN (mA)
IREG – ILIN (mA)
4.5
4.0
–20
–30
3.5
0
20
60
40
80
–40
100
0
0.5
1.5
1.0
ILIN (mA)
2.0
ISW (A)
Figure 2. 5.0 V Regulator Bias Current vs. Load Current
Figure 3. Supply Current vs. Switch Current
1.4
180
160
1.2
140
Frequency (kHz)
VSW (V)
1.0
0.8
0.6
0.4
120
100
80
60
40
0.2
0
20
0
0.5
1.0
1.5
0
2.0
0
ISW (A)
500
1000
1500
2000
2500
COSC (pF)
Figure 4. Switch Saturation Voltage
Figure 5. Oscillator Frequency (kHz) vs.
COSC (pF), Assuming RBIAS = 64.9 k
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3000
CS5111
CIRCUIT DESCRIPTION
VREG
Overvoltage
+
–
R1
Linear
Error
Amplifier
Q2
Q3
Q1
VLIN
COUT = 100 µF
ESR < 8.0 Ω
R2
Current
Limit
R3
IBIAS
Bandgap
Reference
RBIAS
64.9 kΩ
1.25 V
Over
Temperature
R4
R5
CDelay
RESET &
Watchdog Timer
RESET
WDI
Figure 6. Block Diagram of 5.0 V Linear Regulator Portion of the CS5111
5.0 V LINEAR REGULATOR
edge of this watchdog signal which it expects to see within
an externally programmable time (see Figure 7).
The watchdog time is given by:
The 5.0 V linear regulator consists of an error amplifier,
bandgap voltage reference, and a composite pass transistor.
The 5.0 V linear regulator circuitry is shown in Figure 6.
When an unregulated voltage greater than 6.6 V is applied
to the VREG input, a 5.0 V regulated DC voltage will be
present at VLIN. For proper operation of the 5.0 V linear
regulator, the IBIAS lead must have a 64.9 kΩ pull down
resistor to ground. A 100 µF or larger capacitor with an ESR
< 8.0 Ω must be connected between VLIN and ground. To
operate the 5.0 V linear regulator as an independent
regulator (i.e. separate from the switching supply), the input
voltage must be tied to the VREG lead.
As the voltage at the VREG input is increased, Q1 is turned
on. Q1 provides base drive for Q2 which in turn provides
base current for Q3. As Q3 is turned on, the output voltage,
VLIN, begins to rise as Q3’s output current charges the output
capacitor, COUT. Once VLIN rises to a certain level, the error
amplifier becomes biased and provides the appropriate
amount of base current to Q1. The error amplifier monitors
the scaled output voltage via an internal voltage divider, R2
through R5, and compares it to the bandgap voltage
reference. The error amplifier output or error signal is an
output current equal to the error amplifier’s input
differential voltage times the transconductance of the
amplifier. Therefore, the error amplifier varies the base
current to Q1, which provides bias to Q2 and Q3, based on the
difference between the reference voltage and the scaled
VLIN output voltage.
tWDI 1.353 CDelayRBIAS
Using CDelay = 0.1 µF and RBIAS = 64.9 kΩ gives a time
ranging from 6.25 ms to 11 ms assuming ideal components.
Based on this, the software must be written so that the
watchdog arrives at least every 6.25 ms. In practice, the
tolerance of CDelay and RBIAS must be taken into account
when calculating the minimum watchdog time (tWDI).
VREG
RESET
WDI
VLIN
tPOR
Normal Operation
Figure 7. Timing Diagram for Normal
Regulator Operation
If a correct watchdog signal is not received within the
specified time a reset pulse train is issued until the correct
watchdog signal is received. The nominal reset signal in this
case is a 5 volt square wave with a 50% duty cycle as shown
in Figure 8.
CONTROL FUNCTIONS
The watchdog timer circuitry monitors an input signal
(WDI) from the microprocessor. It responds to the falling
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CS5111
The POR delay (tPOR) is given by:
50% Duty
Cycle
VREG
tPOR 1.353 CDelayRBIAS
RESET
CURRENT MODE PWM SWITCHING CIRCUITRY
The current mode PWM switching voltage regulator
contains an error amplifier with selectable feedback inputs,
a current sense amplifier, an adjustable oscillator and a 1.4 A
output power switch with antisaturation control. The
switching regulator and external components, connected in
a boost configuration, are shown in Figure 11.
The switching regulator begins operation when VREG and
VIN are raised above 5 volts. VREG is required since the
switching supply’s control circuitry is powered through
VLIN. VIN supplies the base drive to the switcher output
transistor.
The output transistor turns on when the oscillator starts to
charge the capacitor on COSC. The output current will
develop a voltage drop across the internal sense resistor
(RS). This voltage drop produces a proportional voltage at
the output of the current sense amplifier, which is compared
to the output of the error amplifier. The error amplifier
generates an output voltage which is proportional to the
difference between the scaled down output boost voltage
(VFB1 or VFB2) and the internal bandgap voltage reference.
Once the current sense amplifier output exceeds the error
amplifier’s output voltage, the output transistor is turned off.
The energy stored in the inductor during the output
transistor on time is transferred to the load when the output
transistor is turned off. The output transistor is turned back
on at the next rising edge of the oscillator. On a cycle by
cycle basis, the current mode controller in a discontinuous
mode of operation charges the inductor to the appropriate
amount of energy, based on the energy demand of the load.
Figure 12 shows the typical current and voltage waveforms
for a boost supply operating in the discontinuous mode.
WDI
VLIN
tPOR
A
B
A: Watchdog waiting for low–going transition on WDI
B: RESET stays low for tWDI time
Figure 8. Timing Diagram When WDI Fails to
Appear Within the Preset Time Interval, tWDI
The RESET signal frequency is given by:
1
fRESET 2(tWDI)
The Power On Reset (POR) and low voltage RESET use
the same circuitry and issue a reset when the linear output
voltage is below the regulation limit. After VLIN rises above
the minimum specified value, RESET remains low for a
fixed period tPOR as shown in Figures 9 and 10.
VLIN
4.45 V
4.25 V
RESET
VR(LO)
VR(PEAK)
Notes:
tPOR
1. Refer to Figure 5 to determine oscillator frequency.
2. The switching regulator can be disabled by providing
a logic high at the ENABLE input.
3. The boost output voltage can be controlled
dynamically by the feedback select input. If select is
open, VFB2 is selected. If select is low, then VFB1 is
selected.
Figure 9. The Power On Reset Time Interval (tPOR)
Begins When VLIN Rises Above 4.45 V (Typical)
VLIN
5.0 V
4.25 V
RESET
5.0 V
tPOR
Figure 10. RESET Signal Is Issued Whenever
VLIN Falls Below 4.25 V (Typical)
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CS5111
VIN
VLIN
VOUT
VSW
COMP
IBIAS
RBIAS
64.9 kΩ
Base Drive
Logic
Current Sense Amplifier
COSC
Oscillator
+
–
RS
VREG
Switcher Shutdown
1.25 V
COMP
Switcher
Error
Amplifier
GND
+
–
ENABLE
Overvoltage
COUT
1.4 A
Bandgap
Reference
R1
VFB1
–
+
Multiplexer
R2
VFB2
R3
SELECT
Figure 11. Block Diagram of the 1.4 A Current Mode Control Switching Regulator Portion of the
CS5111 in a Boost Configuration
PROTECTION CIRCUITRY
VSW
If the input voltage at VREG is increased above the
overvoltage threshold, the drive to the linear and switcher
output transistors is shut off. Therefore, VLIN is disabled and
VSW can not be pulled low.
The current out of VLIN is sensed in order to limit
excessive power dissipation in the linear output transistor
over the output range of 0 V to regulation. Also, the current
into VSW is sensed in order to provide the current limit
function in the switcher output transistor.
If the die temperature is increased above 160°C, either due
to excessive ambient temperature or excessive power
dissipation, the drive to the linear output transistor is
reduced proportionally with increasing die temperature.
Therefore, VLIN will decrease with increasing die
temperature above 160°C. Since the switcher control
circuitry is powered through VLIN, the switcher
performance, including current limit, will be affected by the
decrease in VLIN.
VOUT
VIN
VSAT
0
t
ISW
IPeak
t
0
ID
IPeak
t
0
Figure 12. Voltage and Current Waveforms
for Boost Topology in CS5111
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CS5111
APPLICATION NOTES
VINtON (VOUT VIN)tOFF
DESIGN PROCEDURE FOR BOOST TOPOLOGY
This section outlines a procedure for designing a boost
switching power supply operating in the discontinuous mode.
where the maximum on time is:
VIN(MIN)
tON(MAX) 1 VOUT(MAX)
Step 1
Determine the output power required by the load.
POUT IOUTVOUT
(1)
2
f
V 2
t
L(MAX) SW(MIN) IN (MIN) ON (MAX)
2POUT
Step 3
(8)
where η = efficiency.
Usually η = 0.75 is a good starting point. The IC’s power
dissipation should be calculated after the peak current has
been determined in Step 6. If the efficiency is less than
originally assumed, decrease the efficiency and recalculate
the maximum inductance and peak current.
Next select the output voltage feedback sense resistor
divider as follows (Figure 13).
For VFB1 active, choose a value for R1 and then solve for
REQ where:
(2)
FB1
Step 6
For VFB2 active, find:
REQ
VFB1 VOUT
R1 REQ
Determine the peak inductor current at the minimum
inductance, minimum VIN and maximum on time to make
sure the inductor current doesn’t exceed 1.4 A.
(3)
V
t
IPK IN(MIN) ON(MAX)
L(MIN)
and then calculate R2 where:
V
V
VFB2
R2 R2 FB1
IR2
VFB1REQ
(9)
(4)
Step 7
Then find R3, where:
R3 REQ R2
Determine the minimum output capacitance and maximum
ESR based on the allowable output voltage ripple.
(5)
COUT(MIN) VOUT
ESR(MIN) R1
VFB1
IPK
8fVRIPPLE
(10)
VRIPPLE
IPK
(11)
In practice, it is normally necessary to use a larger
capacitance value to obtain a low ESR. By placing
capacitors in parallel, the equivalent ESR can be reduced.
R2
VFB2
REQ
(7)
Calculate the maximum inductance allowed for
discontinuous operation:
Choose COSC based on the target oscillator frequency with
an external resistor value, RBIAS = 64.9 kΩ. (See Figure 5).
VR2
1
fSW(MIN)
Step 5
Step 2
R
REQ VOUT 1
1
V
(6)
Step 8
Compensate the feedback loop to guarantee stability
under all operating conditions. To do this, we calculate the
modulator gain and the feedback resistor network
attenuation and set the gain of the error amplifier so that the
overall loop gain is 0 dB at the crossover frequency, fCO. In
addition, the gain slope should be –20 dB/decade at the
crossover frequency.
The low frequency gain of the modulator (i.e. error
amplifier output to output voltage) is:
R3
Figure 13. Feedback Sense Resistor Divider
Connected Between VOUT and Ground
Step 4
Determine the maximum on time at the minimum
oscillator frequency and VIN. For discontinuous operation,
all of the stored energy in the inductor is transferred to the
load prior to the next cycle. Since the current through the
inductor cannot change instantaneously and the inductance
is constant, a volt–second balance exists between the on time
and off time. The voltage across the inductor during the on
cycle is VIN and the voltage across the inductor during the
off cycle is VOUT – VIN. Therefore:
IPK(MAX)
VOUT
VEA(MAX)
VEA
RLOADLf
2
(12)
where:
V
G
2.4 V7
IPK(MAX) EA(MAX) CSA 2.3 A (13)
150
m
RS
The VOUT/VEA transfer function has a pole at:
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CS5111
fp 1(RLOADCOUT)
VOUT
(14)
and a zero due to the output capacitor’s ESR at:
R1
fz 1(2ESR(COUT))
Since the error amplifier reference voltage is 1.25 V, the
output voltage must be divided down or attenuated before
being applied to the input of the error amplifier. The
feedback resistor divider attenuation is:
R2
M
U
X
VFB2
Error
Amplifier
The error amplifier in the CS5111 is an operational
transconductance amplifier (OTA), with a gain given by:
GOTA gmZOUT
+
–
R3
1.25 V
VOUT
C1
R4
SELECT
Figure 14. RC Network Used to Compensate
the Error Amplifier (OTA)
IOUT
VIN
(17)
A pole at point C:
For the CS5111, gm = 2700 µA/V typical.
One possible error amplifier compensation scheme is
shown in Figure 14. This gives the error amplifier a gain plot
as shown in Figure 15.
For the error amplifier gain shown in Figure 15, a low
frequency pole is generated by the error amplifier output
impedance and C1 . This is shown by the line AB with a
–20 dB/decade slope in Figure 15. The slope changes to zero
at point B due to the zero at:
fz 1(2R4C1)
fp 1(R4C2)
Step 9
Finally the watchdog timer period and Power on Reset
time is determined by:
tDelay 1.353 CDelayRBIAS
(18)
G
A
(19)
offsets the zero set by the ESR of the output capacitors.
An alternative scheme uses a single capacitor as shown in
Figure 16, to roll the gain off at a relatively low frequency.
Pole due to error amplifier
output impedance and C1
fz = 1/(2πR4C1)
fp = 1/(πR4C2)
+G
C
B
error amplifier gain
Gain (dB)
C2
(16)
where:
gm 1.25 V
VFB1
(15)
–20 dB/dec
fp = 1/(πRLOADCOUT)
fCO
0
modulator gain +
feedback resistor divider attenuation
–G
fz = 1/(2πESR(COUT))
Figure 15. Bode Plot of Error Amplifier (OTA) Gain and Modulator Gain Added to the Feedback
Resistor Divider Attenuation
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(20)
CS5111
VIN
VOUT = 18 V, Select > 2.0 V
VOUT = 16 V, Select < 0.8 V
L = 33 µH
COUT
88 µF
VIN
ENABLE
NC
VREG
NC
VLIN
VSW
IBIAS
GND
GND
(2)
GND
5.0 V
100 µF
ESR < 8.0 Ω
RBIAS
64.9 kΩ
GND
CS5111
R1
100 kΩ
R2
946 Ω
GND
GND
GND
GND
VFB1
RESET
VFB2
CDelay
Microprocessor
(1)
R3
7.5 kΩ
SELECT
COMP
CDelay
0.1 µF
WDI
COSC
COSC
390 pF
CCOMP
0.33 µF
Figure 16. A Typical Application Diagram with External Components Configured
in a Boost Topology
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11
CS5111
LINEAR REGULATOR OUTPUT CURRENT VS. INPUT VOLTAGE
100
ILIN (mA)
ILIN (mA)
100
75
ΘJA = 55°C/W
VIN = 14 V
Max Total Power = 1.18 W
50
25
0
75
ΘJA = 35°C/W
VIN = 14 V
Max Total Power = 1.86 W
50
25
0
5
10
15
20
25
0
30
0
5
10
VREG (V)
15
20
25
30
VREG (V)
Figure 17. The Shaded Area Shows the Safe Operating Area of the CS5111 as a Function of
ILIN, VREG, and JA. Refer to Table 1 for Typical Loads and Voltages.
Table 1.
Worst Case Switcher
Power Available
(ΘJA = 55°C/W) (W)
Worst Case Switcher
Power Available
(ΘJA = 35°C/W) (W)
VREG (V)
VIN (V)
ILIN (mA)
Linear Power
Dissipation (W)
20
14
25
0.44
0.74
1.42
20
14
50
0.83
0.35
1.03
20
14
75
1.22
*
0.64
20
14
100
1.60
*
0.26
25
14
25
0.60
0.58
1.26
25
14
50
1.11
0.07
0.75
25
14
75
1.62
*
0.24
25
14
100
2.14
*
*
*Subjecting the CS5111 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it into thermal
limit.
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CS5111
PACKAGE DIMENSIONS
SO–24L
DWF SUFFIX
CASE 751E–04
ISSUE E
–A–
24
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
–B–
12X
P
0.010 (0.25)
1
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
DIM
A
B
C
D
F
G
J
K
M
P
R
F
R
X 45 C
–T–
SEATING
PLANE
M
22X
G
K
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0
8
10.05
10.55
0.25
0.75
PACKAGE THERMAL DATA
Parameter
SO–24L
Unit
RΘJC
Typical
9
°C/W
RΘJA
Typical
55
°C/W
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13
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0
8
0.395
0.415
0.010
0.029
CS5111
Notes
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14
CS5111
Notes
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15
CS5111
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CS5111/D