IDT IDT71V632S6PF8 64k x 32 3.3v synchronous sram pipelined outputs burst counter, single cycle deselect Datasheet

64K x 32
3.3V Synchronous SRAM
Pipelined Outputs
Burst Counter, Single Cycle Deselect
Features
◆
◆
◆
◆
◆
◆
◆
◆
IDT71V632
with full support of the Pentium™ and PowerPC™ processor interfaces.
The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz.
The IDT71V632 SRAM contains write, data, address, and control
registers. Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the extreme end of the write
cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V632 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address counter
accepts the first cycle address from the processor, initiating the access
sequence. The first cycle of output data will be pipelined for one cycle before
it is available on the next rising clock edge. If burst mode operation is
selected (ADV=LOW), the subsequent three cycles of output data will be
available to the user on the next three rising clock edges. The order of these
three addresses will be defined by the internal burst counter and the LBO
input pin.
The IDT71V632 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density
in both desktop and notebook applications.
64K x 32 memory configuration
Supports high system speed:
Commercial:
– A4 4.5ns clock access time (117 MHz)
Commercial and Industrial:
– 5 5ns clock access time (100 MHz)
– 6 6ns clock access time (83 MHz)
– 7 7ns clock access time (66 MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC64K32D7LG-XX)
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
Description
The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32
Pin Description Summary
A0–A15
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS0, CS1
Chips Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O0–I/O31
Data Input/Output
I/O
Synchronous
VDD, VDDQ
3.3V
Power
N/A
VSS, VSSQ
Array Ground, I/O Ground
Power
N/A
3619 tbl 01
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
AUGUST 2001
1
©2000 Integrated Device Technology, Inc.
DSC-3619/04
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
A0–A15
Description
Address Inputs
I
N/A
Synchronous Address inputs. The address re gister is triggered by a combination
of the rising edge of CLK and ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW
Synchronous Address Status from Cache Controller.ADSC is an active LOW
input that is used to load the add ress registers with new addresses. ADSC is
NOT GATED by CE.
ADSP
Address Status
(Processor)
I
LOW
ADV
Burst Address Advance
I
LOW
Synchronous Address Advance. ADV is an active LOW input that is used to
advance the internal burst counter, controlling burst access after the initial
address is loaded. When this input is HIGH the burst counter is not incremented;
that is, there is no address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1–BW4. If BWE is
LOW at the rising edge of CLK then BWX inputs are passed to the next stage in
the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of
CLK. If ADSP is HIGH and BWX is LOW at the rising edge of CLK then data will
be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked
and only GW can initiate a write cycle.
BW1–BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. BW1 controls I/O(7:0), BW2 controls I/O(15:8),
etc. Any active byte write causes all outputs to be disabled. ADSP LOW
disables all byte writes. BW1–BW4 must meet specified setup and hold times
with respect to CLK.
CE
Chip Enable
I
LOW
Synchronous chip enable. CE is used with CS 0 and CS1 to enable the
IDT71V632. CE also gates ADSP.
CLK
Clock
I
N/A
This is the clock input. All timing references for the device are made with respect
to this input.
CS 0
Chip Select 0
I
HIGH
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable
the chip.
CS1
Chip Select 1
I
LOW
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable
the chip.
GW
Global Write Enable
I
LOW
I/O0–I/O31
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output
path are registered and triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Asynchronous burst order sele ction DC input. When LBO is HIGH the Interleaved
(Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst
sequence is selected. LBO is a static DC input and must not change state while
the device is operating.
OE
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are
enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O
pins are in a high-impedence state.
VDD
Power Supply
N/A
N/A
3.3V core power supply inputs.
VDDQ
Power Supply
N/A
N/A
3.3V I/O power supply inputs.
VSS
Ground
N/A
N/A
Core ground pins.
VSSQ
Ground
N/A
N/A
I/O ground pins.
NC
No Connect
N/A
N/A
NC pins are not electrically connected to the chip.
ZZ
Sleep Mode
I
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
down the IDT71V632 to its lowest power consumption level. Data retention is
guaranteed in Sleep Mode.
Synchrono us Address Status from Processor. ADSP is an active LOW input that
is used to load the address registers with new addresses. ADSP is gated by
CE.
Synchrono us global write enable. This input will write all four 8-bit data bytes
when LOW on the rising edge of CLK. GW supercedes individual byte write
enables.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
3619 tbl 02
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
ADV
CLK
2
Binary
Counter
ADSC
Burst
Logic
Q0
CLR
ADSP
Q1
CLK EN
ADDRESS
REGISTER
A0–A15
GW
BWE
INTERNAL
ADDRESS
Burst
Sequence
CE
2
A0, A1
64K x 32
BIT
MEMORY
ARRAY
16
A0*
A1*
A2–A15
32
32
16
Byte 1
Write Register
Byte 1
Write Driver
BW1
8
Byte 2
Write Register
Byte 2
Write Driver
BW2
8
Byte 3
Write Register
Byte 3
Write Driver
BW3
8
Byte 4
Write Register
Byte 4
Write Driver
BW4
8
OUTPUT
REGISTER
CE
CS0
CS1
D
Q
Enable
Register
DATA INPUT
REGISTER
CLK EN
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OE
OUTPUT
BUFFER
32
I/O0–I/O31
3619 drw 01
6.42
3
.
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
Value
Unit
Terminal Voltage with
Respect to GND
–0.5 to +4.6
V
Terminal Voltage with
Respect to GND
–0.5 to VDD+0.5
TA
Operating Temperature
0 to +70
o
TBIAS
Temperature Under Bias
–55 to +125
o
TSTG
Storage Temperature
–55 to +125
o
PT
Power Dissipation
1.0
IOUT
DC Output Current
50
VTERM
(2)
VTERM
(3)
Rating
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature
VSS
Commercial
0°C to +70°C
0V
3.3V+10/-5% 3.3V+10/-5%
Industrial
–40°C to +85°C
0V
3.3V+10/-5% 3.3V+10/-5%
V
VDD
VDDQ
3619 tbl 03
C
C
Recommended DC Operating
Conditions
C
W
mA
3619 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD, VDDQ and Input terminals only.
3. I/O terminals.
Sym bol
Param eter
M in.
M ax.
Unit
V DD
Co re S up p ly Vo ltag e
3.135
3.63
V
V DDQ
I/O S up p ly Vo ltag e
3.135
3.63
V
V SS, V SSQ
G ro und
0
0
V
V IH
V IH
V IL
Inp ut Hig h Vo ltag e — Inp uts
Inp ut Hig h Vo ltag e — I/O
Inp ut Lo w Vo ltag e
2.0
2.0
–0.3
(3)
5.0
(1)
V DDQ + 0.3
0.8
V
(2)
V
V
3619 tbl 04
NOTES:
1. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
3. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
Symbol
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
Conditions
Max.
Unit
VIN = 3dV
6
pF
VOUT = 3dV
7
pF
3619 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
4
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
A6
A7
CE
CS0
BW4
BW3
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
I/O16
I/O17
VDDQ
VSSQ
I/O18
I/O19
I/O20
I/O21
VSSQ
VDDQ
I/O22
I/O23
VDD/NC(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSSQ
I/O26
I/O27
I/O28
I/O29
VSSQ
VDDQ
I/O30
I/O31
NC
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
15
66
PK100-1
16
65
64
17
18
19
63
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
51
30
NC
I/O15
I/O14
VDDQ
VSSQ
I/O13
I/O12
I/O11
I/O10
VSSQ
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSSQ
I/O5
I/O4
I/O3
I/O2
VSSQ
VDDQ
I/O1
I/O0
NC
NC
NC
A10
A11
A12
A13
A14
A15
NC
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3619 drw 02
Top View TQFP
NOTES:
1. Pin 14 can either be directly connected to VDD or not connected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,2)
Address
Used
CE
CS0
CS1
ADSP
ADSC
ADV
GW
BWE
BWX
OE(3)
CLK
I/O
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
X
H
L
X
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
L
X
L
X
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
X
H
X
L
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
L
X
X
L
X
X
X
X
X
↑
Hi-Z
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
H
↑
Hi-Z
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
H
X
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
H
↑
Hi-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L
X
↑
DIN
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
X
X
↑
DIN
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
L
↑
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
H
↑
Hi-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
L
↑
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
H
↑
Hi-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
L
↑
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
H
↑
Hi-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
L
↑
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
H
↑
Hi-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L
X
↑
DIN
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
X
X
↑
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L
X
↑
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
X
X
↑
DIN
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
L
↑
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
H
↑
Hi-Z
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
L
↑
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
H
↑
Hi-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
L
↑
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
H
↑
Hi-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
L
↑
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
H
↑
Hi-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L
X
↑
DIN
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
X
X
↑
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L
X
↑
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
X
X
↑
Operation
DIN
3619 tbl 07
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. ZZ = LOW for this table.
3. OE is an asynchronous input.
6.42
6
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1)
GW
BWE
BW1
BW2
BW3
BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
Write Byte 1
(2)
H
L
L
H
H
H
Write Byte 2
(2)
H
L
H
L
H
H
Write Byte 3
(2)
H
L
H
H
L
H
Write Byte 4(2)
H
L
H
H
H
L
Operation
3619 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table(1)
OE
ZZ
I/O Status
Power
Read
L
L
Data Out (I/O0 - I/O31)
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z — Data In (I/O 0 - I/O31)
Active
Deselected
X
L
High-Z
Standby
Sleep
X
H
High-Z
Sleep
Operation(2)
3619 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
1
1
1
0
0
1
0
0
(1)
Fourth Address
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
3619 tbl 10
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
Fourth Address
(1)
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
7
3619 tbl 11
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 3.3V +10/-5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
—
5
µA
|ILZZ|
ZZ and LBO Input Leakage Current (1)
VDD = Max., VIN = 0V to VDD
—
30
µA
|ILO|
Output Leakage Current
CE > VIH or OE > VIH, VOUT = 0V to VDD, VDD = Max.
—
5
µA
VOL (3.3V)
Output Low Voltage
IOL = 5mA, VDD = Min.
—
0.4
V
VOH (3.3V)
Output High Voltage
IOH = –5mA, VDD = Min.
2.4
—
V
3619 tbl 12
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(1) (VHD = VDDQ – 0.2V, VLD = 0.2V)
SA4(3,4)
Symbol
Parameter
Test Conditions
S5
S6
S7
Com'l.
Ind.
Com'l.
Ind.
Com'l.
Ind.
Com'l.
Ind.
Unit
IDD
Operating Power
Supply Current
Device Selected, Outputs Open,
VDD = Max., VIN > VIH or < VIL,
f = fMAX(2)
220
—
200
200
180
180
160
160
mA
ISB
Standby Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VIH or < VIL,
f = fMAX(2)
70
—
65
65
60
60
55
55
mA
ISB1
Full Standby Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = 0(2)
15
—
15
15
15
15
15
15
mA
IZZ
Full Sleep Mode
Power Supply Current
ZZ > VHD, VDD = Max.
10
—
10
10
10
10
10
10
mA
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. SA4 speed grade corresponds to a tCD of 4.5 ns.
4. 0°C to +70°C temperature range only.
+3.3V
AC Test Loads
317Ω
VDDQ/2
I/O
50Ω
I/O
3619 tbl 13
Z0 = 50Ω
Figure 1. AC Test Load
351Ω
5pF*
3619 drw 03
3619 drw 04
6
* Including scope and jig capacitance.
5
Figure 2. High-Impedence Test Load
(for tOHZ, tCHZ, tOLZ, and tDC1)
4
AC Test Conditions
3
∆tCD
(Typical, ns)
2
Input Pulse Levels
1
20 30 50
80 100
Capacitance (pF)
200
3619 drw 05
Input Rise/Fall Times
2ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
AC Test Load
Figure 3. Lumped Capacitive Load, Typical Derating
0 to 3.0V
See Figures 1 and 2
3619 tbl 14
6.42
8
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD, VDDQ = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
71V632SA4(5,6)
Symbol
Parameter
71V632S5
71V632S6
71V632S7
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Clock Cycle Time
8.5
____
10
____
12
____
15
____
ns
(1)
Clock High Pulse Width
3.5
____
4
____
4.5
____
5
____
ns
tCL(1)
Clock Low Pulse Width
3.5
____
4
____
4.5
____
5
____
ns
____
4.5
____
5
____
6
____
7
ns
Clock High to Data Change
1.5
____
1.5
____
2
____
2
____
ns
Clock High to Output Active
0
____
0
____
0
____
0
____
ns
Clock High to Data High-Z
1.5
4
1.5
5
2
5
2
6
ns
Output Enable Access Time
____
4
____
5
____
5
____
6
ns
Output Enable Low to Data Active
0
____
0
____
0
____
0
____
ns
Output Enable High to Data High-Z
____
4
____
4
____
5
____
6
ns
tSA
Address Setup Time
2.2
____
2.5
____
2.5
____
2.5
____
ns
tSS
Address Status Setup Time
2.2
____
2.5
____
2.5
____
2.5
____
ns
2.2
____
2.5
____
2.5
____
2.5
____
ns
2.5
____
2.5
____
2.5
____
ns
CLOCK PARAMETERS
tCYC
tCH
OUTPUT PARAMETERS
tCD
Clock High to Valid Data
tCDC
tCLZ
(2)
tCHZ(2)
tOE
tOLZ
(2)
tOHZ
(2)
SETUP TIMES
tSD
Data in Setup Time
tSW
Write Setup Time
2.2
____
tSAV
Address Advance Setup Time
2.2
____
2.5
____
2.5
____
2.5
____
ns
tSC
Chip Enable/Select Setup Time
2.2
____
2.5
____
2.5
____
2.5
____
ns
Address Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
0.5
____
ns
HOLD TIMES
tHA
tHS
Address Status Hold Time
0.5
____
tHD
Data In Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHW
Write Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHAV
Address Advance Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
SLEEP MODE AND CONFIGURATION PARAMETERS
tZZPW
ZZ Pulse Width
100
____
100
—
100
____
100
____
ns
tZZR(3)
ZZ Recovery Time
100
____
100
—
100
____
100
____
ns
tCFG (4)
Configuration Set-up Time
34
____
40
—
50
____
50
____
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. The 71V632SA4 speed grade corresponds to a tCD of 4.5ns.
6. 0°C to +70°C temperature range only.
6.42
9
ns
3619 tbl 15
6.42
10
Output
Disabled
tSC
tSA
tSS
tHS
Ax
Pipelined
Read
tOLZ
tOE
tHC
tHA
O1(Ax)
Ay
(1)
tCH
tCLZ
tOHZ
tCD
tSW
tCL
O1(Ay)
tCDC
tSAV
tHAV
O2(Ay)
tHW
Burst Pipelined Read
O3(Ay)
O4(Ay)
(Burst wraps around
to its initial state)
ADV inserts a wait-state
O1(Ay)
tCHZ
O2(Ay)
3619 drw 06
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base
address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
OE
ADV
(Note 3)
CE, CS1
GW, BWE, BWx
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
6.42
11
tSA
tHA
tSS
tHS
tCLZ
tCD
Single Read
Ax
(2)
tOE
O1(Ax)
tOHZ
tSW
Ay
tCH
Pipelined
Write
I1(Ay)
tSD tHD
tCL
tHW
Az
tOLZ
tCDC
O2(Az)
Pipelined Burst Read
O1(Az)
3619 drw 07
O3(Az)
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3. O1(Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay. O1(Az) represents the first output from the external addresss Az; O2(Az)
represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
DATAOUT
DATAIN
OE
ADV
GW
ADDRESS
ADSP
CLK
tCYC
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
6.42
12
tHC
O4(Aw)
Ax
Burst Read
O3(Aw)
tSC
tSA
tHA
tSS
tHS
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
BWE is ignored when ADSP initiates burst
tCH
I2(Ay)
Burst Write
I2(Ay)
(ADV suspends burst)
tSAV
.
I3(Ay)
tHAV
I4(Ay)
tSD
I1(Az)
tHW
tSW
Az
I3(Az)
3619 drw 08
Burst Write
I2(Az)
tHD
NOTES:
1. ZZ input is LOW, BWE is HIGH, and LBO is Don’t Care for this cycle.
2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
6.42
13
tHC
Burst
Read
O3(Aw)
tSC
tSA
tHA
tSS
tHS
O4(Aw)
Ax
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
BWx is ignored when ADSP initiates burst
BWE is ignored when ADSP initiates burst
tCH
Burst Write
I2(Ay)
(ADV suspends burst)
I2(Ay)
I3(Ay)
I4(Ay)
tSD
Extended
Burst Write
I1(Az)
tSAV
tHW
tSW
tHW
tSW
Az
I2(Az)
tHD
3619 drw 09
I3(Az)
NOTES:
1. ZZ input is LOW, GW is HIGH, and LBO is Don’t Care for this cycle.
2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
BWx
BWE
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)
6.42
14
tSS
tSC
tSA
tHS
Ax
Single Read
tOLZ
tOE
tHC
tHA
O1(Ax)
tCH
tCL
t ZZPW
Snooze Mode
t ZZR
NOTES:
1. Device must power up in deselected Mode.
2. LBO input is Don’t Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
ZZ
DATAOUT
OE
ADV
(Note 4)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
Az
3619 drw 10
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW, BWE, BWx
CE, CS1
CS0
OE
DATAOUT
(Av)
(Aw)
(Ax)
(Ay)
,
3619 drw 11
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don’t Care for this cycle.
2. (AX) represents the data for address AX, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
6.42
15
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
(Ax)
(Ay)
(Az)
GW
CE, CS1
CS0
DATAIN
(Av)
(Aw)
,
3619 drw 12
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don’t Care for this cycle.
2. (AX) represents the data for address AX, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
16
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
100-pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
6.42
17
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Ordering Information
IDT
71V632
S
X
PF
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
PF
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
A4*
5
6
7
Synchronous Access Time in nanoseconds
* Commercial only.
PART NUMBER
SPEED IN MEGAHERTZ
tCD PARAMETER
CLOCK CYCLE TIME
71V632SA4PF
117 MHz
4.5 ns
8.5 ns
71V632S5PF
100 MHz
5 ns
10 ns
71V632S6PF
83 MHz
6 ns
12 ns
71V632S7PF
66 MHz
7 ns
15 ns
3619 drw 13
6.42
18
IDT71V632, 64K x 32, 3.3V Synchronous SRAM
with Pipelined Outputs and Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
9/9/99
09/30/99
04/04/00
08/09/00
08/17/01
Pg. 1, 8, 9, 17
Pg. 15, 16
Pg. 18
Pg. 1, 4, 8, 9, 17
Pg. 17
Updated to new format
Revised speed offerings to 66–117MHz
Added non-burst read and write cycle timing diagrams
Added Datasheet Document History
Added industrial temperature range offerings
Added 100pinTQFP package Diagram Outline
Not recommended for new designs
Removed “Not recommended for new designs” from the background on the datasheet
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
19
for Tech Support:
[email protected]
800-544-7726, x4033