ON MC100LVE310 3.3 v ecl 2:8 differential fanout buffer Datasheet

MC100LVE310
3.3 V ECL 2:8 Differential
Fanout Buffer
Description
The MC100LVE310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and
system skew. The LVE310 offers two selectable clock inputs to allow
for redundant or test clocks to be incorporated into the system clock
trees.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50 W, even if
only one side is being used. In most applications all eight differential
pairs will be used and therefore terminated. In the case where fewer
than eight pairs are used it is necessary to terminate at least the output
pairs adjacent to the output pair being used in order to maintain
minimum skew. Failure to follow this guideline will result in small
degradations of propagation delay (on the order of 10−20 ps) of the
outputs being used, while not catastrophic to most designs this will
result in an increase in skew. Note that the package corners isolate
outputs from one another such that the guideline expressed above
holds only for outputs on the same side of the package.
The MC100LVE310, as with most ECL devices, can be operated
from a positive VCC supply in LVPECL mode. This allows the
LVE310 to be used for high performance clock distribution in +3.3 V
systems. Designers can take advantage of the LVE310’s performance
to distribute low skew clocks across the backplane or the board. In
a PECL environment series or Thevenin line terminations are
typically used as they require no additional power supplies, if parallel
termination is desired a terminating voltage of VCC − 2.0 V will need
to be provided. For more information on using PECL, designers
should refer to Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
• 200 ps Part-to-Part Skew
• 50 ps Output-to-Output Skew
• PECL Mode Operating Range:
•
•
•
•
VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.8 V
Q Output will Default LOW with All Inputs Open or at VEE
The 100 Series Contains Temperature Compensation
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 6
1
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MC100LVE310G
AWLYYWW
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Package
Shipping†
MC100LVE310FNG
Device
PLCC−28
(Pb-Free)
37 Units / Tube
MC100LVE310FNR2G
PLCC−28
(Pb-Free)
500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
MC100LVE310/D
MC100LVE310
Q0
Q0
25
24
Q1 VCCO Q1
23
22
21
Q2
Q2
20
19
Q0
Q0
Q1
VEE
26
18
Q3
CLK_SEL
27
17
Q3
16
Q4
15
VCCO
CLKa
Q4
CLKb
CLKa
VCC
CLKa
28
Pinout: 28-Lead PLCC
(Top View)
1
2
14
VBB
3
13
Q5
CLKb
4
12
Q5
5
6
CLKb
NC
7
8
Q7 VCCO
9
10
Q7
Q6
Q1
Q2
Q2
CLKa
Q3
Q3
Q4
CLKb
Q4
Q5
CLK_SEL
Q5
11
Q6
Q6
Q6
Q7
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Q7
Figure 1. Logic Diagram and Pinout Assignment
VBB
Figure 2. Logic Symbol
Table 1. PIN DESCRIPTION
FUNCTION
PIN
CLKa, CLKa; ,CLKb CLKb
Q0:7, Q0:7
CLK_SEL
VBB
VCC, VCCO
VEE
NC
Table 2. TRUTH TABLE
ECL Differential Input Clocks
ECL Differential Outputs
ECL Input Clock Select
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Input Clock
CLK_SEL
L
H
CLKa Selected
CLKb Selected
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
YES
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
PLCC−28
Flammability Rating
Oxygen Index: 28 to 34
Pb-Free Pkg
Level 3
UL 94 V−0 @ 0.125 in
Transistor Count
212 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100LVE310
Table 4. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
IBB
VBB Sink/Source
±0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
PLCC−28
22 to 26 ±5%
°C/W
Tsol
Wave Solder (Pb-Free)
265
°C
VI ≤ VCC
VI ≥ VEE
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 5. LVPECL DC CHARACTERISTICS (VCC = 3.3 V, VEE = 0 V (Note 1))
−40°C
Symbol
Typ
Max
55
60
2215
2295
2420
1470
1605
1745
2135
2420
1490
1825
Output Voltage Reference
1.92
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
1.8
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
VOL
Output LOW Voltage (Note 2)
VIH
Input HIGH Voltage (Single-Ended)
VIL
Input LOW Voltage (Single-Ended)
VBB
VIHCMR
IIH
Input HIGH Current
IIL
Input LOW Current
Min
25°C
Min
85°C
Typ
Max
55
60
2275
2345
2420
1490
1595
1680
2135
2420
1490
1825
2.04
1.92
2.9
1.8
150
0.5
Min
Typ
Max
Unit
65
70
mA
2275
2345
2420
mV
1490
1595
1680
mV
2135
2420
mV
1490
1825
mV
2.04
1.92
2.04
V
2.9
1.8
2.9
V
150
mA
150
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.3 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device
still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than
or equal to VPP(min).
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3
MC100LVE310
Table 6. LVNECL DC CHARACTERISTICS (VCC = 5.0 V, VEE = −3.3 V (Note 1))
−40°C
Symbol
Min
Characteristic
25°C
Typ
Max
55
60
Min
85°C
Typ
Max
55
60
Min
Typ
Max
Unit
65
70
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 2)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage
(Single-Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage
(Single-Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
−1.5
−0.4
−1.5
−0.4
−1.5
−0.4
V
150
mA
VIHCMR
IIH
Input HIGH Current
IIL
Input LOW Current
150
150
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ± 0.3 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device
still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than
or equal to VPP(min).
Table 7. AC CHARACTERISTICS (VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 1))
−40°C
Symbol
Characteristic
fmax
Maximum Toggle Frequency
@ Vout > 500 mVpp
tPLH
tPHL
Propagation Delay to Output
IN (Differential Configuration) (Note 2)
IN (Single-Ended) (Note 3)
tskew
Within-Device Skew (Note 4)
Part-to-Part Skew (Differential Configuration)
tJITTER
Min
Typ
0.5
1.0
525
500
25°C
Max
725
750
Min
Typ
0.5
1.0
550
550
1.5
Max
750
800
75
250
Additive CLOCK Jitter (RMS) < 0.5 GHz
85°C
Min
Typ
0.5
1.0
575
600
1.5
2.0
1.5
Unit
GHz
775
850
50
200
2.0
Max
ps
50
200
ps
2.0
ps
VPP
Input Swing (Note5)
500
1000
500
1000
500
1000
mV
tr/tf
Output Rise/Fall Time (20%−80%)
200
600
200
600
200
600
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. VEE can vary ± 0.3 V.
2. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
3. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the LVE310 as a differential input as low as 50 mV will still produce full ECL levels at the output.
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4
MC100LVE310
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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5
MC100LVE310
PACKAGE DIMENSIONS
28 LEAD PLLC
CASE 776−02
ISSUE F
B
Y BRK
−N−
0.007 (0.180)
U
M
T L-M
0.007 (0.180)
M
N
S
T L-M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
G1
0.010 (0.250)
T L-M
S
N
S
S
VIEW D−D
Z
A
0.007 (0.180)
R
0.007 (0.180)
M
M
T L-M
S
T L-M
S
N
N
H
S
0.007 (0.180)
M
T L-M
N
S
S
S
K1
C
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
−T−
T L-M
S
N
VIEW S
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.021
0.050 BSC
0.026
0.032
0.020
--0.025
--0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2_
10_
0.410
0.430
0.040
---
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6
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.53
1.27 BSC
0.66
0.81
0.51
--0.64
--11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2_
10_
10.42
10.92
1.02
---
0.007 (0.180)
M
T L-M
S
N
S
MC100LVE310
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