PD- 94227A
IRFPS35N50L
SMPS MOSFET
HEXFET® Power MOSFET
Applications
• Zero Voltage Switching SMPS
VDSS RDS(on) typ.
• Telecom and Server Power Supplies
0.125Ω
500V
• Uninterruptible Power Supplies
• Motor Control applications
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
• Higher Gate voltage threshold offers improved noise immunity .
Trr typ. ID
170ns
34A
Super-247™
Absolute Maximum Ratings
Parameter
Max.
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
22
IDM
140
Pulsed Drain Current
PD @TC = 25°C Power Dissipation
c
VGS
Linear Derating Factor
Gate-to-Source Voltage
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
TSTG
Storage Temperature Range
Units
34
e
A
450
W
3.6
±30
W/°C
V
15
-55 to + 150
V/ns
°C
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
Mounting torque, 6-32 or M3 screw
1.1(10)
N•m (lbf•in)
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
34
ISM
(Body Diode)
Pulsed Source Current
–––
–––
140
c
Conditions
MOSFET symbol
A
(Body Diode)
showing the
integral reverse
VSD
Diode Forward Voltage
–––
–––
1.5
V
p-n junction diode.
TJ = 25°C, IS = 34A, VGS = 0V
trr
Reverse Recovery Time
–––
170
250
ns
TJ = 25°C, IF = 34A
–––
220
330
Qrr
Reverse Recovery Charge
–––
670
1010
–––
1500 2200
IRRM
Reverse Recovery Current
ton
Forward Turn-On Time
–––
8.5
–––
TJ = 125°C, di/dt = 100A/µs
f
f
f
f
nC TJ = 25°C, IS = 34A, VGS = 0V
TJ = 125°C, di/dt = 100A/µs
A
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
8/26/04
IRFPS35N50L
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
V(BR)DSS
Drain-to-Source Breakdown Voltage
500
∆V(BR)DSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
VGS(th)
Gate Threshold Voltage
3.0
IDSS
Drain-to-Source Leakage Current
IGSS
RG
–––
–––
0.12
–––
0.125 0.145
–––
5.0
V
Conditions
VGS = 0V, I D = 250µA
V/°C Reference to 25°C, ID = 1mA
Ω
V
VGS = 10V, ID = 20A
f
VDS = VGS, ID = 250µA
–––
–––
50
µA
VDS = 500V, V GS = 0V
–––
–––
2.0
mA
VDS = 400V, V GS = 0V, TJ = 125°C
nA
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
1.1
–––
VGS = 30V
VGS = -30V
Ω
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
gfs
Qg
Forward Transconductance
18
Total Gate Charge
Qgs
Gate-to-Source Charge
Qgd
Gate-to-Drain ("Miller") Charge
td(on)
S
Conditions
–––
–––
VDS = 50V, I D = 20A
–––
–––
230
–––
–––
65
–––
–––
110
VGS = 10V, See Fig. 7 & 15
Turn-On Delay Time
–––
24
–––
VDD = 250V
tr
Rise Time
–––
100
–––
td(off)
Turn-Off Delay Time
–––
42
–––
tf
Fall Time
–––
42
–––
VGS = 10V, See Fig. 10a & 10b
Ciss
Input Capacitance
–––
5580
–––
VGS = 0V
Coss
Output Capacitance
–––
590
–––
Crss
Reverse Transfer Capacitance
–––
58
–––
Coss
Output Capacitance
–––
7290
–––
Coss
Output Capacitance
–––
160
–––
VGS = 0V, V DS = 400V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
320
–––
VGS = 0V,VDS = 0V to 400V
Coss eff. (ER)
Effective Output Capacitance
–––
220
–––
ID = 34A
nC
ns
VDS = 400V
f
ID = 34A
RG = 1.2Ω
f
VDS = 25V
pF
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, V DS = 1.0V, ƒ = 1.0MHz
g
(Energy Related)
Avalanche Characteristics
Symbol
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
–––
Max.
560
Units
mJ
–––
34
A
–––
45
mJ
Typ.
Max.
Units
–––
0.28
0.24
–––
–––
40
Thermal Resistance
Symbol
Parameter
h
RθJC
Junction-to-Case
RθCS
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
RθJA
h
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
Starting TJ = 25°C, L = 0.97mH, RG =25Ω,
IAS = 34A (See Figure 13)
ISD ≤ 34A, di/dt ≤ 765A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C.
2
°C/W
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff.(ER) is a fixed capacitance that stores the same energy
as Coss while VDS is rising from 0 to 80% VDSS.
Rθ is measured at TJ approximately 90°C
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IRFPS35N50L
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
ID, Drain-to-Source Current (A)
100
10
I D , Drain-to-Source Current (A)
TOP
1
0.1
4.5V
0.01
100
10
4.5V
1
20µs PULSE WIDTH
Tj = 25°C
0.001
0.1
1
10
0.1
0.1
100
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
1000
100
TJ = 150 ° C
10
1
TJ = 25 ° C
V DS = 50V
20µs PULSE WIDTH
5.0
6.0
7.0
8.0
9.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
0.01
4.0
1
VDS , Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
0.1
20µs PULSE WIDTH
TJ = 150 ° C
10.0
ID = 34A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFPS35N50L
30
100000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
10000
Ciss
20
Energy (µJ)
C, Capacitance(pF)
25
Coss = Cds + Cgd
1000
Coss
15
10
100
Crss
5
10
0
1
10
100
1000
0
VDS, Drain-to-Source Voltage (V)
ISD , Reverse Drain Current (A)
VGS , Gate-to-Source Voltage (V)
16
500
600
100
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
80
120
160
200
QG , Total Gate Charge (nC)
Fig 7. Typical Gate Charge Vs.
Gate-to-Source Voltage
4
400
1000
VDS = 400V
VDS = 250V
VDS = 100V
40
300
Fig 6. Typ. Output Capacitance
Stored Energy vs. VDS
ID = 34A
0
200
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
20
100
240
TJ = 150 ° C
10
TJ = 25 ° C
1
0.1
0.2
V GS = 0 V
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSD ,Source-to-Drain Voltage (V)
Fig 8. Typical Source-Drain Diode
Forward Voltage
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IRFPS35N50L
35
V DS
VGS
ID , Drain Current (A)
30
RD
D.U.T.
RG
+
-VDD
25
VGS
20
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
15
Fig 10a. Switching Time Test Circuit
10
VDS
5
90%
0
25
50
75
100
125
150
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.1
0.01
0.20
0.10
0.05
0.02
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFPS35N50L
ID , Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10us
100us
10
1ms
1
1
10ms
10
100
1000
TOP
1000
100
TC = 25 ° C
TJ = 150 ° C
Single Pulse
EAS , Single Pulse Avalanche Energy (mJ)
1200
1000
10000
VDS , Drain-to-Source Voltage (V)
BOTTOM
ID
15A
22A
34A
800
600
400
200
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig 12. Maximum Safe Operating Area
Fig 13. Maximum Avalanche Energy
Vs. Drain Current
15V
V(BR)DSS
DRIVER
L
VDS
D.U.T
RG
+
- VDD
IAS
20V
0.01Ω
tp
tp
A
I AS
Fig 14a. Unclamped Inductive Test Circuit
Fig 14b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
VGS
.2µF
.3µF
D.U.T.
+
V
- DS
QGS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 15a. Gate Charge Test Circuit
6
Charge
Fig 15b. Basic Gate Charge Waveform
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IRFPS35N50L
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
+
-
-
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFPS35N50L
Super-247™ (TO-274AA) Package Outline
0.13 [.005]
16.10 [.632]
15.10 [.595]
2X R 3.00 [.118]
2.00 [.079]
0.25 [.010]
5.50 [.216]
4.50 [.178]
A
B A
13.90 [.547]
13.30 [.524]
2.15 [.084]
1.45 [.058]
1.30 [.051]
0.70 [.028]
4
20.80 [.818]
19.80 [.780]
16.10 [.633]
15.50 [.611]
4
C
1
2
3
B
14.80 [.582]
13.80 [.544]
5.45 [.215]
2X
Ø 1.60 [.063]
MAX.
4.25 [.167]
3.85 [.152]
3X
1.60 [.062]
1.45 [.058]
0.25 [.010]
B A
3X
1.30 [.051]
1.10 [.044]
E
E
2.35 [.092]
1.65 [.065]
S ECTION E-E
NOTES:
1. DIMENS IONING AND TOLERANCING PER ASME Y14.5M-1994.
2. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]
3. CONTROLLING DIMENS ION: MILLIMETER
4. OUTLINE CONFORMS TO JEDEC OUTLINE TO-274AA
LEAD ASS IGNMENTS
MOS FET
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
IGBT
1 - GATE
2 - COLLECTOR
3 - EMITTER
4 - COLLECTOR
Super-247™ (TO-274AA)Part Marking Information
EXAMPLE: THIS IS AN IRFPS37N50A WITH
ASSEMBLY LOT CODE A8B9
INTERNATIONAL RECTIFIER
LOGO
PART NUMBER
IRFPS37N50A
A8B9
0020
ASSEMBLY LOT CODE
TOP
DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
Super TO-247™ package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/04
8
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