NSC DS91C180TMA 100 mhz m-lvds line driver/receiver pair Datasheet

DS91D180/DS91C180
100 MHz M-LVDS Line Driver/Receiver Pair
no offset.The DS91C180 device has a type 2 receiver input
which enable failsafe functionality.
General Description
The DS91D180 and DS91C180 are 100 MHz M-LVDS (Multipoint Low Voltage Differential Signaling) line driver/receiver
pairs designed for applications that utilize multipoint networks
(e.g. clock distribution in ATCA and uTCA based systems).
M-LVDS is a new bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight
input receiver tresholds and increased drive strength are one
of the key enhencments that make M-LVDS devices an ideal
choice for distributing signals via multipoint networks.
The DS91D180/DS91C180 driver input accepts LVTTL/LVCMOS signals and converts them to differential M-LVDS signal
levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL
and CML) and converts them to 3V LVCMOS signals. The
DS91D180 device has a M-LVDS type 1 receiver input with
Features
■ DC to 100+ MHz / 200+ Mbps low power, low EMI
operation
■ Optimal for ATCA, uTCA clock distribution networks
■ Meets or exceeds TIA/EIA-899 M-LVDS Standard
■ Wide Input Common Mode Voltage for Increased Noise
Immunity
■ DS91D180 has type 1 receiver input
■ DS91C180 has type 2 receiver input for fail-safe
functionality
■ Industrial temperature range
■ Space saving SOIC-14 package (JEDEC MS-012)
Typical Application in an ATCA Clock Distribution Network
20041930
© 2007 National Semiconductor Corporation
200419
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DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair
November 20, 2007
DS91D180/DS91C180
Connection Diagram
Logic Diagram
20041926
Top View
Order Number DS91D180TMA, DS91C180TMA
See NS Package Number M14A
20041925
Ordering Information
Order Number
Receiver Input
Function
Package Type
DS91D180TMA
type 1
Data (0V threshold receiver)
SOIC/M14A
DS91C180TMA
type 2
Control (offset fail-safe receiver)
SOIC/M14A
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different
types of receiver input stages. A type 1 receiver has a conventional threshold that is centered at the midpoint of the input
amplitude, VID/2. A type 2 receiver has a built in offset that is
100mV greater then VID/2. The type 2 receiver offset acts as
a failsafe circuit where open or short circuits at the input will
always result in the output stage being driven to a low logic
state.
20041940
FIGURE 1. M-LVDS Receiver Input Thresholds
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2
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(CDM 0Ω, 0pF)
Supply Voltage, VCC
−0.3V to +4V
Control Input Voltages
−0.3V to (VCC + 0.3V)
Driver Input Voltage
−0.3V to (VCC + 0.3V)
Driver Output Voltages
−1.8V to +4.1V
Receiver Input Voltages
−1.8V to +4.1V
Receiver Output Voltage
−0.3V to (VCC + 0.3V)
Maximum Package Power Dissipation at +25°C
SOIC Package
1.1 W
Derate SOIC Package
8.8 mW/°C above +25°C
Thermal Resistance
θJA
113.7 °C/W
θJC
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature
(Soldering, 4 seconds)
≥ 5 kV
≥ 250 V
≥ 1000 V
(EIAJ 0Ω, 200pF)
Recommended Operating
Conditions
Supply Voltage, VCC
Voltage at Any Bus Terminal
Min Typ Max Units
3.0 3.3 3.6
V
−1.4
+3.8
V
(Separate or Common-Mode)
Differential Input Voltage VID
High Level Input Voltage VIH
2.0
Low Level Input Voltage VIL
0
Operating Free Air
Temperature TA
−40
36.9 °C/W
150°C
−65°C to +150°C
+25
2.4
VCC
0.8
V
V
V
+85
°C
260°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4, 8)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
650
mV
M-LVDS Driver
|VYZ|
Differential output voltage magnitude
RL = 50Ω, CL = 5pF
ΔVYZ
Change in differential output voltage magnitude
between logic states
Figure 2 and Figure 4
VOS(SS)
Steady-state common-mode output voltage
RL = 50Ω, CL = 5pF
|ΔVOS(SS)| Change in steady-state common-mode output
voltage between logic states
Figure 2 and Figure 3
VOS(PP)
Peak-to-peak common-mode output voltage
(VOS(pp) @ 500KHz clock)
VY(OC)
Maximum steady-state open-circuit output voltage
Figure 5
VZ(OC)
Maximum steady-state open-circuit output voltage
VP(H)
Voltage overshoot, low-to-high level output
VP(L)
Voltage overshoot, high-to-low level output
480
−50
0
+50
mV
0.3
1.8
2.1
V
+50
mV
0
143
0
0
RL = 50Ω, CL = 5pF,
CD = 0.5pF
Figure 7 and Figure 8 (Note 9)
mV
2.4
V
2.4
V
1.2VSS
V
−0.2VS
V
S
IIH
High-level input current (LVTTL inputs)
VIH = 2.0V
-15
15
μA
IIL
Low-level input current (LVTTL inputs)
VIL = 0.8V
-15
15
μA
VIKL
Input Clamp Voltage (LVTTL inputs)
IIN = -18 mA
-1.5
IOS
Differential short-circuit output current
Figure 6
-43
V
43
mA
M-LVDS Receiver
VIT+
Positive-going differential input voltage threshold
See Function Tables
VIT−
Negative-going differential input voltage threshold
See Function Tables
VOH
High-level output voltage
IOH = −8mA
VOL
Low-level output voltage
IOL = 8mA
IOZ
TRI-STATE output current
VO = 0V or 3.6V
IOSR
Short circuit Rrceiver output current (LVTTL Output) VO = 0V
Type 1
20
50
mV
Type 2
94
150
mV
Type 1
Type 2
3
−50
20
mV
50
94
mV
2.4
2.7
V
0.28
−10
-90
-48
0.4
V
10
μA
mA
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DS91D180/DS91C180
ESD Ratings:
(HBM 1.5kΩ, 100pF)
Absolute Maximum Ratings (Note 1)
DS91D180/DS91C180
Symbol
Parameter
Conditions
Min
Typ
Max
Units
32
µA
+20
µA
M-LVDS Bus (Input and Output) Pins
IA, IY
IB, IZ
Receiver input or driver high-impedance output
current
Receiver input or driver high-impedance output
current
VA,Y = 3.8V, VB,Z = 1.2V,
DE = GND
VA,Y = 0V or 2.4V, VB,Z = 1.2V, DE
= GND
−20
VA,Y = −1.4V, VB,Z = 1.2V,
DE = GND
−32
VB,Z = 3.8V, VA,Y = 1.2V,
DE = GND
VB,Z = 0V or 2.4V, VA,Y = 1.2V, DE
= GND
−20
VB,Z = −1.4V, VA,Y = 1.2V,
DE = GND
−32
−4
IAB, IYZ
Receiver input or driver high-impedance output
differential current (IA − IB or IY − IZ)
VA,Y = VB,Z, −1.4V ≤ V ≤ 3.8V, DE
= GND
IA(OFF),
IY(OFF)
Receiver input or driver high-impedance output
power-off current
VA,Y = 3.8V, VB,Z = 1.2V,
DE = VCC = 1.5V
IB(OFF),
IZ(OFF)
Receiver input or driver high-impedance output
power-off current
µA
VA,Y = 0V or 2.4V, VB,Z = 1.2V,
DE = VCC = 1.5V
−20
VA,Y = −1.4V, VB,Z = 1.2V,
DE = VCC = 1.5V
−32
−20
VB,Z = −1.4V, VA,Y = 1.2V,
DE = VCC = 1.5V
−32
µA
+20
µA
µA
+4
µA
32
µA
+20
µA
µA
VB,Z = 3.8V, VA,Y = 1.2V,
DE = VCC = 1.5V
VB,Z = 0V or 2.4V, VA,Y = 1.2V,
DE = VCC = 1.5V
32
32
µA
+20
µA
µA
IAB(OFF),
IYZ(OFF)
Receiver input or driver high-impedance output
power-off differential current
(IA(OFF) − IB(OFF) or IY(OFF) − IZ(OFF))
VA,Y = VB,Z, −1.4V ≤ V ≤ 3.8V,
VCC = 1.5V, DE = 1.5V
CA, CB
Receiver input capacitance
VCC = OPEN
5.1
pF
CY, CZ
Driver output capacitance
8.5
pF
CAB
Receiver input differential capacitance
2.5
pF
CYZ
Driver output differential capacitance
5.5
pF
CA/B,
CY/Z
Receiver input or driver output capacitance balance
(CA/CB or CY/CZ)
1.0
−4
+4
µA
SUPPLY CURRENT (VCC)
ICCD
Driver Supply Current
RL = 50Ω, DE = VCC, RE = VCC
17
29.5
mA
ICCZ
TRI-STATE Supply Current
DE = GND, RE = VCC
7
9.0
mA
ICCR
Receiver Supply Current
DE = GND, RE = GND
14
18.5
mA
ICCB
Supply Current, Driver and Receiver Enabled
DE = VCC, RE = GND
20
29.5
mA
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4
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 3, 8)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER AC SPECIFICATION
tPLH
Differential Propagation Delay Low to High
RL = 50Ω, CL = 5 pF,
1.0
3.4
5.5
ns
tPHL
Differential Propagation Delay High to Low
CD = 0.5 pF
1.0
3.1
5.5
ns
tSKD1 (tsk(p))
Pulse Skew |tPLHD − tPHLD| (Notes 5, 9)
Figure 7 and Figure 8
300
420
ps
tSKD3
Part-to-Part Skew (Notes 6, 9)
1.9
ns
tTLH (tr)
Rise Time (Note 9)
1.0
1.8
3.0
ns
tTHL (tf)
Fall Time (Note 9)
1.0
1.8
3.0
ns
tPZH
Enable Time (Z to Active High)
RL = 50Ω, CL = 5 pF,
8
ns
tPZL
Enable Time (Z to Active Low )
CD = 0.5 pF
8
ns
tPLZ
Disable Time (Active Low to Z)
Figure 9 and Figure 10
8
ns
tPHZ
Disable Time (Active High to Z)
8
ns
tJIT
Random Jitter, RJ (Note 9)
5.5
psrms
fMAX
Maximum Data Rate
100MHz clock pattern (Note 7)
2.5
200
Mbps
RECEIVER AC SPECIFICATION
tPLH
Propagation Delay Low to High
CL = 15 pF
2.0
4.7
7.5
ns
tPHL
Propagation Delay High to Low
Figures 11, 12 and Figure 13
2.0
5.3
7.5
ns
tSKD1 (tsk(p))
Pulse Skew |tPLHD − tPHLD| (Notes 5, 9)
0.6
1.9
ns
tSKD3
Part-to-Part Skew (Notes 6, 9)
tTLH (tr)
Rise Time (Note 9)
tTHL (tf)
Fall Time (Note 9)
tPZH
Enable Time (Z to Active High)
RL = 500Ω, CL = 15 pF
tPZL
Enable Time (Z to Active Low)
Figure 14 and Figure 15
tPLZ
Disable Time (Active Low to Z)
tPHZ
Disable Time (Active High to Z)
fMAX
Maximum Data Rate
1.5
ns
0.5
1.2
3.0
ns
0.5
1.2
3.0
ns
10
ns
10
ns
10
ns
10
200
ns
Mbps
Note 1: “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 3: All typicals are given for VCC = 3.3V and TA = 25°C.
Note 4: The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
Note 5: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 6: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 7: Stimulus and fixture jitter has been subtracted.
Note 8: CL includes fixture capacitance and CD includes probe capacitance.
Note 9: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization.
5
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DS91D180/DS91C180
Switching Characteristics
DS91D180/DS91C180
Test Circuits and Waveforms
20041914
FIGURE 2. Differential Driver Test Circuit
20041924
FIGURE 3. Differential Driver Waveforms
20041922
FIGURE 4. Differential Driver Full Load Test Circuit
20041912
FIGURE 5. Differential Driver DC Open Test Circuit
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DS91D180/DS91C180
20041927
FIGURE 6. Differential Driver Short-Circuit Test Circuit
20041916
FIGURE 7. Driver Propagation Delay and Transition Time Test Circuit
20041918
FIGURE 8. Driver Propagation Delays and Transition Time Waveforms
7
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DS91D180/DS91C180
20041919
FIGURE 9. Driver TRI-STATE Delay Test Circuit
20041921
FIGURE 10. Driver TRI-STATE Delay Waveforms
20041915
FIGURE 11. Receiver Propagation Delay and Transition Time Test Circuit
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8
DS91D180/DS91C180
20041917
FIGURE 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms
20041923
FIGURE 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms
20041913
FIGURE 14. Receiver TRI-STATE Delay Test Circuit
9
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DS91D180/DS91C180
20041920
FIGURE 15. Receiver TRI-STATE Delay Waveforms
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10
DS91D180/DS91C180
Function Tables
DS91D180/DS91C180 Transmitting
Inputs
Outputs
DE
D
Z
Y
2.0V
2.0V
0.8V
2.0V
0.8V
X
L
H
Z
H
L
Z
X — Don't care condition
Z — High impedance state
DS91C180 Receiving
DS91D180 Receiving
Inputs
Output
Inputs
Output
RE
A−B
R
RE
A−B
R
0.8V
0.8V
L
0.8V
≥ +0.15V
≤ +0.05V
H
0.8V
≥ +0.05V
≤ −0.05V
H
0.8V
2.0V
0V
X
X
Z
0.8V
2.0V
0V
X
L
Z
X — Don't care condition
Z — High impedance state
L
X — Don't care condition
Z — High impedance state
DS91D180 Receiver Input Threshold Test Voltages
Applied Voltages
Resulting Differential Input
Voltage
Resulting Common-Mode
Input Voltage
Receiver
Output
VIA
VIB
VID
VIC
R
2.400V
0.000V
3.800V
3.750V
−1.400V
−1.350V
0.000V
2.400V
3.750V
3.800V
−1.350V
−1.400V
2.400V
−2.400V
0.050V
−0.050V
−0.050V
0.050V
1.200V
1.200V
3.775V
3.775V
−1.375V
−1.375V
H
L
H
L
H
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
DS91C180 Receiver Input Threshold Test Voltages
Applied Voltages
Resulting Differential Input
Voltage
Resulting Common-Mode
Input Voltage
Receiver
Output
VIA
VIB
VID
VIC
R
2.400V
0.000V
3.800V
3.800V
−1.250V
−1.350V
0.000V
2.400V
3.650V
3.750V
−1.400V
−1.400V
2.400V
−2.400V
0.150V
0.050V
0.150V
0.050V
1.200V
1.200V
3.725V
3.775V
−1.325V
−1.375V
H
L
H
L
H
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
11
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DS91D180/DS91C180
Pin Descriptions
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Pin No.
Name
1, 8
NC
Description
No connect.
2
R
3
RE
Receiver output pin
Receiver enable pin: When RE is high, the receiver is disabled. When
RE is low or open, the receiver is enabled.
4
DE
Driver enable pin: When DE is low, the driver is disabled. When DE
is high, the driver is enabled.
5
D
6, 7
GND
9
Y
Non-inverting driver output pin
10
Z
Inverting driver output pin
11
B
Inverting receiver input pin
12
A
Non-inverting receiver input pin
13, 14
VCC
Power supply pin, +3.3V ± 0.3V
Driver input pin
Ground pin
12
DS91D180/DS91C180
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS91D180TMA, DS91C180TMA
See NS package Number M14A
13
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DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair
Notes
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