LP38843 www.ti.com SNVS290C – DECEMBER 2004 – REVISED APRIL 2013 LP38843 3A Ultra Low Dropout Linear Regulators Stable with Ceramic Output Capacitors Check for Samples: LP38843 FEATURES DESCRIPTION • • The LP38843 is a high-current, fast-response regulator which can maintain output voltage regulation with minimum input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: Vbias provides voltage to drive the gate of the N-MOS power transistor, while Vin is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low Vin voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. 1 2 • • • • • • • • Ideal for Conversion From 1.8V or 1.5V Inputs Designed for use with low ESR Ceramic Capacitors 0.8V, 1.2V and 1.5V Standard Voltages Available Ultra Low Dropout Voltage (210mV at 3A typ) 1.5% Initial Output Accuracy Load Regulation of 0.1%/A (Typical) 30nA Quiescent Current in Shutdown (Typical) Low Ground Pin Current at all Loads Over Temperature/Over Current Protection Available in 5 Lead TO-220 and DDPAK/TO-263 Packages −40°C to +125°C Junction Temperature Range APPLICATIONS The fast transient response of these devices makes them suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The parts are available in TO-220 and DDPAK/TO-263 packages. • Dropout Voltage: 210 mV (typ) at 3A load current. • • • • ASIC Power Supplies In: – Desktops, Notebooks, and Graphics Cards, Servers – Gaming Set Top Boxes, Printers and Copiers Server Core and I/O Supplies DSP and FPGA Power Supplies SMPS Post-Regulator Quiescent Current: 30 mA (typ) at full load. Shutdown Current: 30 nA (typ) when S/D pin is low. Precision Output Voltage: 1.5% room temperature accuracy. TYPICAL APPLICATION CIRCUIT LP38843 IN IN BIAS 5V ± 10% 4.7 PF* BIAS 0.1 PF OUT OUT 10 PF Ceramic S/D S/D GND GND GND * Minimum value required if Tantalum capacitor is used (see Application Hints). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated LP38843 SNVS290C – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM Figure 1. TO-220, Top View Figure 2. DDPAK/TO-263, Top View PIN DESCRIPTIONS Pin Name BIAS OUTPUT GND INPUT SHUTDOWN Description The bias pin is used to provide the low current bias voltage to the chip which operates the internal circuitry and provides drive voltage for the N-FET. The regulated output voltage is connected to this pin. This is both the power and analog ground for the IC. Note that both pin three and the tab of the TO-220 and DDPAK/TO-263 packages are at ground potential. Pin three and the tab should be tied together using the PC board copper trace material and connected to circuit ground. The high current input voltage which is regulated down to the nominal output voltage must be connected to this pin. Because the bias voltage to operate the chip is provided separately, the input voltage can be as low as a few hundred millivolts above the output voltage. This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if this function is not used. BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38843 LP38843 www.ti.com SNVS290C – DECEMBER 2004 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Semiconductor Sales Office/ Distributors for availability and specifications. −65°C to +150°C Storage Temperature Range Lead Temp. (Soldering, 5 seconds) ESD Rating Human Body Model Machine Model (3) Power Dissipation 260°C (2) 2 kV 200V (4) Internally Limited VIN Supply Voltage (Survival) −0.3V to +6V VBIAS Supply Voltage (Survival) −0.3V to +7V Shutdown Input Voltage (Survival) −0.3V to +7V IOUT (Survival) Internally Limited −0.3V to +6V Output Voltage (Survival) −40°C to +150°C Junction Temperature (1) (2) (3) (4) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. The machine model is a 220 pF capacitor discharged directly into each pin. At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be assumed. θJ-A for DDPAK/TO-263 devices is approximately 35°C/W if soldered down to a copper plane which is at least 1 square inches in area. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. RECOMMENDED OPERATING CONDITIONS VIN Supply Voltage (VOUT + VDO) to 5.5V Shutdown Input Voltage 0 to +5.5V IOUT Operating Junction 3A −40°C to +125°C Temperature Range VBIAS Supply Voltage 4.5V to 5.5V VOUT 0.8V to 1.5V Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38843 3 LP38843 SNVS290C – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = 10 µF CER, COUT = 22 µF CER, CBIAS = 1 µF CER, VS/D = VBIAS. Min/Max limits are specified through testing, statistical correlation, or design. (1) Symbol VO Parameter Conditions Output Voltage Tolerance 10 mA < IL < 3A VO(NOM) + 1V ≤ VIN ≤ 5.5V 4.5V ≤ VBIAS ≤ 5.5V (3) ΔVO/ΔVIN Output Voltage Line Regulation ΔVO/ΔIL Output Voltage Load Regulation VDO Dropout Voltage IQ(VIN) Quiescent Current Drawn from VIN Supply (4) (5) MIN ISC Quiescent Current Drawn from VBIAS Supply Short-Circuit Current MAX 0.8 0.812 0.824 1.182 1.164 1.2 1.218 1.236 1.478 1.455 1.5 1.523 1.545 0.01 Units V %/V 0.1 0.4 0.6 %/A IL = 3A 210 270 500 mV 10 mA < IL < 3A 30 35 40 mA 0.06 1 30 µA 2 4 6 mA VS/D ≤ 0.3V 0.03 1 30 µA VOUT = 0V 8 VS/D ≤ 0.3V IQ(VBIAS) (2) 0.788 0.776 VO(NOM) + 1V ≤ VIN ≤ 5.5V 10 mA < IL < 3A TYP 10 mA < IL < 3A A Shutdown Input VSDT Output Turn-off Threshold Output = ON Output = OFF 0.7 0.3 0.7 Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15 IS/D S/D Input Current VS/D =1.3V 1 VS/D ≤ 0.3V −1 TO-220, No Heatsink 65 DDPAK/TO-263, 1 sq.in Copper 35 VIN = VOUT +1V, f = 120 Hz 80 VIN = VOUT + 1V, f = 1 kHz 65 VBIAS = VOUT + 3V, f = 120 Hz 58 VBIAS = VOUT + 3V, f = 1 kHz 58 θJ-A Junction to Ambient Thermal Resistance 1.3 V µs µA °C/W AC Parameters PSRR (VIN) Ripple Rejection for VIN Input Voltage PSRR (VBIAS) Ripple Rejection for VBIAS Voltage en (1) (2) (3) (4) (5) 4 Output Noise Density f = 120 Hz Output Noise Voltage VOUT = 1.5V BW = 10 Hz − 100 kHz 150 1 BW = 300 Hz − 300 kHz 90 dB µV/Hz µV (rms) If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. Typical numbers represent the most likely parametric norm for 25°C operation. Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38843 LP38843 www.ti.com SNVS290C – DECEMBER 2004 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: TJ = 25°C, CIN = 10 µF CER, COUT = 22 µF CER, CBIAS = 1 µF CER, S/D Pin is tied to VBIAS, VOUT = 1.2V, IL = 10mA, VBIAS = 5V, VIN = VOUT + 1V. Load Transient Response ILOAD (A) VBIAS (V) VBIAS Transient Response VBIAS 6 5 2 ILOAD 1 0 10 0 IL = 10 mA -10 'VOUT (mV) VOUT 'VOUT (mV) 4 VOUT = 1.2V 50 VOUT 0 VOUT = 0.8V -50 VIN = 1.7V COUT = 22 PF Cer 50 Ps/DIV ILOAD (A) 20 Ps/DIV Figure 3. Figure 4. Load Transient Response Dropout Voltage Over Temperature ILOAD 2 1 'VOUT (mV) 0 50 VOUT 0 COUT = 4.7 PF Tantalum -50 VOUT = 0.8V 50 Ps/DIV Figure 5. Figure 6. VOUT vs Temperature 1.55 1.54 1.53 1.51 PSRR (dB) VOUT (V) 1.52 1.50 1.49 1.48 1.47 1.46 1.45 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (oC) 100 90 _ 80 _ 70 _ 60 _ 50 _ 40 _ 30 _ 20 _ 10 _ 0 1000 VBIAS PSRR COUT = 4.7 PF Tantalum ILOAD = 10 mA 10000 _ 100000 _ 1000000_ FREQUENCY (Hz) Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38843 5 LP38843 SNVS290C – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TJ = 25°C, CIN = 10 µF CER, COUT = 22 µF CER, CBIAS = 1 µF CER, S/D Pin is tied to VBIAS, VOUT = 1.2V, IL = 10mA, VBIAS = 5V, VIN = VOUT + 1V. VBIAS PSRR 100 VIN PSRR 80 COUT = 4.7 PF Tantalum CBIAS = 1 PF Tantalum 90 IL = 0 80 VOUT = 1.2V PSRR (dB) PSRR (dB) 70 60 50 40 70 CBIAS = 1 PF Tantalum 60 IL = 10 mA 50 40 30 30 20 20 10 10 0 100 1000 10000 100000 0 1000 1000000 FREQUENCY (Hz) 1.8 10000 100000 1000000 FREQUENCY (Hz) Figure 9. Figure 10. Output Noise Voltage VOUT Start Up 1.6 IL = 1A 1.4 COUT = 100 PF Tant. 3 VIN 1.2 2 1.0 0.8 VOUT 1 1 0.6 0.4 1.5 VOUT = 1.2V 0 0.2 IL = 3A VOUT (V) VIN (V) NOISE (PVRMS) VOUT = 1.2V 0 0 1 100 10k 1M 5 Ps/DIV FREQUENCY (MHz) Figure 11. 6 Figure 12. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38843 LP38843 www.ti.com SNVS290C – DECEMBER 2004 – REVISED APRIL 2013 Application Hints EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. OUTPUT CAPACITOR An output capacitor is required on the LP3884X devices for loop stability. The minimum value of capacitance necessary depends on type of capacitor: if a solid Tantalum capacitor is used, the part is stable with capacitor values as low as 4.7µF. If a ceramic capacitor is used, a minimum of 22 µF of capacitance must be used (capacitance may be increased without limit). The reason a larger ceramic capacitor is required is that the output capacitor sets a pole which limits the loop bandwidth. The Tantalum capacitor has a higher ESR than the ceramic which provides more phase margin to the loop, thereby allowing the use of a smaller output capacitor because adequate phase margin can be maintained out to a higher crossover frequency. The tantalum capacitor will typically also provide faster settling time on the output after a fast changing load transient occurs, but the ceramic capacitor is superior for bypassing high frequency noise. The output capacitor must be located less than one centimeter from the output pin and returned to a clean analog ground. Care must be taken in choosing the output capacitor to ensure that sufficient capacitance is provided over the full operating temperature range. If ceramics are selected, only X7R or X5R types may be used because Z5U and Y5F types suffer severe loss of capacitance with temperature and applied voltage and may only provide 20% of their rated capacitance in operation. INPUT CAPACITOR The input capacitor is also critical to loop stability because it provides a low source impedance for the regulator. The minimum required input capacitance is 10 µF ceramic (Tantalum not recommended). The value of CIN may be increased without limit. As stated above, X5R or X7R must be used to ensure sufficient capacitance is provided. The input capacitor must be located less than one centimeter from the input pin and returned to a clean analog ground. BIAS CAPACITOR The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended). BIAS VOLTAGE The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage must be in the range of 4.5 - 5.5V to assure proper operation of the part. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage is below approximately 4V. SHUTDOWN OPERATION Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to VBIAS if not used. POWER DISSIPATION/HEATSINKING A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: PD = (VIN−VOUT)IOUT+ (VIN)IGND (1) where IGND is the operating ground current of the device. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38843 7 LP38843 SNVS290C – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax− TAmax (2) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: θJA = TRmax / PD (3) These parts are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 °C/W for TO-220 package and ≥ 60 °C/W for DDPAK/TO-263 package no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required. HEATSINKING TO-220 PACKAGE The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for DDPAK/TO-263 package. The heatsink to be used in the application should have a heatsink to ambient thermal resistance, θHA≤ θJA − θCH − θJC. (4) In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO-220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value is unknown, 2°C/W can be assumed. HEATSINKING DDPAK/TO-263 PACKAGE The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of this package is soldered to the copper plane for heat sinking. The graph below shows a curve for the θJA of DDPAK/TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. Figure 13. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 package As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W. Figure 14 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. 8 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38843 LP38843 www.ti.com SNVS290C – DECEMBER 2004 – REVISED APRIL 2013 Figure 14. Maximum power dissipation vs ambient temperature for DDPAK/TO-263 package Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38843 9 LP38843 SNVS290C – DECEMBER 2004 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 8 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LP38843 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP38843S-1.2 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP38843S -1.2 LP38843S-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38843S -1.2 LP38843S-1.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38843S -1.5 LP38843SX-1.2 NRND DDPAK/ TO-263 KTT 5 500 TBD Call TI Call TI -40 to 125 LP38843S -1.2 LP38843SX-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38843S -1.2 LP38843SX-1.5 NRND DDPAK/ TO-263 KTT 5 500 TBD Call TI Call TI -40 to 125 LP38843S -1.5 LP38843SX-1.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38843S -1.5 LP38843T-0.8/NOPB ACTIVE TO-220 KC 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38843T -0.8 LP38843T-1.2/NOPB ACTIVE TO-220 KC 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38843T -1.2 LP38843T-1.5/NOPB ACTIVE TO-220 KC 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38843T -1.5 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP38843SX-1.2 DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP38843SX-1.2/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP38843SX-1.5 DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LP38843SX-1.5/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38843SX-1.2 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP38843SX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP38843SX-1.5 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP38843SX-1.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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