MC74AC573, MC74ACT573 Octal Buffer/Line Driver with 3−State Outputs The MC74AC573/74ACT573 is a high−speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The MC74AC573/74ACT573 is functionally identical to the MC74AC373/74ACT373 but has inputs and outputs on opposite sides. http://onsemi.com MARKING DIAGRAM Features • Inputs and Outputs on Opposite Sides of Package Allowing Easy • • • • • • Interface with Microprocessors Useful as Input or Output Port for Microprocessors Functionally Identical to MC74AC373/74ACT373 3−State Outputs for Bus Interfacing Outputs Source/Sink 24 mA ′ACT573 Has TTL Compatible Inputs Pb−Free Packages are Available* MC74xxx573N AWLYYWWG 20 1 PDIP−20 N SUFFIX CASE 738 VCC O0 O1 O2 O3 O4 O5 O6 O7 LE 20 19 18 17 16 15 14 13 12 11 xxx573 AWLYYWWG 20 1 SO−20 DW SUFFIX CASE 751D 1 2 3 4 5 6 7 8 9 10 OE D0 D1 D2 D3 D4 D5 D6 D7 GND 20 1 Figure 1. Pinout 20−Lead Packages Conductors (Top View) TSSOP−20 DT SUFFIX CASE 948E PIN ASSIGNMENT PIN xxx 573 ALYW G G FUNCTION D0−D7 Data Inputs LE Latch Enable Input OE 3−State Output Enable Input O0−O7 3−State Latch Outputs 1 EIAJ−20 M SUFFIX CASE 967 D0 D1 D2 D3 D4 D5 D6 D7 LE xxx = AC or ACT A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) OE O0 O1 O2 O3 O4 O5 O6 O7 Figure 2. Logic Symbol *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 September, 2005 − Rev. 7 74xxx573 AWLYWWG 20 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Publication Order Number: MC74AC573/D MC74AC573, MC74ACT573 Functional Description TRUTH TABLE Inputs The MC74AC573/74ACT574 contains eight D−type latches with 3−state output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH−to−LOW transition of LE. The 3−state buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Outputs OE LE Dn On L H H H L H L L L L X O0 H X X Z H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before LOW−to−HIGH Transition of Clock D0 D1 D D2 D LE Q D3 D LE Q D4 D LE Q D5 D LE Q D6 D LE Q D7 D LE Q D LE Q LE Q LE OE O0 O1 NOTE: O2 O3 O4 O5 That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram http://onsemi.com 2 O6 O7 MC74AC573, MC74ACT573 MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) −0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±20 mA IOUT DC Output Sink/Source Current, per Pin ±50 mA ICC DC VCC or GND Current per Output Pin ±50 mA Tstg Storage Temperature −65 to +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage VIN, VOUT DC Input Voltage, Output Voltage (Ref. to GND) tr, tf Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs Min Typ Max Unit ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 − VCC VCC @ 3.0 V − 150 − VCC @ 4.5 V − 40 − VCC @ 5.5 V − 25 − VCC @ 4.5 V − 10 − VCC @ 5.5 V − 8.0 − − − 140 °C −40 25 85 °C V V ns/V tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH Output Current − High − − −24 mA IOL Output Current − Low − − 24 mA ns/V 1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. http://onsemi.com 3 MC74AC573, MC74ACT573 DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = −40°C to +85°C Typ VIH VIL VOH VOL Unit Conditions Guaranteed Limits Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC − 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC − 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 3.0 4.5 5.5 − − − 2.56 3.86 4.86 2.46 3.76 4.76 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 − − − 0.36 0.36 0.36 0.44 0.44 0.44 Maximum Low Level Output Voltage IOUT = −50 mA V *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA IOUT = 50 mA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 mA VI = VCC, GND IOZ Maximum 3−State Current 5.5 − ±0.5 ±5.0 mA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 − − 75 mA VOLD = 1.65 V Max 5.5 − − −75 mA VOHD = 3.85 V Min 5.5 − 8.0 80 mA VIN = VCC or GND IOLD IOHD ICC †Minimum Dynamic Output Current Maximum Quiescent Supply Current NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. http://onsemi.com 4 MC74AC573, MC74ACT573 AC CHARACTERISTICS (For Figures and Waveforms − See Section 3) Symbol VCC* (V) Parameter 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay Dn to On 3.3 5.0 2.5 2.5 − − 13.0 10.0 2.0 2.0 15.0 11.5 ns 3−5 tPHL Propagation Delay Dn to On 3.3 5.0 2.5 2.5 − − 12.0 9.5 2.0 2.0 14.0 11.0 ns 3−5 tPLH Propagation Delay LE to On 3.3 5.0 2.5 2.5 − − 13.0 9.5 2.0 2.0 15.0 11.0 ns 3−6 tPHL Propagation Delay LE to On 3.3 5.0 2.5 2.5 − − 12.0 8.5 2.0 2.0 14.0 10.0 ns 3−6 tPZH Output Enable Time 3.3 5.0 2.5 2.5 − − 11.0 9.0 2.0 2.0 12.0 10.0 ns 3−7 tPZL Output Enable Time 3.3 5.0 2.5 2.5 − − 11.0 8.5 2.0 2.0 12.5 9.5 ns 3−8 tPHZ Output Disable Time 3.3 5.0 2.5 2.5 − − 12.5 11.0 2.0 2.0 13.5 12.0 ns 3−7 tPLZ Output Disable Time 3.3 5.0 2.5 2.5 − − 9.5 8.0 2.0 2.0 10.5 9.0 ns 3−8 Unit Fig. No. *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol VCC* (V) Parameter Typ 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to LE 3.3 5.0 − − 3.5 3.0 4.0 3.5 ns 3−9 th Hold Time, HIGH or LOW Dn to LE 3.3 5.0 − − 2.0 2.0 2.0 2.0 ns 3−9 tw LE Pulse Width, HIGH 3.3 5.0 − − 6.0 4.0 7.0 5.0 ns 3−6 *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. http://onsemi.com 5 MC74AC573, MC74ACT573 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = −40°C to +85°C Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 4.5 5.5 − − 3.86 4.86 3.76 4.76 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 4.5 5.5 − − 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA VOL Maximum Low Level Output Voltage IOUT = −50 mA *VIN = VIL or VIH −24 mA IOH −24 mA V IOUT = 50 mA V IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 mA VI = VCC, GND DICCT Additional Max. ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V IOZ Maximum 3-State Current 5.5 − ±0.5 ±5.0 mA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 − − 75 mA VOLD = 1.65 V Max 5.5 − − −75 mA VOHD = 3.85 V Min 5.5 − 8.0 80 mA VIN = VCC or GND IOLD IOHD ICC †Minimum Dynamic Output Current Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. AC CHARACTERISTICS (For Figures and Waveforms − See Section 3) Symbol VCC* (V) Parameter 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. tPLH Propagation Delay Dn to On 5.0 2.5 − 10.5 2.0 12 ns 3−5 tPHL Propagation Delay Dn to On 5.0 2.5 − 10.5 2.0 12 ns 3−5 tPLH Propagation Delay LE to On 5.0 3.0 − 10.5 2.5 12 ns 3−6 tPHL Propagation Delay LE to On 5.0 2.5 − 9.5 2.0 10.5 ns 3−6 tPZH Output Enable Time 5.0 2.0 − 10 1.5 11 ns 3−7 tPZL Output Enable Time 5.0 1.5 − 9.5 1.5 10.5 ns 3−8 tPHZ Output Disable Time 5.0 2.5 − 11 1.5 12.5 ns 3−7 tPLZ Output Disable Time 5.0 1.5 − 8.5 1.0 9.5 ns 3−8 *Voltage Range 5.0 V is 5.0 V ±0.5 V. http://onsemi.com 6 MC74AC573, MC74ACT573 AC OPERATING REQUIREMENTS Symbol VCC* (V) Parameter 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to LE 5.0 − 3.0 3.5 ns 3−9 th Hold Time, HIGH or LOW Dn to LE 5.0 − 0 0 ns 3−9 tw LE Pulse Width, HIGH 5.0 − 3.5 4.0 ns 3−6 *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 5.0 pF VCC = 5.0 V CPD Power Dissipation Capacitance 25 pF VCC = 5.0 V http://onsemi.com 7 MC74AC573, MC74ACT573 ORDERING INFORMATION Package Shipping† MC74AC573N PDIP−20 18 Units / Rail MC74AC573NG PDIP−20 (Pb−Free) 18 Units / Rail MC74AC573DW SOIC−20 38 Units / Rail MC74AC573DWG SOIC−20 (Pb−Free) 38 Units / Rail MC74AC573DWR2 SOIC−20 1000 Units / Tape & Reel MC74AC573DWR2G SOIC−20 (Pb−Free) 1000 Units / Tape & Reel MC74AC573DTR2 TSSOP−20* 2500 Units / Tape & Reel MC74AC573DTR2G TSSOP−20* 2500 Units / Tape & Reel MC74AC573MEL SOEIAJ−20 2000 Units / Tape & Reel MC74AC573MELG SOEIAJ−20 (Pb−Free) 2000 Units / Tape & Reel MC74ACT573N PDIP−20 18 Units / Rail MC74ACT573NG PDIP−20 (Pb−Free) 18 Units / Rail MC74ACT573DW SOIC−20 38 Units / Rail MC74ACT573DWG SOIC−20 (Pb−Free) 38 Units / Rail MC74ACT573DWR2 SOIC−20 1000 Units / Tape & Reel MC74ACT573DWR2G SOIC−20 (Pb−Free) 1000 Units / Tape & Reel MC74ACT573DTR2 TSSOP−20* 2500 Units / Tape & Reel MC74ACT573DTR2G TSSOP−20* 2500 Units / Tape & Reel Device †For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 8 MC74AC573, MC74ACT573 PACKAGE DIMENSIONS PDIP−20 N SUFFIX 20 PIN PLASTIC DIP PACKAGE CASE 738−03 ISSUE E −A− 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C −T− K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A M M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 SO−20 DW SUFFIX 20 PIN PLASTIC SOIC PACKAGE CASE 751D−05 ISSUE G q A 20 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 9 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74AC573, MC74ACT573 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E−02 ISSUE B 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V S K K1 11 J J1 B L −U− PIN 1 IDENT ÍÍÍ ÍÍÍ ÍÍÍ SECTION N−N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C D G H DETAIL E 0.100 (0.004) −T− SEATING PLANE http://onsemi.com 10 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 1.20 −−− 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 0.047 −−− 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74AC573, MC74ACT573 PACKAGE DIMENSIONS SOEIAJ−20 M SUFFIX 20 PIN PLASTIC EIAJ PACKAGE CASE 967−01 ISSUE O 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D VIEW P e A c A1 b 0.13 (0.005) M 0.10 (0.004) http://onsemi.com 11 DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 0.81 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.032 MC74AC573, MC74ACT573 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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