LM2700Q
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LM2700Q 600kHz/1.25MHz, 2.5A, Step-up PWM DC/DC Converter
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FEATURES
DESCRIPTION
•
•
•
•
•
•
The LM2700Q is a step-up DC/DC converter with a
3.6A, 80mΩ internal switch and pin selectable
operating frequency. With the ability to produce
500mA at 8V from a single Lithium Ion battery, the
LM2700Q is an ideal part for biasing LCD displays.
The LM2700Q can be operated at switching
frequencies of 600kHz and 1.25MHz allowing for
easy filtering and low noise. An external
compensation pin gives the user flexibility in setting
frequency compensation, which makes possible the
use of small, low ESR ceramic capacitors at the
output. The LM2700Q features continuous switching
at light loads and operates with a switching quiescent
current of 2.0mA at 600kHz and 3.0mA at 1.25MHz.
The LM2700Q is available in a low profile 14-lead
TSSOP package or a 14-lead WSON package.
1
2
•
•
AEC-Q100 Grade 2 Qualified (-40°c to +105°c)
3.6A, 0.08Ω, Internal Switch
Operating Input Voltage Range of 2.2V to 12V
Input Undervoltage Protection
Adjustable Output Voltage up to 17.5V
600kHz/1.25MHz Pin Selectable Frequency
Operation
Over Temperature Protection
Small 14-Lead TSSOP or WSON Package
APPLICATIONS
•
•
•
•
•
LCD Bias Supplies
Handheld Devices
Portable Applications
GSM/CDMA Phones
Digital Cameras
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM2700Q
SNVS794A – MARCH 2012 – REVISED MARCH 2013
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Typical Application Circuit
Figure 1. 600 kHz Operation
Connection Diagram
Figure 2. 14-Lead TSSOP
Top View
PIN DESCRIPTION
2
Pin
Name
1
VC
Compensation network connection. Connected to the output of the voltage error amplifier.
Function
2
FB
Output voltage feedback input.
3
SHDN
Shutdown control input, active low.
4
AGND
Analog ground.
5
PGND
Power ground. PGND pins must be connected together directly at the part.
6
PGND
Power ground. PGND pins must be connected together directly at the part.
7
PGND
Power ground. PGND pins must be connected together directly at the part.
8
SW
Power switch input. Switch connected between SW pins and PGND pins.
9
SW
Power switch input. Switch connected between SW pins and PGND pins.
10
SW
Power switch input. Switch connected between SW pins and PGND pins.
11
NC
Pin not connected internally.
12
VIN
Analog power input.
13
FSLCT
14
NC
Switching frequency select input. VIN = 1.25MHz. Ground = 600kHz.
Connect to ground.
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Block Diagram
Detailed Description
The LM2700Q utilizes a PWM control scheme to regulate the output voltage over all load conditions. The
operation can best be understood referring to the block diagram and Figure 16 of the Operation section. At the
start of each cycle, the oscillator sets the driver logic and turns on the NMOS power device conducting current
through the inductor, cycle 1 of Figure 16 (a). During this cycle, the voltage at the VC pin controls the peak
inductor current. The VC voltage will increase with larger loads and decrease with smaller. This voltage is
compared with the summation of the SW voltage and the ramp compensation. The ramp compensation is used in
PWM architectures to eliminate the sub-harmonic oscillations that occur during duty cycles greater than 50%.
Once the summation of the ramp compensation and switch voltage equals the VC voltage, the PWM comparator
resets the driver logic turning off the NMOS power device. The inductor current then flows through the schottky
diode to the load and output capacitor, cycle 2 of Figure 16 (b). The NMOS power device is then set by the
oscillator at the end of the period and current flows through the inductor once again.
The LM2700Q has dedicated protection circuitry running during normal operation to protect the IC. The Thermal
Shutdown circuitry turns off the NMOS power device when the die temperature reaches excessive levels. The
UVP comparator protects the NMOS power device during supply power startup and shutdown to prevent
operation at voltages less than the minimum input voltage. The OVP comparator is used to prevent the output
voltage from rising at no loads allowing full PWM operation over all load conditions. The LM2700Q also features
a shutdown mode decreasing the supply current to 5µA.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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(1) (2)
Absolute Maximum Ratings
VIN
12V
SW Voltage
18V
FB Voltage
7V
VC Voltage
0.965V ≤ VC ≤ 1.565V
(3)
SHDN Voltage
FSLCT
7V
(3)
12V
Maximum Junction Temperature
Power Dissipation
150°C
(4)
Internally Limited
Lead Temperature
300°C
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
ESD Susceptibility
220°C
(5)
Human Body Model
2kV
Machine Model
(1)
200V
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
This voltage should never exceed VIN.
The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance. The maximum
allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) − TA)/θJA. Exceeding the maximum
allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin.
(2)
(3)
(4)
(5)
Operating Conditions
Operating Junction Temperature Range
(1)
−40°C to +105°C
−65°C to +150°C
Storage Temperature
Supply Voltage
2.2V to 12V
SW Voltage
(1)
17.5V
All limits ensured at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% tested or specified through statistical analysis. All limits at temperature extremes are ensured via correlation using standard
Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Electrical Characteristics
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating
Temperature Range (TJ = −40°C to +125°C) Unless otherwise specified. VIN =2.2V and IL = 0A, unless otherwise specified.
Symbol
IQ
Parameter
Quiescent Current
Typ
Max
(1)
Units
FB = 2.2V (Not Switching)
FSLCT = 0V
1.2
2
mA
FB = 2.2V (Not Switching)
FSLCT = VIN
1.3
2
mA
Conditions
Min
(1)
(2)
VSHDN = 0V
VFB
Feedback Voltage
ICL (3)
Switch Current Limit
VIN = 2.7V
%VFB/ΔVIN
Feedback Voltage Line
Regulation
2.2V ≤ VIN ≤ 12.0V
(1)
(2)
(3)
(4)
4
(4)
5
20
µA
1.2285
1.26
1.2915
V
2.55
3.6
4.3
A
0.02
0.07
%/V
All limits ensured at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% tested or specified through statistical analysis. All limits at temperature extremes are ensured via correlation using standard
Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely norm.
Duty cycle affects current limit due to ramp generator.
Current limit at 0% duty cycle. See TYPICAL PERFORMANCE section for Switch Current Limit vs. VIN
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Electrical Characteristics (continued)
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating
Temperature Range (TJ = −40°C to +125°C) Unless otherwise specified. VIN =2.2V and IL = 0A, unless otherwise specified.
Symbol
Parameter
Conditions
Min
(1)
(5)
Typ
Max
(1)
Units
0.5
40
nA
(2)
IB
FB Pin Bias Current
VIN
Input Voltage Range
gm
Error Amp Transconductance
AV
Error Amp Voltage Gain
DMAX
Maximum Duty Cycle
FSLCT = Ground
DMIN
Minimum Duty Cycle
FSLCT = Ground
15
FSLCT = VIN
30
fS
2.2
Switching Frequency
ΔI = 5µA
40
78
FSLCT = Ground
Shutdown Pin Current
135
V/V
85
%
%
600
720
kHz
1.25
1.5
MHz
VSHDN = VIN
0.008
1
VSHDN = 0V
−0.5
−1
0.02
20
µA
80
150
mΩ
Switch Leakage Current
VSW = 18V
RDSON
Switch RDSON (6)
VIN = 2.7V, ISW = 2A
ThSHDN
SHDN Threshold
Output High
UVP
µA
0.9
0.6
0.6
0.3
V
On Threshold
1.95
2.05
2.2
V
Off Threshold
1.85
1.95
2.1
V
Output Low
(5)
(6)
(7)
µmho
1
IL
θJA
V
290
480
FSLCT = VIN
ISHDN
155
12
Thermal Resistance
(7)
TSSOP, package only
150
WSON, package only
45
V
°C/W
Bias current flows into FB pin.
Does not include the bond wires. Measured directly at the die.
Refer to for more detailed thermal information and mounting techniques for the WSON and TSSOP packages.
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Typical Performance Characteristics
6
Efficiency vs. Load Current
(VOUT = 8V, fS = 600 kHz)
Efficiency vs. Load Current
(VOUT = 8V, fS = 1.25 MHz)
Figure 3.
Figure 4.
Efficiency vs. Load Current
(VOUT = 5V, fS = 600 kHz)
Efficiency vs. Load Current
(VOUT = 12V, fS = 600 kHz)
Figure 5.
Figure 6.
Switch Current Limit vs. Temperature
Switch Current Limit vs. VIN
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
RDSON vs. VIN
(ISW = 2A)
IQ vs. VIN
(600 kHz, not switching)
Figure 9.
Figure 10.
IQ vs. VIN
(600 kHz, switching)
IQ vs. VIN
(1.25 MHz, not switching)
Figure 11.
Figure 12.
IQ vs. VIN
(1.25 MHz, switching)
IQ vs. VIN
(In shutdown)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
8
Frequency vs. VIN
(600 kHz)
Frequency vs. VIN
(1.25 MHz)
Figure 15.
Figure .
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OPERATION
Figure 16. Simplified Boost Converter Diagram
(a) First Cycle of Operation (b) Second Cycle Of Operation
CONTINUOUS CONDUCTION MODE
The LM2700Q is a current-mode, PWM boost regulator. A boost regulator steps the input voltage up to a higher
output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady state),
the boost regulator operates in two cycles.
In the first cycle of operation, shown in Figure 16 (a), the transistor is closed and the diode is reverse biased.
Energy is collected in the inductor and the load current is supplied by COUT.
The second cycle is shown in Figure 16 (b). During this cycle, the transistor is open and the diode is forward
biased. The energy stored in the inductor is transferred to the load and output capacitor.
The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as:
VOUT =
VIN
1-D
, D' = (1-D) =
VIN
VOUT
where
•
•
D is the duty cycle of the switch
D and D′ will be required for design calculations
(1)
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the feedback pin and a resistor divider connected to the output as shown in
Figure 18. The feedback pin voltage is 1.26V, so the ratio of the feedback resistors sets the output voltage
according to the following equation:
VOUT - 1.26
:
RFB1 = RFB2 x
1.26
(2)
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INTRODUCTION TO COMPENSATION
Figure 17. (a) Inductor current. (b) Diode current.
The LM2700Q is a current mode PWM boost converter. The signal flow of this control scheme has two feedback
loops, one that senses switch current and one that senses output voltage.
To keep a current programmed control converter stable above duty cycles of 50%, the inductor must meet
certain criteria. The inductor, along with input and output voltage, will determine the slope of the current through
the inductor (see Figure 17 (a)). If the slope of the inductor current is too great, the circuit will be unstable above
duty cycles of 50%. A 4.7µH inductor is recommended for most 600 kHz applications, while a 2.2µH inductor
may be used for most 1.25 MHz applications. If the duty cycle is approaching the maximum of 85%, it may be
necessary to increase the inductance by as much as 2X. See Inductor and Diode Selection for more detailed
inductor sizing.
The LM2700Q provides a compensation pin (VC) to customize the voltage loop feedback. It is recommended that
a series combination of RC and CC be used for the compensation network, as shown in Figure 18. For any given
application, there exists a unique combination of RC and CC that will optimize the performance of the LM2700Q
circuit in terms of its transient response. The series combination of RC and CC introduces a pole-zero pair
according to the following equations:
fZC =
1
Hz
2SRCCC
fPC =
(3)
1
Hz
2S(RC + RO)CC
where
10
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•
RO is the output impedance of the error amplifier, approximately 850kΩ
(4)
For most applications, performance can be optimized by choosing values within the range 5kΩ ≤ RC ≤ 20kΩ (RC
can be up to 200kΩ if CC2 is used, see High Output Capacitor ESR Compensation) and 680pF ≤ CC ≤ 4.7nF.
Refer to the Applications Information section for recommended values for specific circuits and conditions. Refer
to the Compensation section for other design requirement.
COMPENSATION
This section will present a general design procedure to help insure a stable and operational circuit. The designs
in this datasheet are optimized for particular requirements. If different conversions are required, some of the
components may need to be changed to ensure stability. Below is a set of general guidelines in designing a
stable circuit for continuous conduction operation (loads greater than approximately 100mA), in most all cases
this will provide for stability during discontinuous operation as well. The power components and their effects will
be determined first, then the compensation components will be chosen to produce stability.
INDUCTOR AND DIODE SELECTION
Although the inductor sizes mentioned earlier are fine for most applications, a more exact value can be
calculated. To ensure stability at duty cycles above 50%, the inductor must have some minimum value
determined by the minimum input voltage and the maximum output voltage. This equation is:
2
L>
VINRDSON
0.144 fs
( )
( )
D -1
D'
D +1
D'
(in H)
where
•
•
•
fs is the switching frequency
D is the duty cycle
RDSON is the ON resistance of the internal switch taken Figure 9
(5)
This equation is only good for duty cycles greater than 50% (D>0.5), for duty cycles less than 50% the
recommended values may be used. The corresponding inductor current ripple as shown in Figure 17 (a) is given
by:
'iL =
VIND
2Lfs
(in Amps)
(6)
The inductor ripple current is important for a few reasons. One reason is because the peak switch current will be
the average inductor current (input current or ILOAD/D') plus ΔiL. As a side note, discontinuous operation occurs
when the inductor current falls to zero during a switching cycle, or ΔiL is greater than the average inductor
current. Therefore, continuous conduction mode occurs when ΔiL is less than the average inductor current. Care
must be taken to make sure that the switch will not reach its current limit during normal operation. The inductor
must also be sized accordingly. It should have a saturation current rating higher than the peak inductor current
expected. The output voltage ripple is also affected by the total ripple current.
The output diode for a boost regulator must be chosen correctly depending on the output voltage and the output
current. The typical current waveform for the diode in continuous conduction mode is shown in Figure 17 (b). The
diode must be rated for a reverse voltage equal to or greater than the output voltage used. The average current
rating must be greater than the maximum load current expected, and the peak current rating must be greater
than the peak inductor current. During short circuit testing, or if short circuit conditions are possible in the
application, the diode current rating must exceed the switch current limit. Using Schottky diodes with lower
forward voltage drop will decrease power dissipation and increase efficiency.
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DC GAIN AND OPEN-LOOP GAIN
Since the control stage of the converter forms a complete feedback loop with the power components, it forms a
closed-loop system that must be stabilized to avoid positive feedback and instability. A value for open-loop DC
gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover
frequency and the phase margin. A high phase margin (greater than 45°) is desired for the best stability and
transient response. For the purpose of stabilizing the LM2700Q, choosing a crossover point well below where the
right half plane zero is located will ensure sufficient phase margin. A discussion of the right half plane zero and
checking the crossover using the DC gain will follow.
INPUT AND OUTPUT CAPACITOR SELECTION
The switching action of a boost regulator causes a triangular voltage waveform at the input. A capacitor is
required to reduce the input ripple and noise for proper operation of the regulator. The size used is dependant on
the application and board layout. If the regulator will be loaded uniformly, with very little load changes, and at
lower current outputs, the input capacitor size can often be reduced. The size can also be reduced if the input of
the regulator is very close to the source output. The size will generally need to be larger for applications where
the regulator is supplying nearly the maximum rated output or if large load steps are expected. A minimum value
of 10µF should be used for the less stressful condtions while a 33µF or 47µF capacitor may be required for
higher power and dynamic loads. Larger values and/or lower ESR may be needed if the application requires very
low ripple on the input source voltage.
The choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output
voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted RESR) capacitors be used
such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require
more compensation which will be explained later on in the section. The ESR is also important because it
determines the peak to peak output voltage ripple according to the approximate equation:
ΔVOUT ≊ 2ΔiLRESR (in Volts)
(7)
A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output
capacitor you can determine a pole-zero pair introduced into the control loop by the following equations:
fP1 =
fZ1 =
1
(in Hz)
2S(RESR + RL)COUT
1
2SRESRCOUT
(8)
(in Hz)
where
•
RL is the minimum load resistance corresponding to the maximum load current
(9)
The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low
ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the High Output Capacitor
ESR Compensation section.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect
of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the
phase, subtracting another 90° in the phase plot. This can cause undesirable effects if the control loop is
influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be
designed to have a bandwidth of less than ½ the frequency of the RHP zero. This zero occurs at a frequency of:
VOUT(D')2
(in Hz)
RHPzero =
2S,LOADL
where
•
12
ILOAD is the maximum load current
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SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components RC and CC is to set a dominant low frequency pole in
the control loop. Simply choose values for RC and CC within the ranges given in the Introduction to
Compensation section to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is
determined by the equation:
fPC =
1
(in Hz)
2S(RC + RO)CC
where
•
RO is the output impedance of the error amplifier, approximately 850kΩ
(11)
Since RC is generally much less than RO, it does not have much effect on the above equation and can be
neglected until a value is chosen to set the zero fZC. fZC is created to cancel out the pole created by the output
capacitor, fP1. The output capacitor pole will shift with different load currents as shown by the equation, so setting
the zero is not exact. Determine the range of fP1 over the expected loads and then set the zero fZC to a point
approximately in the middle. The frequency of this zero is determined by:
fZC =
1
(in Hz)
2SCCRC
(12)
Now RC can be chosen with the selected value for CC. Check to make sure that the pole fPC is still in the 10Hz to
500Hz range, change each value slightly if needed to ensure both component values are in the recommended
range. After checking the design at the end of this section, these values can be changed a little more to optimize
performance if desired. This is best done in the lab on a bench, checking the load step response with different
values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should
produce a stable, high performance circuit. For improved transient response, higher values of RC should be
chosen. This will improve the overall bandwidth which makes the regulator respond more quickly to transients. If
more detail is required, or the most optimal performance is desired, refer to a more in depth discussion of
compensating current mode DC/DC switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control
loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding
another capacitor, CC2, directly from the compensation pin VC to ground, in parallel with the series combination of
RC and CC. The pole should be placed at the same frequency as fZ1, the ESR zero. The equation for this pole
follows:
1
(in Hz)
fPC2 =
2SCC2(RC //RO)
(13)
To ensure this equation is valid, and that CC2 can be used without negatively impacting the effects of RC and CC,
fPC2 must be greater than 10fZC.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP
zero. This is done by calculating the open-loop DC gain, ADC. After this value is known, you can calculate the
crossover visually by placing a −20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The
point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is
less than ½ the RHP zero, the phase margin should be high enough for stability. The phase margin can also be
improved by adding CC2 as discussed earlier in the section. The equation for ADC is given below with additional
equations required for the calculation:
gmROD'
RFB2
{[(ZcLeff)// RL]//RL} (in dB)
ADC(DB) = 20log10
RFB1 + RFB2 RDSON
(
)
(14)
2fs
Zc #
nD'
(in rad/s)
(15)
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Leff =
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L
(D')2
(16)
2mc
(no unit)
n = 1+
m1
(17)
(18)
mc ≊ 0.072fs (in V/s)
m1 #
VINRDSON
L
(in V/s)
where
•
•
•
RL is the minimum load resistance
VIN is the minimum input voltage, gm is the error amplifier transconductance found in the Electrical
Characteristics table
RDSON is the value chosen from Figure 9
(19)
LAYOUT CONSIDERATIONS
The LM2700Q uses two separate ground connections, PGND for the driver and NMOS power device and AGND
for the sensitive analog control circuitry. The AGND and PGND pins should be tied directly together at the
package. The feedback and compensation networks should be connected directly to a dedicated analog ground
plane and this ground plane must connect to the AGND pin. If no analog ground plane is available then the
ground connections of the feedback and compensation networks must tie directly to the AGND pin. Connecting
these networks to the PGND can inject noise into the system and effect performance.
The input bypass capacitor CIN, as shown in Figure 18, must be placed close to the IC. This will reduce copper
trace resistance which effects input voltage ripple of the IC. For additional input voltage filtering, a 100nF bypass
capacitor can be placed in parallel with CIN, close to the VIN pin, to shunt any high frequency noise to ground.
The output capacitor, COUT, should also be placed close to the IC. Any copper trace connections for the COUT
capacitor can increase the series resistance, which directly effects output voltage ripple. The feedback network,
resistors RFB1 and RFB2, should be kept close to the FB pin, and away from the inductor, to minimize copper
trace connections that can inject noise into the system. Trace connections made to the inductor and schottky
diode should be minimized to reduce power dissipation and increase overall efficiency. For more detail on
switching power supply layout considerations see Application Note AN-1149 (SNVA021). Layout Guidelines for
Switching Power Supplies.
Application Information
Figure 18. 600 kHz operation, 8V output
14
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SNVS794A – MARCH 2012 – REVISED MARCH 2013
Figure 19. 1.25 MHz operation, 8V output
Figure 20. 600 kHz operation, 5V output
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VIN = 3.3V, IOUT = 200mA~> 700mA ~>200mA
CH1: IOUT 0.5A/div DC Coupled
CH2: VOUT 500mV/div AC Coupled
CH3: Inductor Current 1A/div DC Coupled
20µs/div
Figure 21. Load Transient for Figure 20
Figure 22. 600 kHz operation, 12V output
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VIN = 3.3V, IOUT = 50mA~> 350mA ~>50mA
CH1: IOUT 0.5A/div DC Coupled
CH2: VOUT 500mV/div AC Coupled
CH3: Inductor Current 1A/div DC Coupled
50µs/div
Figure 23. Load Transient for Figure 22
Figure 24. Triple Output TFT Bias (600 kHz operation)
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VIN = 3.3V, IOUT = 500mA
CH1: VIN 2V/div DC Coupled
CH2: VOUT 5V/div DC Coupled
CH3: Inductor Current 500mA/div DC Coupled
1ms/div
Figure 25. Start Up Waveform for Figure 24
VIN = 3.3V, IOUT = 50mA~> 375mA ~>50mA
CH1: IOUT 0.2A/div DC Coupled
CH2: VOUT 2V/div AC Coupled
CH3: Inductor Current 1A/div DC Coupled
500µs/div
Figure 26. Load Transient for Figure 24, 8V Output
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REVISION HISTORY
Changes from Original (March 2013) to Revision A
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
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19
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
LM2700QMT-ADJ/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM2700QMTX-ADJ/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 105
2700QMT
-ADJ
2700QMT
-ADJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LM2700QMTX-ADJ/NOPB TSSOP
PW
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM2700QMTX-ADJ/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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