LM10010 VID Voltage Programmer for Point of Load Regulator General Description Features The LM10010 is a precision, digitally programmed device used to control the output voltage of a DC/DC converter. The LM10010 outputs a DC current inversely proportional to a 6bit input word. This current DAC output connects to the feedback pin of a regulator in order to adjust its output voltage to a desired range and resolution set by the user. As the 6-bit word counts up, the output voltage is adjusted higher based on the setting of the feedback resistors in the converter. The LM10010 is designed to program point of load regulators with adjustable resistor feedback networks for VID (Voltage Identification). ■ Output current accuracy (-40°C to +125°C) ■ Input voltage range: 3V to 5.5V ■ 6-bit current DAC that connects directly to the feedback node of an external regulator to provide output voltage control ■ Precision enable to support custom UVLO ■ LLP-10 3 mm x 3 mm footprint, 0.5 mm pitch ■ Compatible with the TMS320C66XX DSP Smart Reflex Technology Applications ■ ■ ■ ■ ■ Broadband, networking, and wireless communications Notebook and palmtop computers, PDAs Portable instruments Battery-powered equipment Powering digital loads with a 6-bit, 4 pin VID interface Typical Application Circuit 30156807 © 2012 Texas Instruments Incorporated 301568 SNVS717B www.ti.com LM10010 VID Voltage Programmer for Point of Load Regulator March 14, 2012 LM10010 Connection Diagram 30156808 Top View LLP-10 3mm x 3mm 0.5mm pitch Ordering Information Order Number Package Type NSC Package Drawing Package Marking Supplied As LM10010SD LLP-10 SDA10A L254B 1000 Units / Tape and Reel LM10010SDX LLP-10 SDA10A L254B 4500 Units / Tape and Reel Pin Descriptions Pin No. Name Description 1 GND Ground. 2 IDAC_OUT 3 VDD 4 EN Precision enable input. 5 NC No Connect. 6 NC No Connect. 7 VIDA VID digital input: Bit 0 when VIDS transitions low; Bit 3 when VID transitions high. 8 VIDB VID digital input: Bit 1 when VIDS transitions low; Bit 4 when VID transitions high. 9 VIDC VID digital input: Bit 2 when VIDS transitions low; Bit 5 when VID transitions high. 10 VIDS VID select line: Transition low selects lower 3 bits, Transition high selects upper 3 bits. DAP DAP Die Attach Pad. Not electrically connected to device, connect to system ground plane for reduced thermal resistance. www.ti.com Output current DAC that connects to the feedback node of the regulator. Positive supply input. 2 Operating Ratings If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VDD VDD, EN, IDAC_OUT VIDA, VIDB, VIDC, VIDS ESD Rating (Note 2) Human Body Model Storage Temperature Junction Temperature 3.0V to 5.5V IDAC_OUT -0.3V to 6V -0.3V to 6V 2 kV -65°C to +150°C +150°C -0.3V to VDD-1.75V VIDA, VIDB, VIDC, VIDS -0.3V to 5.5V EN -0.3V to 5.5V Junction Temperature −40°C to +125°C Ambient Temperature −40°C to +125°C 40°C/W LLP-10 Thermal Resistance (θJA) (Note 3) Electrical Characteristics Limits in standard type are for TJ = 25°C only. Limits appearing in boldface type apply over the full operating junction temperature range (-40°C < TJ < +125°C). Unless otherwise noted, specifications apply to the Typical Application Circuit. See (Note 4). Symbol Parameter Conditions Min. Typ. Max. Units VDD=5.0V, VEN=2.0V 250 280 µA VDD=5.0V, VEN=2.0V, IFS 340 VDD=5.0V, VEN=0.0V 45 70 µA 2.65 2.95 V mV Supply, UVLO, and Enable IQ UVLO VEN Quiescent current Under voltage rising threshold Under voltage falling threshold 2.2 2.45 Hysteresis 100 200 300 Enable rising threshold 1.20 1.34 1.45 V 50 100 180 mV Enable hysteresis IEN µA Enable pullup current V 2 µA IDAC ACC Accuracy Measured at full scale LSB DAC step size IFS /(26-1) 940 nA Output code At startup 46d Code Output current At startup 16 µA IFS Full-scale output current VID[5:0] = 000000b 59.2 µA INL Integral non-linearity DNL Differential non-linearity Default Offset VOUT_MAX 2 -2 % -1 0.15 1 LSB -0.25 0.06 0.25 LSB Offset current VID[5:0] = 111111b 60 Output compliance VDD-VIDAC_OUT, VDD=3V 1.3 nA 1.75 V 0.4 V VID Logic Inputs (Note 5) VIL Input voltage low VIH Input voltage high 1.1 -5 IIL Input current low IIH Input current high tDEGLITCH Input deglitch time V µA 5 3.4 t1 VIDS delay time to VID latch VIDS rising edge t2 t3 t4 Input hold time VIDA, VIDB, VIDC valid VIDS edge t5 Delay to beginning of IDAC_OUT transition Measured from VIDS rising edge 10 t6 IDAC_OUT transition time Time constant for exponential rise 40 µA µs 1 µs Input hold time VIDA, VIDB, VIDC valid VIDS edge 20 µs VIDS delay time to VID latch 1 µs VIDS falling edge 3 µs 20 17 µs µs www.ti.com LM10010 Absolute Maximum Ratings (Note 1) LM10010 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 3: Junction to ambient thermal resistance is highly application and board layout dependent. Specified thermal resistance values for the package specified is based on a 4-layer, 4"x3", 2/1/1/2 oz. Cu board as per JEDEC standards is used. Note 4: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 5: For VID timing, see Figure 1 Timing Diagram 30156809 FIGURE 1. Timing Diagram for LM10010 Communications www.ti.com 4 LM10010 Typical Performance Characteristics Unless otherwise specified, the following conditions apply: TJ = 25°C, VDD = 5V. All graphs show junction temperature. Supply Current (Default Startup) Supply Current (Max IDAC Current) 270 360 350 VDD=5V CURRENT (μA) CURRENT ( μA) 260 250 240 VDD=3V VDD=5V 340 330 VDD=3V 230 320 220 310 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 30156813 30156815 Supply Current (EN Low) Output Compliance to Positive Rail (VDD-VIDAC_OUT) 60 1.6 VDD=5V 50 VDD=5V VOLTAGE (V) CURRENT (μA) 1.5 40 1.3 VDD=3V VDD=3V 1.2 30 -40 -20 1.4 1.1 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 30156814 30156817 IDAC Offset Current 65 0.8 64 0.6 63 0.4 62 CURRENT (nA) GAIN ERROR (%) Gain Error 1.0 0.2 0.0 -0.2 -0.4 61 60 59 58 -0.6 57 -0.8 56 -1.0 55 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) -40 -20 30156819 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 30156818 5 www.ti.com LM10010 UVLO Thresholds EN (Enable) Threshold 1.45 1.40 Rising Rising VOLTAGE (V) VOLTAGE (V) 2.7 2.6 2.5 2.4 Falling 2.3 -40 -20 1.35 1.30 1.25 1.20 Falling 1.15 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 30156812 30156816 Differential Non-Linearity DIFFERENTIAL NON-LINEARITY (LSB) INTEGRAL NON-LINEARITY (LSB) Integral Non-Linearity 125°C 0.10 85°C 0.05 0.00 -0.05 25°C -0.10 -0.15 -40°C 0 10 20 30 40 CODES 50 60 70 -40°C 85°C 0.06 125°C 25°C 0.04 0.02 0.00 -0.02 -0.04 0 30156820 www.ti.com 0.08 10 20 30 40 CODES 50 60 70 30156821 6 LM10010 Block Diagram 30156810 FIGURE 2. LM10010 Block Diagram numerous applications with regulators from 3.0V to 5.5V supplies. A block diagram of the LM10010 is shown in Figure 2 above. Functional Description GENERAL The LM10010 is a precision current DAC used for controlling any point of load regulator with an adjustable resistor feedback network. Four communication lines are used to write to a 6-bit IDAC value. The output of the IDAC is used to send current to the feedback node of a regulator, adjusting the output voltage. With this method, it is possible to precisely control the output voltage of the regulator. An enable pin (EN) is provided to allow for a reduced quiescent current when not in use. Also, the VDD line is monitored so that an under-voltage event will shut down the device. The device is available in a 10-pad No-Pullback Leadless Leadframe Package (LLP-10). The LM10010 can be used in THEORY OF OPERATION The LM10010 can be thought of as a D/A converter, converting the VID communication to analog outputs. In this device, the output is a current DAC (IDAC_OUT), which is connected to the feedback node of a slave regulator. Therefore, all VID data words are decoded into a 6-bit current DAC output. The impedance of the feedback node at DC appears as the top feedback resistor. This is because the control loop of the slave regulator effectively maintains a constant current/voltage across the bottom feedback resistor, and creates low impedance at the VOUT node. Therefore, as more current is 7 www.ti.com LM10010 sourced into the feedback node, the more the output voltage is reduced. See Figure 3. 30156811 FIGURE 3. Output voltage is controlled via current injection into the feedback node CURRENT DAC The LM10010 current DAC is based on a low voltage bandgap reference setting a current through a precision adjustable resistor. This bandgap is trimmed for precision and gives excellent performance over temperature. The output current has a maximum full-scale range of 59.2 µA and is adjustable with the 6-bit VID word. This allows for 64 settings, with a resolution of 940 nA. The current DAC also has a slew limit to prevent abrupt changes in the output. As the VID data lines are set for the output voltage for the regulator, deglitch filters provide a small delay and the output current rises with a 1-et function that can be identified by a time constant. trimmed at final test. For applications with a different default output current at startup, please contact National Semiconductor. VID PROGRAMMING Four pins are used to communicate with the LM10010. VIDC, VIDB, and VIDA are data lines, while VIDS is a latching strobe that programs in the LM10010 data. As shown in the Timing Diagram in Figure 1, the falling edge of VIDS latches in the data from VIDC, VIDB, and VIDA as the lower three LSB of the IDAC value. After a minimum hold time, the rising edge of VIDS latches in the data from VIDC, VIDB, and VIDA as the upper three LSB of the IDAC value. Internally, a delay on VIDS allows for the setting of all VID lines simultaneously. The VID data word is set so that the lowest output current is seen at the highest VID data word (59.2 µA at a code of 0d). Conversely, the lowest current is seen at the highest VID data word (0 µA at 63d). During VID operation with the regulator, this will translate to the lowest output voltage with the lowest VID word, and the highest output voltage with the highest VID word. The communications pins can be used with a low voltage microcontroller, with a maximum VIL of 0.4V and a minimum VIH of 1.1V. Upon startup, the IDAC is set at a code of 46d, which translates to approximately 16 µA. This default startup value is ENABLE PIN AND UVLO The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.34V (typical). The EN pin has 100 mV of hysteresis and will disable the output when the enable voltage falls below 1.24V (typical). If EN is not used, it can be left open, and will be pulled high by an internal 2 µA current source. Since the enable pin has a precise turn-on threshold it can be used along with an external resistor divider network from VIN to configure the device to turn-on at a precise input voltage. The LM10010 has a built-in under-voltage lockout (UVLO) protection circuit that keeps the device from operating until the input voltage reaches 2.65V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the device from responding to power-on glitches during startup. Note that the enable and the UVLO are functionally the same as a reset. Bringing the device back from a low enable setting or from a VDD under-voltage event will reset the device back to its startup default setting. www.ti.com DEGLITCH TIME The four digital input pins all have deglitch filters which prevent transient noise from affecting the operation of the LM10010. These filters will also impart a small delay to the digital signal. On the VIDS latching signal, there is an additional delay. As mentioned previously, this allows for the VID data lines and the VIDS strobe to be set simultaneously without the need for setup time. 8 DESIGN EXAMPLE In this example, an LM21215A-1 is used as the buck regulator to provide CVDD to the TMS320C6670 or TMS320C6678 from 0.7V to 1.1V and an output current of up to 15A. The LM10010 in conjunction with VID control from the DSP, pro- 30156823 FIGURE 4. Typical Application Circuit SETTING THE VOUT RANGE AND LSB Looking at the Typical Application Circuit in Figure 4, the following equation defines VOUT of a given regulator (valid for VOUT > VFB): (2) Based on the desired default VOUT (with IDAC_OUT = 0 µA), RFB2 can be solved from Eq. 1 above. EXAMPLE SOLUTION Assuming a 400 mV output range, 64 VID codes, and an IDAC LSB of 0.940 µA, it is desired to have a VOUT with an LSB of 6.4 mV and a default value of 1.1V using an LM21215A-1 regulator: (1) Here, the output voltage is a function of the resistor divider from RFB1 and RFB2. Additionally, there is a current supplied by the LM10010 that helps drive the feedback resistor RFB2, thus lowering the necessary current supplied through RFB1, and lowering VOUT. The change in the output voltage can be analyzed based on the resolution of the current DAC from the LM10010 compared to the desired resolution of the output swing of the regulator. RFB1 is designed to provide the desired LSB for VOUT with the equation: (3) (4) (5) 9 www.ti.com LM10010 vides control of the output voltage within this range with 6 bits of resolution. For this example, the 400 mV of voltage range translates to a 6.4 mV resolution in the control of the regulator output voltage. In this calculation, 1% resistor values are used. A schematic for this example is shown in the circuit of Figure 4. Application Information LM10010 PC BOARD GUIDELINES The following guidelines should be followed when designing the PC board for the LM10010: - Place the LM10010 close to the regulator feedback pin to minimize the FB trace length. - Place a small capacitor, CVDD, (1 nF) directly adjacent to the VDD and GND pins of the LM10010 to help minimize transients which may occur on the input supply line. - The high current path from the board’s input to the load and the return path should be parallel and close to each other to minimize loop inductance. - The ground connections for the various components around the LM10010 should be connected directly to each other, and to the LM10010’s GND pins, and then connected to the system ground at one point. Do not connect the various component grounds to each other through the high current ground line. - For additional information about the operation of the regulator, please consult the respective datasheet and application notes on the repective evaluation boards. (6) Using 1% resistor values, RFB1 can be set to 6.81 kΩ and RFB2 can be set to 8.06 kΩ. This will yield a regulator output range of 0.704V to 1.107V. At startup, the code of the LM10010 will be 46d (101110b) and will output a 15.97 µA. This will give an output voltage of approximately 1.0V (0.998V) when power is applied and both the LM10010 and the LM21215A-1 come out of UVLO. Of course, values calculated here will be dependent on the accuracy of the regulator, the LM10010 IDAC, and the resistor values used in the circuit. Table 1 shows the codes and some of the resultant values of the IDAC current and the corresponding regulator output voltage for the previous example. TABLE 1. VID Codes with IDAC Current and Regulator Voltage for the Example in Figure 4. VID Code IDAC Current (µA) Regulator Voltage (V) 000000b 59.20 0.7038 000001b 58.26 0.7102 000010b 57.32 0.7166 000011b 56.38 0.7230 ... 111100b 2.82 1.0878 111101b 1.88 1.0941 111110b 0.94 1.1005 111111b 0.00 1.1069 www.ti.com 10 LM10010 Physical Dimensions inches (millimeters) unless otherwise noted NS Package Number SDA10A 11 www.ti.com LM10010 VID Voltage Programmer for Point of Load Regulator Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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