Features • EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, • • • • • • • • • • • • 2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) Supports both 3.3V and 5.0V Operating Voltage Applications In-System Programmable (ISP) via Two-Wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera® FLEX®, APEX™ Devices, ORCA®, Xilinx® XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Very Low-power CMOS EEPROM Process Programmable Reset Polarity Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP Packages Emulation of Atmel’s AT24CXXX Serial EEPROMs Low-power Standby Mode High-reliability – Endurance: 100,000 Write Cycles – Data Retention: 90 Years for Industrial Parts (at 85° C) and 190 Years for Commercial Parts (at 70° C) Green (Pb/Halide-free/RoHS Compliant) Package Options Available 1. Description The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easyto-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20lead PLCC, 20-lead SOIC and 44-lead TQFP, see Table 1-1. The AT17LV series Configurators uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. These devices also support a write-protection mechanism within its programming mode. The AT17LV series configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. FPGA Configuration EEPROM Memory AT17LV65 AT17LV128 AT17LV256 AT17LV512 AT17LV010 AT17LV002 AT17LV040 3.3V and 5V System Support 2321I–CNFG–2/08 Table 1-1. AT17LV Series Packages AT17LV65/ AT17LV128/ AT17LV256 AT17LV512/ AT17LV010 AT17LV002 AT17LV040 8-lead LAP Yes Yes Yes (3) 8-lead PDIP Yes Yes – – 8-lead SOIC Yes Use 8-lead LAP(1) Use 8-lead LAP(1) (3) 20-lead PLCC Yes Yes Yes – 20-lead SOIC Yes(2) Yes(2) Yes(2) – 44-lead TQFP – – Yes Yes Package Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC package is not available for the AT17LV512/010/002 devices, it is possible to use an 8-lead LAP package instead. 2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the AT17LV512/010/002 devices. 3. Refer to the AT17Fxxx datasheet, available on the Atmel web site. 2. Pin Configuration Figure 2-1. 8-lead LAP DATA CLK (1) (WP ) RESET/OE CE Figure 2-2. 1 2 3 4 8 7 6 5 VCC SER_EN CEO (A2) GND VCC SER_EN CEO (A2) GND 8-lead PDIP DATA CLK (WP(1)) RESET/OE CE 2 8 7 6 5 8-lead SOIC DATA CLK (WP(1)) RESET/OE CE Figure 2-3. 1 2 3 4 1 2 3 4 8 7 6 5 VCC SER_EN CEO (A2) GND AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 20-lead PLCC 18 17 16 15 14 9 10 11 12 13 4 5 6 7 8 NC SER_EN NC NC (READY(2)) CEO (A2) NC GND NC NC NC CLK (WP1(2)) NC (WP(1)) RESET/OE (WP2(2)) NC CE 3 2 1 20 19 NC DATA NC VCC NC Figure 2-4. Notes: 1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. 3. The CEO feature is not available on the AT17LV65 device. Figure 2-5. 20-lead SOIC(1) NC DATA NC CLK NC RESET/OE NC CE NC GND Note: 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC NC NC SER_EN NC NC CEO (A2) NC NC NC 1. This pinout only applies to AT17LV65/128/256 devices. 3 2321I–CNFG–2/08 Figure 2-6. 20-lead SOIC(1) DATA NC CLK NC NC NC NC RESET/OE NC CE Notes: 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC NC SER_EN NC NC NC NC CEO NC GND 1. This pinout only applies to AT17LV512/010/002 devices. 2. The CEO feature is not available on the AT17LV65 device. 44 TQFP 44 43 42 41 40 39 38 37 36 35 34 NC CLK NC NC DATA NC VCC NC NC SER_EN NC Figure 2-7. 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 NC NC NC NC NC NC NC NC NC NC READY NC RESET/OE NC CE NC NC GND NC NC CEO(A2) NC 12 13 14 15 16 17 18 19 20 21 22 NC NC NC NC NC NC (WP1(1)) NC NC NC NC NC Note: 4 1. This pin is only available on AT17LV002 devices. AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 Figure 2-8. Block Diagram SER_EN WP1(2) WP2(2) POWER ON RESET (2) READY Notes: (1) 1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. 3. The CEO feature is not available on the AT17LV65 device. 5 2321I–CNFG–2/08 3. Device Description The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller. The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17LV series configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET/OE. 4. Pin Description AT17LV65/ AT17LV128/ AT17LV256 AT17LV512/ AT17LV010 AT17LV002 AT17LV040 Name I/O 8 DIP/ LAP/ SOIC DATA I/O 1 2 2 1 2 1 1 2 1 40 40 CLK I 2 4 4 2 4 3 2 4 3 43 43 WP1 I – – – – 5 – – 5 – – – RESET/OE I 3 6 6 3 6 8 3 6 8 13 13 WP2 I – 7 – – 7 – – – CE I GND 20 SOIC 20 PLCC 20 SOIC 8 DIP/ LAP/ SOIC 20 PLCC 20 SOIC 44 TQFP 44 TQFP 4 8 8 4 8 10 4 8 10 15 15 5 10 10 5 10 11 5 10 11 18 18 6 14 14 6 14 6 14 21 21 O CEO 13 13 A2 I READY O – – – – 15 – – 15 – 23 23 SER_EN I 7 17 17 7 17 18 7 17 18 35 35 8 20 20 8 20 20 8 20 20 38 38 VCC Note: 6 20 PLCC 8 DIP/ LAP – – 1. The CEO feature is not available on the AT17LV65 device. AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 4.1 DATA Three-state DATA output for configuration. Open-collector bi-directional pin for programming. 4.2 CLK Clock input. Used to increment the internal address and bit counter for reading and programming. 4.3 WP1 WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. This pin is only available on AT17LV512/010/002 devices. 4.4 RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. For most applications, RESET should be programmed active Low. This document describes the pin as RESET/OE. 4.5 WP Write protect (WP) input (when CE is Low) during programming only (SER_EN Low). When WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of the memory cannot be written. This pin is only available on AT17LV65/128/256 devices. 4.6 WP2 WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. This pin is only available on AT17LV512/010 devices. 4.7 CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN Low). 4.8 GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended. 4.9 CEO Chip Enable Output (active Low). This output goes Low when the address counter has reached its maximum value. In a daisy chain of AT17LV series devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is read again. This CEO feature is not available on the AT17LV65 device. 7 2321I–CNFG–2/08 4.10 A2 Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. 4.11 READY Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin is used. 4.12 SER_EN Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. 4.13 VCC 3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin. 5. FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications. 6. Control of Configuration Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and self-explanatory. • The DATA output of the AT17LV series configurator drives DIN of the FPGA devices. • The master FPGA CCLK output drives the CLK input of the AT17LV series configurator. • The CEO output of any AT17LV series configurator drives the CE input of the next configurator in a cascaded chain of EEPROMs. • SER_EN must be connected to VCC (except during ISP). • The READY(1) pin is available as an open-collector indicator of the device’s reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. Note: 8 1. This pin is not available for the AT17LV65/128/256 devices. AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 7. Cascading Serial Configuration EEPROMs For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level. The AT17LV65 devices do not have the CEO feature to perform cascaded configurations. 8. AT17LV Series Reset Polarity The AT17LV series configurator allows the user to program the reset polarity as either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms. 9. Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the Two-Wire serial bus. The programming is done at V CC supply only. Programming super voltages are generated inside the chip. 10. Standby Mode The AT17LV series configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the AT17LV65/128/256 configurator consumes less than 50 µA of current at 3.3V (100 µA for the AT17LV512/010 and 200 µA for the AT17LV002/040). The output remains in a high-impedance state regardless of the state of the OE input. 9 2321I–CNFG–2/08 11. Absolute Maximum Ratings* Operating Temperature................................... -40° C to +85° C *NOTICE: Storage Temperature .................................... -65° C to +150° C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Maximum Soldering Temp. (10 sec. @ 1/16 in.)............ 260° C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V 12. Operating Conditions 3.3V Symbol Description Min Max Min Max Units Commercial Supply voltage relative to GND -0° C to +70° C 3.0 3.6 4.75 5.25 V Industrial Supply voltage relative to GND -40° C to +85° C 3.0 3.6 4.5 5.5 V VCC 10 5V AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 13. DC Characteristics VCC = 3.3V ± 10% AT17LV65/ AT17LV128/ AT17LV256 AT17LV512/ AT17LV010 AT17LV002/ AT17LV040 Symbol Description Min Max Min Max Min Max Units VIH High-level Input Voltage 2.0 VCC 2.0 VCC 2.0 VCC V VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +3 mA) ICCA Supply Current, Active Mode IL Input or Output Leakage Current (VIN = VCC or GND) ICCS Supply Current, Standby Mode 2.4 2.4 2.4 V Commercial 0.4 2.4 0.4 2.4 0.4 2.4 V V Industrial -10 0.4 0.4 0.4 V 5 5 5 mA 10 µA 10 -10 10 -10 Commercial 50 100 150 µA Industrial 100 100 150 µA 14. DC Characteristics VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial AT17LV65/ AT17LV128/ AT17LV256 AT17LV512/ AT17LV010 AT17LV002/ AT17LV040 Symbol Description Min Max Min Max Min Max Units VIH High-level Input Voltage 2.0 VCC 2.0 VCC 2.0 VCC V VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +3 mA) ICCA Supply Current, Active Mode IL Input or Output Leakage Current (VIN = VCC or GND) ICCS Supply Current, Standby Mode 3.7 3.86 3.86 V Commercial 0.32 3.6 0.32 3.76 0.32 3.76 V V Industrial -10 0.37 0.37 0.37 V 10 10 10 mA 10 µA 10 -10 10 -10 Commercial 75 200 350 µA Industrial 150 200 350 µA 11 2321I–CNFG–2/08 15. AC Waveforms CE TSCE TSCE THCE RESET/OE TLC THOE THC CLK TOE TOH TCAC TDF TCE DATA TOH 16. AC Waveforms when Cascading RESET/OE CE CLK TCDF DATA FIRST BIT LAST BIT TOCK TOCE TOOE CEO TOCE 12 AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 17. AC Characteristics VCC = 3.3V ± 10% AT17LV65/128/256 Commercial Description TOE(1) OE to Data Delay 50 55 TCE(1) CE to Data Delay 60 TCAC(1) CLK to Data Delay 75 TOH Data Hold from CE, OE, or CLK TDF Max Industrial Symbol (2) Min AT17LV512/010/002/040 0 CE or OE to Data Float Delay Min Max Min Max Industrial Max Units 50 55 ns 60 55 60 ns 80 55 60 ns 0 55 Commercial 0 Min 0 55 ns 50 50 ns TLC CLK Low Time 25 25 25 25 ns THC CLK High Time 25 25 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 35 60 30 35 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 0 0 ns THOE OE High Time (guarantees counter is reset) 25 25 25 25 ns FMAX Maximum Clock Frequency Notes: 10 10 15 10 MHz 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. 18. AC Characteristics when Cascading VCC = 3.3V ± 10% AT17LV65/128/256 Commercial Symbol Description Min Max AT17LV512/010/002/040 Industrial Min Max Units 50 50 ns 60 50 55 ns CLK to Data Float Delay 60 60 TOCK (1) CLK to CEO Delay 55 TOCE (1) Min Max Industrial Max (2) TCDF Commercial Min CE to CEO Delay 55 60 35 40 ns TOOE(1) RESET/OE to CEO Delay 40 45 35 35 ns FMAX Maximum Clock Frequency 8 8 12.5 Notes: 10 MHz 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. 13 2321I–CNFG–2/08 19. AC Characteristics VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial AT17LV65/128/256 Commercial Description TOE(1) OE to Data Delay 30 35 TCE(1) CE to Data Delay 45 TCAC(1) CLK to Data Delay 50 TOH Data Hold from CE, OE, or CLK TDF Max Industrial Symbol (2) Min AT17LV512/010/002/040 0 CE or OE to Data Float Delay Min Max Min Max Industrial Max Units 30 35 ns 45 45 45 ns 55 50 50 ns 0 50 Commercial 0 Min 0 50 ns 50 50 ns TLC CLK Low Time 20 20 20 20 ns THC CLK High Time 20 20 20 20 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 35 40 20 25 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 0 0 ns THOE OE High Time (guarantees counter is reset) 20 20 20 20 ns FMAX Maximum Clock Frequency Notes: 12.5 12.5 15 15 MHz 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. 20. AC Characteristics when Cascading VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial AT17LV65/128/256 Commercial Symbol Description Min Max AT17LV512/010/002/040 Industrial Min Max Units 50 50 ns 40 35 40 ns CLK to Data Float Delay 50 50 TOCK (1) CLK to CEO Delay 35 TOCE (1) Min Max Industrial Max (2) TCDF Commercial Min CE to CEO Delay 35 35 35 35 ns TOOE(1) RESET/OE to CEO Delay 30 35 30 30 ns FMAX Maximum Clock Frequency 10 10 12.5 12.5 MHz Notes: 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. 14 AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 21. Thermal Resistance Coefficients(1) AT17LV65/ AT17LV128/ AT17LV256 AT17LV512/ AT17LV010 AT17LV002 AT17LV040 θJC [° C/W] 45 45 45 – θJA [° C/W](2) 115.71 135.71 159.60 – θJC [° C/W] 37 37 – – θJA [° C/W](2) 107 107 – – θJC [° C/W] 45 – – – θJA [° C/W](2) 150 – – – θJC [° C/W] 35 35 35 – θJA [° C/W](2) 90 90 90 – Package Type 8CN 4 Leadless Array Package (LAP) 8P3 Plastic Dual Inline Package (PDIP) 8S1 20J 20S2 44A Notes: Plastic Gull Wing Small Outline (SOIC) Plastic Leaded Chip Carrier (PLCC) Plastic Gull Wing Small Outline (SOIC) Thin Plastic Quad Flat Package (TQFP) θJC [° C/W] – θJA [° C/W](2) – θJC [° C/W] – – 17 17 θJA [° C/W](2) – – 62 62 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site. 2. Airflow = 0 ft/min. 15 2321I–CNFG–2/08 Figure 21-1. Ordering Code AT17LV65A-10PC Voltage Size (Bits) Special Pinouts Package Temperature 3.0V to 5.5V 65 = 65K A = Altera C = 8CN4 C = Commercial 128 = 128K P = 8P3 I = Industrial 256 = 256K Blank = Xilinx /Atmel/ Other N = 8S1 U = Fully Green 512 = 512K J = 20J 010 = 1M S = 20S2 002 = 2M TQ = 44A 040 = 4M BJ = 44J Package Type 8CN4 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 16 AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 22. Ordering Information 22.1 Standard Package Options Memory Size 64-Kbit(1) 128-Kbit(1) 256-Kbit(1) 512-Kbit(1) 1-Mbit(1) Ordering Code Package(2)(3) AT17LV65-10PC 8P3 AT17LV65-10NC 8S1 AT17LV65-10JC 20J AT17LV65-10PI 8P3 AT17LV65-10NI 8S1 AT17LV65-10JI 20J AT17LV128-10PC 8P3 AT17LV128-10NC 8S1 AT17LV128-10JC 20J AT17LV128-10SC 20S2 AT17LV128-10PI 8P3 AT17LV128-10NI 8S1 AT17LV128-10JI 20J AT17LV128-10SI 20S2 AT17LV256-10PC 8P3 AT17LV256-10NC 8S1 AT17LV256-10JC 20J AT17LV256-10SC 20S2 AT17LV256-10PI 8P3 AT17LV256-10NI 8S1 AT17LV256-10JI 20J AT17LV256-10SI 20S2 AT17LV512-10PC 8P3 AT17LV512-10JC 20J AT17LV512-10PI 8P3 Operation Range Industrial (-40° C to 85° C) Commercial (0° C to 70° C) Industrial (-40° C to 85° C) Commercial (0° C to 70° C) Industrial (-40° C to 85° C) Commercial (0° C to 70° C) Industrial (-40° C to 85° C) AT17LV512-10JI 20J AT17LV010-10PC 8P3 AT17LV010-10JC 20J AT17LV010-10PI 8P3 AT17LV010-10JI 20J AT17LV002-10JC 20J Commercial (0° C to 70° C) AT17LV002-10JI 20J Industrial (-40° C to 85° C) 2-Mbit(1) Notes: Commercial (0° C to 70° C) Commercial (0° C to 70° C) Industrial (-40° C to 85° C) 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics. 2. For the -10SC and -10SI packages, customers may migrate to the AT17LVXXX-10SU. 3. For the -10TQC and -10TQI packages, customers may migrate to the AT17LVXXX-10TQU. 17 2321I–CNFG–2/08 22.2 Green Package Options (Pb/Halide-free/RoHS Compliant) Memory Size 256-Kbit(1) 512-Kbit(1) 1-Mbit(1) 2-Mbit(1) 4-Mbit(1) Note: 18 Ordering Code Package AT17LV256-10CU 8CN4 AT17LV256-10JU 20J AT17LV256-10NU 8S1 AT17LV256-10PU 8P3 AT17LV256-10SU 20S2 AT17LV512-10CU 8CN4 AT17LV512-10JU 20J AT17LV010-10CU 8CN4 AT17LV010-10JU 20J AT17LV010-10PU 8P3 AT17LV002-10CU 8CN4 AT17LV002-10JU 20J AT17LV002-10SU 20S2 AT17LV002-10TQU 44A AT17LV040-10TQU 44A Operation Range Industrial (-40° C to 85° C) 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics. AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 23. Packaging Information 23.1 8CN4 – LAP Marked Pin1 Indentifier E A A1 D Side View Top View Pin1 Corner L1 0.10 mm TYP 8 1 COMMON DIMENSIONS (Unit of Measure = mm) e 7 2 6 3 b 5 4 e1 L Bottom View Note: SYMBOL MIN NOM MAX A 0.94 1.04 1.14 A1 0.30 0.34 0.38 b 0.45 0.50 0.55 D 5.89 5.99 6.09 E 5.89 5.99 6.09 e 1.27 BSC e1 1.10 REF NOTE 1 L 0.95 1.00 1.05 1 L1 1.25 1.30 1.35 1 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm 2/15/08 Package Drawing Contact: [email protected] TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27mm, Leadless Array Package (LAP) GPC DMH DRAWING NO. 8CN4 REV. D 19 2321I–CNFG–2/08 23.2 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A MIN NOM A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 SYMBOL A b2 L b3 b 4 PLCS Side View Notes: 0.210 0.100 BSC eA 0.300 BSC 0.115 NOTE 2 3 3 e L MAX 0.130 4 0.150 2 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 20 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 23.3 8S1 – SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 SYMBOL MIN NOM MAX A1 0.10 – 0.25 NOTE D SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 3/17/05 R 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. REV. 8S1 C 21 2321I–CNFG–2/08 23.4 20J – PLCC PIN NO. 1 1.14(0.045) X 45˚ 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER e E1 E D2/E2 B1 B A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 9.779 – 10.033 D1 8.890 – 9.042 E 9.779 – 10.033 E1 8.890 – 9.042 D2/E2 7.366 – 8.382 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 22 2325 Orchard Parkway San Jose, CA 95131 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 20J B AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 23.5 20S2 – SOIC 23 2321I–CNFG–2/08 23.6 44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.80 TYP 10/5/2001 R 24 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 44A B AT17LV65/128/256/512/010/002/040 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 24. Revision History Revision Level – Release Date History H – March 2006 Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI. I – February 2008 Removed -10SC, 10SI, -10TQC, -10TQI, -10BJC and -10BJI devices from ordering information. 25 2321I–CNFG–2/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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