Renesas ISL6336DIRZ Vr11.1, 6-phase pwm controller with phase dropping, droop disabled and load current monitoring feature Datasheet

DATASHEET
ISL6336D
FN8320
Rev 0.00
Oct 6, 2014
VR11.1, 6-Phase PWM Controller with Phase Dropping, Droop Disabled and Load
Current Monitoring Features
The ISL6336D controls voltage regulators by driving up to 6
interleaved synchronous-rectified buck channels in parallel.
This multiphase architecture results in multiplying channel
ripple frequency and reducing input and output ripple currents.
Lower ripple results in fewer components, lower cost, reduced
power dissipation, and smaller implementation area.
The ISL6336D utilizes Intersil’s proprietary Active Pulse
Positioning (APP), Adaptive Phase Alignment (APA)
modulation scheme, active phase adding and dropping to
achieve and maintain the extremely fast transient response
with fewer output capacitors and high efficiency from light to
full load.
The ISL6336D is designed to be completely compliant with
Intel VR11.1 specifications with exception of droop disabled. It
accurately reports the load current via the IMON pin to the
microprocessor, which sends an active low PSI# signal to the
controller at low power mode. The controller then enters 1- or
2-phase operation option to reduce magnetic core and
switching losses, yielding high efficiency at light load. After the
PSI# signal is deasserted, the dropped phase(s) are added
back to sustain heavy load transient response and efficiency.
The ISL6336D senses the output current continuously by
utilizing patented techniques to measure the voltage across
the dedicated current sense resistor or the DCR of the output
inductor. Current sensing circuits also provide the needed
signals for channel-current balancing, average overcurrent
protection and individual phase current limiting. An NTC
thermistor’s temperature is sensed via the TM pin and
internally digitized for thermal monitoring and for integrated
thermal compensation of the current sense elements.
A unity gain, differential amplifier is provided for remote
voltage sensing and completely eliminates any potential
difference between remote and local grounds. This improves
regulation and protection accuracy. The threshold-sensitive
enable input is available to accurately coordinate the start-up
of the ISL6336D with any other voltage rail. Dynamic VID™
technology allows seamless on-the-fly VID changes. The offset
pin allows accurate voltage offset settings that are
independent of VID setting.
FN8320 Rev 0.00
Oct 6, 2014
Features
• Intel VR11.1 compliant with droop disabled
• Proprietary active pulse positioning (APP) and adaptive
phase alignment (APA) modulation scheme
• Proprietary active phase adding and dropping for high light
load efficiency
• Precision multiphase core voltage regulation
- Differential remote voltage sensing
- 0.5% closed-loop system accuracy over load, line and
temperature
- Bidirectional, adjustable reference-voltage offset
• Precision resistor or DCR differential current sensing
- Accurate channel-current balancing
- Accurate load current monitoring via IMON pin
• Microprocessor voltage identification input
- Dynamic VID™ technology for VR11.1 requirement
- 8-bit VID, VR11 compatible
• Average overcurrent protection and channel current limit
• Precision overcurrent protection on IMON pin
• Thermal monitoring and overvoltage protection
• Integrated programmable temperature compensation
• Integrated open sense line protection
• 1- to 6-phase operation, coupled inductor compatibility
• Adjustable switching frequency up to 1MHz per phase
• Package option
- QFN compliant to JEDEC PUB95 MO-220 QFN - quad flat
no leads - product outline
• Pb-free (RoHS compliant)
Page 1 of 30
ISL6336D
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Modulation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM and PSI# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel-Current Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output-Voltage Offset Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
13
13
14
14
14
14
16
16
19
20
Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Current Sense Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VR_RDY Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
21
22
Thermal Monitoring (VR_HOT/VR_FAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Temperature Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integrated Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sensing Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
24
24
25
25
26
27
27
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Voltage-Regulator (VR) Design Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FN8320 Rev 0.00
Oct 6, 2014
Page 2 of 30
ISL6336D
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL6336DIRZ
PART
MARKING
TEMP. RANGE
(°C)
ISL6336D IRZ
PACKAGE
(Pb-Free)
-40 to +85
48 Ld 7x7 QFN
PKG.
DWG. #
L48.7x7
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6336D. For more information on MSL please see TB363.
TABLE 1. ISL6336x/4x FAMILY SUMMARY
INTERSIL PN
NUMBER OF PHASES
DIODE
EMULATION
DROOP
H_CPURST_N INPUT
TARGETED APPLICATIONS
ISL6336
6
Yes
Yes
No
VR11.x CPU
ISL6336A
6
No
Yes
No
VR11.x CPU
ISL6336B
6
Yes
Yes
Yes
VR11.x CPU
ISL6336D
6
No
No
No
General Purpose, Memory
ISL6334
4
Yes
Yes
No
VR11.x CPU
ISL6334A
4
No
Yes
No
VR11.x CPU
ISL6334B
4
Yes
Yes
Yes
VR11.x CPU
ISL6334C
4
No
No
Yes
VR11.x CPU
ISL6334D
4
No
No
No
General Purpose, Memory
FN8320 Rev 0.00
Oct 6, 2014
Page 3 of 30
ISL6336D
Pin Configuration
TM
VR_HOT
VR_FAN
VR_RDY
OVP
SS
FS
EN_VTT
EN_PWR
ISEN6+
ISEN6-
PWM6
ISL6336D
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
VID7
1
36 PWM3
VID6
2
35 ISEN3-
VID5
3
34 ISEN3+
VID4
4
33 ISEN1+
VID3
5
32 ISEN1-
VID2
6
31 PWM1
GND
30 PWM4
13
14
15
16
17
18
19
20
21
22
23
24
PWM5
25 PWM2
ISEN5-
26 ISEN2-
DAC 12
ISEN5+
IMON 11
VCC
27 ISEN2+
VSEN
OFS 10
TCOMP
28 ISEN4+
RGND
9
VDIFF
PSI#
FB
29 ISEN4-
APA
VID0
8
COMP
7
REF
VID1
Pin Descriptions
PIN #
PIN NAME
DESCRIPTION
1, 2, 3, 4,
5, 6, 7, 8
VID7, VID6, VID5, VID4,
VID3, VID2, VID1, VID0
These are the inputs to the internal DAC that generate the reference voltage for output regulation. All VID pins
have no internal pull-up current sources until after TD3. Connect these pins either to open-drain outputs with
external pull-up resistors or to active pull-up outputs, as high as VCC plus 0.3V.
9
PSI#
A low input signal indicates the low power mode operation of the processor. The controller drops the number of
active phases to single or 2-phase operation, according to the logic on Table 2 on page 14. The PSI# pin, SS, and
FS pins are used to program the controller in operation of noncoupled, 2-Phase coupled, or (n-x)-Phase coupled
inductors when PSI# is asserted (active low). Different cases yield different PWM output behavior on both
dropped phase(s) and remaining phase(s) as PSI# is asserted and deasserted. A high input signal pulls the
controller back to normal operation.
10
OFS
The OFS pin can be used to program a DC offset current, which will generate a DC offset voltage between the
REF and DAC pins. The offset current is generated via an external resistor and precision internal voltage
references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS
pin should be left unterminated.
11
IMON
IMON is the output pin of sensed, thermally compensated (if internal thermal compensation is used) average
current. The voltage at IMON pin is proportional to the load current and the resistor value, and internally clamped
to 1.11V plus the remote ground potential difference. If the clamped voltage (1.11V) is triggered, it will initiate the
overcurrent shutdown. By choosing the proper value for the resistor at IMON pin, the overcurrent trip level can be
set to be lower than the fixed internal overcurrent threshold. During the dynamic VID, the OCP function of this pin
is disabled to avoid false triggering. Tie it to GND if not used.
12, 13
DAC, REF
The DAC pin is the output of the precision internal DAC reference. The REF pin is the positive input of the Error
Amplifier. In typical applications, a 1kΩ, 1% resistor is used between DAC and REF to generate a precision offset
voltage. This voltage is proportional to the offset current determined by the offset resistor from OFS to ground
or VCC. A capacitor is used between REF and ground to smooth the voltage transition during Dynamic VID™
operations.
14
APA
The APA pin is used to adjust the Adaptive Phase Alignment trip level. A 50µA current source flows into this pin. A
resistor connected from this pin to COMP sets the voltage trip level. A small decoupling capacitor should be placed
in parallel with the resistor for high frequency decoupling.
FN8320 Rev 0.00
Oct 6, 2014
Page 4 of 30
ISL6336D
Pin Descriptions (Continued)
PIN #
PIN NAME
DESCRIPTION
16, 15
FB, COMP
Inverting input and output of the error amplifier respectively. FB can be connected to VDIFF through a resistor.
COMP is tied back to FB through an external R-C network to compensate the regulator.
17, 19, 18
VDIFF, VSEN, RGND
VSEN and RGND form the precision differential remote-sense amplifier. This amplifier converts the differential
voltage of the remote output to a single-ended voltage referenced to local ground. VDIFF is the amplifier’s output
and the input to the regulation and protection circuitry. Connect VSEN and RGND to the sense pins of the remote
load.
20
TCOMP
Temperature compensation scaling input. The voltage sensed on the TM pin is utilized as the temperature input to
adjust IMON and the overcurrent protection limit to effectively compensate for the temperature coefficient of the
current sense element. To implement the integrated temperature compensation, a resistor divider circuit is needed
with one resistor being connected from TCOMP to VCC of the controller and another resistor being connected from
TCOMP to GND. Changing the ratio of the resistor values will set the gain of the integrated thermal compensation.
When integrated temperature compensation function is not used, connect TCOMP to GND.
21
VCC
Supplies the power necessary to operate the chip. The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR
threshold. Connect this pin directly to a +5V supply.
22, 23,
26, 27,
28, 29,
32, 33,
34, 35,
38, 39
ISEN5+, ISEN5-,
ISEN2-, ISEN2+,
ISEN4+, ISEN4-,
ISEN1-, ISEN1+,
ISEN3+, ISEN3-,
ISEN6-, ISEN6+
The ISEN+ and ISEN- pins are current sense inputs to individual differential amplifiers. The sensed current is
used for channel current balancing and overcurrent protection. Inactive channels should have their respective
current sense inputs left open (for example, open ISEN6+ and ISEN6- for 5-phase operation).
For DCR sensing, connect each ISEN- pin to the node between the RC sense elements. Tie the ISEN+ pin to the
other end of the sense capacitor through a resistor, RISEN. The voltage across the sense capacitor is proportional
to the inductor current. Therefore, the sense current is proportional to the inductor current and scaled by the DCR
of the inductor and RISEN. To match the time delay of the internal circuit, a capacitor is needed between each
ISEN+ pin and GND, as described in “Current Sensing” on page 14.
24, 25, 30,
31, 36, 37
PWM5, PWM2, PWM4,
PWM1, PWM3, PWM6
Pulse width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number
of active channels is determined by the state of PWM2, PWM3, PWM4, PWM5 and PWM6. Tie PWM2 to VCC to
configure for 1-phase operation. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to
configure for 3-phase operation. Tie PWM5 to VCC to configure for 4-phase operation. Tie PWM6 to VCC to
configure for 5-phase operation. In addition, tie PSI# to GND to configure for single phase operation as well.
40
EN_PWR
This pin is a threshold-sensitive enable input for the controller. Connecting the 12V supply to EN_PWR through
an appropriate resistor divider provides a means to synchronize power-up of the controller and the MOSFET
driver ICs. When EN_PWR is driven above 0.875V, the ISL6336D is active depending on status of the EN_VTT,
the internal POR, and pending fault states. Driving EN_PWR below 0.745V will clear all fault states and prime
the ISL6336D to soft-start when reenabled.
41
EN_VTT
This pin is another threshold-sensitive enable input for the controller. It’s typically connected to VTT output of VTT
voltage regulator in the computer mother board. When EN_VTT is driven above 0.875V, the ISL6336D is active
depending on status of the EN_PWR, the internal POR, and pending fault states. Driving EN_VTT below 0.745V
will clear all fault states and prime the ISL6336D to soft-start when reenabled.
42
FS
Use this pin to set up the desired switching frequency. A resistor placed from FS to ground/VCC will set the
switching frequency. The relationship between the value of the resistor and the switching frequency will be
approximated by Equation 3. This pin is also used with SS and PSI# pins for phase dropping decoding (see
Table 2 on page 14).
43
SS
Use this pin to set up the desired start-up oscillator frequency. A resistor placed from SS to ground/VCC will set
up the soft-start ramp rate. The relationship between the value of the resistor and the soft-start ramp-up time
will be approximated by Equations 14 and 15. This pin is also used with FS and PSI# pins for phase dropping
decoding (see Table 2 on page 14).
44
OVP
45
VR_RDY
VR_RDY indicates that soft-start has completed and the output voltage is within the regulated range around the
VID setting. It is an open-drain logic output. When OCP or OVP occurs, VR_RDY will be pulled to low. It will also
be pulled low if the output voltage is below the undervoltage threshold.
46
VR_FAN
VR_FAN is an output pin with open-drain logic output. It will be pulled low if the measured VR temperature is less
than a certain level, and open when the measured VR temperature reaches a certain level. An external pull-up
resistor is needed.
FN8320 Rev 0.00
Oct 6, 2014
The overvoltage protection output indication pin. This pin can be pulled to VCC and is latched when an
overvoltage condition is detected. When the OVP indication is not used, keep this pin open.
Page 5 of 30
ISL6336D
Pin Descriptions (Continued)
PIN #
PIN NAME
DESCRIPTION
47
VR_HOT
VR_HOT is used as an indication of high VR temperature. It is an open-drain logic output. It will be pulled low if
the measured VR temperature is less than a certain level, and open when the measured VR temperature
reaches a certain level. An external pull-up resistor is needed.
48
TM
TM is an input pin for the VR temperature measurement. Connect this pin through an NTC thermistor to GND and
a resistor to VCC of the controller. The voltage at this pin is reverse proportional to the VR temperature. The
ISL6336D monitors the VR temperature based on the voltage at the TM pin and outputs VR_HOT and VR_FAN
signals.
GND
FN8320 Rev 0.00
Oct 6, 2014
Bias and reference ground for the IC. The bottom metal base of ISL6336D is the GND.
Page 6 of 30
ISL6336D
ISL6336D Block Diagram
VDIFF
VR_RDY
OVP
PSI#
VCC
APA
0.875V
RGND
POWER-ON
x1
VSEN
S
OVP
DRIVE
EN_VTT
RESET (POR)
R
0.875V
Q
EN_PWR
OVP
+175mV
TRI-STATE
SOFT-START
AND
FAULT LOGIC
CLOCK,
RAMP GENERATOR,
APA CONTROL
SS
OFS
OFFSET
FS
APP AND APA
MODULATOR
PWM1
APP AND APA
MODULATOR
PWM2
APP AND APA
MODULATOR
PWM3
APP AND APA
MODULATOR
PWM4
APP AND APA
MODULATOR
PWM5
APP AND APA
MODULATOR
PWM6
REF
DAC
VID7
VID6
VID5
DYNAMIC
VID
DAC
VID4
VID3
VID2
E/A
VID1
VID0
CHANNEL CURRENT
BALANCE AND
CURRENT LIMIT
COMP
CHANNEL
DETECT
ISEN1+
FB
ISEN1I_TRIP
1.11V
OC2
OC1
1
N
ISEN2+
Σ
TEMPERATURE
COMPENSATION
IMON
1.11V
CHANNEL
ISEN2-
CURRENT
ISEN3+
SENSE
ISEN3ISEN4+
I_TOT
ISEN4ISEN5+
THERMAL
MONITORING
GND
FN8320 Rev 0.00
Oct 6, 2014
TM
VR_FAN
VR_HOT
TEMPERATURE
COMPENSATION
GAIN
ISEN5ISEN6+
ISEN6-
TCOMP
Page 7 of 30
ISL6336D
Typical Application: 5-Phase VR with PSI# and No Droop
+5V
ISL6596
VCC
VIN
BOOT
UGATE
PHASE
EN
PWM
+5V
GND
+5V
LGATE
ISL6596
VCC
VIN
BOOT
UGATE
FB
GND
VSEN
GND
EN_VTT
VR_RDY
+5V
ISL6336D
VID7
ISL6596
VCC
PWM1
VID6
VID4
VID3
VID2
PWM
GND
PWM2
ISEN2ISEN2+
+5V
PWM
ISEN3+
VR_HOT
EN_PWR
TCOMP OFS FS
+5V
RT
GND
+5V
LGATE
ISL6596
+5V
VCC
SS
VIN
BOOT
UGATE
+5V
R OFS
µP
LOAD
BOOT
PHASE
EN
PWM3
ISEN3PWM6
ISEN6ISEN6+
VIN
UGATE
ISEN5ISEN5+
VR_FAN
LGATE
ISL6596
VCC
PWM5
IMON
BOOT
PHASE
EN
PWM4
ISEN4ISEN4+
VID1
VID0
PSI#
OVP
VIN
UGATE
ISEN1ISEN1+
VID5
TM
LGATE
VCC
RGND
VTT
PWM
DAC
VDIFF
PHASE
EN
COMP APA REF
R SS
VIN
EN
PWM
GND
PHASE
LGATE
NTC
FN8320 Rev 0.00
Oct 6, 2014
Page 8 of 30
ISL6336D
Typical Application - 4-Phase Couple Inductor VR with 2-Phase PSI# and No Droop
+5V
ISL6596
VCC
VIN
BOOT
UGATE
PHASE
EN
PWM
+5V
GND
+5V
LGATE
ISL6596
VCC
VIN
BOOT
UGATE
PHASE
EN
FB
COMP APA REF
VSEN
LGATE
VCC
RGND
GND
EN_VTT
VR_RDY
GND
DAC
VDIFF
VTT
PWM
ISL6336D
VID7
PWM1
VID6
ISEN1ISEN1+
VID5
VID4
VID3
VID2
+5V
PWM3
ISEN3ISEN3+
VID1
VID0
PSI#
OVP
VCC
PWM
GND
ISEN4-
+5V
ISEN4+
PWM5
ISEN5ISEN5+
PWM6
ISEN6ISEN6+
VR_HOT
TM
EN_PWR
TCOMP OFS FS
+5V
BOOT
PHASE
EN
PWM4
VR_FAN
VIN
UGATE
PWM2
ISEN2ISEN2+
IMON
ISL6596
LGATE
ISL6596
VCC
µP
LOAD
VIN
BOOT
UGATE
+5V
EN
PWM
GND
PHASE
LGATE
SS
+5V
R OFS
RT
R SS
VIN
NTC
FN8320 Rev 0.00
Oct 6, 2014
+5V +5V
Page 9 of 30
ISL6336D
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V to VCC + 0.3V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
48 Ld 7x7 QFN Package (Notes 4, 5). . . . .
29
2
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
Ambient Temperature
ISL6336DIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .2.5kV
Charged Device Model (Tested per JESD22-C101F . . . . . . . . . . . . .1.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . 100mA at +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
temperature ranges, -40°C to +85°C.
Operating Conditions: VCC = 5V, Unless Otherwise Specified. Boldface limits apply across the operating
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
VCC SUPPLY CURRENT
Nominal Supply
VCC = 5VDC; EN_PWR = 5VDC; RT = 100kΩ
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA
-
16
20
mA
Shutdown Supply
VCC = 5VDC; EN_PWR = 0VDC; RT = 100kΩ
-
14
17
mA
VCC Rising POR Threshold
4.3
4.4
4.5
V
VCC Falling POR Threshold
3.75
3.88
4.0
V
EN_PWR Rising Threshold
0.830
0.850
0.870
V
EN_PWR Falling Threshold
0.735
0.752
0.770
V
EN_VTT Rising Threshold
0.830
0.850
0.870
V
EN_VTT Falling Threshold
0.735
0.752
0.770
V
POWER-ON RESET AND ENABLE
REFERENCE VOLTAGE AND DAC
System Accuracy of ISL6336DIRZ
(VID = 1V to 1.6V, TJ = -40°C to +85°C)
(Note 7, Closed-Loop)
-0.6
-
0.6
%VID
System Accuracy of ISL6336DIRZ
(VID = 0.8V to 1V, TJ = -40°C to +85°C)
(Note 7, Closed-Loop)
-6
-
6
mV
System Accuracy of ISL6336DIRZ
(VID = 0.5V to 0.8V, TJ = -40°C to +85°C)
(Note 7, Closed-Loop)
-7
-
7
mV
VID Pull-up
After tD3
30
40
50
µA
VID Input Low Level
-
-
0.4
V
VID Input High Level
0.8
-
-
V
Max DAC Source Current
3.5
-
-
mA
100
-
-
µA
50
-
-
µA
Max DAC Sink Current
Max REF Source/Sink Current
FN8320 Rev 0.00
Oct 6, 2014
(Note 8)
Page 10 of 30
ISL6336D
Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. Boldface limits apply across the operating
temperature ranges, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
390
400
415
mV
1.574
1.60
1.635
V
PIN-ADJUSTABLE OFFSET
Voltage at OFS Pin
Offset resistor connected to ground
Voltage below VCC, offset resistor connected to VCC
OSCILLATORS
Accuracy of Switching Frequency Setting
RT = 100kΩ
225
250
275
kHz
Adjustment Range of Switching Frequency
(Note 8)
0.08
-
1.0
MHz
Soft-start Ramp Rate
RSS = 100kΩ(Notes 8, 9, 10)
-
1.563
-
mV/µs
Adjustment Range of Soft-Start Ramp Rate
(Note 8)
0.625
-
6.25
mV/µs
(Note 8)
-
1.5
-
V
Open-Loop Gain
RL = 10kΩ to ground (Note 8)
-
96
-
dB
Open-Loop Bandwidth
(Note 8)
-
80
-
MHz
Slew Rate
(Note 8)
PWM GENERATOR
Sawtooth Amplitude
ERROR AMPLIFIER
-
25
-
V/µs
Maximum Output Voltage
3.8
4.4
4.9
V
Output High Voltage at 2mA
3.6
-
-
V
Output Low Voltage at 2mA
-
-
1.6
V
-
20
-
MHz
REMOTE-SENSE AMPLIFIER (Note 8)
Bandwidth
Output High Current
VSEN - RGND = 2.5V
-500
-
500
µA
Output High Current
VSEN - RGND = 0.6
-500
-
500
µA
Sink Impedance
PWM = Low with 1mA Load
100
220
300
Ω
Source Impedance
PWM = High, Forced to 3.7V
200
320
400
Ω
Low Signal Threshold
-
-
0.4
V
High Signal Threshold
0.8
-
-
V
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 40µA;
CS Offset and Mirror Error Included, RISENx = 200Ω
36.5
-
42
µA
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA;
CS Offset and Mirror Error Included, RISENx = 200Ω
74
-
83
µA
CS Offset and Mirror Error Included, RISENx = 200Ω
96
105
117
µA
-
135
-
µA
115
129
146
µA
1.085
1.11
1.14
V
PWM OUTPUT
PSI# INPUT
CURRENT SENSE AND OVERCURRENT PROTECTION
Sensed Current Tolerance
Overcurrent Trip Level for Average Current At Normal
CCM PWM Mode (PSI# = 1)
Overcurrent Trip Level for Average Current at PSI# Mode N = 6, Drop to 1-Phase
(PSI# = 0)
Peak Current Limit for Individual Channel
IMON Clamped and OCP Trip Level
FN8320 Rev 0.00
Oct 6, 2014
Page 11 of 30
ISL6336D
Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified. Boldface limits apply across the operating
temperature ranges, -40°C to +85°C. (Continued)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
TM Input Voltage for VR_FAN Trip
38.7
39.1
39.6
%VCC
TM Input Voltage for VR_FAN Reset
44.6
45.1
45.5
%VCC
TM Input Voltage for VR_HOT Trip
32.9
33.3
33.7
%VCC
TM Input Voltage for VR_HOT Reset
38.7
39.1
39.6
%VCC
PARAMETER
TEST CONDITIONS
THERMAL MONITORING AND FAN CONTROL
Leakage Current of VR_FAN
With external pull-up resistor connected to VCC
-
-
5
µA
VR_FAN Low Voltage
With 1.24k resistor pull-up to VCC, IVR_FAN = 4mA
-
-
0.3
V
Leakage Current of VR_HOT
With external pull-up resistor connected to VCC
-
-
5
µA
VR_HOT Low Voltage
With 1.24k resistor pull-up to VCC, IVR_HOT = 4mA
-
-
0.3
V
Leakage Current of VR_RDY
With pull-up resistor externally connected to VCC
-
-
5
µA
VR_RDY Low Voltage
IVR_RDY = 4mA
-
-
0.3
V
Undervoltage Threshold
VDIFF Falling
48
50
52
%VID
VR READY AND PROTECTION MONITORS
VR_RDY Reset Voltage
VDIFF Rising
Overvoltage Protection Threshold
Before valid VID
After valid VID, the voltage above VID
Overvoltage Protection Reset Hysteresis
57
59.6
62
%VID
1.250
1.273
1.300
V
158
175
190
mV
-
100
-
mV
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
8. Limits should be considered typical and are not production tested.
9. During soft-start, VDAC rises from 0V to 1.1V first and then ramp to VID voltage after receiving valid VID.
10. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.
FN8320 Rev 0.00
Oct 6, 2014
Page 12 of 30
ISL6336D
Operation
In Equation 1, VIN and VOUT are the input and output voltages
respectively, L is the single-channel inductor value, and fSW is the
switching frequency.
Multiphase Power Conversion
Microprocessor load current profiles have changed to the point
that the advantages of multiphase power conversion are
impossible to ignore. The technical challenges associated with
producing a single-phase converter (which are both cost-effective
and thermally viable), have forced a change to the cost-saving
approach of multiphase. The ISL6336D controller helps reduce
the complexity of implementation by integrating vital functions
and requiring minimal output components. The block diagrams
on pages 7, 8, and 9 provide top level views of multiphase power
conversion using the ISL6336D controller.
Interleaving
The switching of each channel in a multiphase converter is timed
to be symmetrically out-of-phase with each of the other channels.
In a 3-phase converter, each channel switches 1/3 cycle after the
previous channel and 1/3 cycle before the following channel. As
a result, the 3-phase converter has a combined ripple frequency
3x greater than the ripple frequency of any one phase. In
addition, the peak-to-peak amplitude of the combined inductor
currents is reduced in proportion to the number of phases
(Equations 1 and 2). Increased ripple frequency and lower ripple
amplitude mean that the designer can use less per-channel
inductance and lower total output capacitance for any
performance specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3) combine
to form the AC ripple current and the DC load current. The ripple
component has 3x the ripple frequency of each individual
channel current. Each PWM pulse is terminated 1/3 of a cycle
after the PWM pulse of the previous phase. The DC components of
the inductor currents combine to feed the load.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-CAPACITOR
RMS CURRENT FOR 3-PHASE CONVERTER
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each of
the individual channels. Compare Equation 1 to the expression
for the peak-to-peak current after the summation of N
symmetrically phase-shifted inductor currents in Equation 2.
Peak-to-peak ripple current decreases by an amount proportional
to the number of channels. Output voltage ripple is a function of
capacitance, capacitor equivalent series resistance (ESR), and
inductor ripple current. Reducing the inductor ripple current
allows the designer to use fewer or less costly output capacitors.
 V IN – N V OUT  V OUT
I C, PP = ----------------------------------------------------------L f SW V
(EQ. 2)
IN
Another benefit of interleaving is to reduce input ripple current.
Input capacitance is determined in part by the maximum input
ripple current. Multiphase topologies can improve overall system
cost and size by lowering input ripple current and allowing the
designer to reduce the cost of input capacitance. The example in
Figure 2 illustrates input currents from a 3-phase converter
combining to reduce the total input ripple current.
IL1 + IL2 + IL3, 7A/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
IL2, 7A/DIV
PWM2, 5V/DIV
IL3, 7A/DIV
PWM3, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR
3-PHASE CONVERTER
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine Equation 1, which represents an
individual channel’s peak-to-peak inductor current.
 V IN – V OUT  V OUT
I PP = ----------------------------------------------------L f SW V
IN
FN8320 Rev 0.00
Oct 6, 2014
(EQ. 1)
The converter depicted in Figure 2 delivers 36A to a 1.5V load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9ARMS
input capacitor current. The single-phase converter must use an
input capacitor bank with twice the RMS current capacity as the
equivalent 3-phase converter.
Figures 23, 24 and 25 in the section entitled “Input Capacitor
Selection” on page 27 can be used to determine the input
capacitor RMS current based on load current, duty cycle, and the
number of channels. They are provided as aids in determining
the optimal input capacitor solution. Figure 26 shows the single
phase input-capacitor RMS current for comparison.
Page 13 of 30
ISL6336D
The ISL6336D adopts Intersil's proprietary Active Pulse
Positioning (APP) modulation scheme to improve transient
performance. APP control is a unique dual-edge PWM
modulation scheme with both PWM leading and trailing edges
being independently moved to give the best response to transient
loads. The PWM frequency, however, is constant and set by the
external resistor between the FS pin and GND. To further improve
the transient response, the ISL6336D also implements Intersil's
proprietary Adaptive Phase Alignment (APA) technique. APA,
with sufficiently large load step currents, can turn on all phases
together. With both APP and APA control, ISL6336D can achieve
excellent transient performance and reduce demand on the
output capacitors.
Under steady state conditions, the operation of the ISL6336D
PWM modulators appear to be that of a conventional trailing
edge modulator. Conventional analysis and design methods can
therefore be used for steady state and small signal operation.
PWM and PSI# Operation
The timing of each channel is set by the number of active
channels. The default channel setting for the ISL6336D is four.
The switching cycle is defined as the time between PWM pulse
termination signals of each channel. The cycle time of the pulse
signal is the inverse of the switching frequency set by the resistor
between the FS pin and ground. The PWM signals command the
MOSFET driver to turn on/off the channel MOSFETs.
For the default 6-channel operation, the channel firing order is
1-2-3-4-5-6. The PWM2 pulse happens 1/6 of a cycle after
PWM1, the PWM3 pulse happens 1/6 of a cycle after PWM2,
etc. In PSI# low power mode, the remaining active phase(s) is 1
and/or 4.
For 5-channel operation (PWM6 = 5V), the channel firing order is
1-2-3-4-5. In PSI# low power mode, the remaining active phase(s)
is 1 and/or 3. For 4-channel operation (PWM5 = 5V), the channel
firing order is 1-2-3-4. In PSI# low power mode, the remaining
active phase(s) is 1 and/or 3.
Connecting PWM4 to VCC selects three channel operation and
the pulse times are spaced in 1/3 cycle increments. In PSI# low
power mode, the remaining active phase(s) is 1 and/or 2. If
PWM3 is connected to VCC, two channel operation is selected
and the PWM2 pulse happens 1/2 of a cycle after PWM1 pulse.
In PSI# low power mode, the remaining active phase(s) is 1
and/or 2. If PWM2 is connected to VCC, only Channel 1 operation
is selected.
When PSI# is asserted low, indicating the low power mode
operation of the processor, the controller drops the number of
active phases according to the logic on Table 2 for high light-load
efficiency performance. SS and FS pins are used to program the
controller in operation of noncoupled, 2-phase coupled, or
(n-x)-Phase coupled inductors. Different cases yield different
PWM output behaviors on both dropped phase(s) and remaining
phase(s) as PSI# is asserted and deasserted. A high PSI# input
signal pulls the controller back to normal CCM PWM operation to
sustain an immediate heavy transient load and high efficiency.
FN8320 Rev 0.00
Oct 6, 2014
Note that “n-x” means n-x phase coupled and x-phase(s) are
uncoupled.
TABLE 2. PSI# OPERATION DECODING
PSI#
FS
SS
Non CI or (n-1) CI Drops to 1-phase
0
0
0
Non CI or (n-2) CI Drops to 2-phase
0
0
1
2-phase CI Drops to 1-phase
0
1
0
2-phase CI Drops to 2-phase
0
1
1
Normal CCM PWM Mode
1
x
x
While the controller is operational (VCC above POR, EN_VTT and
EN_PWR are both high, valid VID inputs), it can pull the PWM pins
to ~40% of VCC (~2V for 5V VCC bias) during various stages, such
as soft-start delay, phase shedding operation, or fault conditions
(OC or OV events). The matching driver's internal PWM resistor
divider can further raise the PWM potential, but not lower it
below the level set by the controller IC. Therefore, the controller's
PWM outputs are directly compatible with Intersil drivers that
require 5V PWM signal amplitudes. Drivers requiring 3.3V PWM
signal amplitudes are generally incompatible.
Switching Frequency
Switching frequency is determined by the selection of the
frequency-setting resistor, RT, which is connected from FS pin to
GND or VCC. Equation 3 and Figure 3 are provided to assist in
selecting the correct resistor value.
10
2.5X10
R T = -------------------------f SW
(EQ. 3)
where fSW is the switching frequency of each phase.
FREQUENCY-SETTING RESISTOR VALUE (RT)
PWM Modulation Scheme
250
200
150
100
50
0
100k 200k 300k 400k 500k 600k 700k 800k 900k
1M
SWITCHING FREQUENCY (Hz)
FIGURE 3. SWITCHING FREQUENCY vs RT
Current Sensing
The ISL6336D senses current continuously for fast response. The
ISL6336D supports inductor DCR sensing, or resistive sensing
techniques. The associated channel current sense amplifier uses
the ISEN inputs to reproduce a signal proportional to the inductor
current, IL. The sense current, ISEN, is proportional to the inductor
current. The sensed current is used for current balance and
overcurrent protection.
Page 14 of 30
ISL6336D
The internal circuitry, shown in Figures 4 and 5, represents one
channel of an N-channel converter. This circuitry is repeated for
each channel in the converter, but may not be active depending
on the status of the PWM2, PWM3 and PWM4 pins, as described
in “PWM and PSI# Operation” on page 14. The input bias current
of the current sensing amplifier is typically 60nA; less than 5kΩ
input impedance is preferred to minimized the offset error.
INDUCTOR DCR SENSING
An inductor’s winding is characteristic of a distributed resistance,
as measured by the DCR (Direct Current Resistance) parameter.
Consider the inductor DCR as a separate lumped quantity, as
shown in Figure 4. The channel current IL, flowing through the
inductor, will also pass through the DCR. Equation 4 shows the
S-domain equivalent voltage across the inductor VL.
(EQ. 4)
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 4.
VIN
IL  s 
L
ISL6596
DCR
+
+
R
PWM(n)
-
VC(s)
DCR
I SEN = I L  -----------------R
(EQ. 6)
ISEN
The inductor DCR value will increase as the temperature increases.
Therefore, the sensed current will increase as the temperature of
the current sense element increases. In order to compensate the
temperature effect on the sensed current signal, a Positive
Temperature Coefficient (PTC) resistor can be selected for the
sense resistor RISEN, or the integrated temperature compensation
function of ISL6336D should be utilized. The integrated
temperature compensation function is described in “External
Temperature Compensation” on page 24.
For accurate current sense, a dedicated current-sense resistor
RSENSE in series with each output inductor can serve as the
current sense element (see Figure 5). This technique is more
accurate, but reduces overall converter efficiency due to the
additional power loss on the current sense element RSENSE.
COUT
-
VL
Equation 6 shows that the ratio of the channel current to the
sensed current, ISEN, is driven by the value of the sense resistor
and the DCR of the inductor.
RESISTIVE SENSING
VOUT
INDUCTOR
Because of the internal filter at ISEN- pin, one capacitor, CT, is
needed to match the time delay between the ISEN- and ISEN+
signals. Select the proper CT to keep the time constant of RISEN
and CT (RISEN x CT) close to 27ns.
C
I
L
RSEN
RISEN(n)
In
ISL6336D INTERNAL CIRCUIT
CURRENT
SENSE
RSENSE
VR
VC(s)
C
In
ISENn-
R
ESL
+ +
ISL6336D INTERNAL CIRCUIT
L
VOUT
COUT
-
V L  s  = I L   s  L + DCR 
Therefore, the current out of ISEN+ pin, ISEN, is proportional to
the inductor current.
RISEN(n)
+
CURRENT
ISENn+
+
-
DCR
I SEN = I ------------------LR
ISEN
ISENn+
FIGURE 4. DCR SENSING CONFIGURATION
The voltage on the capacitor VC, can be shown to be proportional
to the channel current IL (see Equation 5).
L
 s  ------------+ 1   DCR  I L 
 DCR

V C  s  = -------------------------------------------------------------------- s  RC + 1 
(EQ. 5)
If the R-C network components are selected such that the RC
time constant (= R*C) matches the inductor time constant
(= L/DCR), the voltage across the capacitor VC is equal to the
voltage drop across the DCR, i.e., proportional to the channel
current.
With the internal low-offset current amplifier, the capacitor
voltage VC is replicated across the sense resistor RISEN.
FN8320 Rev 0.00
Oct 6, 2014
ISENn-
SENSE
CT
CT
R SEN
I SEN = I ----------------LR
ISEN
FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS
A current sensing resistor has a distributed parasitic inductance,
known as ESL (equivalent series inductance, typically less than
1nH) parameter. Consider the ESL as a separate lumped
quantity, as shown in Figure 5. The channel current IL, flowing
through the inductor, will also pass through the ESL. Equation 7
shows the s-domain equivalent voltage across the resistor VR.
V R  s  = I L   s  ESL + R SEN 
(EQ. 7)
A simple R-C network across the current sense resistor extracts
the RSEN voltage, as shown in Figure 5.
Page 15 of 30
ISL6336D
The voltage on the capacitor VC, can be shown to be proportional
to the channel current IL. See Equation 8.
ESL
 s  --------------- + 1   R SEN  I L 
 R

SEN
V C  s  = ------------------------------------------------------------------------ s  RC + 1 
(EQ. 8)
If the R-C network components are selected such that the RC
time constant matches the ESL-RSEN time constant (R*C =
ESL/RSEN), the voltage across the capacitor VC is equal to the
voltage drop across the RSEN, i.e., proportional to the channel
current. As an example, a typical 1mΩ sense resistor can use
R = 348 and C = 820pF for the matching. Figures 6 and 7 show
the sensed waveforms without and with matching RC when using
resistive sense.
on current sensing will not provide a fast OCP response and hurt
system reliability.
LOAD
VIMON
FIGURE 8. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
LOAD
Because of the internal filter at the ISENn- pin, one capacitor, CT,
is needed to match the time delay between the ISENn- and
ISENn+ signals. Select the proper CT to keep the time constant of
RISEN and CT (RISEN x CT) close to 27ns.
VIMON
FIGURE 9. LOAD TRANSIENT RESPONSE WHEN R-C TIME
CONSTANT IS TOO SMALL
LOAD
FIGURE 6. VOLTAGE ACROSS R WITHOUT RC
VIMON
FIGURE 10. LOAD TRANSIENT RESPONSE WHEN R-C TIME
CONSTANT IS TOO LARGE
FIGURE 7. VOLTAGE ACROSS C WITH MATCHING RC
Equation 9 shows that the ratio of the channel current to the
sensed current, ISEN, is driven by the value of the sense resistor
and the RISEN.
R SEN
I SEN = I L  -----------------R
(EQ. 9)
ISEN
L/DCR OR ESL/RSEN MATCHING
Assuming the compensator design is correct, Figure 8 shows the
expected load transient response waveforms if L/DCR or
ESL/RSEN is matching the R-C time constant. When the load
current has a square change, the IMON voltage (VIMON) without
a decoupling capacitor also has a square response. However,
there is always some PCB contact impedance of current sensing
components between the two current sensing points; it hardly
accounts into the L/DCR or ESL/RSEN matching calculation. Fine
tuning the matching is necessarily done in the board level to
improve overall transient performance and system reliability.
If the R-C timing constant is too large or too small, VC(s) will not
accurately represent real-time IOUT(s) and will worsen fault
response at the transient event. Figure 9 shows the IMON
transient voltage response when the R-C timing constant is too
small. VIMON will sag excessively upon load insertion and may
create a system failure or early overcurrent trip. Figure 10 shows
the transient response when the R-C timing constant is too large.
VIMON is sluggish in reaching its final value. The excessive delay
FN8320 Rev 0.00
Oct 6, 2014
Channel-Current Balance
The sensed current In from each active channel is summed
together and divided by the number of active channels. The
resulting average current IAVG provides a measure of the total
load current. Channel current balance is achieved by comparing
the sensed current of each channel to the average current to
make an appropriate adjustment to the PWM duty cycle of each
channel with Intersil’s patented current-balance method.
Channel current balance is essential in achieving the thermal
advantage of multiphase operation. With good current balance,
the power loss is equally dissipated over multiple devices and a
greater area.
Voltage Regulation
The compensation network shown in Figure 11 assures that the
steady-state error in the output voltage is limited only to the error
in the reference voltage (output of the DAC) and offset errors in
the OFS current source, remote-sense and error amplifiers.
Intersil specifies the guaranteed tolerance of the ISL6336D to
include the combined tolerances of each of these elements.
The output of the error amplifier, VCOMP, is compared to
sawtooth waveforms to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference voltage.
The internal and external circuitry, which control voltage
regulation, are illustrated in Figure 11.
Page 16 of 30
ISL6336D
TABLE 3. VR11 VID 8-BIT (Continued)
EXTERNAL CIRCUIT ISL6336D INTERNAL CIRCUIT
RC CC
COMP
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOLTAGE
0
0
0
0
1
0
1
0
1.55000
0
0
0
0
1
0
1
1
1.54375
0
0
0
0
1
1
0
0
1.53750
0
0
0
0
1
1
0
1
1.53125
0
0
0
0
1
1
1
0
1.52500
0
0
0
0
1
1
1
1
1.51875
0
0
0
1
0
0
0
0
1.51250
0
0
0
1
0
0
0
1
1.50625
0
0
0
1
0
0
1
0
1.50000
+
0
0
0
1
0
0
1
1
1.49375
-
0
0
0
1
0
1
0
0
1.48750
0
0
0
1
0
1
0
1
1.48125
0
0
0
1
0
1
1
0
1.47500
0
0
0
1
0
1
1
1
1.46875
0
0
0
1
1
0
0
0
1.46250
0
0
0
1
1
0
0
1
1.45625
0
0
0
1
1
0
1
0
1.45000
0
0
0
1
1
0
1
1
1.44375
0
0
0
1
1
1
0
0
1.43750
0
0
0
1
1
1
0
1
1.43125
0
0
0
1
1
1
1
0
1.42500
0
0
0
1
1
1
1
1
1.41875
0
0
1
0
0
0
0
0
1.41250
0
0
1
0
0
0
0
1
1.40625
0
0
1
0
0
0
1
0
1.40000
0
0
1
0
0
0
1
1
1.39375
0
0
1
0
0
1
0
0
1.38750
0
0
1
0
0
1
0
1
1.38125
DAC
RREF
REF
CREF
+
-
FB
VCOMP
ERROR AMPLIFIER
RFB
VDIFF
VSEN
VOUT+
RGND
VOUT-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 11. OUTPUT VOLTAGE REGULATION LOOP
The ISL6336D incorporates an internal differential remote sense
amplifier in the feedback path. The amplifier removes the
voltage error encountered when measuring the output voltage
relative to the local controller ground reference point, resulting in
a more accurate means of sensing output voltage. Connect the
microprocessor sense pins to the noninverting input, VSEN, and
inverting input, RGND, of the remote-sense amplifier. The
remote-sense output, VDIFF, is connected to the inverting input of
the error amplifier through an external resistor.
A digital-to-analog converter (DAC) generates a reference voltage
based on the state of logic signals at pins VID7 through VID0. The
DAC decodes the eight 6-bit logic signal (VID) into one of the discrete
voltages shown in Table 3. All VID pins have no internal pull-up
current sources before tD3. After tD3, each VID input offers a
minimum 30µA pull-up to an internal 2.5V source for use with opendrain outputs. The pull-up current diminishes to zero above the logic
threshold to protect voltage-sensitive output devices. External pullup resistors can augment the pull-up current sources in case
leakage into the driving device is greater than 30µA.
TABLE 3. VR11 VID 8-BIT
0
0
1
0
0
1
1
0
1.37500
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOLTAGE
0
0
1
0
0
1
1
1
1.36875
0
0
0
0
0
0
0
0
OFF
0
0
1
0
1
0
0
0
1.36250
0
0
0
0
0
0
0
1
OFF
0
0
1
0
1
0
0
1
1.35625
0
0
0
0
0
0
1
0
1.60000
0
0
1
0
1
0
1
0
1.35000
0
0
0
0
0
0
1
1
1.59375
0
0
1
0
1
0
1
1
1.34375
0
0
0
0
0
1
0
0
1.58750
0
0
1
0
1
1
0
0
1.33750
0
0
0
0
0
1
0
1
1.58125
0
0
1
0
1
1
0
1
1.33125
0
0
0
0
0
1
1
0
1.57500
0
0
1
0
1
1
1
0
1.32500
0
0
0
0
0
1
1
1
1.56875
0
0
1
0
1
1
1
1
1.31875
0
0
0
0
1
0
0
0
1.56250
0
0
1
1
0
0
0
0
1.31250
0
0
0
0
1
0
0
1
1.55625
0
0
1
1
0
0
0
1
1.30625
FN8320 Rev 0.00
Oct 6, 2014
Page 17 of 30
ISL6336D
TABLE 3. VR11 VID 8-BIT (Continued)
TABLE 3. VR11 VID 8-BIT (Continued)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOLTAGE
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOLTAGE
0
0
1
1
0
0
1
0
1.30000
0
1
0
1
1
0
1
0
1.05000
0
0
1
1
0
0
1
1
1.29375
0
1
0
1
1
0
1
1
1.04375
0
0
1
1
0
1
0
0
1.28750
0
1
0
1
1
1
0
0
1.03750
0
0
1
1
0
1
0
1
1.28125
0
1
0
1
1
1
0
1
1.03125
0
0
1
1
0
1
1
0
1.27500
0
1
0
1
1
1
1
0
1.02500
0
0
1
1
0
1
1
1
1.26875
0
1
0
1
1
1
1
1
1.01875
0
0
1
1
1
0
0
0
1.26250
0
1
1
0
0
0
0
0
1.01250
0
0
1
1
1
0
0
1
1.25625
0
1
1
0
0
0
0
1
1.00625
0
0
1
1
1
0
1
0
1.25000
0
1
1
0
0
0
1
0
1.00000
0
0
1
1
1
0
1
1
1.24375
0
1
1
0
0
0
1
1
0.99375
0
0
1
1
1
1
0
0
1.23750
0
1
1
0
0
1
0
0
0.98750
0
0
1
1
1
1
0
1
1.23125
0
1
1
0
0
1
0
1
0.98125
0
0
1
1
1
1
1
0
1.22500
0
1
1
0
0
1
1
0
0.97500
0
0
1
1
1
1
1
1
1.21875
0
1
1
0
0
1
1
1
0.96875
0
1
0
0
0
0
0
0
1.21250
0
1
1
0
1
0
0
0
0.96250
0
1
0
0
0
0
0
1
1.20625
0
1
1
0
1
0
0
1
0.95625
0
1
0
0
0
0
1
0
1.20000
0
1
1
0
1
0
1
0
0.95000
0
1
0
0
0
0
1
1
1.19375
0
1
1
0
1
0
1
1
0.94375
0
1
0
0
0
1
0
0
1.18750
0
1
1
0
1
1
0
0
0.93750
0
1
0
0
0
1
0
1
1.18125
0
1
1
0
1
1
0
1
0.93125
0
1
0
0
0
1
1
0
1.17500
0
1
1
0
1
1
1
0
0.92500
0
1
0
0
0
1
1
1
1.16875
0
1
1
0
1
1
1
1
0.91875
0
1
0
0
1
0
0
0
1.16250
0
1
1
1
0
0
0
0
0.91250
0
1
0
0
1
0
0
1
1.15625
0
1
1
1
0
0
0
1
0.90625
0
1
0
0
1
0
1
0
1.15000
0
1
1
1
0
0
1
0
0.90000
0
1
0
0
1
0
1
1
1.14375
0
1
1
1
0
0
1
1
0.89375
0
1
0
0
1
1
0
0
1.13750
0
1
1
1
0
1
0
0
0.88750
0
1
0
0
1
1
0
1
1.13125
0
1
1
1
0
1
0
1
0.88125
0
1
0
0
1
1
1
0
1.12500
0
1
1
1
0
1
1
0
0.87500
0
1
0
0
1
1
1
1
1.11875
0
1
1
1
0
1
1
1
0.86875
0
1
0
1
0
0
0
0
1.11250
0
1
1
1
1
0
0
0
0.86250
0
1
0
1
0
0
0
1
1.10625
0
1
1
1
1
0
0
1
0.85625
0
1
0
1
0
0
1
0
1.10000
0
1
1
1
1
0
1
0
0.85000
0
1
0
1
0
0
1
1
1.09375
0
1
1
1
1
0
1
1
0.84375
0
1
0
1
0
1
0
0
1.08750
0
1
1
1
1
1
0
0
0.83750
0
1
0
1
0
1
0
1
1.08125
0
1
1
1
1
1
0
1
0.83125
0
1
0
1
0
1
1
0
1.07500
0
1
1
1
1
1
1
0
0.82500
0
1
0
1
0
1
1
1
1.06875
0
1
1
1
1
1
1
1
0.81875
0
1
0
1
1
0
0
0
1.06250
1
0
0
0
0
0
0
0
0.81250
0
1
0
1
1
0
0
1
1.05625
1
0
0
0
0
0
0
1
0.80625
FN8320 Rev 0.00
Oct 6, 2014
Page 18 of 30
ISL6336D
TABLE 3. VR11 VID 8-BIT (Continued)
TABLE 3. VR11 VID 8-BIT (Continued)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOLTAGE
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VOLTAGE
1
0
0
0
0
0
1
0
0.80000
1
0
1
0
1
0
1
0
0.55000
1
0
0
0
0
0
1
1
0.79375
1
0
1
0
1
0
1
1
0.54375
1
0
0
0
0
1
0
0
0.78750
1
0
1
0
1
1
0
0
0.53750
1
0
0
0
0
1
0
1
0.78125
1
0
1
0
1
1
0
1
0.53125
1
0
0
0
0
1
1
0
0.77500
1
0
1
0
1
1
1
0
0.52500
1
0
0
0
0
1
1
1
0.76875
1
0
1
0
1
1
1
1
0.51875
1
0
0
0
1
0
0
0
0.76250
1
0
1
1
0
0
0
0
0.51250
1
0
0
0
1
0
0
1
0.75625
1
0
1
1
0
0
0
1
0.50625
1
0
0
0
1
0
1
0
0.75000
1
0
1
1
0
0
1
0
0.50000
1
0
0
0
1
0
1
1
0.74375
1
1
1
1
1
1
1
0
OFF
1
0
0
0
1
1
0
0
0.73750
1
1
1
1
1
1
1
1
OFF
1
0
0
0
1
1
0
1
0.73125
1
0
0
0
1
1
1
0
0.72500
1
0
0
0
1
1
1
1
0.71875
1
0
0
1
0
0
0
0
0.71250
1
0
0
1
0
0
0
1
0.70625
1
0
0
1
0
0
1
0
0.70000
1
0
0
1
0
0
1
1
0.69375
1
0
0
1
0
1
0
0
0.68750
1
0
0
1
0
1
0
1
0.68125
1
0
0
1
0
1
1
0
0.67500
1
0
0
1
0
1
1
1
0.66875
1
0
0
1
1
0
0
0
0.66250
1
0
0
1
1
0
0
1
0.65625
1
0
0
1
1
0
1
0
0.65000
1
0
0
1
1
0
1
1
0.64375
1
0
0
1
1
1
0
0
0.63750
1
0
0
1
1
1
0
1
0.63125
Output-Voltage Offset Programming
The ISL6336D allows the designer to accurately adjust the offset
voltage. When a resistor, ROFS, is connected between OFS to
VCC, the voltage across it is regulated to 1.6V. This causes a
proportional current (IOFS) to flow into OFS. If ROFS is connected
to ground, the voltage across it is regulated to 0.4V, and IOFS
flows out of OFS. A resistor between DAC and REF, RREF, is
selected so that the product (IOFS x ROFS) is equal to the desired
offset voltage. These functions are shown in Figure 12.
FB
DYNAMIC
VID D/A
DAC
RREF
E/A
REF
CREF
VCC
OR
GND
1.6V
+
ROFS
+
1
0
0
1
1
1
1
0
0.62500
1
0
0
1
1
1
1
1
0.61875
1
0
1
0
0
0
0
0
0.61250
FIGURE 12. OUTPUT VOLTAGE OFFSET PROGRAMMING
1
0
1
0
0
0
0
1
0.60625
1
0
1
0
0
0
1
0
0.60000
Once the desired output offset voltage has been determined, use
Equations 10 and 11 to calculate ROFS.
1
0
1
0
0
0
1
1
0.59375
For Positive Offset (connect ROFS to VCC):
1
0
1
0
0
1
0
0
0.58750
1
0
1
0
0
1
0
1
0.58125
1.6  R REF
R OFS = -----------------------------V OFFSET
1
0
1
0
0
1
1
0
0.57500
1
0
1
0
0
1
1
1
0.56875
1
0
1
0
1
0
0
0
0.56250
1
0
1
0
1
0
0
1
0.55625
FN8320 Rev 0.00
Oct 6, 2014
0.4V
VCC
-
ISL6336D
OFS
GND
(EQ. 10)
For Negative Offset (connect ROFS to GND):
0.4  R REF
R OFS = -----------------------------V OFFSET
(EQ. 11)
Page 19 of 30
ISL6336D
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-voltage
regulator to do this by making changes to the VID inputs during
regulator operation. The power management solution is required
to monitor the DAC inputs and respond to on-the-fly VID changes
in a controlled manner. Supervising the safe output voltage
transition within the DAC range of the processor without
discontinuity or disruption is a necessary function of the
core-voltage regulator.
In order to ensure the smooth transition of output voltage during
VID change, a VID step change smoothing network, composed of
RREF and CREF, as shown in Figure 12, can be used. The selection
of RREF is based on the desired offset voltage, as detailed in
“Output-Voltage Offset Programming” on page 19. The selection
of CREF is based on the time duration for 1-bit VID change and
the allowable delay time.
Assuming the microprocessor controls the VID change at 1-bit
every tVID, the relationship between the time constant of RREF
and CREF network and tVID is given by Equation 12.
C REF R REF = t VID
ISL66xx family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.875V to enable
the controller. This pin is typically connected to the output of
VTT VR.
When all conditions previously mentioned are satisfied, ISL6336D
begins the soft-start and ramps the output voltage to 1.1V first.
After remaining at 1.1V for some time, ISL6336D reads the VID
code at VID input pins. If the VID code is valid, ISL6336D will
regulate the output to the final VID setting. If the VID code is OFF
code, ISL6336D will shut down, and cycling VCC, EN_PWR or
EN_VTT is needed to restart.
ISL6336D INTERNAL CIRCUIT
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
Operation Initialization
0.875V
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6336D is
released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal poweron reset (POR) rising threshold. Once this threshold is reached,
proper operation of all aspects of the ISL6336D are guaranteed.
Hysteresis between the rising and falling thresholds assure that
once enabled, ISL6336D will not inadvertently turn off unless
the bias voltage drops substantially (see “Electrical
Specifications” table beginning on page 10).
100kΩ
EN_PWR
9.1kΩ
During dynamic VID transition and VID step-up, the overcurrent
trip point increases by 140% to avoid falsely triggering OCP
circuits, while the overvoltage trip point is set to its maximum VID
OVP trip level. If the dynamic VID occurs at PSI# asserted, the
system should exit PSI# and complete the transition, and then
resume PSI# operation 50µs after the transition.
Enable and Disable
+12V
VCC
(EQ. 12)
Prior to converter initialization, proper conditions must exist on
the enable inputs and VCC. When the conditions are met, the
controller begins soft-start. Once the output voltage is within the
proper window of operation, VR_RDY asserts logic high.
EXTERNAL CIRCUIT
+
EN_VTT
-
SOFT-START
AND
FAULT LOGIC
FIGURE 13. POWER SEQUENCING USING THRESHOLD SENSITIVE
ENABLE (EN) FUNCTION
Soft-Start
ISL6336D based VR has 4 periods during soft-start, as shown in
Figure 14. After VCC, EN_VTT and EN_PWR reach their POR/enable
thresholds, the controller will have a fixed delay period tD1. After this
delay period, the VR will begin first soft-start ramp until the output
voltage reaches 1.1V VBOOT voltage. Then, the controller will
regulate the VR voltage at 1.1V for another fixed period tD3. At the
end of tD3 period, ISL6336D reads the VID signals. If the VID code is
valid, ISL6336D will initiate the second soft-start ramp until the
voltage reaches the VID voltage minus offset voltage.
2. The ISL6336D features an enable input (EN_PWR) for power
sequencing between the controller bias voltage and another
voltage rail. The enable comparator holds the ISL6336D in
shutdown until the voltage at EN_PWR rises above 0.875V.
The enable comparator has about 130mV of hysteresis to
prevent bounce. It is important that the driver reaches its POR
level before the ISL6336D becomes enabled. The schematic
in Figure 13 demonstrates sequencing the ISL6336D with the
FN8320 Rev 0.00
Oct 6, 2014
Page 20 of 30
ISL6336D
The soft-start time is the sum of the 4 periods, as shown in
Equation 13.
resistance of the current sense element, either the DCR of the
inductor or RSENSE depending on the sensing method.
t SS = t D1 + t D2 + t D3 + t D4
The resistor from the IMON pin to GND should be chosen to
ensure that the voltage at the IMON pin is less than 1.11V under
the maximum load current. If the IMON pin voltage is higher than
1.11V, overcurrent shutdown will be triggered, as described in
“Overcurrent Protection” on page 22.
(EQ. 13)
tD1 is a fixed delay with the typical value as 1.36ms. tD3 is
determined by the fixed 85µs plus the time to obtain valid VID
voltage. If the VID is valid before the output reaches the 1.1V, the
minimum time to validate the VID input is 500ns. Therefore, the
minimum tD3 is about 86µs.
During tD2 and tD4, ISL6336D digitally controls the DAC voltage
change at 6.25mV per step. The time for each step is determined
by the frequency of the soft-start oscillator, which is defined by
the resistor RSS from SS pin to GND. The second soft-start ramp
time tD2 and tD4 can be calculated based on Equations 14
and 15:
1.1xR SS
t D2 = ------------------------  s 
6.25x25
(EQ. 14)
 V VID – 1.1 xR SS
t D4 = ------------------------------------------------  s 
6.25x25
(EQ. 15)
For example, when VID is set to 1.5V and RSS is set at 100kΩ, the
first soft-start ramp time tD2 will be 704µs and the second softstart ramp time tD4 will be 256µs.
After the DAC voltage reaches the final VID setting, VR_RDY will
be set to high with the fixed delay tD5. The typical value for tD5 is
85µs. Before the VR_RDY is released, the controller disregards
the PSI# input and always operates in normal CCM PWM mode.
A small capacitor can be placed between the IMON pin and GND
to reduce the noise impact. If this pin is not used, tie it to GND.
Fault Monitoring and Protection
The ISL6336D actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power-good indicator is provided for linking to external
system monitors. The schematic in Figure 15 outlines the
interaction between the fault monitors and the VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output which indicates
that the soft-start period is complete and the output voltage is
within the regulated range. VR_RDY is pulled low during
shutdown and releases high after a successful soft-start and a
fixed delay tD5. VR_RDY will be pulled low when an undervoltage
or overvoltage condition is detected, or the controller is disabled
by a reset from EN_PWR, EN_VTT, POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code. When
the output voltage at VSEN is below the undervoltage threshold,
VR_RDY is pulled low.
VOUT, 500mV/DIV
Overvoltage Protection
tD1
tD2
tD3 tD4
Regardless of the VR being enabled or not, the ISL6336D
overvoltage protection (OVP) circuit will be active after its POR.
The OVP thresholds are different under different operation
conditions. When VR is not enabled and during the soft-start
intervals tD1, tD2 and tD3, the OVP threshold is 1.273V. Once the
controller detects valid VID input, the OVP trip point will be
changed to DAC plus 175mV.
tD5
EN_VTT
VR_RDY
Two actions are taken by ISL6336D to protect the
microprocessor load when an overvoltage condition occurs.
500µs/DIV
FIGURE 14. SOFT-START WAVEFORMS
Current Sense Output
The current flowing out of the IMON pin is equal to the sensed
average current inside ISL6336D. In typical applications, a
resistor is placed from the IMON pin to GND to generate a
voltage, which is proportional to the load current and the resistor
value, as shown in Equation 16:
R IOUT R X
- ------------------ I LOAD
V IMON = -----------------N
R ISEN
(EQ. 16)
where VIMON is the voltage at the IMON pin, RIOUT is the resistor
between the IMON pin and GND, ILOAD is the total output current
of the converter, RISEN is the sense resistor connected to the
ISEN+ pin, N is the active channel number, and RX is the DC
FN8320 Rev 0.00
Oct 6, 2014
At the inception of an overvoltage event, all PWM outputs are
commanded low instantly (less than 20ns). This causes the
Intersil drivers to turn on the lower MOSFETs and pull the output
voltage below a level to avoid damaging the load. When the
VDIFF voltage falls below the DAC plus 75mV, PWM signals enter
a high-impedance state. The Intersil drivers respond to the
high-impedance input by turning off both upper and lower
MOSFETs. If the overvoltage condition reoccurs, ISL6336D will
again command the lower MOSFETs to turn on. The ISL6336D
will continue to protect the load in this fashion as long as the
overvoltage condition occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until ISL6336D is reset. Cycling the voltage on
EN_PWR, EN_VTT or VCC below the POR-falling threshold will
Page 21 of 30
ISL6336D
reset the controller. Cycling the VID codes will not reset the
controller.
full-load operation, so there is no thermal hazard during this kind
of operation.
VR_RDY
OUTPUT CURRENT
-
+
UV
50%
0A
DAC
VDIFF
SOFT-START, FAULT
AND CONTROL LOGIC
+
OV
-
+
105µA
-
IAVG
OC
+
OC
-
OUTPUT VOLTAGE
1.11V
0V
IMON
2ms/DIV
FIGURE 16. OVERCURRENT BEHAVIOR IN HICCUP MODE
fSW = 500kHz
VID + 0.175V
FIGURE 15. VR_RDY AND PROTECTION CIRCUITRY
Overcurrent Protection
The ISL6336D has two levels of overcurrent protection. Each
phase is protected from a sustained overcurrent condition by
limiting its peak current, while the combined phase currents are
protected on an instantaneous basis.
In instantaneous protection mode, ISL6336D utilizes the sensed
average current IAVG to detect an overcurrent condition. See
“Voltage Regulation” on page 16 for more details on how the
average current is measured. The average current is continually
compared with a constant 105µA reference current, as shown in
Figure 15. Once the average current exceeds the reference
current, a comparator triggers the converter to shutdown.
The current out of IMON pin is equal to the sensed average
current IAVG. With a resistor from IMON to GND, the voltage at
IMON will be proportional to the sensed average current and the
resistor value. The ISL6336D continuously monitors the voltage
at IMON pin. If the voltage at IMON pin is higher than 1.11V, a
comparator triggers the overcurrent shutdown. By increasing the
resistor between IMON and GND, the overcurrent protection
threshold can be adjusted to be less than 105µA. For example,
the overcurrent threshold for the sensed average current IAVG
can be set to 95µA by using a 11.8kΩ resistor from IMON to GND.
At the beginning of overcurrent shutdown, the controller places
all PWM signals in a high-impedance state within 20ns,
commanding the Intersil MOSFET driver ICs to turn off both upper
and lower MOSFETs. The system remains in this state a period of
4096 switching cycles. If the controller is still enabled at the end
of this wait period, it will attempt a soft-start. If the fault remains,
the trip-retry cycles will continue indefinitely (see Figure 16) until
either controller is disabled or the fault is cleared. Note that the
energy delivered during trip-retry cycling is much less than during
For the individual channel overcurrent protection, ISL6336D
continuously compares the sensed current signal of each
channel with the 129µA reference current. If one channel current
exceeds the reference current, ISL6336D will pull the PWM
signal of this channel to low for the rest of the switching cycle.
This PWM signal can be turned on next cycle if the sensed
channel current is less than the 129µA reference current. The
peak current limit of an individual channel will not trigger the
converter to shutdown.
Thermal Monitoring
(VR_HOT/VR_FAN)
There are two thermal signals to indicate the temperature status
of the voltage regulator: VR_HOT and VR_FAN. Both VR_FAN and
VR_HOT pins are open-drain outputs, and external pull-up
resistors are required. Those signals are valid only after the
controller is enabled.
The VR_FAN signal indicates that the temperature of the voltage
regulator is high and more cooling airflow is needed. The VR_HOT
signal can be used to inform the system that the temperature of
the voltage regulator is too high and the CPU should reduce its
power consumption. The VR_HOT signal may be tied to the CPU’s
PROC_HOT signal.
The diagram of thermal monitoring function block is shown in
Figure 17. One NTC resistor should be placed close to the power
stage of the voltage regulator to sense the operational
temperature, and one pull-up resistor is needed to form the
voltage divider for the TM pin. As the temperature of the power
stage increases, the resistance of the NTC will reduce, resulting
in the reduced voltage at the TM pin. Figure 18 shows the TM
voltage over the temperature for a typical design with a
recommended 6.8kΩ NTC (P/N: NTHS0805N02N6801 from
Vishay) and 1kΩ resistor RTM1. We recommend using those
resistors for the accurate temperature compensation.
There are two comparators with hysteresis to compare the TM
pin voltage to the fixed thresholds for VR_FAN and VR_HOT
FN8320 Rev 0.00
Oct 6, 2014
Page 22 of 30
ISL6336D
signals respectively. The VR_FAN signal is set to high when the
TM voltage is lower than 39.1% of VCC voltage, and is pulled to
GND when the TM voltage increases to above 45.1% of VCC
voltage. The VR_FAN signal is set to high when the TM voltage
goes below 33.3% of VCC voltage, and is pulled to GND when the
TM voltage goes back to above 39.1% of VCC voltage. Figure 19
shows the operation of those signals.
Based on the NTC temperature characteristics and the desired
threshold of the VR_HOT signal, the pull-up resistor RTM1 of TM
pin is given by Equation 17:
R TM1 = 2.75xR NTC  T3 
(EQ. 17)
RNTC(T3) is the NTC resistance at the VR_HOT threshold
temperature T3.
The NTC resistance at the set point T2 and release point T1 of
VR_FAN signal can be calculated as shown in Equations 18 and 19:
VCC
VR_FAN
R
0.391V
CC
TM1
°C
0.333V
CC
(EQ. 19)
Temperature Compensation
FIGURE 17. BLOCK DIAGRAM OF THERMAL MONITORING
FUNCTION
100
90
80
VTM/VCC (%)
R NTC  T1  = 1.644xR NTC  T3 
With the NTC resistance value obtained from Equations 18 and
19, the temperature value T2 and T1 can be found from the NTC
datasheet.
NTC
The ISL6336D supports inductor DCR sensing, or resistive
sensing techniques. The inductor DCR has a positive temperature
coefficient, which is about +0.385%/°C. Since the voltage across
the inductor is sensed for the output current information, the
sensed current has the same positive temperature coefficient as
the inductor DCR.
In order to obtain the correct current information, there should be
a way to correct the temperature impact on the current sense
component. The ISL6336D provides two methods: integrated
temperature compensation and external temperature
compensation.
70
60
50
40
Integrated Temperature Compensation
30
20
(EQ. 18)
VR_HOT
TM
R
R NTC  T2  = 1.267xR NTC  T3 
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 18. THE RATIO OF TM VOLTAGE TO NTC TEMPERATURE
WITH RECOMMENDED PARTS
When the TCOMP voltage is equal or greater than VCC/15,
ISL6336D will utilize the voltage at TM and TCOMP pins to
compensate the temperature impact on the sensed current. The
block diagram of this function is shown in Figure 20.
VCC
TM
0.451*Vcc
0.391*Vcc
0.333*Vcc
TM
o
c
NON-LINEAR
A/D
R NTC
VR_FAN
D/A
VCC
VR_HOT
TEMPERATURE
T1
T2
T3
FIGURE 19. VR_HOT AND VR_FAN SIGNAL vs TM VOLTAGE
ISEN4
ISEN3
ISEN2
ISEN1
CHANNEL
CURRENT
SENSE
R TM1
I4
I3
I2
I1
ki
R TC1
TCOMP
4-BIT
A/D
OVERCURRENT
PROTECTION
R TC2
FIGURE 20. BLOCK DIAGRAM OF INTEGRATED TEMPERATURE
COMPENSATION
FN8320 Rev 0.00
Oct 6, 2014
Page 23 of 30
ISL6336D
When the TM NTC is placed close to the current sense
component (inductor), the temperature of the NTC will track the
temperature of the current sense component. Therefore, the TM
voltage can be utilized to obtain the temperature of the current
sense component.
Based on VCC voltage, the ISL6336D converts the TM pin voltage
to a 6-bit TM digital signal for temperature compensation. With
the nonlinear A/D converter of ISL6336D, the TM digital signal is
linearly proportional to the NTC temperature. For accurate
temperature compensation, the ratio of the TM voltage to the
NTC temperature of the practical design should be similar to that
in Figure 18.
Depending on the location of the NTC and the airflow, the NTC
may be cooler or hotter than the current sense component. The
TCOMP pin voltage can be utilized to correct the temperature
difference between NTC and the current sense component. When
a different NTC type or different voltage divider is used for the TM
function, the TCOMP voltage can also be used to compensate for
the difference between the recommended TM voltage curve in
Figure 19 and that of the actual design. According to the VCC
voltage, ISL6336D converts the TCOMP pin voltage to a 4-bit
TCOMP digital signal as TCOMP factor N.
The TCOMP factor N is an integer between 0 and 15. The
integrated temperature compensation function is disabled for
N = 0. For N = 4, the NTC temperature is equal to the
temperature of the current sense component. For N < 4, the NTC
is hotter than the current sense component. The NTC is cooler
than the current sense component for N > 4. When N > 4, the
larger TCOMP factor N is, the larger the difference between the
NTC temperature and the temperature of the current sense
component.
The ISL6336D multiplexes the TCOMP factor N with the TM
digital signal to obtain the adjustment gain to compensate the
temperature impact on the sensed channel current. The
compensated channel current signal is used for IMON and
overcurrent protection functions.
Design Procedure
1. Properly choose the voltage divider for the TM pin to match
the TM voltage vs temperature curve with the recommended
curve in Figure 18.
2. Run the actual board under the full load and the desired
cooling condition.
3. After the board reaches the thermal steady state, record the
temperature (TCSC) of the current sense component (inductor
or MOSFET) and the voltage at TM and VCC pins.
4. Use Equation 20 to calculate the resistance of the TM NTC,
and find out the corresponding NTC temperature TNTC from
the NTC datasheet.
R NTC  T
V TM xR
TM1
= ------------------------------
V CC – V
NTC
TM
6. Choose an integral number close to the above result for the
TCOMP factor. If this factor is higher than 15, use N = 15. If it
is less than 1, use N = 1.
7. Choose the pull-up resistor RTC1 (typical 10kΩ);
8. If N = 15, one does not need the pull-down resistor RTC2. If
otherwise, obtain RTC2 using Equation 22:
NxR TC1
R TC2 = ----------------------15 – N
(EQ. 22)
9. Run the actual board under full load again with the proper
resistors connected to the TCOMP pin.
10. Record the output voltage as V1 immediately after the output
voltage is stable with the full load. Record the output voltage
as V2 after the VR reaches the thermal steady state.
11. If the output voltage increases over 2mV as the temperature
increases (i.e., V2 - V1 > 2mV), reduce N and redesign RTC2; if
the output voltage decreases over 2mV as the temperature
increases (i.e., V1 - V2 > 2mV), increase N and redesign RTC2.
External Temperature Compensation
By pulling the TCOMP pin to GND, the integrated temperature
compensation function is disabled. In addition, external
temperature compensation network on the IMON pin, shown in
Figure 21, can be used to cancel the temperature impact on the
IMON voltage.
IMON
o
C
ISL6336D
INTERNAL
CIRCUIT
FIGURE 21. EXTERNAL TEMPERATURE COMPENSATION
The sensed current will flow out of the IMON pin and develop a
voltage across the resistor equivalent (RIMON). If the resistance
on the IMON pin reduces as the temperature increases, the
temperature impact on the IMON voltage can be compensated.
An NTC resistor can be placed close to the power stage and used
to form a RIMON. Due to the nonlinear temperature
characteristics of the NTC, a resistor network is needed to make
the equivalent resistance on the IMON pin reverse proportional to
the temperature.
The external temperature compensation network can only
compensate the temperature impact on the IMON voltage, while it
has no impact to the sensed current inside ISL6336D. Therefore,
this network cannot compensate for the temperature impact on
the overcurrent protection function.
(EQ. 20)
5. Use Equation 21 to calculate the TCOMP factor N:
209x  T CSC – T

NTC
N = -------------------------------------------------------- + 4
3xT NTC + 400
FN8320 Rev 0.00
Oct 6, 2014
(EQ. 21)
Page 24 of 30
ISL6336D
General Design Guide
UPPER MOSFET POWER CALCULATION
This design guide is intended to provide a high-level explanation of
the steps necessary to create a multiphase power converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced in the following. In addition to this
guide, Intersil provides complete reference designs, which include
schematics, bills of materials, and example board layouts for all
common microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to determine
the number of phases. This determination depends heavily upon
the cost analysis, which in turn depends on system constraints
that differ from one design to the next. Principally, the designer
will be concerned with whether components can be mounted on
both sides of the circuit board; whether through-hole components
are permitted; and the total board space available for power
supply circuitry. Generally speaking, the most economical
solutions are those in which each phase handles between 15A
and 25A. All surface-mount designs will tend toward the lower
end of this current range. If through-hole MOSFETs and inductors
can be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current can be
pushed as high as 40A per phase, but these designs require heat
sinks and forced air to cool the MOSFETs, inductors and
heat-dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each MOSFET will
be required to conduct; the switching frequency; the capability of
the MOSFETs to dissipate heat; and the availability and nature of
heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower MOSFET is
due to current conducted through the channel resistance
(rDS(ON)). In Equation 23, IM is the maximum continuous output
current; IP-P is the peak-to-peak inductor current (see
Equation 1); d is the duty cycle (VOUT/VIN); and L is the
per-channel inductance.
I L  P-P 2 1 – d 
 I M 2
P LOW 1 = r DS  ON   -----  1 – d  + -----------------------------------12
 N
(EQ. 23)
An additional term can be added to the lower MOSFET loss
equation to account for additional loss accrued during the dead
time when inductor current is flowing through the lower MOSFET
body diode. This term is dependent on the diode forward voltage
at IM, VD(ON); the switching frequency, fSW; and the length of
dead times, td1 and td2, at the beginning and the end of the
lower MOSFET conduction interval respectively.
I

IM I 
M I P-P
P-P- t
P LOW 2 = V D  ON  f sw  ----d1 +  ------ – ---------- t d2
 N- + --------
2 
2
N
(EQ. 24)
Thus the total maximum power dissipated in each lower MOSFET
is approximated by the summation of PLOW,1 and PLOW,2.
FN8320 Rev 0.00
Oct 6, 2014
In addition to rDS(ON) losses, a large portion of the upper MOSFET
losses are due to currents conducted across the input voltage (VIN)
during switching. Since a substantially higher portion of the upper
MOSFET losses are dependent on switching frequency, the power
calculation is more complex. Upper MOSFET losses can be divided
into separate components involving the upper MOSFET switching
times; the lower MOSFET body-diode reverse-recovery charge, Qrr;
and the upper MOSFET rDS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does not
conduct any portion of the inductor current until the voltage at
the phase node falls below ground. Once the lower MOSFET
begins conducting, the current in the upper MOSFET falls to zero
as the current in the lower MOSFET ramps up to assume the full
inductor current. In Equation 25, the required time for this
commutation is t1 and the approximated associated power loss
is PUP,1.
I M I P-P  t 1 
P UP,1  V IN  -----  ----  f
 N- + --------2   2  SW
(EQ. 25)
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 26, the approximate
power loss is PUP,2.
 I M I P-P  t 2 
P UP, 2  V IN  ----- – ----------  ----  f SW
2  2
N
(EQ. 26)
A third component involves the lower MOSFET’s reverse recovery
charge, Qrr. Since the inductor current has fully commutated to
the upper MOSFET before the lower MOSFET’s body diode can
draw all of Qrr, it is conducted through the upper MOSFET across
VIN. The power dissipated as a result is PUP,3 and is
approximated in Equation 27:
P UP,3 = V IN Q rr f SW
(EQ. 27)
Finally, the resistive part of the upper MOSFET’s is given in
Equation 28 as PUP,4.
The total power dissipated by the upper MOSFET at full load can
now be approximated as the summation of the results from
Equations 25, 26, and 27. Since the power equations depend on
MOSFET parameters, choosing the correct MOSFETs can be an
iterative process involving repetitive solutions to the loss
equations for different MOSFETs and different switching
frequencies, as shown in Equation 28.
2
I P-P2
 I M
P UP,4  r DS  ON   ----- d + ---------- d
12
 N
(EQ. 28)
Current Sensing Resistor
The resistors connected to the ISEN+ pins determine the gain in
the channel-current balance loop and set the overcurrent trip
point. Select values for these resistors by using Equation 29:
RX
I OCP
R ISEN = -------------------------- ------------–6 N
105 10
(EQ. 29)
Page 25 of 30
ISL6336D
where RISEN is the sense resistor connected to the ISEN+ pin, N
is the active channel number, RX is the resistance of the current
sense element, either the DCR of the inductor or RSENSE
depending on the sensing method, and IOCP is the desired
overcurrent trip point. Typically, IOCP can be chosen to be 1.2x
the maximum load current of the specific application.
With integrated temperature compensation, the sensed current
signal is independent on the operational temperature of the
power stage, i.e., the temperature effect on the current sense
element RX is cancelled by the integrated temperature
compensation function. RX in Equation 29 should be the
resistance of the current sense element at the room
temperature.
When the integrated temperature compensation function is
disabled by pulling the TCOMP pin to GND, the sensed current will
be dependent on the operational temperature of the power
stage, since the DC resistance of the current sense element may
be changed according to the operational temperature. RX in
Equation 29 should be the maximum DC resistance of the
current sense element at the all operational temperature.
In certain circumstances, it may be necessary to adjust the value
of one or more ISEN resistors. When the components of one or
more channels are inhibited from effectively dissipating their
heat so that the affected channels run hotter than desired,
choose new, smaller values of RISEN for the affected phases (see
“Voltage Regulation” on page 16). Choose RISEN,2 in proportion to
the desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase, as shown
in Equation 30:
T
R ISEN ,2 = R ISEN ----------2
T 1
(EQ. 30)
In Equation 30, make sure that T2 is the desired temperature
rise above the ambient temperature, and T1 is the measured
temperature rise above the ambient temperature. While a single
adjustment according to Equation 30 is usually sufficient, it may
occasionally be necessary to adjust RISEN two or more times to
achieve optimal thermal balance between all channels.
Compensation
The ISL6336D converter can be accurately modeled as a
voltage-mode regulator with two poles at the L-C resonant
frequency and a zero at the ESR frequency. A type III controller,
as shown in Figure 22, provides the necessary compensation.
C2
RC
CC
COMP
FB
C1
ISL6336D
RFB
R1
VDIFF
FIGURE 22. COMPENSATION CIRCUIT
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to assure
adequate transient performance but not higher than 1/3 of the
switching frequency. The type III compensator has an extra
high-frequency pole, fHF. This pole can be used for added noise
rejection or to assure adequate attenuation at the error-amplifier
high-order pole and zero frequencies. A good general rule is to
choose fHF = 10f0, but it can be higher if desired. Choosing fHF to
be lower than 10f0 can cause problems with too much phase
shift below the system bandwidth.
C  ESR
R 1 = R FB  -------------------------------------------L  C – C  ESR
L  C – C  ESR
C 1 = -------------------------------------------R FB
V IN
C 2 = ---------------------------------------------------------------------------------------------------2
 2     f 0  f HF   L  C   R FB  V P-P
(EQ. 31)
2
V PP   2  f 0  f HF  L  C  R FB
 
R C = ---------------------------------------------------------------------------------------V   2    f HF  L  C – 1 
IN
V IN   2    f HF  L  C – 1 
C C = --------------------------------------------------------------------------------------------------- 2    2  f 0  f HF   L  C   R FB  V P-P
In the solutions to the compensation equations, there is a single
degree of freedom. For the solutions presented in Equation 31,
RFB can be arbitrarily chosen as 1kΩ to 2kΩ. The remaining
compensation components are then selected.
In Equation 31, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
capacitors; ESR is the equivalent-series resistance of the bulk
output-filter capacitance; and VP-P is the peak-to-peak sawtooth
signal amplitude, typically 1.5V.
FN8320 Rev 0.00
Oct 6, 2014
Page 26 of 30
ISL6336D
Output Filter Design
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because it
has a low bandwidth compared to the switching frequency, the
output filter necessarily limits the system transient response. The
output capacitor must supply or sink load current while the
current in the output inductors increases or decreases to meet
the demand.
In high-speed converters, the output capacitor bank is usually the
most costly (and often the largest) part of the circuit. Output filter
design begins with minimizing the cost of this part of the circuit.
The critical load parameters in choosing the output capacitors are
the maximum size of the load step, I; the load-current slew rate,
di/dt; and the maximum allowable output-voltage deviation under
transient loading, VMAX. Capacitors are characterized according
to their capacitance, ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors supply
all of the transient current. The output voltage will initially deviate by
an amount approximated by the voltage drop across the ESL. As the
load current increases, the voltage drop across the ESR increases
linearly until the load current reaches its final value. The capacitors
selected must have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount, as
shown in Equation 32:
di
V   ESL  ----- +  ESR  I
dt
(EQ. 32)
The filter capacitor must have sufficiently low ESL and ESR so
that V < VMAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the bulk
capacitors allows them to supply the increased current with less
output voltage deviation.
The ESR of the bulk capacitors also creates the majority of the
output-voltage ripple. As the bulk capacitors sink and source the
inductor AC ripple current (see “Interleaving” on page 13 and
Equation 2), a voltage develops across the bulk-capacitor ESR
equal to IC,PP (ESR). Thus, once the output capacitors are
selected, the maximum allowable ripple voltage, VP-P(MAX),
determines the lower limit on the inductance, as shown in
Equation 33.
V – N V

OUT V OUT
 IN
L   ESR  -----------------------------------------------------------f SW V IN V P-P MAX 
before the output voltage decreases more than VMAX. This
places an upper limit on inductance.
Equation 34 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater outputvoltage deviation than the leading edge. Equation 35 addresses
the leading edge. Normally, the trailing edge dictates the
selection of L because duty cycles are usually less than 50%.
Nevertheless, both inequalities should be evaluated, and L
should be selected based on the lower of the two results. In each
equation, L is the per-channel inductance, C is the total output
capacitance, and N is the number of active channels.
2NCVO
L  -------------------- V MAX – I  ESR 
 I  2
(EQ. 34)
 1.25  NC
L  -------------------------- V MAX – I  ESR   V IN – V O


 I  2
(EQ. 35)
Switching Frequency Selection
There are a number of variables to consider when choosing the
switching frequency, as there are considerable effects on the
upper MOSFET loss calculation. These effects are outlined in
“MOSFETs” on page 25, and they establish the upper limit for the
switching frequency. The lower limit is established by the
requirement for fast transient response and small output-voltage
ripple as outlined in “Output Filter Design” on page 27. Choose
the lowest switching frequency that allows the regulator to meet
the transient-response requirements.
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper MOSFETs.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the upper MOSFETs, which is
related to duty cycle and the number of active phases.
For a 2-phase design, use Figure 23 to determine the input
capacitor RMS current requirement given the duty cycle,
maximum sustained output current (IO), and the ratio of the
per-phase peak-to-peak inductor current (IL(P-P)) to IO. Select a
bulk capacitor with a ripple current rating which will minimize the
total number of input capacitors required to support the RMS
current calculated. The voltage rating of the capacitors should
also be at least 1.25x greater than the maximum input voltage.
(EQ. 33)
Since the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
FN8320 Rev 0.00
Oct 6, 2014
Page 27 of 30
ISL6336D
Low capacitance, high-frequency ceramic capacitors are needed
in addition to the bulk capacitors to suppress leading and falling
edge voltage spikes. The result from the high current slew rates
produced by the upper MOSFETs turn on and off. Select low ESL
ceramic capacitors and place one as close as possible to each
upper MOSFET drain to minimize board parasitic impedances
and maximize suppression.
0.2
0.6
0.1
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR 2-PHASE CONVERTER
Figures 24 and 25 provide the same input RMS current
information for 3- and 4-phase designs respectively. Use the
same approach to selecting the bulk capacitor type and number,
as previously described.
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.25 IO
IL(P-P) = 0.75 IO
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR 3-PHASE CONVERTER
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
IL(P-P) = 0
IL(P-P) = 0.25 IO
0.2
IL(P-P) = 0
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0
0
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
MULTIPHASE RMS IMPROVEMENT
0.1
0
0.4
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR SINGLE-PHASE CONVERTER
0.2
0
INPUT-CAPACITOR CURRENT (IRMS/IO)
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.3
Figure 26 is provided as a reference to demonstrate the dramatic
reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a 2-phase
converter versus that of a single phase. Assume both converters
have a duty cycle of 0.25, a maximum sustained output current
of 40A, and a ratio of IL(P-P) to IO of 0.5. The single phase
converter would require 17.3ARMS current capacity while the twophase converter would only require 10.9ARMS. The advantages
become even more pronounced when output current is increased
and additional phases are added to keep the component cost
down relative to the single phase approach.
Layout Considerations
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter performance
and to optimize the heat-dissipating capabilities of the
printed-circuit board. These sections highlight some important
practices which should not be overlooked during the layout
process.
IL(P-P) = 0.5 IO
IL(P-P) = 0.75 IO
0.2
Component Placement
0.1
0
0
0.2
0.4
0.6
DUTY CYCLE (VO/VIN)
0.8
1.0
FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR 4-PHASE CONVERTER
FN8320 Rev 0.00
Oct 6, 2014
Within the allotted implementation area, orient the switching
components first. The switching components are the most critical
because they carry large amounts of energy and tend to generate
high levels of noise. Switching component placement should take
into account power dissipation. Align the output inductors and
MOSFETs such that space between the components is minimized
while creating the PHASE plane. Place the Intersil MOSFET driver
IC as close as possible to the MOSFETs they control to reduce the
parasitic impedances due to trace length between critical driver
input and output signals. If possible, duplicate the same
placement of these components for each phase.
Page 28 of 30
ISL6336D
Next, place the input and output capacitors. Position one high
frequency ceramic input capacitor next to each upper MOSFET
drain. Place the bulk input capacitors as close to the upper
MOSFET drains, as dictated by the component size and
dimensions. Long distances between input capacitors and
MOSFET drains result in too much trace inductance and a
reduction in capacitor performance. Locate the output capacitors
between the inductors and the load, while keeping them in close
proximity to the microprocessor socket.
Voltage-Regulator (VR) Design
Materials
Intersil has also developed a set of worksheets to support VR
design and layout. Contact Intersil’s local office or field support
for the latest available information.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
October 6, 2014
FN8320.0
CHANGE
Initial Release
About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8320 Rev 0.00
Oct 6, 2014
Page 29 of 30
ISL6336D
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 4/10
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
0.10 C
BASE PLANE
0 . 90 ± 0 . 1
4 . 30 )
C
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN8320 Rev 0.00
Oct 6, 2014
Page 30 of 30