TI1 LMV7275MGX/NOPB Single & dual, 1.8v low power comparators with rail-to-rail input Datasheet

LMV7271
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SNOSA56H – FEBRUARY 2003 – REVISED FEBRUARY 2013
LMV7271/LMV7275/LMV7272 Single & Dual, 1.8V Low Power Comparators with Rail-to-Rail
Input
Check for Samples: LMV7271
FEATURES
DESCRIPTION
•
The LMV727X are rail-to-rail input low power
comparators, which are characterized at supply
voltage 1.8V, 2.7V and 5.0V. They consume only 9uA
supply current per channel while achieving a 800ns
propagation delay.
1
2
•
•
•
•
•
•
•
•
(VS = 1.8V, TA = 25°C, Typical values unless
specified).
Single or Dual Supplies
Ultra low supply current 9µA per channel
Low input bias current 10nA
Low input offset current 200pA
Low guaranteed VOS 4mV
Propagation delay 880ns (20mV overdrive)
Input common mode voltage range 0.1V
beyond rails
LMV7272 is available in DSBGA package
The LMV7271/LMV7275 (single) are available in
SC70 and SOT-23 packages. The LMV7272 (dual) is
available in DSBGA package. With these tiny
packages, the PC board area can be significantly
reduced. They are ideal for low voltage, low power
and space critical designs.
The LMV7271/LMV7272 both feature a push-pull
output stage which allows operation with minimum
power consumption when driving a load. The
LMV7275 features an open drain output stage that
allows for wired-OR configurations. The open drain
output also offers the advantage of allowing the
output to be pulled to any voltage up to 5.5V,
regardless of the supply voltage of the LMV7275.
APPLICATIONS
•
•
•
•
Mobile communications
Laptops and PDA's
Battery powered electronics
General purpose low voltage applications
The LMV727X are built with Texas Instruments'
advance submicron silicon-gate BiCMOS process.
They all have bipolar inputs for improved noise
performance and CMOS outputs for rail-to-rail output
swing.
Typical Circuit
VIN
VCC
R1
C1 =
0.1µF
C2 =
10µF
+
VOUT
R2
-
VREF
Figure 1. Threshold Detector
Part Number
Single/Dual
Package
Output
LMV7271
Single
SC70, SOT-23
Push/Pull
LMV7272
Dual
DSBGA
Push/Pull
LMV7275
Single
SC70, SOT-23
Open Drain
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LMV7271
SNOSA56H – FEBRUARY 2003 – REVISED FEBRUARY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
ESD Tolerance
VIN Differential
2KV
(3)
200V
(4)
±Supply Voltage
Supply Voltage (V+ - V−)
6V
V+ +0.1V, V− −0.1V
Voltage at Input/Output pins
Soldering Information
Infrared or Convection (20 sec.)
235°C
Wave Soldering (10 sec.)
260°C
−65°C to +150°C
Storage Temperature Range
Junction Temperature
(1)
(5)
+150°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
Human body model, 1.5kΩ in series with 100pF.
Machine Model, 0Ω in series with 200pF.
Typical values represent the most likely parametric norm.
(2)
(3)
(4)
(5)
Operating Ratings
(1)
Supply Voltage Range
Temperature Range
1.8V to 5.5V
(2)
−40°C to +85°C
Package Thermal Resistance
(2)
SOT-23
325°C/W
SC70
265°C/W
8-Bump DSBGA
220°C/W
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board.
1.8V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 1.8V, V− = 0V. Boldface limits apply at the temperature
extremes.
Symbol
Parameter
Condition
Min
(1)
Typ
Max
(1)
Units
0.3
4
6
mV
(2)
VOS
Input Offset Voltage
TC VOS
Input Offset Temperature Drift
20
uV/°C
IB
Input Bias Current
10
nA
IOS
Input Offset Current
200
pA
IS
Supply Current
VCM = 0.9V
(3)
LMV7271/LMV7275
LMV7272
(1)
(2)
(3)
2
9
12
14
µA
18
25
28
µA
All limits are guaranteed by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
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1.8V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 1.8V, V− = 0V. Boldface limits apply at the temperature
extremes.
Symbol
ISC
Min
Typ
3.5
6
4
6
IO = 0.5mA
1.7
1.74
IO = 1.5mA
1.47
1.63
Parameter
Output Short Circuit Current
Condition
Sourcing, VO = 0.9V
(LMV7271/LMV7272 only)
Sinking, VO = 0.9V
(1)
(2)
Max
(1)
Units
mA
VOH
Output Voltage High
(LMV7271/LMV7272 only)
VOL
Output Voltage Low
VCM
Input Common Mode Voltage Range
CMRR > 45 dB
CMRR
Common Mode Rejection Ratio
0 < VCM < 1.8V
46
78
dB
PSRR
Power Supply Rejection Ratio
V+ = 1.8V to 5V
55
80
dB
ILEAKAGE
Output Leakage Current
VO = 1.8V (LMV7275 only)
2
pA
V
IO = −0.5mA
52
100
IO = −1.5mA
166
220
mV
1.9
V
−0.1
V
1.8V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 1.8V, V− = 0V, VCM = 0.5V, VO = V+/2 and RL > 1MΩ to
V−. Boldface limits apply at the temperature extremes.
Symbol
Propagation Delay
(High to Low)
tPHL
Propagation Delay
(Low to High)
tPLH
(1)
(2)
Parameter
Condition
Min
(1)
Typ
(2)
Max
(1)
Units
Input Overdrive = 20mV
Load = 50pF//5kΩ
880
ns
Input Overdrive = 50mV
Load = 50pF//5kΩ
570
ns
Input Overdrive = 20mV
Load = 50pF//5kΩ
1100
ns
Input Overdrive = 50mV
Load = 50pF//5kΩ
800
ns
Machine Model, 0Ω in series with 200pF.
All limits are guaranteed by testing or statistical analysis.
2.7V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 2.7V, V− = 0V. Boldface limits apply at the temperature
extremes.
Symbol
Parameter
Conditions
Min
(1)
Typ
Max
(1)
Units
0.3
4
6
mV
(2)
VOS
Input Offset Voltage
TC VOS
Input Offset Temperature Drift
20
µV/°C
IB
Input Bias Current
10
nA
IOS
Input offset Current
200
VCM = 1.35V
(3)
LMV7271/LMV7275
IS
Supply Current
LMV7272
ISC
(1)
(2)
(3)
Output Short Circuit Current
pA
9
13
15
18
25
28
Sourcing, VO = 1.35V
(LMV7271/LMV7272 only)
10
15
Sinking, VO = 1.35V
10
15
µA
µA
mA
Machine Model, 0Ω in series with 200pF.
All limits are guaranteed by testing or statistical analysis.
Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
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2.7V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 2.7V, V− = 0V. Boldface limits apply at the temperature
extremes.
Symbol
Min
Typ
IO = 0.5mA
2.63
2.66
IO = 2.0mA
2.48
2.55
Parameter
Conditions
(1)
(2)
Max
(1)
Units
VOH
Output Voltage High
(LMV7271/LMV7272 only)
VOL
Output Voltage Low
VCM
Input Common Voltage Range
CMRR > 45dB
CMRR
Common Mode Rejection Ratio
0 < VCM < 2.7V
46
78
dB
PSRR
Power Supply Rejection Ratio
V+ = 1.8V to 5V
55
80
dB
ILEAKAGE
Output Leakage Current
VO = 2.7V (LMV7275 only)
2
pA
V
IO = −0.5mA
50
70
IO = −2mA
155
220
mV
2.8
V
−0.1
V
2.7V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = 0.5V, VO = V+/2 and RL > 1MΩ to
V−. Boldface limits apply at the temperature extremes.
Symbol
Propagation Delay
(High to Low)
tPHL
Propagation Delay
(Low to High)
tPLH
(1)
(2)
Parameter
Condition
Min
(1)
Typ
(2)
Max
(1)
Units
Input Overdrive = 20mV
Load = 50pF//5kΩ
1200
ns
Input Overdrive = 50mV
Load = 50pF//5kΩ
810
ns
Input Overdrive = 20mV
Load = 50pF//5kΩ
1300
ns
Input Overdrive = 50mV
Load = 50pF//5kΩ
860
ns
Machine Model, 0Ω in series with 200pF.
All limits are guaranteed by testing or statistical analysis.
5.0V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 5V, V− = 0V. Boldface limits apply at the temperature
extremes.
Symbol
Parameter
Conditions
Min
(1)
Typ
Max
(1)
Units
0.3
4
6
mV
(2)
VOS
Input Offset Voltage
TC VOS
Input Offset Temperature Drift
20
µV/°C
IB
Input Bias Current
10
nA
IOS
Input Offset Current
200
pA
IS
Supply Current
VCM = 2.5V
(3)
LMV7271/LMV7275
LMV7272
ISC
VOH
(1)
(2)
(3)
4
Output Short Circuit Current
Output Voltage High
(LMV7271/LMV7272 only)
10
14
16
µA
20
27
30
µA
Sourcing, VO = 2.5V
(LMV7271/LMV7272 only)
18
34
Sinking, VO = 2.5V
18
34
IO = 0.5mA
4.93
4.96
IO = 4.0mA
4.675
4.77
mA
V
Machine Model, 0Ω in series with 200pF.
All limits are guaranteed by testing or statistical analysis.
Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
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5.0V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 5V, V− = 0V. Boldface limits apply at the temperature
extremes.
Symbol
Parameter
Min
Conditions
Typ
(1)
Max
(2)
(1)
IO = −0.5mA
27
70
IO = −4.0mA
225
315
Units
VOL
Output Voltage Low
mV
VCM
Input Common Voltage Range
CMRR > 45dB
CMRR
Common Mode Rejection Ratio
0 < VCM < 5.0V
46
78
dB
PRSS
Power Supply Rejection Ratio
V+ = 1.8V to 5V
55
80
dB
ILEAKAGE
Output Leakage Current
VO = 5V (LMV7275 only)
2
pA
5.1
V
−0.1
5.0V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 5.0V, V− = 0V, VCM = 0.5V, VO = V+/2 and RL > 1MΩ to
V−. Boldface limits apply at the temperature extremes.
Symbol
tPHL
tPLH
(1)
(2)
Parameter
Min
Condition
Propagation Delay
(High to Low)
Propagation Delay
(Low to High)
Typ
(1)
Max
(2)
(1)
Units
Input Overdrive = 20mV
Load = 50pF//5kΩ
2100
ns
Input Overdrive = 50mV
Load = 50pF//5kΩ
1380
ns
Input Overdrive = 20mV
Load = 50pF//5kΩ
1800
ns
Input Overdrive = 50mV
Load = 50pF//5kΩ
1100
ns
Machine Model, 0Ω in series with 200pF.
All limits are guaranteed by testing or statistical analysis.
CONNECTION DIAGRAMS
1
5
+IN
V
+
+
V
OUT A
A1
-IN A
B1
+IN A
C1
A2
A3
OUT B
B3
-IN B
C3
+ IN B
2
GND
-IN
3
4
VOUT
C2
V
Figure 2. 5-Pin SOT-23/SC70 (LMV7271/LMV7275)
(Top View)
-
Figure 3. 8-Bump DSBGA (LMV7272)
(bump side down)
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TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, Unless otherwise specified).
VOS
vs.
VCM
800
VOS
vs.
VCM
VSUPPLY = ±0.9V
800
VSUPPLY = ±1.35V
-40°C
-40°C
400
400
VOS (PV)
VOS (PV)
25°C
0
0
85°C
-400
-400
25°C
85°C
-800
-800
-0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9
-1.35
-0.9
-0.45
VCM (V)
Figure 4.
Figure 5.
VOS
vs.
VCM
Short Circuit
vs.
Supply Voltage
VSUPPLY = ±2.5V
400
VOS (PV)
-40°C
0
-400
25°C
85°C
-800
-2.5 -2
-1
0
0.9
1.35
1
40
SOURCE
30
20
SINK
10
2 2.5
VCM (V)
0
1.8
2.44
3.08
3.72
4.36
5.0
SUPPLY VOLTAGE (V)
Figure 6.
6
0.45
VCM (V)
SHORT CIRCUIT OUTPUT CURRENT (mA)
800
0
Figure 7.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(TA = 25°C, Unless otherwise specified).
Supply Current
vs.
Supply Voltage (LMV7271)
Supply Current
vs.
Supply Voltage (LMV7272)
25
10
9
SUPPLY CURRENT (PA)
SUPPLY CURRENT (PA)
85°C
85°C
85°C
8
25°C
7
6
20
15
25°C
10
-40°C
5
-40°C
VOUT = HIGH
0
5
1.8
2.44
3.08
3.72
4.36
1.5
5.0
2
2.5
3
3.5
4
5
4.5
VSUPPLY (V)
SUPPLY VOLTAGE (V)
Figure 8.
Figure 9.
Supply Current
vs.
Supply Voltage (LMV7272)
Output Positive Swing
vs.
VSUPPLY
600
25
20
500
V - VOUT (mV)
15
10
25°C
+
SUPPLY CURRENT (PA)
ISOURCE
85°C
-40°C
400
4mA
300
2mA
200
1.5mA
5
100
0.5mA
VOUT = LOW
0
0
1.5
2
2.5
3
3.5
4
4.5
5
1.8
2.3
2.8
3.3
3.8
4.3
4.8
VSUPPLY (V)
VSUPPLY (V)
Figure 10.
Figure 11.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(TA = 25°C, Unless otherwise specified).
Output Negative Swing
vs.
VSUPPLY
Output Positive Swing
vs.
ISOURCE
600
0.8
VSUPPLY = 1.8V
ISINK
0.7
500
85°C
V - VOUT (V)
400
4mA
-
VOUT - V (mV)
0.6
300
25°C
0.4
+
2mA
0.5
200
0.3
1.5mA
0.2
-40°C
100
0.1
0.5mA
0
0
1.8
2.3
2.8
3.3
3.8
4.3
4.8
0
0.5
1
1.5
2
2.5
3
3.5
4
ISOURCE (mA)
VSUPPLY (V)
Figure 12.
Figure 13.
Output Negative Swing
vs.
ISINK
Output Positive Swing
vs.
ISOURCE
0.5
0.8
VSUPPLY = 1.8V
VSUPPLY = 2.7V
0.45
0.7
85°C
85°C
0.4
0.6
V - VOUT (V)
-
VOUT - V (V)
0.35
0.5
25°C
0.25
0.2
+
0.4
25°C
0.3
0.3
0.15
0.2
-40°
0.1
-40°C
0.1
0.05
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
ISINK (mA)
0.5
1
1.5
2
2.5
3
3.5
4
ISOURCE (mA)
Figure 14.
8
0
Figure 15.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(TA = 25°C, Unless otherwise specified).
Output Negative Swing
vs.
ISINK
Output Negative Swing
vs.
ISINK
0.5
0.4
VSUPPLY = 2.7V
0.45
VSUPPLY = 5V
85°C
85°C
0.4
0.35
25°C
-
0.3
VOUT - V (V)
-
VOUT - V (V)
0.3
25°C
0.25
0.2
0.2
0.15
0.1
0.1
-40°C
-40°C
0.05
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
Figure 16.
2.5
3
3.5
4
Figure 17.
Output Positive Swing
vs.
ISOURCE
Propagation Delay (tPLH)
5
OUTPUT VOLTAGE
(V)
0.4
VSUPPLY = 5V
85°C
0.3
25°C
VCC = 1.8V
TEMP = 25°C
LOAD = 5k: 50pF
4
3
50mV
20mV
2
1
0
0.2
|
INPUT VOLTAGE
(mV)
+
V - VOUT (V)
2
ISINK (mA)
ISINK (mA)
0.1
-40°C
0
0
0.5
1
1.5
2
2.5
3
3.5
|
100
0
OVERDRIVE
-100
4
0
500
1000
1500 2000
2500 3000
TIME (ns)
ISOURCE (mA)
Figure 18.
Figure 19.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(TA = 25°C, Unless otherwise specified).
Propagation Delay (tPLH)
VCC = 1.8 V
4 TEMP = 25°C
3 LOAD = 5k: 50pF
2
50mV
1
5
OUTPUT VOLTAGE
(V)
OUTPUT VOLTAGE
(V)
Propagation Delay (tPHL)
5
20mV
3
50mV
2
20mV
1
0
|
|
100
OVERDRIVE
0
-100
0
500
1000
1500
INPUT VOLTAGE
(mV)
0
INPUT VOLTAGE
(mV)
VCC = 2.7V
TEMP = 25°C
LOAD = 5k: 50pF
4
|
|
100
0
OVERDRIVE
-100
2000 2500 3000
0
500
Figure 20.
Figure 21.
Propagation Delay (tPLH)
VCC = 2.7 V
TEMP = 25°C
LOAD = 5k: 50pF
4
3
5
OUTPUT VOLTAGE
(V)
OUTPUT VOLTAGE
(V)
Propagation Delay (tPHL)
50mV
1
20mV
VCC = 5.0V
TEMP = 25°C
3 LOAD = 5k: 50pF
20mV
2
1
OUTPUT VOLTAGE
(V)
100
OVERDRIVE
0
-100
500
1000 1500
INPUT VOLTAGE
(mV)
|
|
|
|
100
0
OVERDRIVE
-100
2000 2500 3000
0
500
1000 1500 2000
TIME (ns)
TIME (ns)
Figure 22.
Figure 23.
Propagation Delay (tPHL)
tPHL
vs.
Overdrive
5
8
VCC = 5.0 V
TEMP = 25°C
3 LOAD = 5k: 50pF
7
4
2500 3000
VS = 5V
6
2
50mV
1
0
20mV
|
|
100
tPHL (PS)
INPUT VOLTAGE
(mV)
0
0
INPUT VOLTAGE
(mV)
50mV
4
0
OVERDRIVE
5
4
VS = 2.7V
3
2
0
1
-100
VS = 1.8V
0
0
500
1000 1500
2000 2500 3000
TIME (ns)
0
10
100
1000
OVERDRIVE (mV)
Figure 24.
10
1500 2000 2500 3000
TIME (ns)
5
2
1000
TIME (ns)
Figure 25.
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SNOSA56H – FEBRUARY 2003 – REVISED FEBRUARY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(TA = 25°C, Unless otherwise specified).
tPLH
vs.
Overdrive
5
VS = 5V
4.5
4
tPLH (PS)
3.5
3
2.5
VS = 2.7V
2
1.5
1
VS = 1.8V
0.5
0
1
10
100
1000
OVERDRIVE (mV)
Figure 26.
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APPLICATION NOTES
BASIC COMPARATOR
A comparator is often used to convert an analog signal to a digital signal. As shown in Figure 28, the comparator
compares an input voltage (VIN) to a reference voltage (VREF). If VIN is less than VREF, the output (VO) is low.
However, if VIN is greater than VREF, the output voltage (VO) is high.
Figure 27. LMV7271
V
VREF
+
VO
VIN
+
V
-
VOLTS
VO
VREF
TIME
VIN
Figure 28. LMV7271 Basic Comparator
RAIL-TO-RAIL INPUT STAGE
The LMV727X has an input common mode voltage range (VCM) of −0.1V below the V− to 0.1V above V+. This is
achieved by using paralleled PNP and NPN differential input pairs. When the VCM is near V+, the NPN pair is on
and the PNP pair is off. When the VCM is near V−, the NPN pair is off and the PNP pair is on. The crossover point
between the NPN and PNP input stages is around 950mV from V+. Since each input stage has its own offset
voltage (VOS), the VOS of the comparator becomes a function of the VCM. See curves for VOS vs. VCM in Typical
Performance Characteristics section. In application design, it is recommended to keep the VCM away from the
crossover point to avoid problems. The wide input voltage range makes LMV727X ideal in power supply
monitoring circuits, where the comparators are used to sense signals close to ground and power supplies.
OUTPUT STAGE
The LMV7271 and LMV7272 have a push-pull output stage. This output stage keeps the total system power
consumption to the absolute minimum. The only current consumed is the low supply current and the current
going directly into the load. When the output switches, both PMOS and NMOS at the output stage are on at the
same time for a very short time. This allows current to flow directly between V+ and V− through output transistors.
The result is a short spike of current (shoot-through current) drawn from the supply and glitches in the supply
voltages. The glitches can spread to other parts of the board as noise. To prevent the glitches in supply lines,
power supply bypass capacitors must be installed. See section for supply bypassing in the Application Notes for
details.
12
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HYSTERESIS
It is a standard procedure to use hysteresis (positive feedback) around a comparator, to prevent oscillation, and
to avoid excessive noise on the output because the comparator is a good amplifier of its own noise.
Inverting Comparator with Hysteresis
The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage
VCC of the comparator (Figure 29). When VIN at the inverting input is less than VA, the voltage at the noninverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VO switches as high
as VCC). The three network resistors can be represented as R1||R3 in series with R2. The lower input trip voltage
VA1 is defined as
VA1 =
VCC R2
(R1||R3) + R2
(1)
When VIN is greater than VA (VIN > VA), the output voltage is low and very close to ground. In this case the three
network resistors can be presented as R2//R3 in series with R1. The upper trip voltage VA2 is defined as
VA2 =
VCC (R2||R3)
R1 + (R2||R3)
(2)
The total hysteresis provided by the network is defined as
ΔVA = VA1 - VA2
(3)
A good typical value of ΔVA would be in the range of 5 to 50mV. This is easily obtained by choosing R3 as 1000
to 100 times (R1||R2) for 5V operation, or as 300 to 30 times (R1||R2) for 1.8V operation.
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Figure 29. Inverting Comparator with Hysteresis
Non-Inverting Comparator with Hysteresis
A non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the
inverting input (Figure 30). When VIN is low, the output is also low. For the output to switch from low to high, VIN
must rise up to VIN1, where VIN1 is calculated by
(4)
When VIN is high, the output is also high. To make the comparator switch back to its low state, VIN must equal
VREF before VA will again equal VREF. VIN can be calculated by:
(5)
The hysteresis of this circuit is the difference between VIN1 and VIN2.
ΔVIN = VCCR1/R2
14
(6)
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Figure 30. Non-Inverting Comparator with Hysteresis
CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS
Feedback to almost any pin of a comparator can result in oscillation. In addition, when the input signal is a slow
voltage ramp or sine wave, the comparator may also burst into oscillation near the crossing point. To avoid
oscillation or instability, PCB layout should be engineered thoughtfully. Several precautions are recommended:
1.
Power supply bypassing is critical, and will improve stability and transient response. Resistance and
inductance from power supply wires and board traces increase power supply line impedance. When
supply current changes, the power supply line will move due to its impedance. Large enough supply line
shift will cause the comparator to mis-operate. To avoid problems, a small bypass capacitor, such as
0.1uF ceramic, should be placed immediately adjacent to the supply pins. An additional 6.8μF or greater
tantalum capacitor should be placed at the point where the power supply for the comparator is introduced
onto the board. These capacitors act as an energy reservoir and keep the supply impedance low. In dual
supply application, a 0.1μF capacitor is recommended to be placed across V+ and V− pins.
2.
Keep all leads short to reduce stray capacitance and lead inductance. It will also minimize any unwanted
coupling from any high-level signals (such as the output). The comparators can easily oscillate if the
output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows
up only during the output voltage transition intervals as the comparator changes states. Try to avoid a long
loop which could act as an inductor (coil).
3.
It is a good practice to use an unbroken ground plane on a printed circuit board to provide all components
with a low inductive ground connection. Make sure ground paths are low-impedance where heavier
currents are flowing to avoid ground level shift. Preferably there should be a ground plane under the
component.
4.
The output trace should be routed away from inputs. The ground plane should extend between the output
and inputs to act as a guard. This can be achieved by running a topside ground plane between the output
and inputs. A typical PCB layout is shown in Figure 31.
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V
+
OUT B
OUT A
-INA
-INB
+INA
+INB
V
-
Figure 31. Typical PCB Layout
5.
When the signal source is applied through a resistive network to one input of the comparator, it is usually
advantageous to connect the other input with a resistor with the same value, for both DC and AC
consideration. Input traces should be laid out symmetrically if possible.
6.
All pins of any unused comparators should be tied to the negative supply.
DSBGA LIGHT SENSITIVITY
Exposing the DSBGA device to direct sunlight will cause mis-operation of the device. Light sources such as
Halogen lamps can also affect electrical performance if brought near to the device. The wavelengths, which have
the most detrimental effect, are reds and infrareds.
DSBGA MOUNTING
The DSBGA package requires specific mounting techniques, which are detailed in Application Note AN-1112
(SNVA009).
LMV7272 DSBGA to DIP Conversion Board
To facilitate characterization and testing, a DSBGA to DIP conversion board, LMV7272TLCONV, is available. It is
a 2-layer board, with the LMV7272 mounted on the bottom layer, and a capacitor (C1, between the positive and
negative supplies) added to the top layer.
LMV7272
+
OUTB
LMV7272 (DSBGA)
(Bottom Layer)
V
-INB
OUTA
+INB
-INA
-
+INA
V
C1 (Top Layer)
Figure 32. LMV7272TLCONV Diagram
Typical Applications
UNIVERSAL LOGIC LEVEL SHIFTER
The output of LMV7275 is an unconnected drain of an NMOS device, which can be pulled up, through a resistor,
to any desired output level within the permitted power supply range. Hence, the following simple circuit works as
a universal logic level shifter, pulling up the signal to the desired level.
16
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SNOSA56H – FEBRUARY 2003 – REVISED FEBRUARY 2013
VB
VA
LOGIC
IN
REXT
-
1k:
LOGIC
OUT
LMV7275
+
1k:
Figure 33. Logic Level Shifter
POSITIVE PEAK DETECTOR
A positive peak detect circuit is basically a comparator operated in a unity gain follower configuration, with a
capacitor as a load to maintain the highest voltage. A diode is added at the output to prevent the capacitor from
discharging through the pull-up resistor, and a 1MΩ resistor added in parallel to the capacitor to provide a high
impedance discharge path. When the input VIN increases, the inverting input of the comparator follows it, thus
charging the capacitor. When it decreases, the cap discharges through the 1MΩ resistor. The decay time can be
modified by changing the resistor. The output should be accessed through a follower circuit to prevent loading.
+VCC
VIN
R1
1k:
+
-
VOUT
C1
10PF
+
R2
1M:
Figure 34. Positive Peak Detector
OR'ING THE OUTPUT
Since the output is an unconnected NMOS drain, many drains can be tied together, pulled up to VDD by a single
resistor to provide an output OR'ing function. If any of the comparator outputs is pulled low the output VO goes
down.
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Figure 35. OR’ing the Outputs
NEGATIVE PEAK DETECTOR
For the negative detector, the output transistor of the comparator acts as a low impedance current sink. Since
there is no pull-up resistor, the only discharge path will be the 1MΩ resistor and any load impedance used.
Decay time is changed by varying the 1MΩ resistor.
+VCC
VIN
+
VOUT
-
R1
1M:
+
C1
10PF
-VCC
Figure 36. Negative Peak Detector
SQUARE WAVE GENERATOR
A typical application for a comparator is as a square wave oscillator. The circuit below generates a square wave
whose period is set by the RC time constant of the capacitor C1and resistor R4. The maximum frequency is
limited by the large signal propagation delay of the comparator, and by the capacitive loading at the output,
which limits the output slew rate.
18
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+
V
4.3k:
R4 = 100k:
C1 = 750pF
VC
VO
+
R1 = 100k:
VA
R3 = 100k:
+
R2 = 100k:
V
0
f | 10KHz
Figure 37. Squarewave Oscillator
To analyze the circuit, consider it when the output is high. That implies that the inverted input (VC) is lower than
the non-inverting input (VA). This causes the C1 to get charged through R4, and the voltage VC increases till it is
equal to the non-inverting input. The value of VA at this point is
VCC.R2
VA1 =
R2 + R1||R3
(7)
If R1 = R2 = R3, then VA1 = 2VCC/3
At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is
VCC (R2||R3)
VA2 =
R1 + (R2||R3)
(8)
If R1 = R2 = R3, then VA2 = VCC/3
The capacitor C1 now discharges through R4, and the voltage VC decreases till it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1.ln2. Hence the formula for the frequency is:
F = 1/(2·R4·C1·ln2)
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LMV7271
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REVISION HISTORY
Changes from Revision G (February 2013) to Revision H
•
20
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 19
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMV7271MF
ACTIVE
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 85
C25A
LMV7271MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C25A
LMV7271MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C25A
LMV7271MG
ACTIVE
SC70
DCK
5
1000
TBD
Call TI
Call TI
-40 to 85
C34
LMV7271MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C34
LMV7271MGX
ACTIVE
SC70
DCK
5
3000
TBD
Call TI
Call TI
-40 to 85
C34
LMV7271MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C34
LMV7272TL/NOPB
ACTIVE
DSBGA
YZR
8
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C
01
LMV7272TLX/NOPB
ACTIVE
DSBGA
YZR
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
C
01
LMV7275MF
ACTIVE
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 85
C26A
LMV7275MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C26A
LMV7275MFX
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 85
C26A
LMV7275MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C26A
LMV7275MG
ACTIVE
SC70
DCK
5
1000
TBD
Call TI
Call TI
-40 to 85
C35
LMV7275MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C35
LMV7275MGX
ACTIVE
SC70
DCK
5
3000
TBD
Call TI
Call TI
-40 to 85
C35
LMV7275MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
C35
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LMV7271MF
SOT-23
DBV
5
1000
178.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
3.2
1.4
4.0
8.0
Q3
LMV7271MF/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7271MFX/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7271MG
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7271MG/NOPB
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7271MGX
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7271MGX/NOPB
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7272TL/NOPB
DSBGA
YZR
8
250
178.0
8.4
1.7
1.7
0.76
4.0
8.0
Q1
LMV7272TLX/NOPB
DSBGA
YZR
8
3000
178.0
8.4
1.7
1.7
0.76
4.0
8.0
Q1
LMV7275MF
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7275MF/NOPB
SOT-23
DBV
5
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7275MFX
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7275MFX/NOPB
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMV7275MG
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7275MG/NOPB
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7275MGX
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV7275MGX/NOPB
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV7271MF
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV7271MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV7271MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV7271MG
SC70
DCK
5
1000
210.0
185.0
35.0
LMV7271MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV7271MGX
SC70
DCK
5
3000
210.0
185.0
35.0
LMV7271MGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
LMV7272TL/NOPB
DSBGA
YZR
8
250
210.0
185.0
35.0
LMV7272TLX/NOPB
DSBGA
YZR
8
3000
210.0
185.0
35.0
LMV7275MF
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV7275MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV7275MFX
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV7275MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV7275MG
SC70
DCK
5
1000
210.0
185.0
35.0
LMV7275MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV7275MGX
SC70
DCK
5
3000
210.0
185.0
35.0
LMV7275MGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0008xxx
D
0.600±0.075
E
TLA08XXX (Rev C)
D: Max = 1.55 mm, Min = 1.489 mm
E: Max = 1.55 mm, Min = 1.489 mm
4215045/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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