NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM General Description The NM27C512 is a high performance 512K UV Erasable Electrically Programmable Read Only Memory (EPROM). It is manufactured using National’s proprietary 0.8 micron CMOS AMGTM EPROM technology for an excellent combination of speed and economy while providing excellent reliability. The NM27C512 provides microprocessor-based systems storage capacity for portions of operating system and application software. Its 90 ns access time provides nowait-state operation with high-performance CPUs. The NM27C512 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly enhancing system utility. The NM27C512 is configured in the standard JEDEC EPROM pinout which provides an easy upgrade path for systems which are currently using standard EPROMs. The NM27C512 is one member of a high density EPROM Family which range in densities up to 4 Megabit. Features Y Y Y Y High performance CMOS Ð 90 ns access time Fast turn-off for microprocessor compatibility Manufacturers identification code JEDEC standard pin configuration Ð 28-pin DIP package Ð 32-pin chip carrier Block Diagram TL/D/10834 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. NSC800TM is a trademark of National Semiconductor Corporation. AMGTM is a trademark of WSI, Inc. C1995 National Semiconductor Corporation TL/D/10834 RRD-B30M65/Printed in U. S. A. NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM February 1994 Connection Diagrams 27C080 27C040 27C020 27C010 27C256 27C256 DIP NM27C512 A19 XX/VPP XX/VPP XX/VPP A16 A16 A16 A16 A15 A15 A15 A15 VPP A12 A12 A12 A12 A12 A7 A7 A7 A7 A7 A6 A6 A6 A6 A6 A5 A5 A5 A5 A5 A4 A4 A4 A4 A4 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 O0 O0 O0 O0 O0 O1 O1 O1 O1 O1 O2 O2 O2 O2 O2 GND GND GND GND GND 27C010 27C020 27C040 27C080 VCC VCC VCC VCC XX/PGM XX/PGM A18 A18 VCC XX A17 A17 A17 A14 A14 A14 A14 A14 A13 A13 A13 A13 A13 A8 A8 A8 A8 A8 A9 A9 A9 A9 A9 A11 A11 A11 A11 A11 OE OE OE OE OE/VPP A10 A10 A10 A10 A10 CE/PGM CE CE CE/PGM CE/PGM O7 O7 O7 O7 O7 O6 O6 O6 O6 O6 O5 O5 O5 O5 O5 O4 O4 O4 O4 O4 O3 O3 O3 O3 O3 TL/D/10834 – 2 Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C512 pins. Commercial Temp Range (0§ C to a 70§ C) Parameter/Order Number Extended Temp Range (b40§ C to a 85§ C) Access Time (ns)* Parameter/Order Number NM27C512 Q, N, V 90 90 NM27C512 QE, NE, VE 90 90 NM27C512 Q, N, V 120 120 NM27C512 QE, NE, VE 120 120 NM27C512 Q, N, V 150 150 NM27C512 QE, NE, VE 150 150 NM27C512 Q, N, V 200 200 NM27C512 QE, NE, VE 200 200 Military Temp Range (b55§ C to a 125§ C) Parameter/Order Number Note: Surface mount PLCC package available for commercial and extended temperature ranges only. Access Time (ns)* NM27C512 QM 200 Access Time (ns)* *All versions are guaranteed to function for slower speeds. 200 Package Types: NM27C512 Q, N, V XXX Q e Quartz-Windowed Ceramic DIP Package N e Plastic OTP DIP Package V e PLCC Package # All packages conform to the JEDEC standard. PLCC Pin Names A0 – A15 Addresses CE Chip Enable OE Output Enable O0 – O7 Outputs PGM Program XX Don’t Care (During Read) TL/D/10834 – 3 2 Absolute Maximum Ratings (Note 1) VCC Supply Voltage with Respect to Ground If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C All Input Voltages Except A9 with Respect to Ground VPP and A9 with Respect to Ground b 0.6V to a 7V ESD Protection (MIL Std. 883, Method 3015.2) All Output Voltages with Respect to Ground b 0.6V to a 7V l 2000V VCC a 1.0V to GND b0.6V b 0.7V to a 14V Operating Range Range Temperature VCC Tolerance Comm’l 0§ C to a 70§ C a 5V g 10% b 40§ C to a 85§ C a 5V g 10% b 55§ C to a 125§ C a 5V g 10% Industrial Military Read Operation DC Electrical Characteristics Symbol Min Max Units VIL Input Low Level Parameter Test Conditions b 0.5 08 V VIH Input High Level 2.0 VCC a 1 V VOL Output Low Voltage IOL e 2.1 mA VOH Output High Voltage IOH e b2.5 mA ISB1 VCC Standby Current (CMOS) CE e VCC g 0.3V ISB2 VCC Standby Current CE e VIH ICC1 VCC Active Current CE e OE e VIL ICC2 VCC Active Current CMOS Inputs IPP VPP Supply Current VPP e VCC VPP VPP Read Voltage ILI Input Load Current VIN e 5.5V or GND ILO Output Leakage Current VOUT e 5.5V or GND 0.4 V 3.5 V 100 mA 1 mA f e 5 MHz 40 mA CE e GND, f e 5 MHz Inputs e VCC or GND, I/O e 0 mA C, I Temp Ranges 35 mA 10 mA VC b 0.7 VCC V b1 1 mA b 10 10 mA AC Electrical Characteristics Symbol 90 Parameter Min tACC Address to Output Delay tCE tOE 120 Max Min 150 Max Min 200 Max Min Units Max 90 120 150 200 CE to Output Delay 90 120 150 200 OE to Output Delay 40 50 50 50 tDF Output Disable to Output Float 35 25 45 55 tOH Output Hold from Addresses, CE or OE, Whichever Occurred First ns 0 0 3 0 Capacitance TA e a 25§ C, f e 1 MHz (Note 2) Typ Max Units CIN1 Symbol Input Capacitance except OE/VPP VIN e 0V 6 12 pF COUT Output Capacitance VOUT e 0V 9 12 pF OE/VPP Input Capacitance VIN e 0V 20 25 pF CIN2 Parameter Conditions AC Test Conditions Output Load Input Rise and Fall Times Input Pulse Levels 1 TTL Gate and CL e 100 pF (Note 8) s 5 ns 0.45V to 2.4V Timing Measurement Reference Level (Note 9) Inputs 0.8V and 2V Outputs 0.8V and 2V AC Waveforms (Notes 6, 7) TL/D/10834 – 4 Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC – tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE, the measured VOH1 (DC) b 0.10V; Low to TRI-STATE, the measured VOL1 (DC) a 0.10V. Note 5: TRI-STATE may be attained using OE or CE. Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC a 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL e 1.6 mA, IOH e b 400 mA. CL: 100 pF includes fixture capacitance. Note 9: Inputs and outputs can undershoot to b 2.0V for 20 ns Max. 4 Programming Characteristics (Notes 1 and 2) Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 1 tOES OE Setup Time 1 ms tDS Data Setup Time 1 ms tVCS VCC Setup Time 1 ms tAH Address Hold Time 0 ms tDH Data Hold Time tCF Chip Enable to Output Float Delay tPW Program Pulse Width tOEH OE Hold Time tDV Data Valid from CE tPRT OE Pulse Rise Time during Programming tVR VPP Recovery Time IPP VPP Supply Current during Programming Pulse ICC VCC Supply Current TR Temperature Ambient 20 25 VCC Power Supply Voltage 6 6.25 6.5 V VPP Programming Supply Voltage 12.5 12.75 13 tFR Input Rise, Fall Time VIL Input Low Voltage VIH Input High Voltage 2.4 tIN Input Timing Reference Voltage 0.8 2 V tOUT Output Timing Reference Voltage 0.8 2 V ms 1 OE e VIL ms 0 95 100 60 ns 105 ms 1 ms OE e VIL 250 ns 50 ns 1 ms CE e VIL OE e VPP 30 mA 50 mA 30 §C 5 V ns 0 0.45 4 V V Programming Waveforms TL/D/10834 – 5 Note 1: National’s standard product warranty applies to devices programmed to specifications described herein. Note 2: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 3: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across VCC to GND to suppress spurious voltage transients which may damage the device. Note 4: Programming and program verify are tested with the fast Program Algorithm at typical power supply voltages and timings. 5 Fast Programming Algorithm Flow Chart TL/D/10834 – 6 FIGURE 1 6 Functional Description The EPROM is in the programming mode when the OE/VPP is at 12.75V. It is required that at least a 0.1 mF capacitor be placed across VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1 . Each Address is programmed with a series of 100 ms pulses until it verifies good, up to a maximum of 25 pulses. Most memory cells will program with a single 100 ms pulse. The EPROM must not be programmed with a DC signal applied to the CE/PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the CE/PGM input programs the paralleled EPROM. DEVICE OPERATION The six modes of operation of the EPROM are listed in Table I. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and OE/VPP. The OE/VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The VCC power supply must be at 6.25V during the three programming modes, and at 5V in the other three modes. Read Mode The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE/VPP) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC – tOE. Standby Mode The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 385 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE/PGM input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Program Inhibit Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE/PGM all like inputs (including OE/VPP) of the parallel EPROMs may be common. A TTL low level program pulse applied to an EPROM’s CE/PGM input with OE/VPP at 12.75V will program that EPROM. A TTL high level CE/PGM input inhibits the other EPROMs from being programmed. Output Disable The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRI-STATE). Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify is accomplished with OE/VPP and CE at VIL. Data should be verified TDV after the falling edge of CE. Output OR-Typing Because the EPROM is usually used in larger memory arrays, National has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary device selecting function, while OE/VPP be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. AFTER PROGRAMMING Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents. MANUFACTURER’S IDENTIFICATION CODE The EPROM has a manufacturer’s identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturer’s Identification code, shown in Table II, specifically identifies the manufacturer and device type. The code for NM27C512 is ‘‘8F85’’, where ‘‘8F’’ designates that it is made by National Semiconductor, and ‘‘85’’ designates a 512K part. The code is accessed by applying 12V g 0.5V to address pin A9. Addresses A1 – A8, A10 – A16, and all control pins Programming CAUTION: Exceeding 14V on pin 22 (OE/VPP) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the ‘‘1’s’’ state. Data is introduced by selectively programming ‘‘0’s’’ into the desired bit locations. Although only ‘‘0’s’’ will be programmed, both ‘‘1’s’’ and ‘‘0’s’’ can be presented in the data word. The only way to change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure. 7 Functional Description (Continued) are held at VIL. Address pin A0 is held at VIL for the manufacturer’s code, and held at VIH for the device code. The code is read on the eight data pins, O0 – O7. Proper code access is only guaranteed at 25§ C g 5§ C. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem. ERASURE CHARACTERISTICS The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Ð). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Ж4000Ð range. The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537Ð. The integrated dose (i.e., UV intensity c exposure time) for erasure should be minimum of 15W-sec/cm2. The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. Table III shows the minimum EPROM erasure time for various light intensities. An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increase as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). Lamps lose intensity as they age. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance loading of the device. The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 mF ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 mF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. Mode Selection The modes of operation of the NM27C512 are listed in Table I. A single 5V power supply is required in the read mode. All inputs are TTL levels excepts for VPP and A9 for device signature. TABLE I. Mode Selection Pins Mode Read Output Disable CE/PGM OE/VPP VCC Outputs VIL VIL 5.0V DOUT X (Note 1) VIH 5.0V High Z High Z Standby VIH X 5.0V Programming VIL 12.75V 6.25V DIN Program Verify VIL VIL 6.25V DOUT Program Inhibit VIH 12.75V 6.25V High Z Note 1: X can be VIL or VIH. TABLE II. Manufacturer’s Identification Code Pins A0 (10) A9 (24) 07 (19) 06 (18) 05 (17) 04 (16) 03 (15) 02 (13) 01 (12) 00 (11) Hex Data Manufacturer Code VIL 12V 1 0 0 0 1 1 1 1 8F Device Code VIH 12V 1 0 0 0 0 1 0 1 85 8 Physical Dimensions inches (millimeters) UV Window Cavity Dual-In-Line Cerdip Package (JQ) Order Number NM27C512Q NS Package Number J28CQ 28-Lead Plastic One-Time-Programmable Dual-In-Line Order Number NM27C512N NS Package Number N28B 9 NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM Physical Dimensions inches (millimeters) (Continued) 32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number NM27C512V NS Package Number VA32A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. Sumitomo Chemical Engineering Center Bldg. 7F 1-7-1, Nakase, Mihama-Ku Chiba-City, Ciba Prefecture 261 Tel: (043) 299-2300 Fax: (043) 299-2500 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductores Do Brazil Ltda. Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel: (55-11) 212-5066 Telex: 391-1131931 NSBR BR Fax: (55-11) 212-1181 National Semiconductor (Australia) Pty, Ltd. Building 16 Business Park Drive Monash Business Park Nottinghill, Melbourne Victoria 3168 Australia Tel: (3) 558-9999 Fax: (3) 558-9998 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.