Cherry CS51031YN8 Fast pfet buck controller does not require compensation Datasheet

CS51031
CS51031
Fast PFET Buck Controller
Does Not Require Compensation
Features
Description
The CS51031 is a switching controller for use in DC-DC converters.
It can be used in the buck topology
with a minimum number of external components. The CS51031 consists of a VCC monitor for controlling the state of the device, 1.0A
power driver for controlling the
gate of a discrete P-channel transistor, fixed frequency oscillator, short
circuit protection timer, programmable soft start, precision reference, fast output voltage monitoring comparator, and output stage
driver logic with latch.
The high frequency oscillator
allows the use of small inductors
and output capacitors, minimizing
PC board area and systems cost.
The programmable soft start
reduces current surges at start up.
The short circuit protection timer
significantly reduces the duty cycle
to approximately 1/30 of its cycle
during short circuit conditions.
The CS51031 is available in 8L SO
and 8L PDIP plastic packages.
■ 1A Totem Pole Output
Driver
■ High Speed Oscillator
(700kHz max)
■ No Stability
Compensation Required
■ Lossless Short Circuit
Protection
■ VCC Monitor
■ 2% Precision Reference
■ Programmable Soft Start
Typical Application Diagram
5V - 12V
CIN
47mF
Package Options
20W
MP1
IRF7416
8 Lead SO Narrow & PDIP
VGATE
VGATE
VGATE
VC
PGnd
CS
MBRS360
CS51031
COSC
VCC
Gnd
VFB
VC
1
PGnd
CS
COSC
VCC
Gnd
VFB
D1
CS
0.1mF
RVCC
10W
L
4.7mH
CVCC
100mF
COSC
150pF
100
RB
2.5kW
.01mF
RA
1.5kW
CRR
0.1mF
VO
3.3V @ 3A
CO
100mF ´ 2
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
Rev. 2/13/98
1
A
¨
Company
CS51031
Absolute Maximum Ratings
Power Supply Voltage, VCC ........................................................................................................................................................20V
Driver Supply Voltage, VC ..........................................................................................................................................................20V
Driver Output Voltage, VGATE ...................................................................................................................................................20V
COSC, CS, VFB (Logic Pins) ............................................................................................................................................................6V
Peak Output Current ................................................................................................................................................................. 1.0A
Steady State Output Current ................................................................................................................................................200mA
Operating Junction Temperature, TJ ..................................................................................................................................... 150¡C
Operating Temperature Range, TA ............................................................................................................................-40¡ to 125¡C
Storage Temperature Range, TS ...................................................................................................................................-65 to 150¡C
ESD (Human Body Model).........................................................................................................................................................2kV
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183¡C, 230¡C peak
Electrical Characteristics: Specifications apply for 4.5 ² VCC ² 16V, 3V ² VC ² 16V,
-40¡C ² TJ ² 125¡C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
■ Oscillator
Frequency
Charge Current
Discharge Current
Maximum Duty Cycle
VFB = 1.2V
COSC = 470pF
1.4V < VCOSC < 2V
2.7V > VCOSC > 2V
1 Ð (tOFF/tON)
■ Short Circuit Timer
Charge Current
Fast Discharge Current
Slow Discharge Current
Start Fault Inhibit Time
Valid Fault Time
GATE Inhibit Time
Fault Duty Cycle
VFB = 1.0V; CS = 0.1µF; VCOSC = 2V
1V < VCS < 2V
2.55V > VCS > 2.4V
2.4V > VCS > 1.5V
0V < VCS < 2.5V
2.6V > VCS > 2.4V
2.4V > VCS > 1.5V
■ CS Comparator
Fault Enable CS Voltage
Max. CS Voltage
Fault Detect Voltage
Fault Inhibit Voltage
Hold Off Release Voltage
Regulator Threshold
Voltage Clamp
VFB = 1V
■ VFB Comparators
Regulator Threshold Voltage
Fault Threshold Voltage
Threshold Line Regulation
Input Bias Current
Voltage Tracking
MIN
TYP
MAX
UNIT
240
80.0
200
110
660
83.3
kHz
µA
µA
%
175
40
4
0.70
0.2
9
2.5
264
66
6
0.85
0.3
15
3.1
325
80
10
1.40
0.45
23
4.6
µA
µA
µA
ms
ms
ms
%
0.4
0.725
2.5
2.6
2.4
1.5
0.7
0.866
1.0
1.035
V
V
V
V
V
V
1.225
1.210
1.12
1.10
1.250
1.250
1.15
1.15
6
1
1.275
1.290
1.17
1.19
15
4
V
V
V
V
mV
µA
70
100
120
mV
4
20
mV
160
VFB = 1.5V
VCS when GATE goes high
Minimum VCS
VFB = 0V
VCS = 1.5V
VCOSC = VCS = 2V
TJ = 25¡C (note 1)
TJ = -40 to 125¡C
TJ = 25¡C (note 1)
TJ = -40 to 125¡C
4.5V ² VCC ² 16V
VFB = 0V
(Regulator Threshold Voltage Fault Threshold Voltage)
Input Hysteresis Voltage
2
PARAMETER
■ Power Stage
GATE DC Low Saturation
Voltage
GATE DC High Saturation
Voltage
Rise Time
Fall Time
TEST CONDITIONS
TYP
MAX
UNIT
VCC = VC = 10V; VFB = 1.2V
VCOSC = 1V; 200mA Sink
1.2
1.5
V
VCOSC = 2.7V; 200mA Source; VC = VGATE
1.5
2.1
V
CGATE = 1nF; 1.5V < VGATE < 9V
CGATE = 1nF; 9V > VGATE > 1.5V
25
25
60
60
ns
ns
4.400
4.300
130
4.600
4.515
200
V
V
mV
4.5
2.7
500
6.0
4.0
900
mA
mA
µA
■ VCC Monitor
Turn On Threshold
Turn Off Threshold
Hysteresis
■ Current Drain
ICC
IC
Shutdown ICC
MIN
4.200
4.085
65
4.5V < VCC < 16V, Gate switching
3V < VC < 16V, Gate non-switching
VCC = 4,
Note 1: Guaranteed by design not 100% tested in production.
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
8L SO Narrow & PDIP
1
VGATE
Driver pin to gate of external PFET.
2
PGnd
Output power stage ground connection.
3
COSC
Oscillator frequency programming capacitor.
4
Gnd
Logic ground.
5
VFB
Feedback voltage input.
6
VCC
Logic supply voltage.
7
CS
Soft start and fault timing capacitor.
8
VC
Driver supply voltage.
3
CS51031
Electrical Characteristics: Specifications apply for 4.5 ² VCC ² 16V, 3V ² VC ² 16V, -40¡C ² TJ ² 125¡C,
unless otherwise specified.
CS51031
Block Diagram
VC
VREF
RG
IC
Oscillator
Comparator
A1
G1
COSC
7IC
VGATE
Flip-Flop
VGATE
Q
R
PGnd
F2
S
G2
Q
VCC
+
1.25V
0.7V
Hold
Off
Comp
VREF
VCCOK
VFB
A6
+
2.5V
1.5V
VCC
VFB
Comparator
-
3.3V
Fault
Comp
VREF = 3.3V
+ 1.15V
G4
CS Charge
Sense
Comparator
G3
IT
R
-
+
CS
IT
55
A4
CS
Comparator
A2
2.3V
Q
F1
IT
5
1.5V
G5
2.5V
S
Q
Slow Discharge
Flip-Flop
2.4V
A3
+
Slow Discharge
Comparator
Gnd
Figure 1: Block Diagram for CS51031
Circuit Description
At startup, the voltage on all pins is zero. As VCC rises, the
VC voltage along with the internal resistor RG keeps the
PFET off. As VCC and VC continue to rise, the oscillator
capacitor (COSC ) and the Soft start/Fault Timing capacitor
(CS) charges via internal current sources. COSC gets
charged by the current source IC and CS gets charged by
the IT source combination described by:
Theory of Operation
Control Scheme
The CS51031 monitors and the output voltage to determine
when to turn on the PFET. If VFB falls below the internal
reference voltage of 1.25V during the oscillatorÕs charge
cycle, the PFET is turned on and remains on for the duration of the charge time. The PFET gets turned off and
remains off during the oscillatorÕs discharge time with the
maximum duty cycle to 80%. It requires 7mV typical, and
20mV maximum ripple on the VFB pin is required to operate. This method of control does not require any loop stability compensation.
Startup
The CS51031 has an externally programmable soft start feature that allows the output voltage to come up slowly, preventing voltage overshoot on the output.
ICS = IT -
(
)
IT IT
+
.
55
5
The internal Holdoff Comparator ensures that the external
PFET is off until VCS > 0.7V, preventing the GATE flip-flop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
start is obtained by clamping the VFB comparatorÕs (A6)
reference input to approximately 1/2 of the voltage at the
CS pin during startup, permitting the control loop and the
output voltage to slowly increase. Once the CS pin charges
above the Holdoff Comparator trip point of 0.7V, the low
feedback to the VFB Comparator sets the GATE flip-flop
during COSC Õs charge cycle. Once the GATE flip-flop is set,
VGATE goes low and turns on the PFET. When VCS exceeds
4
CS51031
Circuit Description: continued
2.4V, the CS charge sense comparator (A4) sets the VFB
comparator reference to 1.25V completing the startup
cycle.
Buck Regulator Operation
L
Q1
VIN
R1
CIN
Lossless Short Circuit Protection
D1
The CS51031 has ÒlosslessÓ short circuit protection since
there is no current sense resistor required. When the voltage at the CS pin (the fault timing capacitor voltage ) reaches 2.5V during startup, the fault timing circuitry is enabled.
During normal operation the CS voltage is 2.6V. During a
short circuit or a transient condition, the output voltage
moves lower and the voltage at VFB drops. If VFB drops
below 1.15V, the output of the fault comparator goes high
and the CS51031 goes into a fast discharge mode. The fault
timing capacitor, CS, discharges to 2.4V. If the VFB voltage
is still below 1.15V when the CS pin reaches 2.4V, a valid
fault condition has been detected. The slow discharge
comparator output goes high and enables gate G5 which
sets the slow discharge flip flop. The Vgate flip flop resets
and the output switch is turned off. The fault timing
capacitor is slowly discharged to 1.5V. The CS51031 then
enters a normal startup routine. If the fault is still present
when the fault timing capacitor voltage reaches 2.5V, the
fast and slow discharge cycles repeat as shown in figure 2.
2.6V
S2
2.4V
S1
S2
Feedback
Figure 3. Buck regulator block diagram.
A block diagram of a typical buck regulator is shown in
Figure 3. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
inductor current IL is zero and the output voltage is at its
nominal value. The current drawn by the load is supplied
by the output capacitor CO . When the voltage across CO
drops below the threshold established by the feedback
resistors R1 and R2 and the reference voltage VREF, the
power transistor Q1 switches on and current flows through
the inductor to the output. The inductor current rises at a
rate determined by (VIN-VOUT)/L. The duty cycle (or ÒonÓ
time) for the CS51031 is limited to 80%. If output voltage
remains higher than nominal during the entire COSC
change time, the Q1 does not turn on, skipping the pulse.
2.5V
S2
S3
S1
S1
S3
RLOAD
Control
If the VFB voltage is above 1.15V when CS reaches 2.4V a
fault condition is not detected, normal operation resumes
and CS charges back to 2.6V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
VCS
CO
R2
S3
S3
1.5V
0V
0V
TSTART
START
td1
NORMAL OPERATION
tFAULT
tRESTART td2
tFAULT
FAULT
VGATE
1.25V
1.15V
VFB
Figure 2. Voltage on start capacitor (VGS ), the gate (VGATE ), and in the
feedback loop (VFB), during startup, normal and fault conditions.
Applications Information
1) Duty cycle estimates
Since the maximum duty cycle D, of the CS51031 is limited
to 80% min., it is necessary to estimate the duty cycle for
the various input conditions over the complete operating
range.
The duty cycle for a buck regulator operating in a continuous conduction mode is given by:
CS51031 Design Example
Specifications 12V to 5V, 3A Buck converter
VIN = 12V ±20% (i.e. 14.4V max., 12Vnom., 9.6V min.)
VOUT = 5V ±2%
IOUT = 0.3A to 3A
Output ripple voltage < 50mV max.
Efficiency > 80%
fSW = 200kHz
D=
5
VOUT + VF
VIN - VSAT
CS51031
Applications Information: continued
where VSAT = Rds(on) ´ IOUT max. and Rds(on)is the value at
TJ 100ûC.
If VF = 0.60V and VSAT = 0.60V then the above equation
becomes:
DMAX =
5.6
9
= 0.62
DMIN =
5.6
13.8
= 0.40
5) Output capacitor
The output capacitor and the inductor form a low pass filter. The output capacitor should have a low ESL and ESR.
Low impedance aluminum electrolytic, tantalum or organic semiconductor capacitors are a good choice for an output capacitor. Low impedance aluminum are less expensive. Solid tantalum chip capacitors are available from a
number of suppliers and are the best choice for surface
mount applications.
The output capacitor limits the output ripple voltage. The
CS51031 needs a maximum of 20mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50mV peak to peak is given by:
2) Switching frequency and on and off time calculations
Given that fSW = 200kHz and DMAX = 0.80
T=
1
fSW
= 5µs
TON(max) = T ´ DMAX = 5µs ´ 0.62 @ 3µs
C=
TON(min) = T ´ DMIN = 5µs ´ 0.40 = 2µs
TOFF(max) = TON(min) = 5µs - 2µs = 3µs
The minimum ESR needed to limit the output voltage ripple to 50mV peak to peak is:
3) Oscillator Capacitor Selection
ESR =
The switching frequency is set by COSC, whose value is
given by:
Fsw
(
1+
Fsw
3 ´ 10
(
6
30 ´ 10 3
Fsw
)
2
)
ÆV=ESR ´ ÆI = 83m½ ´ 0.4 = 33mV.
4) Inductor selection
6) VFB divider
The inductor value is chosen for continuous mode operation down to 0.3Amps.
(
VOUT = 1.25V
The ripple current ÆI = 2 ´ IOUTmin = 2 ´ 0.3A = 0.6A.
Lmin =
(VOUT + VD) ´ TOFF(max)
=
ÆI
5.6V ´ 3µs
0.6A
5.6V ´ 2µs
28µH
(
)
5V
= R1 + R2 = 5k½
1mA
A smaller inductor will result in larger ripple current.
Ripple current at a minimum off time is
(VOUT + VF) ´ TOFF(min)
=
LMIN
)
R1 + R2
R1
= 1.25V
+1
R2
R2
The input bias current to the comparator is 4µA. The resistor divider current should be considerably higher than this
to ensure that there is sufficient bias current. If we choose
the divider current to be at least 250 times the bias current
this permits a divider current of 1mA and simplifies the
calculations.
=28µH
This is the minimum value of inductor to keep the ripple
current to <0.6A during normal operation.
ÆI =
ÆV
50 ´ 10-3
=
= 83m½
ÆI
0.6A
The output capacitor should be chosen so that its ESR is
less than 83m½.
During the minimum off time, the ripple current is 0.4A
and the output voltage ripple will be:
95 ´ 10-6
COSC in pF =
ÆI
0.6A
=
= 7.5µF
3
8 ´ fSW ´ ÆV
8 ´ (200 ´ 10 Hz) ´ (50 ´ 10-3V)
Let R2 = 1K
Rearranging the divider equation gives:
=0.4A
(
R1 = R2
The core must not saturate with the maximum expected
current, here given by:
IMAX = IOUT + ÆI/2 = 3A+0.4A/2 = 3.2A
6
)
(
)
VOUT
5V
- 1 = 1k½
- 1 = 3k½
1.25
1.25
7) Divider bypass Capacitor Crr
Since the feedback resistors divide the output voltage by a
factor of 4, i.e. 5V/1.25V= 4, it follows that the output ripple
is also divided by four. This would require that the output
ripple be at least 60mV (4 ´ 15mV) to trip the feedback comparator. We use a capacitor Crr to act as an AC short .
The ripple voltage frequency is equal to the switching frequency so we choose Crr = 1nF.
tCharge(t) =
CS ´ (2.5V - 1.5V)
ICharge
Where ICharge is 264µA typical.
tCharge(t) = CS ´ 3787
The fault time is given by:
tFault = CS ´ (3787 + 1515 + 1.5 ´ 105)
tFault = CS ´ (1.55 ´ 105)
8) Soft start and Fault timing capacitor CS.
CS performs several important functions. First it provides a
delay time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly.
Secondly it disables the fault circuitry during startup, it
also provides soft start by clamping the reference voltage
during startup, allowing it to rise slowly, and, finally it
controls the hiccup short circuit protection circuitry. This
reduces the duty cycle to approximately 0.035 during short
circuit conditions.
An important consideration in calculating CS is that itÕs
voltage does not reach 2.5V (the voltage at which the fault
detect circuitry is enabled) before VFB reaches 1.15V otherwise the power supply will never start.
For this circuit
tFault = 0.1 ´ 10-6 ´ 1.55 ´ 105 = 15.5µS
A larger value of CS will increase the fault time out time
but will also increase the soft start time.
9) Input Capacitor
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage
on the VCC and VC pins. This capacitor must also ensure
that the VCC remains above the UVLO voltage in the event
of an output short circuit. A low ESR capacitor of at least
100µF is good. A ceramic surface mount capacitor should
also be connected between VCC and ground to filter high
frequency noise.
If the VFB pin reaches 1.15V, the fault timing comparator
will discharge CS and the supply will not start. For the VFB
voltage to reach 1.15V the output voltage must be at least
4 ´ 1.15 = 4.6V.
If we choose an arbitrary startup time of 900µs, the value of
CS is:
t Startup=
CSmin =
10) MOSFET Selection
The CS51031 drives a P-channel MOSFET. The VGATE pin
swings from Gnd to VC. The type of PFET used depends on
the operating conditions but for input voltages below 7V a
logic level FET should be used.
A PFET with a continuous drain current (ID) rating greater
than the maximum output current is required.
The Gate-to-Source voltage VGS and the Drain-to Source
Breakdown Voltage should be chosen based on the input
supply voltage.
The power dissipation due to the conduction losses is
given by:
PD = IOUT2 ´ RDS(ON) ´ D where
CS ´ 2.5V
ICharge
900µs ´ 264µA
= 950nF @ 0.1µF
2.5V
The fault time is the sum of the slow discharge time the fast
discharge time and the recharge time. It is dominated by the
slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4V to 1.5V and is
given by:
CS ´ (2.4V - 1.5V)
tSlowDischarge(t) =
IDischarge
RDS(ON) is the value at TJ = 100ûC.
The power dissipation of the PFET due to the switching losses is given by:
PD = 0.5 ´ VIN ´ IOUT ´ (tr ) ´ fSW
Where IDischarge is 6µA typical.
tSlowDischarge(t) = CS ´ 1.5 ´ 105
Where tr = Rise Time.
The fast discharge time occurs when a fault is first detected. The CS capacitor is discharged from 2.5V to 2.4V.
tFastDischarge(t) =
11) Diode Selection
The flyback or catch diode should be a Schottky diode
because of itÕs fast switching ability and low forward voltage drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should
be at least 20V for this 12V application.
The diode power dissipation is given by:
CS ´ (2.5V - 2.4V)
IFastDischarge
Where I FastDischarge is 66µA typical.
tFastDischarge(t) = CS ´ 1515
PD = IOUT ´ VD ´ (1 - Dmin)
The recharge time is the time for CS to charge from 1.5V to
2.5V.
7
CS51031
Applications Information: continued
CS51031
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
D
Lead Count
Metric
Max
Min
5.00
4.80
10.16
9.02
8L SO Narrow
8L PDIP
Thermal Data
RQJC
typ
RQJA
typ
English
Max Min
.197 .189
.400 .355
8L SO Narrow
45
165
8L PDIP
52
100
ûC/W
ûC/W
8L SO Narrow; 150 mil wide
4.00 (.157)
3.80 (.150)
6.20 (.244)
5.80 (.228)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
1.75 (.069) MAX
1.57 (.062)
1.37 (.054)
1.27 (.050)
0.40 (.016)
0.25 (.010)
0.19 (.008)
D
0.25 (0.10)
0.10 (.004)
REF: JEDEC MS-012
8L PDIP; 300 mil wide
7.11 (.280)
6.10 (.240)
8.26 (.325)
7.62 (.300)
1.77 (.070)
1.14 (.045)
2.54 (.100) BSC
3.68 (.145)
2.92 (.115)
.356 (.014)
.203 (.008)
0.39 (.015)
MIN.
.558 (.022)
.356 (.014)
REF: JEDEC MS-001
D
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
Ordering Information
Part Number
CS51031YD8
CS51031YDR8
CS51031YN8
Rev. 2/13/98
Description
8L SO Narrow
8L SO Narrow (tape & reel)
8L PDIP
Cherry Semiconductor Corporation reserves the right to
make changes to the specifications without notice. Please
contact Cherry Semiconductor Corporation for the latest
available information.
8
© 1999 Cherry Semiconductor Corporation
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