Qimonda HYS64T64020HDL-25F-B 200 pin small-outlined ddr2 sdrams module Datasheet

October 2007
HYS64T32x00HDL–[25F/2.5/3/3S/3.7/5]–B
HYS64T64x20HDL–[25F/2.5/3/3S/3.7/5]–B
HYS64T128x21HDL–[25F/2.5/3/3S/3.7/5]–B
2 0 0 Pi n S m a l l - O u t l i n e d D D R 2 S D R A M s M o d u l e s
DDR2 SDRAM
SO-DIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.12
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
HYS64T32x00HDL–[25F/2.5/3/3S/3.7/5]–B, HYS64T64x20HDL–[25F/2.5/3/3S/3.7/5]–B, HYS64T128x21HDL–
[25F/2.5/3/3S/3.7/5]–B
Revision History: 2007-10, Rev. 1.12
Page
Subjects (major changes since last revision)
6-11
Editorial changes and adapted to internet edition
Previous Revision: 2006-10, Rev 1.11
All
Editorial changes
Previous Revision: 2006-10, Rev 1.10
4
Added –25F Product Types; Added 6Layer –3S and –3.7 Product Types.
70, 71, 72
Updated Package Outline Drawings.
Previous Revision: 2005-09, Rev 1.01
All
Qimonda update
15
Modified AC Timing Parameters
Previous Revision: 2005-06, Rev 1.0
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qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
03292006-5LTN-QML0
2
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 200-pin Small-Outline DDR2 SDRAM modules product family and describes its main
characteristics.
1.1
Features
• 200-Pin PC2-6400, PC2-5300, PC2-4200 and PC2-3200
DDR2 SDRAM memory modules.
• 32M × 64, 64M × 64 and 128M × 64 module
organization,and 32M × 16, 64M × 8 chip organization
• 256MB, 512MB and 1GB modules built with 512-Mbit
DDR2 SDRAMs in P-TFBGA-84 and P-TFBGA-60
chipsize packages
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Programmable CAS Latencies (3, 4, 5 and 6 ), Burst
Length (8 & 4).
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
Serial Presence Detect with E2PROM
SO-DIMM Dimensions (nominal): 30 mm high, 67.6 mm
wide
Based on standard reference layouts Raw Cards 'A', 'C',
and 'E'
RoHS compliant products1)
•
•
•
•
TABLE 1
Performance Table
QAG Speed Code
–25F
–2.5
–3
–3S
–3.7
–5
Unit
DRAM Speed Grade
DDR2
–800D
–800E
–667C
–667D
–533C
–400B
Module Speed Grade
PC2
–6400D
–6400E
–5300C
–5300D
–4200C
–3200B
5–5–5
6–6–6
4–4–4
5–5–5
4–4–4
3–3–3
tCK
200
200
200
200
200
200
MHz
266
266
333
266
266
200
MHz
400
333
333
333
266
–
MHz
–
400
–
–
–
–
MHz
12.5
15
12
15
15
15
ns
12.5
15
12
15
15
15
ns
45
45
45
45
45
40
ns
57.5
60
57
60
60
55
ns
CAS-RCD-RP latencies
Max.
Clock Frequency
CL3
CL4
CL5
CL6
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
fCK3
fCK4
fCK5
fCK6
tRCD
tRP
tRAS
tRC
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.12, 2007-10
03292006-5LTN-QML0
3
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
1.2
Description
The memory array is designed with 512MBit Double-DataRate-Two (DDR2) Synchronous DRAMs.
Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The Qimonda HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
module family are small-outline DIMM modules “SO-DIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules
in 128M × 64 (1GB),
32M × 64 (256MB), 64M × 64 (512MB) in organization and
density, intended for mounting into 200-pin connector
sockets.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM Technology
256MB 1R×16 PC2–6400S–555–12–C0
1 Rank, Non-ECC
512Mbit (×16)
PC2-6400-555
HYS64T32000HDL–25F–B
HYS64T64020HDL–25F–B
512MB 2R×16 PC2–6400S–555–12–A0
2 Ranks, Non-ECC
512Mbit (×16)
HYS64T128021HDL–25F–B
1GB 2R×8 PC2–6400S–555–12–E0
2 Ranks, Non-ECC
512Mbit (×8)
PC2-6400-666
HYS64T32000HDL–2.5–B
256MB 1R×16 PC2–6400S–666–12–C0
1 Rank, Non-ECC
512Mbit (×16)
HYS64T64020HDL–2.5–B
512MB 2R×16 PC2–6400S–666–12–A0
2 Ranks, Non-ECC
512Mbit (×16)
HYS64T128021HDL–2.5–B
1GB 2R×8 PC2–6400S–666–12–E0
2 Ranks, Non-ECC
512Mbit (×8)
256MB 1R×16 PC2–5300S–444–12–C0
1 Rank, Non-ECC
512Mbit (×16)
PC2-5300-444
HYS64T32000HDL–3–B
HYS64T64020HDL–3–B
512MB 2R×16 PC2–5300S–444–12–A0
2 Ranks, Non-ECC
512Mbit (×16)
HYS64T128021HDL–3–B
1GB 2R×8 PC2–5300S–444–12–E0
2 Ranks, Non-ECC
512Mbit (×8)
PC2-5300-555
HYS64T32000HDL–3S–B
256MB 1R×16 PC2–5300S–555–12–C0
1 Rank, Non-ECC
512Mbit (×16)
HYS64T32900HDL–3S–B
256MB 1R×16 PC2–5300S–555–12–C0
1 Rank, Non-ECC
512Mbit (×16)
HYS64T64020HDL–3S–B
512MB 2R×16 PC2–5300S–555–12–A0
2 Ranks, Non-ECC
512Mbit (×16)
HYS64T64920HDL–3S–B
512MB 2R×16 PC2–5300S–555–12–A0
2 Ranks, Non-ECC
512Mbit (×16)
HYS64T128021HDL–3S–B
1GB 2R×8 PC2–5300S–555–12–E0
2 Ranks, Non-ECC
512Mbit (×8)
HYS64T128921HDL–3S–B
1GB 2R×8 PC2–5300S–555–12–E0
2 Ranks, Non-ECC
512Mbit (×8)
256MB 1R×16 PC2–4200S–444–12–C0
1 Rank, Non-ECC
512Mbit (×16)
PC2-4200-444
HYS64T32000HDL–3.7–B
HYS64T32900HDL–3.7–B
256MB 1R×16 PC2–4200S–444–12–C0
1 Rank, Non-ECC
512Mbit (×16)
HYS64T64020HDL–3.7–B
512MB 2R×16 PC2–4200S–444–12–A0
2 Ranks, Non-ECC
512Mbit (×16)
HYS64T64920HDL–3.7–B
512MB 2R×16 PC2–4200S–444–12–A0
2 Ranks, Non-ECC
512Mbit (×16)
HYS64T128021HDL–3.7–B
1GB 2R×8 PC2–4200S–444–12–E0
2 Ranks, Non-ECC
512Mbit (×8)
HYS64T128921HDL–3.7–B
1GB 2R×8 PC2–4200S–444–12–E0
2 Ranks, Non-ECC
512Mbit (×8)
256MB 1R×16 PC2–3200S–333–12–C0
1 Rank, Non-ECC
512Mbit (×16)
PC2-3200-333
HYS64T32000HDL–5–B
Rev. 1.12, 2007-10
03292006-5LTN-QML0
4
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Product Type1)
Compliance Code2)
Description
SDRAM Technology
HYS64T64020HDL–5–B
512MB 2R×16 PC2–3200S–333–12–A0
2 Ranks, Non-ECC
512Mbit (×16)
HYS64T128021HDL–5–B
1GB 2R×8 PC2–3200S–333–12–E0
2 Ranks, Non-ECC
512Mbit (×8)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400S–555–12–E0" where 6400S
means Small-Outline DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency
=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.2 and produced
on the Raw Card "E".
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
1GB
128M × 64
2
Non-ECC
16
14/2/10
E
512MB
64M × 64
2
Non-ECC
8
13/2/10
A
256MB
32M × 64
1
Non-ECC
4
13/2/10
C
TABLE 4
Components on Modules
Product Type
1)2)
HYS64T128021HDL
DRAM Components
1)
DRAM Density
DRAM Organisation
HYB18T512800BF
512Mbit
64M × 8
HYB18T512160BF
512Mbit
32M × 16
HYB18T512160BF
512Mbit
32M × 16
HYS64T128921HDL
HYS64T64020HDL
HYS64T64920HDL
HYS64T32000HDL
HYS64T32900HDL
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.12, 2007-10
03292006-5LTN-QML0
5
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
2
Pin Configurations
2.1
Pin Configurations
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations
used in columns Pin Type and Buffer Type are explained in Table 6 and Table 7 respectively. The Pin numbering is depicted
in Figure 1
TABLE 5
Pin Configuration of SO-DIMM
Pin No.
Name
Pin
Type
Buffer
Type
Function
30
CK0
I
SSTL
164
CK1
I
SSTL
32
CK0
I
SSTL
166
CK1
I
SSTL
Clock Signals 1:0, Complement Clock Signals 1:0
The system clock inputs. All address and command lines
are sampled on the cross point of the rising edge of CK and
the falling edge of CK. A Delay Locked Loop (DLL) circuit is
driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
79
CKE0
I
SSTL
80
CKE1
I
SSTL
NC
NC
—
Not Connected
Note: 1-rank module
110
S0
I
SSTL
115
S1
I
SSTL
Chip Select Rank 1:0
Enables the associated DDR2 SDRAM command decoder
when LOW and disables the command decoder when
HIGH. When the command decoder is disabled, new
commands are ignored but previous operations continue.
Rank 0 is selected by S0; Rank 1 is selected by S1. Ranks
are also called "Physical banks".2 Ranks module
NC
NC
—
Not Connected
Note: 1-rank module
108
RAS
I
SSTL
Row Address Strobe
When sampled at the cross point of the rising edge of CK,
and falling edge of CK, RAS, CAS and WE define the
operation to be executed by the SDRAM.
113
CAS
I
SSTL
Column Address Strobe
Clock Signals
Clock Enable Rank 1:0
Activates the DDR2 SDRAM CK signal when HIGH and
deactivates the CK signal when LOW. By deactivating the
clocks, CKE LOW initiates the Power Down Mode or the
Self Refresh Mode.
Note: 2 Ranks module
Control Signals
Rev. 1.12, 2007-10
03292006-5LTN-QML0
6
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Pin No.
Name
Pin
Type
Buffer
Type
Function
109
WE
I
SSTL
Write Enable
107
BA0
I
SSTL
106
BA1
I
SSTL
Bank Address Bus 2:0
Selects which DDR2 SDRAM internal bank of four or eight
is activated.
85
BA2
I
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
NC
SSTL
Less than 1Gb DDR2 SDRAMS
Address Bus 12:0
During a Bank Activate command cycle, defines the row
address when sampled at the cross-point of the rising edge
of CK and falling edge of CK. During a Read or Write
command cycle, defines the column address when sampled
at the cross point of the rising edge of CK and falling edge
of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If AP is HIGH, autoprecharge is selected and
BA0-BAn defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control
which bank(s) to precharge. If AP is HIGH, all banks will be
precharged regardless of the state of BA0-BAn inputs. If AP
is LOW, then BA0-BAn are used to define which bank to
precharge.
Address Signals
102
A0
I
SSTL
101
A1
I
SSTL
100
A2
I
SSTL
99
A3
I
SSTL
98
A4
I
SSTL
97
A5
I
SSTL
94
A6
I
SSTL
92
A7
I
SSTL
93
A8
I
SSTL
91
A9
I
SSTL
105
A10
I
SSTL
AP
I
SSTL
90
A11
I
SSTL
89
A12
I
SSTL
Address Signal 12
Note: Module based on 256 Mbit or larger dies
116
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based module
NC
NC
—
Not Connected
Note: Module based on 512 Mbit or smaller dies
A14
I
SSTL
Address Signal 14
Note: 2 Gbit based module
NC
NC
—
Not Connected
Note: Module based on 1 Gbit or smaller dies
86
Data Signals
Rev. 1.12, 2007-10
03292006-5LTN-QML0
7
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Pin No.
Name
Pin
Type
Buffer
Type
Function
5
DQ0
I/O
SSTL
7
DQ1
I/O
SSTL
Data Bus 63:0
Note: Data Input / Output pins
17
DQ2
I/O
SSTL
19
DQ3
I/O
SSTL
4
DQ4
I/O
SSTL
6
DQ5
I/O
SSTL
14
DQ6
I/O
SSTL
16
DQ7
I/O
SSTL
23
DQ8
I/O
SSTL
25
DQ9
I/O
SSTL
35
DQ10
I/O
SSTL
37
DQ11
I/O
SSTL
20
DQ12
I/O
SSTL
22
DQ13
I/O
SSTL
36
DQ14
I/O
SSTL
38
DQ15
I/O
SSTL
43
DQ16
I/O
SSTL
45
DQ17
I/O
SSTL
55
DQ18
I/O
SSTL
57
DQ19
I/O
SSTL
44
DQ20
I/O
SSTL
46
DQ21
I/O
SSTL
56
DQ22
I/O
SSTL
58
DQ23
I/O
SSTL
61
DQ24
I/O
SSTL
63
DQ25
I/O
SSTL
73
DQ26
I/O
SSTL
75
DQ27
I/O
SSTL
62
DQ28
I/O
SSTL
64
DQ29
I/O
SSTL
74
DQ30
I/O
SSTL
76
DQ31
I/O
SSTL
123
DQ32
I/O
SSTL
125
DQ33
I/O
SSTL
135
DQ34
I/O
SSTL
137
DQ35
I/O
SSTL
124
DQ36
I/O
SSTL
126
DQ37
I/O
SSTL
134
DQ38
I/O
SSTL
136
DQ39
I/O
SSTL
Rev. 1.12, 2007-10
03292006-5LTN-QML0
8
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Pin No.
Name
Pin
Type
Buffer
Type
Function
141
DQ40
I/O
SSTL
143
DQ41
I/O
SSTL
Data Bus 63:0
Note: Data Input / Output pins
151
DQ42
I/O
SSTL
153
DQ43
I/O
SSTL
140
DQ44
I/O
SSTL
142
DQ45
I/O
SSTL
152
DQ46
I/O
SSTL
154
DQ47
I/O
SSTL
157
DQ48
I/O
SSTL
159
DQ49
I/O
SSTL
173
DQ50
I/O
SSTL
175
DQ51
I/O
SSTL
158
DQ52
I/O
SSTL
160
DQ53
I/O
SSTL
174
DQ54
I/O
SSTL
176
DQ55
I/O
SSTL
179
DQ56
I/O
SSTL
181
DQ57
I/O
SSTL
189
DQ58
I/O
SSTL
191
DQ59
I/O
SSTL
180
DQ60
I/O
SSTL
182
DQ61
I/O
SSTL
192
DQ62
I/O
SSTL
194
DQ63
I/O
SSTL
Data Strobe Signals
13
DQS0
I/O
SSTL
11
DQS0
I/O
SSTL
31
DQS1
I/O
SSTL
29
DQS1
I/O
SSTL
51
DQS2
I/O
SSTL
49
DQS2
I/O
SSTL
70
DQS3
I/O
SSTL
68
DQS3
I/O
SSTL
131
DQS4
I/O
SSTL
129
DQS4
I/O
SSTL
148
DQS5
I/O
SSTL
146
DQS5
I/O
SSTL
169
DQS6
I/O
SSTL
167
DQS6
I/O
SSTL
188
DQS7
I/O
SSTL
Rev. 1.12, 2007-10
03292006-5LTN-QML0
Data Strobe Bus 7:0
The data strobes, associated with one data byte, sourced
with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data
window. In Read mode the data strobe is sourced by the
DDR2 SDRAM and is sent at the leading edge of the data
window. DQS signals are complements, and timing is
relative to the cross-point of respective DQS and DQS. If the
module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and
DDR2 SDRAM mode registers programmed appropriately.
9
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Pin No.
Name
Pin
Type
Buffer
Type
Function
186
DQS7
I/O
SSTL
Data Strobe Bus 7:0
10
DM0
I
SSTL
26
DM1
I
SSTL
52
DM2
I
SSTL
67
DM3
I
SSTL
Data Mask Bus 7:0
The data write masks, associated with one data byte. In
Write mode, DM operates as a byte mask by allowing input
data to be written if it is LOW but blocks the write operation
if it is HIGH. In Read mode, DM lines have no effect.
130
DM4
I
SSTL
147
DM5
I
SSTL
170
DM6
I
SSTL
185
DM7
I
SSTL
197
SCL
I
CMOS
Serial Bus Clock
This signal is used to clock data into and out of the SPD
EEPROM and Thermal sensor.
195
SDA
I/O
OD
Serial Bus Data
This is a bidirectional pin use to transfer data into and out of
the SPD EEPROM and Thermal sensor. A resistor must be
connected from SDA to VDDSPD on the motherboard to act as
a pull-up.
198
SA0
I
CMOS
200
SA1
I
CMOS
Serial Address Select Bus 2:0
Address pins used to select the SPD and Thermal sensor
base address.
50
EVENT
O
OD
EVENT
The optional EVENT pin is reserved for use to flag critical
module temperature and is used in conjunction with
Thermal Sensor.
NC
-
-
Not Connected
Not connected on modules without temperature sensors.
1
VREF
AI
—
I/O Reference Voltage
Reference voltage for the SSTL-18 inputs.
199
VDDSPD
PWR
—
EEPROM Power Supply
Power supplies for Serial Presence Detect, Thermal Sensor
and ground for the module.
81,82,87,88,95,96,103,104,
111,112,117,118
VDD
PWR
—
Power Supply
Power supplies for core, I/O and ground for the module.
2,3,8,9,12,15,18,21,24,27,28,
VSS
33,34,39,40,41,42,47,48,53,
54,59,60,65,66,71,72,77,78,
121,122,127,128,132,133,138,13
9,144,145,149,150,155,156,
161,162,165,168, 171,172,177,
178,183,184,187,190,193,196
GND
—
Ground Plane
Power supplies for core, I/O, Serial Presence Detect,
Thermal Sensor and ground for the module.
I
SSTL
On-Die Termination Control 1:0
Data Mask Signals
EEPROM
Power Supplies
Other pins
114
Rev. 1.12, 2007-10
03292006-5LTN-QML0
ODT0
10
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Pin No.
Name
Pin
Type
Buffer
Type
Function
119
ODT1
I
SSTL
On-Die Termination Control 1
Asserts on-die termination for DQ, DM, DQS, and DQS
signals if enabled via the DDR2 SDRAM mode register.
Note: 2 Rank modules
NC
NC
—
Not Connected
Note: 1 Rank modules
NC
NC
—
Not connected
Pins not connected on Qimonda SO-DIMMs
69,83,84,120,163
TABLE 6
Abbreviations for pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
TABLE 7
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tri-state, and
allows multiple devices to share as a wire-OR.
Rev. 1.12, 2007-10
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Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
FIGURE 1
Pin Configuration SO-DIMM (200 pin)
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Rev. 1.12, 2007-10
03292006-5LTN-QML0
12
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 8
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
Note
Min.
Max.
Voltage on VDD pin relative to VSS
–1.0
+2.3
V
1)
Voltage on VDDQ pin relative to VSS
–0.5
+2.3
V
1)1)
Voltage on VDDL pin relative to VSS
–0.5
+2.3
V
1)1)
Voltage on any pin relative to VSS
–0.5
+2.3
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
V
1)
VDD
VDDQ
VDDL
VIN, VOUT
TABLE 9
Environmental Requirements
Parameter
Symbol
Values
Unit
Note
Min.
Max.
0
+65
°C
Storage Temperature
TOPR
TSTG
– 50
+100
°C
1)
Barometric Pressure (operating & storage)
PBar
+69
+105
kPa
2)
Operating Humidity (relative)
HOPR
HSTG
10
90
%
5
95
%
Operating temperature (ambient)
Storage Humidity (without condensation)
1) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
2) Up to 3000 m.
Rev. 1.12, 2007-10
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SO-DIMM DDR2 SDRAM Module
TABLE 10
DRAM Component Operating Temperature Range
Symbol
TCASE
Parameter
Rating
Operating Temperature
Min.
Max.
0
95
Unit
Note
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
3.2
DC Operating Conditions
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
DC Input Logic High
DC Input Logic Low
Symbol
VDD
VDDQ
VREF
VDDSPD
VIH(DC)
VIL (DC)
IL
Values
Unit
Min.
Typ.
Max.
1.7
1.8
1.9
V
1.7
1.8
1.9
V
1)
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
2)
1.7
—
3.6
V
VREF + 0.125
—
V
– 0.30
—
VDDQ + 0.3
VREF – 0.125
V
In / Output Leakage Current
–5
—
5
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ.
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Rev. 1.12, 2007-10
03292006-5LTN-QML0
Note
14
3)
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
3.3
Timing Characteristics
3.3.1
Speed Grade Definitions
TABLE 12
Speed Grade Definition
Speed Grade
DDR2–800D
DDR2–800E
QAG Sort Name
–25F
–2.5
CAS-RCD-RP latencies
5–5–5
6–6–6
Parameter
Clock Period
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3.75
8
3.75
8
ns
1)2)3)4)
2.5
8
3
8
ns
1)2)3)4)
2.5
8
2.5
8
ns
1)2)3)4)
45
70k
45
70k
ns
1)2)3)4)5)
57.5
—
60
—
ns
1)2)3)4)
12.5
—
15
—
ns
1)2)3)4)
12.5
—
15
—
ns
1)2)3)4)
TABLE 13
Speed Grade Definition
Speed Grade
DDR2–667C
DDR2–667D
DDR2–533C
DDR2–400B
QAG Sort Name
–3
–3S
–3.7
–5
CAS-RCD-RP latencies
4–4–4
5–5–5
4–4–4
3–3–3
Parameter
Clock Period
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
5
8
5
8
ns
1)2)3)4)
3
8
3.75
8
3.75
8
5
8
ns
1)2)3)4)
3
8
3
8
3.75
8
5
8
ns
1)2)3)4)
45
70k
45
70k
45
70k
40
70k
ns
1)2)3)4)5)
57
—
60
—
60
—
55
—
ns
1)2)3)4)
12
—
15
—
15
—
15
—
ns
1)2)3)4)
12
—
15
—
15
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) mentioned in Component datasheet.
Rev. 1.12, 2007-10
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SO-DIMM DDR2 SDRAM Module
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
3.3.2
Component AC Timing Parameters
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Parameter
Symbol
DDR2–800
DDR2–667
Unit
Note2)3)5
)6)7)8)
Min.
tCCD
tCH.AVG
Average clock period
tCK.AVG
CKE minimum pulse width ( high and tCKE
Max.
Min.
Max.
CAS to CAS command delay
2
—
2
—
nCK
Average clock high pulse width
0.48
0.52
0.48
0.52
tCK.AVG
2500
8000
3000
8000
ps
3
—
3
—
nCK
12)
0.48
0.52
0.48
0.52
tCK.AVG
10)11)
WR + tnRP
—
WR + tnRP
—
nCK
13)14)
10)11)
low pulse width)
Average clock low pulse width
Auto-Precharge write recovery +
precharge time
tCL.AVG
tDAL
Minimum time clocks remain ON after tDELAY
CKE asynchronously drops LOW
tIS + tCK .AVG ––
+ tIH
tIS +
––
tCK .AVG + tIH
ns
tDH.BASE
DQ and DM input pulse width for each tDIPW
125
––
175
––
ps
0.35
—
0.35
—
tCK.AVG
DQS input high pulse width
tDQSH
tDQSL
DQS-DQ skew for DQS & associated tDQSQ
0.35
—
0.35
—
DQS input low pulse width
0.35
—
0.35
—
tCK.AVG
tCK.AVG
—
200
—
240
ps
16)
17)
DQ and DM input hold time
input
15)19)20)
DQ signals
DQS latching rising transition to
associated clock edges
tDQSS
– 0.25
+ 0.25
– 0.25
+ 0.25
tCK.AVG
DQ and DM input setup time
tDS.BASE
tDSH
tDSS
tHP
50
––
100
––
ps
18)19)20)
17)
Data-out high-impedance time from
CK / CK
Address and control input hold time
0.2
—
0.2
—
0.2
—
0.2
—
tCK.AVG
tCK.AVG
Min(tCH.ABS,
tCL.ABS)
__
Min(tCH.ABS,
tCL.ABS)
__
ps
21)
tHZ
—
tAC.MAX
—
tAC.MAX
ps
9)22)
tIH.BASE
tIPW
250
—
275
—
ps
23)25)
0.6
—
0.6
—
tCK.AVG
Address and control input setup time tIS.BASE
175
—
200
—
ps
24)25)
DQ low impedance time from CK/CK tLZ.DQ
2 x tAC.MIN
tAC.MAX
2 x tAC.MIN
tAC.MAX
ps
9)22)
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
Control & address input pulse width
for each input
Rev. 1.12, 2007-10
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17)
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Parameter
Symbol
DDR2–800
DDR2–667
Unit
Note2)3)5
)6)7)8)
Min.
Max.
Min.
Max.
tAC.MIN
tAC.MAX
tAC.MIN
tAC.MAX
ps
9)22)
MRS command to ODT update delay tMOD
0
12
0
12
ns
35)
Mode register set command cycle
time
tMRD
2
—
2
—
nCK
OCD drive mode output delay
tOIT
tQH
tQHS
tREFI
0
12
0
12
ns
35)
tHP – tQHS
—
tHP – tQHS
—
ps
26)
—
300
—
340
ps
27)
—
7.8
—
7.8
µs
28)29)
—
3.9
—
3.9
µs
28)30)
31)
DQS/DQS low-impedance time from
CK / CK
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
tLZ.DQS
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
105
—
105
—
ns
Precharge-All (4 banks) command
period
tRP
tRP
—
tRP
—
ns
Read preamble
tRPRE
tRPST
tRRD
0.9
1.1
0.9
1.1
32)33)
0.4
0.6
0.4
0.6
tCK.AVG
tCK.AVG
7.5
—
7.5
—
ns
35)
tRRD
10
—
10
—
ns
35)
Internal Read to Precharge command tRTP
delay
7.5
—
7.5
—
ns
35)
tWPRE
Write postamble
tWPST
Write recovery time
tWR
Internal write to read command delay tWTR
Exit power down to read command
tXARD
Exit active power-down mode to read tXARDS
0.35
—
0.35
—
0.4
0.6
0.4
0.6
tCK.AVG
tCK.AVG
15
—
15
—
ns
35)
7.5
—
7.5
—
ns
35)36)
2
—
2
—
nCK
8 – AL
—
7 – AL
—
nCK
Read postamble
Active to active command period for
1KB page size products
Active to active command period for
2KB page size products
Write preamble
32)34)
command (slow exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
—
2
—
nCK
Exit self-refresh to a non-read
command
tXSNR
tRFC +10
—
tRFC +10
—
ns
—
200
—
Exit self-refresh to read command
tXSRD
200
Write command to DQS associated
clock edges
WL
RL – 1
RL–1
35)
nCK
nCK
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
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Internet Data Sheet
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SO-DIMM DDR2 SDRAM Module
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. component
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT. component datasheet
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters component datasheet are referred to as 'input clock jitter spec parameters' and these
parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship component datasheet between the
average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations
component datasheet).
12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 3.
16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 3.
19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
23) input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 4.
24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 4.
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
26) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
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Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
27)
28)
29)
30)
31)
32)
33)
34)
35)
36)
tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
0 °C≤ TCASE ≤ 85 °C.
85 °C < TCASE ≤ 95 °C.
A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
FIGURE 2
Method for calculating transitions and endpoint
92+[P9
977[P9
92+[P9
977[P9
W/=
W+=
W535(EHJLQSRLQW
W5367
H QGSRLQW
92/[P9
977[P9
92/[P9
977[P9
7 7
7 7
W+=W5367
HQGSRLQW 77
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W/=W535(
E HJLQSRLQW 7
7
19
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
FIGURE 3
Differential input waveform timing tDS and tDH
'46
'46
W'6
W'+
W'
6
W'+
9
''
4
9
PL
Q
,+ D
F 9
PL
Q
,+ G
F 95() GF 9
PD
[
,/
G
F 9
PD
[
,/
D
F 9
66
0377
FIGURE 4
Differential input waveform timing tlS and tlH
&.
&.
W,6
W,+
W,6
W,+
9''4
9,+DF PLQ
9,+GF PLQ
95() GF 9,/ GF PD[
9,/ DF PD[
966
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Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–533 and DDR2–400
Parameter
Symbol
DDR2–533
DDR2–400
Unit
Notes2)3)
4)5)6)7)
Min.
Max.
Min.
Max.
tCCD
tCH
tCKE
2
—
2
—
0.45
0.55
0.45
0.55
3
—
3
—
tCL
tDAL
0.45
0.55
0.45
0.55
WR + tRP
—
WR + tRP
—
tCK
tCK
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
tDELAY
tIS + tCK + tIH ––
tIS + tCK + tIH ––
ns
9)
DQ and DM input hold time
(differential data strobe)
tDH.BASE
225
––
275
––
ps
10)
DQ and DM input hold time (single
ended data strobe)
tDH1.BASE
–25
—
25
—
ps
11)
DQ and DM input pulse width (each tDIPW
input)
0.35
—
0.35
—
tCK
DQS input HIGH pulse width (write
cycle)
tDQSH
0.35
—
0.35
—
tCK
DQS input LOW pulse width (write
cycle)
tDQSL
0.35
—
0.35
—
tCK
DQS-DQ skew (for DQS &
associated DQ signals)
tDQSQ
—
300
—
350
ps
– 0.25
+ 0.25
– 0.25
+ 0.25
tCK
100
—
150
—
ps
11)
DQ and DM input setup time (single tDS1.BASE
ended data strobe)
–25
—
25
—
ps
11)
DQS falling edge hold time from CK tDSH
(write cycle)
0.2
—
0.2
—
tCK
tDSS
0.2
—
0.2
—
tCK
tFAW
tFAW
Four Activate Window period
Clock half period
tHP
Data-out high-impedance time from tHZ
37.5
—
37.5
—
ns
50
—
50
—
ns
—
tAC.MAX
—
tAC.MAX
ps
13)
Address and control input hold time tIH.BASE
375
—
475
—
ps
11)
0.6
—
0.6
—
tCK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse
width
CK, CK low-level width
Auto-Precharge write recovery +
precharge time
Write command to 1st DQS latching tDQSS
transition
DQ and DM input setup time
(differential data strobe)
DQS falling edge to CK setup time
(write cycle)
tDS.BASE
Four Activate Window period
MIN. (tCL, tCH)
CK / CK
Address and control input pulse
width
(each input)
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21
tCK
tCK
tCK
8)
11)
13)
12)
MIN. (tCL, tCH)
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Parameter
Symbol
DDR2–533
DDR2–400
Unit
Notes2)3)
4)5)6)7)
Address and control input setup time tIS.BASE
Min.
Max.
Min.
Max.
250
—
350
—
ps
11)
DQ low-impedance time from CK /
CK
tLZ(DQ)
2 × tAC.MIN
tAC.MAX
2 × tAC.MIN
tAC.MAX
ps
14)
DQS low-impedance from CK / CK
tLZ(DQS)
tMOD
tAC.MIN
tAC.MAX
tAC.MIN
tAC.MAX
ps
14)
0
12
0
12
ns
Mode register set command cycle
time
tMRD
2
—
2
—
tCK
OCD drive mode output delay
tOIT
tQH
tQHS
tREFI
tREFI
tRFC
0
12
0
12
ns
tHP –tQHS
—
tHP –tQHS
—
—
400
—
450
ps
—
7.8
—
7.8
µs
14)15)
—
3.9
—
3.9
µs
16)18)
105
—
105
—
ns
17)
Precharge-All (4 banks) command
period
tRP
tRP
—
tRP
—
ns
Read preamble
tRPRE
tRPST
tRRD
0.9
1.1
0.9
1.1
14)
0.40
0.60
0.40
0.60
tCK
tCK
7.5
—
7.5
—
ns
14)18)
Active bank A to Active bank B
command period
tRRD
10
—
10
—
ns
16)22)
Internal Read to Precharge
command delay
tRTP
7.5
—
7.5
—
ns
0.25
—
0.25
—
0.40
0.60
0.40
0.60
tCK
tCK
15
—
15
—
ns
MRS command to ODT update
delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Average periodic refresh Interval
Auto-Refresh to Active/AutoRefresh command period
Read postamble
Active bank A to Active bank B
command period
tWPRE
Write postamble
tWPST
Write recovery time for write without tWR
Write preamble
14)
19)
Auto-Precharge
Internal Write to Read command
delay
tWTR
7.5
—
10
—
ns
20)
Exit power down to any valid
command
(other than NOP or Deselect)
tXARD
2
—
2
—
tCK
21)
Exit active power-down mode to
Read command (slow exit, lower
power)
tXARDS
6 – AL
—
6 – AL
—
tCK
21)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
—
2
—
tCK
Exit Self-Refresh to non-Read
command
tXSNR
tRFC +10
—
tRFC +10
—
ns
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HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Parameter
Symbol
DDR2–533
DDR2–400
Unit
Notes2)3)
4)5)6)7)
Min.
Max.
Min.
Max.
Exit Self-Refresh to Read command tXSRD
200
—
200
—
Write recovery time for write with
Auto-Precharge
tWR/tCK
WR
tWR/tCK
tCK
tCK
22)
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. component
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT. component datasheet
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C.
16) 85 °C < TCASE ≤ 95 °C.
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device
18) The tRRD timing parameter depends on the page size of the DRAM organization.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
Rev. 1.12, 2007-10
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Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
3.3.3
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
TABLE 16
ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Note
Min.
Max.
ODT turn-on delay
2
2
nCK
1)
ODT turn-on
tAC.MAX + 0.7 ns
2 tCK + tAC.MAX + 1 ns
ns
1)2)
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT turn-off delay
2.5
2.5
nCK
1)
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
1)3)
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT to Power Down Mode Entry Latency
3
—
nCK
nCK
1)
1)
ODT Power Down Exit Latency
8
—
1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800. Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “tCK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
TABLE 17
ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Min.
Max.
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC.MAX + 1 ns
2 tCK + tAC.MAX + 1 ns
ns
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT to Power Down Mode Entry Latency
3
—
ODT Power Down Exit Latency
8
—
tCK
tCK
Note
1)
2)
ns
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
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Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
3.4
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions.
TABLE 18
IDD Measurement Conditions
Symbol Note1)2)
Parameter
3)4)5)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,
tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
IDD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
Active Power-Down Current
IDD3P(0)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
IDD3P(1)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
IDD4R
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX;
tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
Rev. 1.12, 2007-10
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6)
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Symbol Note1)2)
Parameter
3)4)5)
Distributed Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5D
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
6)
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 19
4) For two rank modules: All active current measurements in the same IDD current mode. The other rank is in IDD2P Precharge Power-Down
Mode.
5) For details and notes see the relevant Qimonda component data sheet.
6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 19
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
STABLE
Inputs are stable at a HIGH or LOW level
FLOATING
Inputs are VREF = VDDQ /2
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
Rev. 1.12, 2007-10
03292006-5LTN-QML0
26
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 20
IDD Specification for HYS64T[32/64/128]xxxHDL–[25F/2.5]–B
820
mA
2)
28
56
110
mA
3)
820
200
408
820
mA
3)
360
720
180
360
720
mA
3)
160
312
624
156
310
620
mA
3)
40
72
144
40
70
140
mA
4)3)
240
480
960
240
480
960
mA
5)3)
720
750
1300
720
748
1300
mA
2)
800
830
1300
800
828
1300
mA
2)
580
610
1220
580
608
1220
mA
2)
40
72
144
40
70
140
mA
3)6)
24
40
80
24
40
80
mA
3)6)
1060
1088
HYS64T128021HDL–2.5–B
488
HYS64T64020HDL–2.5–B
2)
HYS64T32000HDL–2.5–B
mA
HYS64T128021HDL–25F–B
696
HYS64T64020HDL–25F–B
Note1)
HYS64T32000HDL–25F–B
Unit
Product Type
Organization
256 MB
512 MB
1 GB
256 MB
512 MB
1 GB
1 Rank
(×16)
2 Ranks
(×16)
2 Ranks
(×8)
1 Rank
(×16)
2 Ranks
(×16)
2 Ranks
(×8)
×64
×64
×64
×64
×64
×64
–25F
–25F
–25F
–2.5
–2.5
–2.5
Symbol
Max.
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
420
448
728
400
428
480
508
856
460
30
60
112
205
410
180
1416
1020
1048
1340
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.12, 2007-10
03292006-5LTN-QML0
27
2)
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 21
HYS64T32000HDL–3–B
HYS64T64020HDL–3–B
HYS64T128021HDL–3–B
HYS64T32000HDL–3S–B
HYS64T32900HDL–3S–B
HYS64T64020HDL–3S–B
HYS64T64920HDL–3S–B
HYS64T128021HDL–3S–B
HYS64T128921HDL–3S–B
IDD Specification for HYS64T[32/64/128]xxxHDL–[3/3S]–B
256 MB
512 MB
1 GB
256 MB
512 MB
1 GB
1 Rank
(×16)
2 Ranks
(×16)
2 Ranks
(×8)
1 Rank
(×16)
2 Ranks
(×16)
2 Ranks
(×8)
×64
×64
×64
×64
×64
×64
–3
–3
–3
–3S
–3S
–3S
Symbol
Max.
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
380
410
660
360
390
620
mA
2)
420
450
780
400
430
740
mA
2)
30
60
110
30
60
110
mA
3)
180
360
720
180
360
720
mA
3)
160
320
640
160
320
640
mA
3)
130
260
530
130
260
530
mA
3)
40
70
140
40
70
140
mA
4)3)
200
400
800
200
400
800
mA
5)3)
620
650
1100
620
650
1100
mA
2)
680
710
1100
680
710
1100
mA
2)
560
590
1180
560
590
1180
mA
2)
40
70
140
40
70
140
mA
3)6)
20
40
80
20
40
80
mA
3)6)
1010
1040
Product Type
Organization
Unit
Note1)
1340
960
990
1270
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.12, 2007-10
03292006-5LTN-QML0
28
2)
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 22
IDD Specification for HYS64T[32/64/128]xxxHDL–[3.7/5]–B
620
mA
2)
30
60
110
mA
3)
610
140
270
540
mA
3)
280
560
130
260
510
mA
3)
110
220
450
100
190
380
mA
3)
40
70
140
40
70
140
mA
4)3)
170
340
690
160
310
620
mA
5)3)
520
550
940
460
490
820
mA
2)
580
610
940
520
550
820
mA
2)
520
550
1100
500
530
1060
mA
2)
40
70
140
40
70
140
mA
3)6)
20
40
80
20
40
80
mA
3)6)
920
950
HYS64T128021HDL–5–B
360
HYS64T64020HDL–5–B
2)
HYS64T32000HDL–5–B
mA
HYS64T128021HDL–3.7–B
HYS64T128921HDL–3.7–B
540
HYS64T64020HDL–3.7–B
HYS64T64920HDL–3.7–B
Note1)
HYS64T32000HDL–3.7–B
HYS64T32900HDL–3.7–B
Unit
Product Type
Organization
256 MB
512 MB
1 GB
256 MB
512 MB
1 GB
1 Rank
(×16)
2 Ranks
(×16)
2 Ranks
(×8)
1 Rank
(×16)
2 Ranks
(×16)
2 Ranks
(×8)
×64
×64
×64
×64
×64
×64
–3.7
–3.7
–3.7
–5
–5
–5
Symbol
Max.
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
320
350
580
300
330
360
390
660
330
30
60
110
150
300
140
1220
880
910
1180
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.12, 2007-10
03292006-5LTN-QML0
29
2)
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
•
•
•
•
Table 23 “HYS64T[32/64/128]0xxHDL-25F-B” on Page 30
Table 24 “HYS64T[32/64/128]0xxHDL-2.5-B” on Page 35
Table 25 “HYS64T[32/64/128]0xxHDL-3-B” on Page 39
Table 26 “HYS64T[32/64/128]0xxHDL-3S-B” on Page 43
Table 27 “HYS64T[32/64/128]9xxHDL-3S-B” on Page 47
Table 28 “HYS64T[32/64/128]0xxHDL-3.7-B” on Page 51
Table 29 “HYS64T[32/64/128]9xxHDL-3.7-B” on Page 55
Table 30 “HYS64T[32/64/128]0xxHDL-5-B” on Page 59
TABLE 23
Product Type
HYS64T32000HDL–25F–B
HYS64T64020HDL–25F–B
HYS64T128021HDL–25F–B
HYS64T[32/64/128]0xxHDL-25F-B
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555
PC2–6400S–555
PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0D
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
61
61
6
Data Width
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
Rev. 1.12, 2007-10
03292006-5LTN-QML0
30
Internet Data Sheet
Product Type
HYS64T32000HDL–25F–B
HYS64T64020HDL–25F–B
HYS64T128021HDL–25F–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555
PC2–6400S–555
PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
9
25
25
25
10
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
40
40
40
11
Error Correction Support (non-ECC, ECC)
00
00
00
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
10
08
14
Error Checking SDRAM Width
00
00
00
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
70
70
70
19
DIMM Mechanical Characteristics
01
01
01
20
DIMM Type Information
04
04
04
21
DIMM Attributes
00
00
00
22
Component Attributes
07
07
07
23
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
24
25
26
27
28
29
30
25
25
25
40
40
40
3D
3D
3D
50
50
50
32
32
32
28
28
1E
32
32
32
2D
2D
2D
31
Module Density per Rank
40
40
80
32
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
17
17
17
25
25
25
05
05
05
33
34
Rev. 1.12, 2007-10
03292006-5LTN-QML0
31
Internet Data Sheet
Product Type
HYS64T32000HDL–25F–B
HYS64T64020HDL–25F–B
HYS64T128021HDL–25F–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555
PC2–6400S–555
PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
35
12
12
12
38
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
30
30
30
36
37
41
42
43
44
45
3C
3C
3C
1E
1E
1E
39
39
39
69
69
69
80
80
80
14
14
14
1E
1E
1E
46
PLL Relock Time
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
56
56
50
48
Psi(T-A) DRAM
7A
7A
7A
49
∆T0 (DT0)
7F
7F
5F
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
3B
3B
3B
51
∆T2P (DT2P)
36
36
36
52
∆T3N (DT3N)
2E
2E
2E
53
∆T3P.fast (DT3P fast)
5A
5A
5A
54
∆T3P.slow (DT3P slow)
2A
2A
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
68
68
5A
56
∆T5B (DT5B)
22
22
22
57
∆T7 (DT7)
3D
3D
27
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
Rev. 1.12, 2007-10
03292006-5LTN-QML0
32
Internet Data Sheet
Product Type
HYS64T32000HDL–25F–B
HYS64T64020HDL–25F–B
HYS64T128021HDL–25F–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555
PC2–6400S–555
PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
61
∆TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
12
12
12
63
Checksum of Bytes 0-62
54
55
3A
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
36
74
Product Type, Char 2
34
34
34
75
Product Type, Char 3
54
54
54
76
Product Type, Char 4
33
36
31
77
Product Type, Char 5
32
34
32
78
Product Type, Char 6
30
30
38
79
Product Type, Char 7
30
32
30
80
Product Type, Char 8
30
30
32
81
Product Type, Char 9
48
48
31
82
Product Type, Char 10
44
44
48
83
Product Type, Char 11
4C
4C
44
84
Product Type, Char 12
32
32
4C
85
Product Type, Char 13
35
35
32
86
Product Type, Char 14
46
46
35
Rev. 1.12, 2007-10
03292006-5LTN-QML0
33
Internet Data Sheet
Product Type
HYS64T32000HDL–25F–B
HYS64T64020HDL–25F–B
HYS64T128021HDL–25F–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–555
PC2–6400S–555
PC2–6400S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
87
Product Type, Char 15
42
42
46
88
Product Type, Char 16
20
20
42
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
3x
3x
3x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
99 - 127 Not used
00
00
00
128 255
FF
FF
FF
Blank for customer use
Rev. 1.12, 2007-10
03292006-5LTN-QML0
34
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 24
Product Type
HYS64T32000HDL–2.5–B
HYS64T64020HDL–2.5–B
HYS64T128021HDL–2.5–B
HYS64T[32/64/128]0xxHDL-2.5-B
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666
PC2–6400S–666
PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0D
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
61
61
6
Data Width
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
25
25
25
10
40
40
40
11
Error Correction Support (non-ECC, ECC)
00
00
00
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
10
08
14
Error Checking SDRAM Width
00
00
00
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
70
70
70
19
DIMM Mechanical Characteristics
01
01
01
20
DIMM Type Information
04
04
04
21
DIMM Attributes
00
00
00
22
Component Attributes
07
07
07
Rev. 1.12, 2007-10
03292006-5LTN-QML0
35
Internet Data Sheet
Product Type
HYS64T32000HDL–2.5–B
HYS64T64020HDL–2.5–B
HYS64T128021HDL–2.5–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666
PC2–6400S–666
PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
23
30
30
30
45
45
45
3D
3D
3D
50
50
50
3C
3C
3C
28
28
1E
3C
3C
3C
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
2D
2D
2D
31
Module Density per Rank
40
40
80
32
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
00
00
00
3C
3C
3C
69
69
69
80
80
80
14
14
14
1E
1E
1E
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
45
17
17
17
25
25
25
05
05
05
12
12
12
3C
3C
3C
1E
1E
1E
46
PLL Relock Time
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
55
55
50
48
Psi(T-A) DRAM
72
72
7A
Rev. 1.12, 2007-10
03292006-5LTN-QML0
36
Internet Data Sheet
Product Type
HYS64T32000HDL–2.5–B
HYS64T64020HDL–2.5–B
HYS64T128021HDL–2.5–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666
PC2–6400S–666
PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
49
∆T0 (DT0)
6F
6F
5B
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
37
37
3B
51
∆T2P (DT2P)
33
33
36
52
∆T3N (DT3N)
2B
2B
2E
53
∆T3P.fast (DT3P fast)
54
54
5A
54
∆T3P.slow (DT3P slow)
27
27
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
62
62
5A
56
∆T5B (DT5B)
1F
1F
22
57
∆T7 (DT7)
37
37
25
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
12
12
12
63
Checksum of Bytes 0-62
10
11
2B
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
36
74
Product Type, Char 2
34
34
34
Rev. 1.12, 2007-10
03292006-5LTN-QML0
37
Internet Data Sheet
Product Type
HYS64T32000HDL–2.5–B
HYS64T64020HDL–2.5–B
HYS64T128021HDL–2.5–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–6400S–666
PC2–6400S–666
PC2–6400S–666
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
75
Product Type, Char 3
54
54
54
76
Product Type, Char 4
33
36
31
77
Product Type, Char 5
32
34
32
78
Product Type, Char 6
30
30
38
79
Product Type, Char 7
30
32
30
80
Product Type, Char 8
30
30
32
81
Product Type, Char 9
48
48
31
82
Product Type, Char 10
44
44
48
83
Product Type, Char 11
4C
4C
44
84
Product Type, Char 12
32
32
4C
85
Product Type, Char 13
2E
2E
32
86
Product Type, Char 14
35
35
2E
87
Product Type, Char 15
42
42
35
88
Product Type, Char 16
20
20
42
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
4x
4x
4x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
99 - 127 Not used
00
00
00
128 255
FF
FF
FF
Blank for customer use
Rev. 1.12, 2007-10
03292006-5LTN-QML0
38
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 25
Product Type
HYS64T32000HDL–3–B
HYS64T64020HDL–3–B
HYS64T128021HDL–3–B
HYS64T[32/64/128]0xxHDL-3-B
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444
PC2–5300S–444
PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0D
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
61
61
6
Data Width
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
30
30
30
10
45
45
45
11
Error Correction Support (non-ECC, ECC)
00
00
00
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
10
08
14
Error Checking SDRAM Width
00
00
00
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
20
DIMM Type Information
04
04
04
21
DIMM Attributes
00
00
00
22
Component Attributes
07
07
07
23
tCK @ CLMAX -1 (Byte 18) [ns]
30
30
30
Rev. 1.12, 2007-10
03292006-5LTN-QML0
39
Internet Data Sheet
Product Type
HYS64T32000HDL–3–B
HYS64T64020HDL–3–B
HYS64T128021HDL–3–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444
PC2–5300S–444
PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
24
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
45
45
45
31
32
25
26
27
28
29
30
33
34
35
36
37
38
50
50
50
60
60
60
30
30
30
28
28
1E
30
30
30
2D
2D
2D
Module Density per Rank
40
40
80
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
20
20
20
27
27
27
10
10
10
17
17
17
3C
3C
3C
1E
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
00
00
00
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
46
PLL Relock Time
41
42
43
44
39
39
39
69
69
69
80
80
80
18
18
18
22
22
22
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
54
54
50
48
Psi(T-A) DRAM
72
72
7A
49
∆T0 (DT0)
67
67
53
Rev. 1.12, 2007-10
03292006-5LTN-QML0
40
Internet Data Sheet
Product Type
HYS64T32000HDL–3–B
HYS64T64020HDL–3–B
HYS64T128021HDL–3–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444
PC2–5300S–444
PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
31
31
34
51
∆T2P (DT2P)
33
33
36
52
∆T3N (DT3N)
24
24
27
53
∆T3P.fast (DT3P fast)
47
47
4C
54
∆T3P.slow (DT3P slow)
27
27
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
54
54
4C
56
∆T5B (DT5B)
1E
1E
20
57
∆T7 (DT7)
37
37
25
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
12
12
12
63
Checksum of Bytes 0-62
E1
E2
FA
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
36
74
Product Type, Char 2
34
34
34
75
Product Type, Char 3
54
54
54
Rev. 1.12, 2007-10
03292006-5LTN-QML0
41
Internet Data Sheet
Product Type
HYS64T32000HDL–3–B
HYS64T64020HDL–3–B
HYS64T128021HDL–3–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–444
PC2–5300S–444
PC2–5300S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
76
Product Type, Char 4
33
36
31
77
Product Type, Char 5
32
34
32
78
Product Type, Char 6
30
30
38
79
Product Type, Char 7
30
32
30
80
Product Type, Char 8
30
30
32
81
Product Type, Char 9
48
48
31
82
Product Type, Char 10
44
44
48
83
Product Type, Char 11
4C
4C
44
84
Product Type, Char 12
33
33
4C
85
Product Type, Char 13
42
42
33
86
Product Type, Char 14
20
20
42
87
Product Type, Char 15
20
20
20
88
Product Type, Char 16
20
20
20
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
3x
3x
4x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
99 - 127 Not used
00
00
00
128 255
FF
FF
FF
Blank for customer use
Rev. 1.12, 2007-10
03292006-5LTN-QML0
42
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 26
Product Type
HYS64T32000HDL–3S–B
HYS64T64020HDL–3S–B
HYS64T128021HDL–3S–B
HYS64T[32/64/128]0xxHDL-3S-B
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555
PC2–5300S–555
PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0D
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
61
61
6
Data Width
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
30
30
30
10
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
45
45
45
11
Error Correction Support (non-ECC, ECC)
00
00
00
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
10
08
14
Error Checking SDRAM Width
00
00
00
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
20
DIMM Type Information
04
04
04
21
DIMM Attributes
00
00
00
22
Component Attributes
07
07
07
Rev. 1.12, 2007-10
03292006-5LTN-QML0
43
Internet Data Sheet
Product Type
HYS64T32000HDL–3S–B
HYS64T64020HDL–3S–B
HYS64T128021HDL–3S–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555
PC2–5300S–555
PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
23
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
24
25
26
27
28
29
30
3D
3D
3D
50
50
50
50
50
50
60
60
60
3C
3C
3C
28
28
1E
3C
3C
3C
2D
2D
2D
31
Module Density per Rank
40
40
80
32
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
20
20
20
27
27
27
10
10
10
17
17
17
33
34
35
36
37
38
3C
3C
3C
1E
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
00
00
00
3C
3C
3C
69
69
69
80
80
80
18
18
18
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
22
22
22
46
PLL Relock Time
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
54
54
50
48
Psi(T-A) DRAM
72
72
7A
41
42
43
44
Rev. 1.12, 2007-10
03292006-5LTN-QML0
44
Internet Data Sheet
Product Type
HYS64T32000HDL–3S–B
HYS64T64020HDL–3S–B
HYS64T128021HDL–3S–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555
PC2–5300S–555
PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
49
∆T0 (DT0)
5F
5F
4B
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
31
31
34
51
∆T2P (DT2P)
33
33
36
52
∆T3N (DT3N)
24
24
27
53
∆T3P.fast (DT3P fast)
47
47
4C
54
∆T3P.slow (DT3P slow)
27
27
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
54
54
4C
56
∆T5B (DT5B)
1E
1E
20
57
∆T7 (DT7)
34
34
23
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
12
12
12
63
Checksum of Bytes 0-62
09
0A
23
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
36
74
Product Type, Char 2
34
34
34
Rev. 1.12, 2007-10
03292006-5LTN-QML0
45
Internet Data Sheet
Product Type
HYS64T32000HDL–3S–B
HYS64T64020HDL–3S–B
HYS64T128021HDL–3S–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555
PC2–5300S–555
PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
75
Product Type, Char 3
54
54
54
76
Product Type, Char 4
33
36
31
77
Product Type, Char 5
32
34
32
78
Product Type, Char 6
30
30
38
79
Product Type, Char 7
30
32
30
80
Product Type, Char 8
30
30
32
81
Product Type, Char 9
48
48
31
82
Product Type, Char 10
44
44
48
83
Product Type, Char 11
4C
4C
44
84
Product Type, Char 12
33
33
4C
85
Product Type, Char 13
53
53
33
86
Product Type, Char 14
42
42
53
87
Product Type, Char 15
20
20
42
88
Product Type, Char 16
20
20
20
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
4x
4x
4x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
99 - 127 Not used
00
00
00
128 255
FF
FF
FF
Blank for customer use
Rev. 1.12, 2007-10
03292006-5LTN-QML0
46
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 27
Product Type
HYS64T32900HDL–3S–B
HYS64T64920HDL–3S–B
HYS64T128921HDL–3S–B
HYS64T[32/64/128]9xxHDL-3S-B
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555
PC2–5300S–555
PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0D
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
61
61
6
Data Width
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
30
30
30
10
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
45
45
45
11
Error Correction Support (non-ECC, ECC)
00
00
00
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
10
08
14
Error Checking SDRAM Width
00
00
00
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
20
DIMM Type Information
04
04
04
21
DIMM Attributes
00
00
00
22
Component Attributes
07
07
07
Rev. 1.12, 2007-10
03292006-5LTN-QML0
47
Internet Data Sheet
Product Type
HYS64T32900HDL–3S–B
HYS64T64920HDL–3S–B
HYS64T128921HDL–3S–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555
PC2–5300S–555
PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
23
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
24
25
26
27
28
29
30
3D
3D
3D
50
50
50
50
50
50
60
60
60
3C
3C
3C
28
28
1E
3C
3C
3C
2D
2D
2D
31
Module Density per Rank
40
40
80
32
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
20
20
20
27
27
27
10
10
10
17
17
17
33
34
35
36
37
38
3C
3C
3C
1E
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
00
00
00
3C
3C
3C
69
69
69
80
80
80
18
18
18
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
22
22
22
46
PLL Relock Time
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
54
54
50
48
Psi(T-A) DRAM
72
72
7A
41
42
43
44
Rev. 1.12, 2007-10
03292006-5LTN-QML0
48
Internet Data Sheet
Product Type
HYS64T32900HDL–3S–B
HYS64T64920HDL–3S–B
HYS64T128921HDL–3S–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555
PC2–5300S–555
PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
49
∆T0 (DT0)
5F
5F
4B
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
31
31
34
51
∆T2P (DT2P)
33
33
36
52
∆T3N (DT3N)
24
24
27
53
∆T3P.fast (DT3P fast)
47
47
4C
54
∆T3P.slow (DT3P slow)
27
27
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
54
54
4C
56
∆T5B (DT5B)
1E
1E
20
57
∆T7 (DT7)
34
34
23
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
12
12
12
63
Checksum of Bytes 0-62
09
0A
23
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
36
74
Product Type, Char 2
34
34
34
Rev. 1.12, 2007-10
03292006-5LTN-QML0
49
Internet Data Sheet
Product Type
HYS64T32900HDL–3S–B
HYS64T64920HDL–3S–B
HYS64T128921HDL–3S–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–5300S–555
PC2–5300S–555
PC2–5300S–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
75
Product Type, Char 3
54
54
54
76
Product Type, Char 4
33
36
31
77
Product Type, Char 5
32
34
32
78
Product Type, Char 6
39
39
38
79
Product Type, Char 7
30
32
39
80
Product Type, Char 8
30
30
32
81
Product Type, Char 9
48
48
31
82
Product Type, Char 10
44
44
48
83
Product Type, Char 11
4C
4C
44
84
Product Type, Char 12
33
33
4C
85
Product Type, Char 13
53
53
33
86
Product Type, Char 14
42
42
53
87
Product Type, Char 15
20
20
42
88
Product Type, Char 16
20
20
20
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
2x
2x
2x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
99 - 127 Not used
00
00
00
128 255
FF
FF
FF
Blank for customer use
Rev. 1.12, 2007-10
03292006-5LTN-QML0
50
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 28
Product Type
HYS64T32000HDL–3.7–B
HYS64T64020HDL–3.7–B
HYS64T128021HDL–3.7–B
HYS64T[32/64/128]0xxHDL-3.7-B
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0D
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
61
61
6
Data Width
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
3D
3D
3D
10
50
50
50
11
Error Correction Support (non-ECC, ECC)
00
00
00
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
10
08
14
Error Checking SDRAM Width
00
00
00
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
20
DIMM Type Information
04
04
04
21
DIMM Attributes
00
00
00
22
Component Attributes
07
07
07
Rev. 1.12, 2007-10
03292006-5LTN-QML0
51
Internet Data Sheet
Product Type
HYS64T32000HDL–3.7–B
HYS64T64020HDL–3.7–B
HYS64T128021HDL–3.7–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
23
3D
3D
3D
50
50
50
50
50
50
60
60
60
3C
3C
3C
28
28
1E
3C
3C
3C
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
2D
2D
2D
31
Module Density per Rank
40
40
80
32
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
00
00
00
3C
3C
3C
69
69
69
80
80
80
1E
1E
1E
28
28
28
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
45
25
25
25
37
37
37
10
10
10
22
22
22
3C
3C
3C
1E
1E
1E
46
PLL Relock Time
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
54
54
50
48
Psi(T-A) DRAM
72
72
7A
Rev. 1.12, 2007-10
03292006-5LTN-QML0
52
Internet Data Sheet
Product Type
HYS64T32000HDL–3.7–B
HYS64T64020HDL–3.7–B
HYS64T128021HDL–3.7–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
49
∆T0 (DT0)
53
53
43
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
29
29
2C
51
∆T2P (DT2P)
33
33
36
52
∆T3N (DT3N)
1F
1F
21
53
∆T3P.fast (DT3P fast)
3D
3D
41
54
∆T3P.slow (DT3P slow)
27
27
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
46
46
40
56
∆T5B (DT5B)
1C
1C
1E
57
∆T7 (DT7)
32
32
22
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
12
12
12
63
Checksum of Bytes 0-62
18
19
37
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
36
74
Product Type, Char 2
34
34
34
Rev. 1.12, 2007-10
03292006-5LTN-QML0
53
Internet Data Sheet
Product Type
HYS64T32000HDL–3.7–B
HYS64T64020HDL–3.7–B
HYS64T128021HDL–3.7–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
75
Product Type, Char 3
54
54
54
76
Product Type, Char 4
33
36
31
77
Product Type, Char 5
32
34
32
78
Product Type, Char 6
30
30
38
79
Product Type, Char 7
30
32
30
80
Product Type, Char 8
30
30
32
81
Product Type, Char 9
48
48
31
82
Product Type, Char 10
44
44
48
83
Product Type, Char 11
4C
4C
44
84
Product Type, Char 12
33
33
4C
85
Product Type, Char 13
2E
2E
33
86
Product Type, Char 14
37
37
2E
87
Product Type, Char 15
42
42
37
88
Product Type, Char 16
20
20
42
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
4x
4x
4x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
99 - 127 Not used
00
00
00
128 255
FF
FF
FF
Blank for customer use
Rev. 1.12, 2007-10
03292006-5LTN-QML0
54
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 29
Product Type
HYS64T32900HDL–3.7–B
HYS64T64920HDL–3.7–B
HYS64T128921HDL–3.7–B
HYS64T[32/64/128]9xxHDL-3.7-B
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0D
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
61
61
6
Data Width
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
3D
3D
3D
10
50
50
50
11
Error Correction Support (non-ECC, ECC)
00
00
00
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
10
08
14
Error Checking SDRAM Width
00
00
00
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
20
DIMM Type Information
04
04
04
21
DIMM Attributes
00
00
00
22
Component Attributes
07
07
07
Rev. 1.12, 2007-10
03292006-5LTN-QML0
55
Internet Data Sheet
Product Type
HYS64T32900HDL–3.7–B
HYS64T64920HDL–3.7–B
HYS64T128921HDL–3.7–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
23
3D
3D
3D
50
50
50
50
50
50
60
60
60
3C
3C
3C
28
28
1E
3C
3C
3C
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
2D
2D
2D
31
Module Density per Rank
40
40
80
32
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
00
00
00
3C
3C
3C
69
69
69
80
80
80
1E
1E
1E
28
28
28
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
45
25
25
25
37
37
37
10
10
10
22
22
22
3C
3C
3C
1E
1E
1E
46
PLL Relock Time
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
54
54
50
48
Psi(T-A) DRAM
72
72
7A
Rev. 1.12, 2007-10
03292006-5LTN-QML0
56
Internet Data Sheet
Product Type
HYS64T32900HDL–3.7–B
HYS64T64920HDL–3.7–B
HYS64T128921HDL–3.7–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
49
∆T0 (DT0)
53
53
43
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
29
29
2C
51
∆T2P (DT2P)
33
33
36
52
∆T3N (DT3N)
1F
1F
21
53
∆T3P.fast (DT3P fast)
3D
3D
41
54
∆T3P.slow (DT3P slow)
27
27
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
46
46
40
56
∆T5B (DT5B)
1C
1C
1E
57
∆T7 (DT7)
32
32
22
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
12
12
12
63
Checksum of Bytes 0-62
18
19
37
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
36
74
Product Type, Char 2
34
34
34
Rev. 1.12, 2007-10
03292006-5LTN-QML0
57
Internet Data Sheet
Product Type
HYS64T32900HDL–3.7–B
HYS64T64920HDL–3.7–B
HYS64T128921HDL–3.7–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–4200S–444
PC2–4200S–444
PC2–4200S–444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
75
Product Type, Char 3
54
54
54
76
Product Type, Char 4
33
36
31
77
Product Type, Char 5
32
34
32
78
Product Type, Char 6
39
39
38
79
Product Type, Char 7
30
32
39
80
Product Type, Char 8
30
30
32
81
Product Type, Char 9
48
48
31
82
Product Type, Char 10
44
44
48
83
Product Type, Char 11
4C
4C
44
84
Product Type, Char 12
33
33
4C
85
Product Type, Char 13
2E
2E
33
86
Product Type, Char 14
37
37
2E
87
Product Type, Char 15
42
42
37
88
Product Type, Char 16
20
20
42
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
2x
2x
2x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
99 - 127 Not used
00
00
00
128 255
FF
FF
FF
Blank for customer use
Rev. 1.12, 2007-10
03292006-5LTN-QML0
58
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
TABLE 30
Product Type
HYS64T32000HDL–5–B
HYS64T64020HDL–5–B
HYS64T128021HDL–5–B
HYS64T[32/64/128]0xxHDL-5-B
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0D
0D
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
60
61
61
6
Data Width
40
40
40
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
50
50
50
10
60
60
60
11
Error Correction Support (non-ECC, ECC)
00
00
00
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
10
10
08
14
Error Checking SDRAM Width
00
00
00
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
20
DIMM Type Information
04
04
04
21
DIMM Attributes
00
00
00
22
Component Attributes
07
07
07
23
tCK @ CLMAX -1 (Byte 18) [ns]
50
50
50
Rev. 1.12, 2007-10
03292006-5LTN-QML0
59
Internet Data Sheet
Product Type
HYS64T32000HDL–5–B
HYS64T64020HDL–5–B
HYS64T128021HDL–5–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
24
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
60
60
60
31
32
25
26
27
28
29
30
33
34
35
36
37
38
50
50
50
60
60
60
3C
3C
3C
28
28
1E
3C
3C
3C
28
28
28
Module Density per Rank
40
40
80
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
35
35
35
47
47
47
15
15
15
27
27
27
3C
3C
3C
28
28
28
1E
1E
1E
39
Analysis Characteristics
00
00
00
40
00
00
00
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
46
PLL Relock Time
41
42
43
44
37
37
37
69
69
69
80
80
80
23
23
23
2D
2D
2D
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
54
54
50
48
Psi(T-A) DRAM
72
72
7A
49
∆T0 (DT0)
4B
4B
3B
Rev. 1.12, 2007-10
03292006-5LTN-QML0
60
Internet Data Sheet
Product Type
HYS64T32000HDL–5–B
HYS64T64020HDL–5–B
HYS64T128021HDL–5–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
25
25
27
51
∆T2P (DT2P)
33
33
36
52
∆T3N (DT3N)
1C
1C
1E
53
∆T3P.fast (DT3P fast)
34
34
38
54
∆T3P.slow (DT3P slow)
27
27
2A
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
3E
3E
38
56
∆T5B (DT5B)
1B
1B
1D
57
∆T7 (DT7)
30
30
21
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
12
12
12
63
Checksum of Bytes 0-62
6F
70
8E
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
36
74
Product Type, Char 2
34
34
34
75
Product Type, Char 3
54
54
54
Rev. 1.12, 2007-10
03292006-5LTN-QML0
61
Internet Data Sheet
Product Type
HYS64T32000HDL–5–B
HYS64T64020HDL–5–B
HYS64T128021HDL–5–B
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Organization
256MB
512MB
1 GByte
×64
×64
×64
1 Rank (×16)
2 Ranks (×16)
2 Ranks (×8)
Label Code
PC2–3200S–333
PC2–3200S–333
PC2–3200S–333
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
76
Product Type, Char 4
33
36
31
77
Product Type, Char 5
32
34
32
78
Product Type, Char 6
30
30
38
79
Product Type, Char 7
30
32
30
80
Product Type, Char 8
30
30
32
81
Product Type, Char 9
48
48
31
82
Product Type, Char 10
44
44
48
83
Product Type, Char 11
4C
4C
44
84
Product Type, Char 12
35
35
4C
85
Product Type, Char 13
42
42
35
86
Product Type, Char 14
20
20
42
87
Product Type, Char 15
20
20
20
88
Product Type, Char 16
20
20
20
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
4x
4x
4x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
99 - 127 Not used
00
00
00
128 255
FF
FF
FF
Blank for customer use
Rev. 1.12, 2007-10
03292006-5LTN-QML0
62
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
5
Package Outlines
FIGURE 5
Package Outline Raw Card C L-DIM-200-30
-!8
›
›
›
›
›
›
›
›
$ETAIL OF CONTACTS
›
›
›
›
›
›
›
-).
$RAWING ACCORDING TO )3/ 'ENERAL TOLERANCES ›
$IMENSIONS IN MM
)32B/B',0BBBB
Notes
1. Thermal Sensor (Optional)
2. SPD or Combidevice (if used then no Thermal Sensor needed)
Rev. 1.12, 2007-10
03292006-5LTN-QML0
63
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
FIGURE 6
Package Outline Raw Card A L-DIM-200-31
-!8
›
›
›
›
›
›
›
›
$ETAIL OF CONTACTS
›
›
›
›
›
›
›
-).
$RAWING ACCORDING TO )3/ 'ENERAL TOLERANCES ›
$IMENSIONS IN MM
)32B/B',0BBBB
Notes
1. Thermal Sensor (Optional)
2. SPD or Combidevice (if used then no Thermal Sensor needed)
Rev. 1.12, 2007-10
03292006-5LTN-QML0
64
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
FIGURE 7
Package Outline Raw Card E L-DIM-200-36
-!8
›
›
›
›
›
›
›
›
$ETAIL OF CONTACTS
›
›
›
›
›
›
›
-).
)32B/B',0BBBB
$RAWING ACCORDING TO )3/ 'ENERAL TOLERANCES ›
$IMENSION IN MM
Notes
1. SPD or Combidevice (if used then no Thermal Sensor needed)
2. Thermal Sensor (Optional)
Rev. 1.12, 2007-10
03292006-5LTN-QML0
65
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
6
Product Type Nomenclature
Qimonda’s nomenclature uses simple coding combined with
some proprietary coding. Table 31 provides examples for
module and component product type number as well as the
field number. The detailed field description together with
possible values and coding explanation is listed for modules
in Table 32 and for components in Table 33.
TABLE 31
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
HYS
64
T
64/128
0
2
0
K
M
–5
–A
DDR2 DRAM
HYB
18
T
512/1G 16
0
A
C
–5
TABLE 32
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
Qimonda Module Prefix
HYS
Constant
2
Module Data Width [bit]
64
Non-ECC
72
ECC
3
DRAM Technology
T
DDR2
4
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
64
512 MByte
128
1 GByte
256
2 GByte
512
4 GByte
5
Raw Card Generation
0 .. 9
Look up table
6
Number of Module Ranks
0, 2, 4
1, 2, 4
7
Product Variations
0 .. 9
Look up table
8
Package, Lead-Free Status
A .. Z
Look up table
9
Module Type
D
SO-DIMM
M
Micro-DIMM
R
Registered
U
Unbuffered
F
Fully Buffered
Rev. 1.12, 2007-10
03292006-5LTN-QML0
66
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Field
Description
Values
Coding
10
Speed Grade
–19F
PC2–8500 6–6–6
–1.9
PC2–8500 7–7–7
11
Die Revision
–25F
PC2–6400 5–5–5
–2.5
PC2–6400 6–6–6
–3
PC2–5300 4–4–4
–3S
PC2–5300 5–5–5
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
–A
First
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 33
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
Qimonda Component Prefix
HYB
Constant
2
Interface Voltage [V]
18
SSTL_18
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
256
256 Mbit
5+6
Number of I/Os
512
512 Mbit
1G
1 Gbit
2G
2 Gbit
40
×4
80
×8
16
×16
7
Product Variations
0 .. 9
Look up table
8
Die Revision
A
First
B
Second
9
Package, Lead-Free Status
C
FBGA, lead-containing
F
FBGA, lead-free
10
Speed Grade
Rev. 1.12, 2007-10
03292006-5LTN-QML0
–19F
PC2–8500 6–6–6
–1.9
PC2–8500 7–7–7
–25F
PC2–6400 5–5–5
–2.5
PC2–6400 6–6–6
–3
PC2–5300 4–4–4
–3S
PC2–5300 5–5–5
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
67
Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Rev. 1.12, 2007-10
03292006-5LTN-QML0
68
13
13
14
15
15
16
24
25
Internet Data Sheet
Edition 2007-10
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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