HANBit HSD16M32M4V Synchronous DRAM Module 64Mbyte ( 16M x 32-Bit ) 72-Pin SIMM based on 16Mx8, 4Banks, 4K Ref., 3.3V Part No. HSD16M32M4V GENERAL DESCRIPTION The HSD16M32M4V is a 16M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 4M x 8 bit with 4banks Synchronous DRAMs in TSOP-II packages mounted on a 72-pin, FR-4-printed circuit board. Two 0.01uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The HSD16M32M4V is a SIMM designed. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible. FEATURES PIN ASSIGNMENT • Part Identification HSD16M32M4V-13/F13 :133MHz ( CL=3) HSD16M32M4V-12/F12: 125MHz (CL=3) HSD16M32M4V-10/F10: 100MHz (CL=2) HSD16M32M4V-10L/F10L: 100MHz HSD16M32M4V-66/F66: 66MHz (CL=2&3) F means Auto & Self refresh with Low-Power (3.3V) • Burst mode operation • Auto & self refresh capability (4096 Cycles/64ms) • LVTTL compatible inputs and outputs • Single 3.3V ±0.3V power supply • MRS cycle with address key programs - Latency (Access from column address) PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 Vss 25 DQ14 49 A5 2 DQ0 26 DQ15 50 A6 3 DQ1 27 DQM1 51 A7 4 DQ2 28 NC 52 A8 5 DQ3 29 /WE 53 A9 6 DQ4 30 /CAS 54 DQ24 7 DQ5 31 Vcc 55 DQ25 8 DQ6 32 /RAS 56 DQ26 9 DQ7 33 /CS0 57 DQ27 10 DQM0 34 NC 58 DQ28 11 Vcc 35 NC 59 DQ29 12 NC 36 CLK0 60 DQ30 13 A0 37 CKE0 61 DQ31 - Burst length (1, 2, 4, 8 & Full page) 14 A1 38 Vss 62 DQM3 - Data scramble (Sequential & Interleave) 15 A2 39 DQ16 63 NC 16 A3 40 DQ17 64 A10/AP • All inputs are sampled at the positive going edge of the system clock 17 A4 41 DQ18 65 A11 • FR4-PCB design 18 Vss 42 DQ19 66 NC • The used device is KM48S16030AT 19 DQ8 43 DQ20 67 Vcc • Pin assignment is compatible with 20 DQ9 44 DQ21 68 BA0 21 DQ10 45 DQ22 69 BA1 22 DQ11 46 DQ23 70 NC 23 DQ12 47 DQM2 71 NC 24 DQ13 48 Vcc 72 Vss - HSD8M32M4V - HSD32M32M4V 72-PIN SIMM TOP VIEW URL: www.hbe.co.kr REV 1.0 (August.2002) -1- HANBit Electronics Co.,Ltd. HANBit HSD16M32M4V FUNCTIONAL BLOCK DIAGRAM DQ0-31 CKE0 CKE /CA CAS S /RAS RAS /CE1 CE CLK U1 CLK0 DQ0-7 DQM0 DQM0 WE A0-A11 BA0- 1 CKE CLK U2 CAS CLK0 DQ8- 15 DQM1 RAS CE DQM0 WE A0-A11 BA0- 1 CKE CLK U3 CAS CLK0 DQ16- 23 DQM2 RAS CE DQM0 WE A0-A11 BA0- 1 CKE CLK U4 CAS CLK0 DQ24- 31 DQM3 RAS CE DQM0 WE A0-A11 BA0- 1 /WE A0 - A11 BA0-1 Vcc Two 0.01uF Capacitor per each SDRAM Vss URL: www.hbe.co.kr REV 1.0 (August.2002) -2- HANBit Electronics Co.,Ltd. HANBit HSD16M32M4V PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. /CE Chip enable Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 ~ Bank select address BA1 /RAS Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. /WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 4W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA Notes : Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. URL: www.hbe.co.kr REV 1.0 (August.2002) -3- HANBit Electronics Co.,Ltd. HANBit HSD16M32M4V DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 3 CAPACITANCE (VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNITS Address(A0~A12, BA0~BA1) CADD 15 25 pF /RAS, /CAS, /WE C IN 15 25 pF CKE(CKE0) CCKE 15 25 pF Clock (CLK0) CCLK 7.5 9 pF /CE (/CE1) CCS 15 25 pF DQM (DQM0 ~ DQM3) CDQM 6.5 7.5 pF DQ (DQ0 ~ DQ32) COUT 7 8.5 pF DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70° C) TEST PARAMETER VERSION NOT SYMBOL UNIT CONDITION -A -8 -H 440 440 -L E -10 Burst length = 1 Operating current ICC1 (One bank active) 48 tRC ≥ tRC(min) 44 0 440 mA 1 0 IO = 0mA Precharge standby current ICC2P CKE ≤ VIL(max) 4 mA 4 mA tCC=10ns in power-down mode ICC2PS CKE & CLK ≤ VIL(max) tCC=∞ URL: www.hbe.co.kr REV 1.0 (August.2002) -4- HANBit Electronics Co.,Ltd. HANBit HSD16M32M4V CKE ≥ VIH(min) ICC2N CS* ≥ VIH(min), tCC=10ns Precharge standby current Input signals are changed in one time during 20ns non power-down mode CKE ≥ VIH(min) ICC2NS 80 mA CLK ≤ VIL(max), tCC=∞ 28 Input signals are stable ICC3P Active standby current in power-down mode ICC3PS CKE ≤ VIL(max), tCC=10ns 20 CKE&CLK ≤ VIL(max) mA 20 tCC=∞ CKE≥VIH(min), CS*≥VIH(min), tCC=10ns 120 ICC3N Active standby current in Input signals are changed non power-down mode one time during 20ns (One bank active) CKE≥VIH(min) ICC3NS mA CLK ≤VIL(max), tCC=∞ 80 Input signals are stable IO = 0 mA Operating current Page burst 60 4Banks Activated 0 ICC4 (Burst mode) 580 500 500 500 mA 1 880 840 840 840 mA 2 6 mA G 3.2 mA F tCCD = 2CLKs Refresh current ICC5 Self refresh current 88 tRC ≥ tRC(min) ICC6 0 CKE ≤ 0.2V Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). AC OPERATING TEST CONDITIONS (vcc = 3.3V ± 0.3V, TA = 0 to 70° C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition URL: www.hbe.co.kr REV 1.0 (August.2002) Value UNIT 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 -5- HANBit Electronics Co.,Ltd. HANBit HSD16M32M4V +3.3V Vtt=1.4V 1200Ω 50Ω DOUT 870Ω DOUT 50pF* Z0=50Ω 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER SYMBOL -A -8 -H -L -10 UNIT NOTE Row active to row active delay tRRD(min) 15 16 20 20 20 ns 1 RAS to CAS delay tRP(min) 20 20 20 20 24 ns 1 Row precharge time tRP(min) 20 20 20 20 24 ns 1 tRAS(min) 45 48 50 50 50 ns 1 Row active time Row cycle time tRAS(max) 100 tRC(min) 65 68 70 ns 70 80 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2.5 Last data in to Active delay tDAL(min) 2 CLK + 20 ns - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 CAS latency=3 2 Number of valid output data CAS latency=2 - 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -8/H/L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported . ( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.) URL: www.hbe.co.kr REV 1.0 (August.2002) -6- HANBit Electronics Co.,Ltd. HANBit HSD16M32M4V AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -A -8 -H -L -10 SYM PARAMETER NOT MIN MAX MIN MAX MIN MA MIN MAX MIN MAX UNIT BOL E X CLK cycle CAS time latency=3 7.5 8 10 1000 10 10 100 tCC 1000 1000 1000 ns 1 ns 1,2 ns 2 0 CAS - - 12 10 13 latency=2 CLK to valid CAS output delay latency=3 5.4 6 6 6 7 tSAC CAS - 7 - 6 7 latency=2 Output data CAS hold time latency=3 2.7 3 3 3 3 tOH CAS - - 3 3 3 latency=2 CLK high pulse width tCH 2.5 3 3 3 3.5 ns 3 CLK low pulse width tCL 2.5 3 3 3 3.5 ns 3 Input setup time tSS 1.5 2 2 2 2.5 ns 3 Input hold time tSH 0.8 1 1 1 1.5 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 1 ns 3 2 CLK to CAS output latency=3 in Hi-Z CAS 5.4 6 6 6 7 ns - 7 - 6 7 ns tSHZ latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered ie., [(tr + tf)/2-1]ns should be added to the parameter. SIMPLIFIED TRUTH TABLE CKE n-1 COMMAND Register Mode register set Auto refresh Refresh Self refres h Entry Exit Bank active & row addr. URL: www.hbe.co.kr REV 1.0 (August.2002) H H CKE n /C S /R A S /C A S /W E D Q M X L L L L X OP code L L L H X X L H H H H X X X X X L L H H H L L H H X -7- X BA 0,1 V A10/ AP A11 A9~A0 NOTE 1,2 Row address HANBit Electronics Co.,Ltd. 3 3 3 3 HANBit HSD16M32M4V Auto Read & precharge disable column Auto address precharge L H X L H L H X Auto Write & address Auto L H X L H L L X precharge X L L H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L Exit L H Bank selection e All banks Clock suspend or active power down Precharge power down mode DQM H X X X L H H H H X X X L V V V H No operation command Address H H Precharg 4,5 H X X H X X X L H H H X 4 (A0 ~ A9) V disable Burst Stop (A0 ~ A9) Column precharge disable column Address H disable 4 Column V 4,5 X V L X H 6 X X X X X X V X X X (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) TIMING DIAGRAMS Please refer to timing diagram chart (II) URL: www.hbe.co.kr REV 1.0 (August.2002) -8- HANBit Electronics Co.,Ltd. 7 HANBit HSD16M32M4V PACKAGING INFORMATION Unit : mm 107.95 ± 20 17.8 ± 0.2 3.38 3.2 t 10.16 6.35 2.03 44.45 1.27 1.00 95.25 6.35 6.35 2.54 0.25 MAX MIN 1.27±0.08 Gold: 1.04±0.10 1.27 Solder: 0.914±0.10 (Solder & Gold Plating) URL: www.hbe.co.kr REV 1.0 (August.2002) -9- HANBit Electronics Co.,Ltd. HANBit HSD16M32M4V ORDERING INFORMATION Part Number Density Org. HSD16M32M4V-13 64MByte 16Mx 32 HSD16M32M4V-F13 64MByte 16Mx 32 HSD16M32M4V-12 64MByte 16Mx 32 HSD16M32M4V-F12 64MByte 16Mx 32 HSD16M32M4V-10 64MByte 16Mx 32 HSD16M32M4V-F10 64MByte 16Mx 32 HSD16M32M4V-10L 64MByte 16Mx 32 HSD16M32M4V-F10L 64MByte 16Mx 32 URL: www.hbe.co.kr REV 1.0 (August.2002) Package 72 Pin SIMM 72 Pin SIMM 72 Pin SMM 72 Pin SIMM 72 Pin SIMM 72 Pin SIMM 72 Pin SIMM 72 Pin SIMM - 10 - Ref. Vcc 4K 3.3V 4K 3.3V 4K 3.3V 4K 3.3V 4K 3.3V 4K 3.3V 4K 3.3V 4K 3.3V Feature MAX.frq 133MHz (CL=3) Low 133MHz Power (CL=3) 125MHz (CL=3) Low Power 125MHz (CL=3) 100MHz (CL=2) Low 100MHz Power (CL=2) 100MHz Low Power 100MHz HANBit Electronics Co.,Ltd.