ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 – AUGUST 1985 – REVISED JUNE 1986
D
D
D
D
D
D
D
D
ADC0831 . . . P PACKAGE
8-Bit Resolution
Easy Microprocessor interface or
Stand-Alone Operation
Operates Ratiometrically or With 5-V
Reference
Single Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
Input Range 0 to 5 V With Single 5-V Supply
Inputs and Outputs Are Compatible With
TTL and MOS
Conversion Time of 32 µs at CLK = 250 kHz
Designed to Be interchangeable With
National Semiconductor ADC0831 and
ADC0832
DEVICE
(TOP VIEW)
CS
IN+
IN–
GND
1
8
2
7
3
6
4
5
VCC
CLK
DO
REF
ADC0832 . . . P PACKAGE
(TOP VIEW)
CS
CH0
CH1
GND
1
8
2
7
3
6
4
5
VCC/REF
CLK
DO
DI
TOTAL UNADJUSTED ERROR
A-SUFFIX
B-SUFFIX
ADC0831
± 1 LSB
± 1/2 LSB
ADC0832
± 1 LSB
± 1/2 LSB
description
These devices are 8-bit successive-approximation analog-to-digital converters. The ADC0831A and
ADC0831B have single input channels; the ADC0832A and ADC0832B have multiplexed twin input channels.
The serial output is configured to interface with standard shift registers or microprocessors. Detailed information
on interfacing to most popular microprocessors is readily available from the factory.
The ADC0832 multiplexer is software configured for single-ended or differential inputs. The differential analog
voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition,
the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits
of resolution.
The operation of the ADC0831 and ADC0832 devices is very similar to the more complex ADC0834 and
ADC0838 devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum
analog input signal value, which gives the highest possible conversion resolution. Typically, REF is set equal
to VCC (done internally on the ADC0832). For more detail on the operation of the ADC0831 and ADC0832
devices, refer to the ADC0834/A DC0838 data sheet.
The ADC0831AC, ADC0831BC, ADC0832AC, and ADC0832BC are characterized for operation from 0°C
to 70°C. The ADC0831AI, ADC0831BI, ADC0832AI, and ADC0832BI are characterized for operation from
– 40°C to 85°C.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•
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•
1
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 – AUGUST 1985 – REVISED JUNE 1986
functional block diagram
CLK
CS
7
Start
Flip-Flop
1
CLK
Shift Register
DI
5
Odd/Even
D
(ADC0832
Only)
S
R
Start
CLK
To Internal
Circuits
CLK
Single/Differential
CH0/IN+
Analog
Mux
CH1/IN –
S
Comparator
R
Time
Delay
EN
1
CS
CS
CS
1
EN
REF
(ADC0831
Only)
5
Ladder
and
Decoder
Bits 0–7
R
EN
SAR
Logic
and
Latch
CLK
Bits 0–7
Bit 1
MSB
First
9-Bit
Shift
Register
LSB
First
One
Shot
2
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•
CS
1
R
EOC
1
R
CLK
D
CS
1
6
DO
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 – AUGUST 1985 – REVISED JUNE 1986
sequence of operation
ADC0831
1
2
3
4
5
6
7
8
9
10
CLK
tsu
tconv
CS
MSB-First Data
MUX
Settling Time
HI-Z
DO
MSB
7
Hi-Z
LSB
6
5
4
3
2
1
0
ADC0832
1
2
3
4
5
6
10
11
12
13
14
18
19
20
21
CLK
tconv
tsu
CS
Start
+Sign
Bit SGL Odd
DI
(ADC0832
only)
Don’t Care
Dif
Even
MSB-First Data
LSB-First Data
MUX
Settling Time
DO
Hi-Z
MSB
7
LSB
6
2
1
MSB
0
1
2
6
7
ADC0832 MUX ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
SGL/DIF
L
L
H
H
CHANNEL NUMBER
ODD/EVEN
L
H
L
H
0
1
+
–
+
–
+
+
H = high level, L = low level,
– or + = polarity of selected input pin
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3
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 – AUGUST 1985 – REVISED JUNE 1986
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Input voltage range: Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3
Input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Total input current for package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating free-air temperature range: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
recommended operating conditions
VCC
VIH
Supply voltage
VIL
fclock
Low-level input voltage
High-level input voltage
MIN
NOM
MAX
4.5
5
6.3
2
Clock frequency
Clock duty cycle (see Note 2)
UNIT
V
V
0.8
V
10
400
kHz
40
60
%
twH(C Pulse duration, CS high
S)
220
ns
tsu
th
Setup time, CS low or ADC0832 data valid before CLK↑
350
ns
90
ns
TA
Operating free
free-air
air temperature
Hold time, ADC0832 data valid after CLK↑
C-suffix
I-suffix
0
70
– 40
85
°C
NOTE 2: The clock duty cycle range ensures proper operation at all clock frequencies. If a clock frequency is used outside the recommended
duty cycle range, the minimum pulse duration (high or low) is 1 µs.
electrical characteristics over recommended range of operating free-air temperature, VCC = 5 V,
fclock = 250 kHz (unless otherwise noted)
digital section
PARAMETER
VOH
High level output voltage
High-level
VOL
IIH
Low-levl output voltage
IIL
IOH
Low-level input current
IOL
Low-level output (sink) current
High-level input current
High-level output (source) current
IOZ
High-impedance-state
g
output
current (DO)
Ci
Input capacitance
TEST CONDITIONS{
MIN
C SUFFIX
TYP‡
MAX
VCC = 4.75 V,
VCC = 4.75 V,
IOH = – 360 µA
IOH = – 10 µA
2.8
2.4
4.6
4.5
VCC = 4.75 V,
VIH = 5 V
IOL = 1.6 mA
0.34
0.4
VIL = 0
VOH = VO,
VOL = VCC,
VO = 5 V,
VO = 0,
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
•
MAX
UNIT
V
V
0.005
1
0.005
1
µA
–1
– 0.005
–1
µA
– 6.5
– 14
– 6.5
– 14
8
16
8
16
mA
mA
0.01
3
0.01
3
– 0.01
–3
– 0.01
–3
5
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•
I SUFFIX
TYP‡
– 0.005
Co
Output capacitance
5
† All parameters are measured under open-loop conditions with zero common-mode input voltage.
‡ All typical values are at VCC = 5 V, TA = 25°C.
4
MIN
µA
5
pF
5
pF
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 – AUGUST 1985 – REVISED JUNE 1986
electrical characteristics over recommended range of operating free-air temperature,
VCC = 5 V, fclock = 250 kHz (unless otherwise noted)
analog and converter section
PARAMETER
VICR
TEST CONDITIONS†
MIN
See Note 3
– 0.05
to
VCC+ 0.05
Common-mode input voltage range
On-channel
Standby input current (see Note 4)
ri(REF)
Input resistance to reference ladder
MAX
On-channel
1
–1
VI = 0
VI = 5 V
Off-channel
UNIT
V
VI = 5 V
VI = 0
Off-channel
II(
I(stdby)
tdb )
TYP‡
–1
µA
1
1.3
2.4
5.9
kΩ
total device
TEST CONDITIONS†
TYP‡
MAX
ADC0831
1
2.5
ADC0832
3
5.2
PARAMETER
ICC
Supply current
MIN
UNIT
mA
† All parameters are measured under open-loop conditions with zero common-mode input voltage.
‡ All typical values are at VCC = 5 V, TA = 25°C.
NOTES: 3. If channel IN– is more positive than channel IN+, the digital output code will be 0000 0000. Connected to each analog input are two
on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC .Care must be taken during testing
at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause this input diode
to conduct and cause errors for analog inputs that are near full-scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V to 5 V input voltage range requires a minimum
VCC of 4.95 V for all variations of temperature and load.
4. Standby input currents are currents going into or out of the on or off channels when the A/D converter is not performing conversion
and the clock is in a high or low steady-state condition.
operating characteristics VCC = REF = 5 V, fclock = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS§
Supply-voltage variation error
Total unadjusted error (see Note 5)
Common-mode error
tpd
d
Propagation delay time,
ouput data after CLK↑
(see Note 6)
tdi
dis
Output disable time,,
DO after CS↑
tconv
Conversion time (multiplexer addressing
time not included)
BI, BC SUFFIX
TYP
MAX
VCC = 4.75 V to 5.25 V
Vref = 5 V,
TA = MIN to MAX
± 1/16
± 1/4
Differential mode
± 1/16
± 1/4
650
MSB-first data
LSB-first data
AI, AC SUFFIX
CL = 100 pF
MIN
MIN
UNIT
TYP
MAX
± 1/16
± 1/4
LSB
± 1/2
LSB
± 1/16
± 1/4
LSB
1500
650
1500
250
600
250
600
125
250
125
250
±1
ns
CL = 10 pF, RL = 10 kΩ
CL = 100 pF, RL = 2 kΩ
500
500
8
8
ns
clock
periods
§ All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES:5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The most significant-bit-first data is output directly from the comparator and therefore requires additional delay to allow for comparator response
time. Least-significant-bit-first data applies only to ADC0832.
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5
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 – AUGUST 1985 – REVISED JUNE 1986
PARAMETER MEASUREMENT INFORMATION
VCC
CLK
50%
50%
GND
tsu
tsu
VCC
VCC
CS
CLK
0.4 V
50%
GND
th
2V
GND
th
tpd
VOH
VCC
2V
DO
50%
DI
0.4 V
0.4 V
VOL
GND
Figure 1. ADC0832 Data Input Timing
Figure 2. Data Output Timing
VCC
Test
Point
S1
RL
From Output
Under Test
CL
(see Note A)
S2
LOAD CIRCUIT
tr
CS
50%
tr
VCC
90%
10%
CS
10%
GND
S1 open
S2 closed
VCC
90%
DO and SARS
Output
GND
S1 open
S2 closed
–VCC
10%
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
6
GND
tdis
tdis
DO and SARS
Output
VCC
90%
50%
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GND
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 – AUGUST 1985 – REVISED JUNE 1986
TYPICAL CHARACTERISTICS
LINEARITY ERROR
vs
REFERENCE VOLTAGE
UNADJUSTED OFFSET ERROR
vs
REFERENCE VOLTAGE
1.5
16
VCC = 5 V
fclock = 250 kHz
TA = 25°C
VI+ = VI – = 0 V
14
1.25
Linearity Error – LSB
Offset Error – LSB
12
10
8
6
1.0
0.75
0.5
4
0.25
2
0
0.01
0.1
1.0
0
10
1
0
2
5
Figure 5
Figure 4
LINEARITY ERROR
vs
CLOCK FREQUENCY
LINEARITY ERROR
vs
FREE-AIR TEMPERATURE
0.5
3
Vref = 5 V
VCC = 5 V
Vref = 5 V
fclock = 250 kHz
2.5
Linearity Error – LSB
0.45
Linearity Error – LSB
4
Vref – Reference Voltage – V
Vref – Reference Voltage – V
0.4
0.35
0.3
0.25
– 50
3
2
1.5
85°C
1
25°C
– 40°C
0.5
– 25
0
25
50
75
0
100
TA – Free-Air Tempertature – °C
0
100
200
300
400
500
600
fclock – Clock Frequency – kHz
Figure 6
Figure 7
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7
ADC0831A, ADC0832A, ADC0831B, ADC0832B
A/D PERIPHERALS WITH SERIAL CONTROL
SLAS006 – AUGUST 1985 – REVISED JUNE 1986
ADC0831
ADC0831
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
CLOCK FREQUENCY
1.5
1.5
VCC = 5 V
TA = 25°C
I CC – Supply Current – mA
I CC – Supply Current – mA
fclock = 250 kHz
CS = High
VCC = 5.5 V
VCC = 5 V
1
VCC = 4.5 V
0.5
– 50
– 25
0
25
50
75
1
0.5
0
100
0
TA – Free-Air Temperature — °C
100
200
Figure 9
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
25
VCC = 5 V
I O – Output Current – mA
20
IOL (VOL = 5 V)
15
– IOH (VOH = 0 V)
10
– IOH (VOH = 2.4 V)
5
IOL (VOL = 0.4 V)
– 25
0
25
50
75
TA – Free-Air Temperature – °C
Figure 10
8
400
fclock – Clock Frequency – kHz
Figure 8
0
– 50
300
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•
100
500
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated